M25P32-VMF6P [STMICROELECTRONICS]
32 Mbit, Low Voltage, Serial Flash Memory With 50MHz SPI Bus Interface; 32兆位，低电压，串行闪存的50MHz SPI总线接口
| 型号： | M25P32-VMF6P |
| 厂家： | 
ST |
| 描述： | 32 Mbit, Low Voltage, Serial Flash Memory With 50MHz SPI Bus Interface |
| 文件： | 总39页 (文件大小：508K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M25P32
32 Mbit, Low Voltage, Serial Flash Memory
With 50MHz SPI Bus Interface
FEATURES SUMMARY
■
32Mbit of Flash Memory
Figure 1. Packages
■
Page Program (up to 256 Bytes) in 1.4ms
(typical)
■
■
■
■
■
■
■
Sector Erase (512Kbit)
Bulk Erase (32Mbit)
2.7 to 3.6V Single Supply Voltage
SPI Bus Compatible Serial Interface
50MHz Clock Rate (maximum)
Deep Power-down Mode 1µA (typical)
Electronic Signatures
VDFPN8 (ME)
8x6mm (MLP8)
–
JEDEC Standard Two-Byte Signature
(2016h)
–
RES Instruction, One-Byte, Signature
(15h), for backward compatibility
■
■
More than 100,000 Erase/Program Cycles per
Sector
More than 20 Year Data Retention
SO16 (MF)
300 mil width
October 2004
1/39
M25P32
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. VDFPN Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Output (Q). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write Protect (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SPI MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. Bus Master and Memory Devices on the SPI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Polling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Active Power, Standby Power and Deep Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. Protected Area Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Hold Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Hold Condition Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2/39
M25P32
Figure 9. Write Enable (WREN) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10.Write Disable (WRDI) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Read Identification (RDID) Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11.Read Identification (RDID) Instruction Sequence and Data-Out Sequence . . . . . . . . . . 15
Read Status Register (RDSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12.Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence . . . . . . . 16
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13.Write Status Register (WRSR) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. Protection Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read Data Bytes (READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14.Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence . . . . . . . . . . . 19
Read Data Bytes at Higher Speed (FAST_READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 15.Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out Se-
quence 20
Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 16.Page Program (PP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 17.Sector Erase (SE) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 18.Bulk Erase (BE) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Deep Power-down (DP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 19.Deep Power-down (DP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Release from Deep Power-down and Read Electronic Signature (RES) . . . . . . . . . . . . . . . . . 25
Figure 20.Release from Deep Power-down and Read Electronic Signature (RES) Instruction Se-
quence and Data-Out Sequence25
Figure 21.Release from Deep Power-down (RES) Instruction Sequence. . . . . . . . . . . . . . . . . . . . 26
POWER-UP AND POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 22.Power-up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 8. Power-Up Timing and VWI Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 9. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 10. Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 11. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3/39
M25P32
Figure 23.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 12. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 13. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 14. AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 24.Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 25.Write Protect Setup and Hold Timing during WRSR when SRWD=1 . . . . . . . . . . . . . . . 33
Figure 26.Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 27.Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 28.MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm, Package Outline . . . . . . . 35
Table 15. MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm, Package Mechanical Data35
Figure 29.SO16 wide – 16-lead Plastic Small Outline, 300 mils body width, Package Outline. . . . 36
Table 16. SO16 wide – 16-lead Plastic Small Outline, 300 mils body width, Mechanical Data. . . . 36
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 17. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 18. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4/39
M25P32
SUMMARY DESCRIPTION
The M25P32 is a 32Mbit (4M x 8) Serial Flash
Memory, with advanced write protection mecha-
nisms, accessed by a high speed SPI-compatible
bus.
Figure 3. VDFPN Connections
The memory can be programmed 1 to 256 bytes at
a time, using the Page Program instruction.
The memory is organized as 64 sectors, each con-
taining 256 pages. Each page is 256 bytes wide.
Thus, the whole memory can be viewed as con-
sisting of 16384 pages, or 4,194,304 bytes.
The whole memory can be erased using the Bulk
Erase instruction, or a sector at a time, using the
Sector Erase instruction.
M25P32
S
Q
1
2
3
4
8
V
CC
HOLD
7
6
W
C
D
V
5
SS
AI08518
Figure 2. Logic Diagram
V
CC
D
C
S
Q
Note: 1. There is an exposed die paddle on the underside of the
MLP8 package. This is pulled, internally, to V , and
SS
must not be allowed to be connected to any other voltage
or signal line on the PCB.
2. See PACKAGE MECHANICAL section for package di-
mensions, and how to identify pin-1.
M25P32
W
Figure 4. SO Connections
HOLD
M25P32
V
SS
HOLD
1
2
3
4
5
6
7
8
16
15
C
AI07483
V
D
CC
DU
14
DU
DU
DU
DU
V
DU
DU
DU
S
13
Table 1. Signal Names
12
C
Serial Clock
Serial Data Input
Serial Data Output
Chip Select
Write Protect
Hold
11
10
D
SS
Q
9
W
Q
AI07484B
S
W
Note: 1. DU = Don’t Use
HOLD
2. See PACKAGE MECHANICAL section for package di-
mensions, and how to identify pin-1.
V
Supply Voltage
Ground
CC
V
SS
5/39
M25P32
SIGNAL DESCRIPTION
Serial Data Output (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
mode (this is not the Deep Power-down mode).
Driving Chip Select (S) Low enables the device,
placing it in the Active Power mode.
After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
Hold (HOLD). The Hold (HOLD) signal is used to
pause any serial communications with the device
without deselecting the device.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be se-
lected, with Chip Select (S) driven Low.
Write Protect (W). The main purpose of this in-
put signal is to freeze the size of the area of mem-
ory that is protected against program or erase
instructions (as specified by the values in the BP2,
BP1 and BP0 bits of the Status Register).
Serial Data Input (D). This input signal is used to
transfer data serially into the device. It receives in-
structions, addresses, and the data to be pro-
grammed. Values are latched on the rising edge of
Serial Clock (C).
Serial Clock (C). This input signal provides the
timing of the serial interface. Instructions, address-
es, or data present at Serial Data Input (D) are
latched on the rising edge of Serial Clock (C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
Chip Select (S). When this input signal is High,
the device is deselected and Serial Data Output
(Q) is at high impedance. Unless an internal Pro-
gram, Erase or Write Status Register cycle is in
progress, the device will be in the Standby Power
6/39
M25P32
SPI MODES
These devices can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes:
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in Figure 6., is the clock polarity when the bus
master is in Stand-by mode and not transferring
data:
–
–
CPOL=0, CPHA=0
CPOL=1, CPHA=1
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
–
–
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
Figure 5. Bus Master and Memory Devices on the SPI Bus
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
C
Q
D
C
Q
D
C Q D
Bus Master
(ST6, ST7, ST9,
ST10, Others)
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
CS3 CS2 CS1
S
S
S
W
HOLD
W
HOLD
HOLD
W
AI03746D
Note: The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 6. SPI Modes Supported
CPOL CPHA
C
C
0
1
0
1
D
MSB
Q
MSB
AI01438B
7/39
M25P32
OPERATING FEATURES
Page Programming
To program one data byte, two instructions are re-
quired: Write Enable (WREN), which is one byte,
and a Page Program (PP) sequence, which con-
sists of four bytes plus data. This is followed by the
until all internal cycles have completed (Program,
Erase, Write Status Register). The device then
goes in to the Standby Power mode. The device
consumption drops to I
.
CC1
The Deep Power-down mode is entered when the
specific instruction (the Deep Power-down (DP) in-
struction) is executed. The device consumption
internal Program cycle (of duration t ).
PP
To spread this overhead, the Page Program (PP)
instruction allows up to 256 bytes to be pro-
grammed at a time (changing bits from 1 to 0), pro-
vided that they lie in consecutive addresses on the
same page of memory.
drops further to I
. The device remains in this
CC2
mode until another specific instruction (the Re-
lease from Deep Power-down and Read Electron-
ic Signature (RES) instruction) is executed.
All other instructions are ignored while the device
is in the Deep Power-down mode. This can be
used as an extra software protection mechanism,
when the device is not in active use, to protect the
device from inadvertent Write, Program or Erase
instructions.
Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to
be reset from 1 to 0. Before this can be applied, the
bytes of memory need to have been erased to all
1s (FFh). This can be achieved either a sector at a
time, using the Sector Erase (SE) instruction, or
throughout the entire memory, using the Bulk
Erase (BE) instruction. This starts an internal
Status Register
The Status Register contains a number of status
and control bits that can be read or set (as appro-
priate) by specific instructions.
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write Status
Register, Program or Erase cycle.
Erase cycle (of duration t or t ).
SE
BE
The Erase instruction must be preceded by a Write
Enable (WREN) instruction.
Polling During a Write, Program or Erase Cycle
A further improvement in the time to Write Status
Register (WRSR), Program (PP) or Erase (SE or
BE) can be achieved by not waiting for the worst
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
case delay (t , t , t , or t ). The Write In
BP2, BP1, BP0 bits. The Block Protect (BP2,
BP1, BP0) bits are non-volatile. They define the
size of the area to be software protected against
Program and Erase instructions.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode. In this mode, the non-volatile bits
of the Status Register (SRWD, BP2, BP1, BP0)
become read-only bits.
W
PP SE
BE
Progress (WIP) bit is provided in the Status Regis-
ter so that the application program can monitor its
value, polling it to establish when the previous
Write cycle, Program cycle or Erase cycle is com-
plete.
Active Power, Standby Power and Deep
Power-Down Modes
When Chip Select (S) is Low, the device is select-
ed, and in the Active Power mode.
When Chip Select (S) is High, the device is dese-
lected, but could remain in the Active Power mode
8/39
M25P32
Protection Modes
–
Write Status Register (WRSR) instruction
completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
The environments where non-volatile memory de-
vices are used can be very noisy. No SPI device
can operate correctly in the presence of excessive
noise. To help combat this, the M25P32 features
the following data protection mechanisms:
–
–
–
■
■
The Block Protect (BP2, BP1, BP0) bits allow
part of the memory to be configured as read-
only. This is the Software Protected Mode
(SPM).
The Write Protect (W) signal allows the Block
Protect (BP2, BP1, BP0) bits and Status
Register Write Disable (SRWD) bit to be
protected. This is the Hardware Protected
Mode (HPM).
In addition to the low power consumption
feature, the Deep Power-down mode offers
extra software protection from inadvertant
Write, Program and Erase instructions, as all
instructions are ignored except one particular
instruction (the Release from Deep Power-
down instruction).
■
■
■
Power On Reset and an internal timer (t
can provide protection against inadvertant
changes while the power supply is outside the
operating specification.
Program, Erase and Write Status Register
instructions are checked that they consist of a
number of clock pulses that is a multiple of
eight, before they are accepted for execution.
All instructions that modify data must be
preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch
(WEL) bit. This bit is returned to its reset state
by the following events:
)
PUW
■
–
–
Power-up
Write Disable (WRDI) instruction
completion
Table 2. Protected Area Sizes
Status Register
Content
Memory Content
BP2
Bit
BP1
Bit
BP0
Bit
Protected Area
Unprotected Area
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
none
All sectors (64 sectors: 0 to 63)
Upper 64th (Sector 63)
Lower 63/64ths (63 sectors: 0 to 62)
Lower 31/32nds (62 sectors: 0 to 61)
Lower 15/16ths (60 sectors: 0 to 59)
Lower seven-eighths (56 sectors: 0 to 55)
Upper 32nd (two sectors: 62 and 63)
Upper sixteenth (four sectors: 60 to 63)
Upper eighth (eight sectors: 56 to 63)
Upper quarter (sixteen sectors: 48 to 63) Lower three-quarters (48 sectors: 0 to 47)
Upper half (thirty-two sectors: 32 to 63)
All sectors (64 sectors: 0 to 63)
Lower half (32 sectors: 0 to 31)
none
Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
9/39
M25P32
Hold Condition
rising edge does not coincide with Serial Clock (C)
being Low, the Hold condition ends after Serial
Clock (C) next goes Low. (This is shown in Figure
7.).
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
The Hold (HOLD) signal is used to pause any se-
rial communications with the device without reset-
ting the clocking sequence. However, taking this
signal Low does not terminate any Write Status
Register, Program or Erase cycle that is currently
in progress.
To enter the Hold condition, the device must be
selected, with Chip Select (S) Low.
The Hold condition starts on the falling edge of the
Hold (HOLD) signal, provided that this coincides
with Serial Clock (C) being Low (as shown in Fig-
ure 7.).
Normally, the device is kept selected, with Chip
Select (S) driven Low, for the whole duration of the
Hold condition. This is to ensure that the state of
the internal logic remains unchanged from the mo-
ment of entering the Hold condition.
If Chip Select (S) goes High while the device is in
the Hold condition, this has the effect of resetting
the internal logic of the device. To restart commu-
nication with the device, it is necessary to drive
Hold (HOLD) High, and then to drive Chip Select
(S) Low. This prevents the device from going back
to the Hold condition.
The Hold condition ends on the rising edge of the
Hold (HOLD) signal, provided that this coincides
with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial
Clock (C) being Low, the Hold condition starts af-
ter Serial Clock (C) next goes Low. Similarly, if the
Figure 7. Hold Condition Activation
C
HOLD
Hold
Hold
Condition
Condition
(standard use)
(non-standard use)
AI02029D
10/39
M25P32
MEMORY ORGANIZATION
The memory is organized as:
Each page can be individually programmed (bits
are programmed from 1 to 0). The device is Sector
or Bulk Erasable (bits are erased from 0 to 1) but
not Page Erasable.
■
■
■
4,194,304 bytes (8 bits each)
64 sectors (512Kbits, 65536 bytes each)
16384 pages (256 bytes each).
Figure 8. Block Diagram
HOLD
High Voltage
Generator
W
S
Control Logic
C
D
Q
I/O Shift Register
Status
Register
Address Register
and Counter
256 Byte
Data Buffer
3FFFFFh
Size of the
read-only
memory area
00000h
000FFh
256 Bytes (Page Size)
X Decoder
AI08519
11/39
M25P32
Table 3. Memory Organization
Sector
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Address Range
1F0000h
Sector
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
Address Range
1FFFFFh
1EFFFFh
1DFFFFh
1CFFFFh
1BFFFFh
1AFFFFh
19FFFFh
18FFFFh
17FFFFh
16FFFFh
15FFFFh
14FFFFh
13FFFFh
12FFFFh
11FFFFh
10FFFFh
0FFFFFh
0EFFFFh
0DFFFFh
0CFFFFh
0BFFFFh
0AFFFFh
09FFFFh
08FFFFh
07FFFFh
06FFFFh
05FFFFh
04FFFFh
03FFFFh
02FFFFh
01FFFFh
00FFFFh
3F0000h
3E0000h
3D0000h
3C0000h
3B0000h
3A0000h
390000h
380000h
370000h
360000h
350000h
340000h
330000h
320000h
310000h
300000h
2F0000h
2E0000h
2D0000h
2C0000h
2B0000h
2A0000h
290000h
280000h
270000h
260000h
250000h
240000h
230000h
220000h
210000h
200000h
3FFFFFh
3EFFFFh
3DFFFFh
3CFFFFh
3BFFFFh
3AFFFFh
39FFFFh
38FFFFh
37FFFFh
36FFFFh
35FFFFh
34FFFFh
33FFFFh
32FFFFh
31FFFFh
30FFFFh
2FFFFFh
2EFFFFh
2DFFFFh
2CFFFFh
2BFFFFh
2AFFFFh
29FFFFh
28FFFFh
27FFFFh
26FFFFh
25FFFFh
24FFFFh
23FFFFh
22FFFFh
21FFFFh
20FFFFh
1E0000h
1D0000h
1C0000h
1B0000h
1A0000h
190000h
180000h
170000h
160000h
150000h
140000h
130000h
120000h
110000h
100000h
0F0000h
0E0000h
0D0000h
0C0000h
0B0000h
0A0000h
090000h
080000h
070000h
060000h
050000h
040000h
030000h
020000h
010000h
000000h
8
7
6
5
4
3
2
1
0
12/39
M25P32
INSTRUCTIONS
All instructions, addresses and data are shifted in
and out of the device, most significant bit first.
Serial Data Input (D) is sampled on the first rising
edge of Serial Clock (C) after Chip Select (S) is
driven Low. Then, the one-byte instruction code
must be shifted in to the device, most significant bit
first, on Serial Data Input (D), each bit being
latched on the rising edges of Serial Clock (C).
data-out sequence. Chip Select (S) can be driven
High after any bit of the data-out sequence is be-
ing shifted out.
In the case of a Page Program (PP), Sector Erase
(SE), Bulk Erase (BE), Write Status Register
(WRSR), Write Enable (WREN), Write Disable
(WRDI) or Deep Power-down (DP) instruction,
Chip Select (S) must be driven High exactly at a
byte boundary, otherwise the instruction is reject-
ed, and is not executed. That is, Chip Select (S)
must driven High when the number of clock pulses
after Chip Select (S) being driven Low is an exact
multiple of eight.
All attempts to access the memory array during a
Write Status Register cycle, Program cycle or
Erase cycle are ignored, and the internal Write
Status Register cycle, Program cycle or Erase cy-
cle continues unaffected.
The instruction set is listed in Table 4..
Every instruction sequence starts with a one-byte
instruction code. Depending on the instruction,
this might be followed by address bytes, or by data
bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read
Data Bytes at Higher Speed (Fast_Read), Read
Status Register (RDSR), Read Identification
(RDID) or Release from Deep Power-down, and
Read Electronic Signature (RES) instruction, the
shifted-in instruction sequence is followed by a
Table 4. Instruction Set
Address
Bytes
Dummy
Bytes
Data
Bytes
Instruction
Description
Write Enable
One-byte Instruction Code
WREN
WRDI
RDID
0000 0110
0000 0100
1001 1111
0000 0101
0000 0001
0000 0011
0000 1011
0000 0010
1101 1000
1100 0111
1011 1001
06h
04h
9Fh
05h
01h
03h
0Bh
02h
D8h
C7h
B9h
0
0
0
0
0
3
3
3
3
0
0
0
0
0
0
0
0
1
0
0
0
0
0
Write Disable
0
1 to 3
1 to ∞
1
Read Identification
Read Status Register
Write Status Register
Read Data Bytes
RDSR
WRSR
READ
1 to ∞
1 to ∞
1 to 256
0
FAST_READ Read Data Bytes at Higher Speed
PP
SE
BE
DP
Page Program
Sector Erase
Bulk Erase
0
Deep Power-down
0
Release from Deep Power-down,
and Read Electronic Signature
0
0
3
0
1 to ∞
RES
1010 1011
ABh
Release from Deep Power-down
0
13/39
M25P32
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 9.)
sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set pri-
or to every Page Program (PP), Sector Erase
(SE), Bulk Erase (BE) and Write Status Register
(WRSR) instruction.
The Write Enable (WREN) instruction is entered
by driving Chip Select (S) Low, sending the in-
struction code, and then driving Chip Select (S)
High.
Figure 9. Write Enable (WREN) Instruction Sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI02281E
Write Disable (WRDI)
–
–
–
Power-up
The Write Disable (WRDI) instruction (Figure 10.)
resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by
driving Chip Select (S) Low, sending the instruc-
tion code, and then driving Chip Select (S) High.
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction
completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
–
–
–
The Write Enable Latch (WEL) bit is reset under
the following conditions:
Figure 10. Write Disable (WRDI) Instruction Sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI03750D
14/39
M25P32
Read Identification (RDID)
struction is shifted in. This is followed by the 24-bit
device identification, stored in the memory, being
shifted out on Serial Data Output (Q), each bit be-
ing shifted out during the falling edge of Serial
Clock (C).
The Read Identification (RDID) instruction allows
the 8-bit manufacturer identification to be read, fol-
lowed by two bytes of device identification. The
manufacturer identification is assigned by JEDEC,
and has the value 20h for STMicroelectronics. The
device identification is assigned by the device
manufacturer, and indicates the memory type in
the first byte (20h), and the memory capacity of the
device in the second byte (16h).
Any Read Identification (RDID) instruction while
an Erase or Program cycle is in progress, is not
decoded, and has no effect on the cycle that is in
progress.
The instruction sequence is shown in Figure 11..
The Read Identification (RDID) instruction is termi-
nated by driving Chip Select (S) High at any time
during data output.
When Chip Select (S) is driven High, the device is
put in the Standby Power mode. Once in the
Standby Power mode, the device waits to be se-
lected, so that it can receive, decode and execute
instructions.
The device is first selected by driving Chip Select
(S) Low. Then, the 8-bit instruction code for the in-
Table 5. Read Identification (RDID) Data-Out Sequence
Device Identification
Manufacturer Identification
Memory Type
Memory Capacity
20h
20h
16h
Figure 11. Read Identification (RDID) Instruction Sequence and Data-Out Sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 16 18
28 29 30 31
C
D
Instruction
Manufacturer Identification
Device Identification
High Impedance
Q
15 14 13
MSB
3
2
1
0
MSB
AI06809
15/39
M25P32
Read Status Register (RDSR)
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is
set, when set to 0 the internal Write Enable Latch
is reset and no Write Status Register, Program or
Erase instruction is accepted.
BP2, BP1, BP0 bits. The Block Protect (BP2,
BP1, BP0) bits are non-volatile. They define the
size of the area to be software protected against
Program and Erase instructions. These bits are
written with the Write Status Register (WRSR) in-
struction. When one or more of the Block Protect
(BP2, BP1, BP0) bits is set to 1, the relevant mem-
ory area (as defined in Table 2.) becomes protect-
ed against Page Program (PP) and Sector Erase
(SE) instructions. The Block Protect (BP2, BP1,
BP0) bits can be written provided that the Hard-
ware Protected mode has not been set. The Bulk
Erase (BE) instruction is executed if, and only if, all
Block Protect (BP2, BP1, BP0) bits are 0.
The Read Status Register (RDSR) instruction al-
lows the Status Register to be read. The Status
Register may be read at any time, even while a
Program, Erase or Write Status Register cycle is in
progress. When one of these cycles is in progress,
it is recommended to check the Write In Progress
(WIP) bit before sending a new instruction to the
device. It is also possible to read the Status Reg-
ister continuously, as shown in Figure 12..
Table 6. Status Register Format
b7
b0
SRWD
0
0
BP2 BP1 BP0 WEL WIP
Status Register
Write Protect
Block Protect Bits
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode (when the Status Register Write
Disable (SRWD) bit is set to 1, and Write Protect
(W) is driven Low). In this mode, the non-volatile
bits of the Status Register (SRWD, BP2, BP1,
BP0) become read-only bits and the Write Status
Register (WRSR) instruction is no longer accepted
for execution.
Write Enable Latch Bit
Write In Progress Bit
The status and control bits of the Status Register
are as follows:
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1,
such a cycle is in progress, when reset to 0 no
such cycle is in progress.
Figure 12. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
D
Instruction
Status Register Out
Status Register Out
High Impedance
Q
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
AI02031E
16/39
M25P32
Write Status Register (WRSR)
(whose duration is t ) is initiated. While the Write
W
Status Register cycle is in progress, the Status
Register may still be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Write Status
Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enable
Latch (WEL) is reset.
The Write Status Register (WRSR) instruction al-
lows new values to be written to the Status Regis-
ter. Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction
has been decoded and executed, the device sets
the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction al-
lows the user to change the values of the Block
Protect (BP2, BP1, BP0) bits, to define the size of
the area that is to be treated as read-only, as de-
fined in Table 2.. The Write Status Register
(WRSR) instruction also allows the user to set or
reset the Status Register Write Disable (SRWD)
bit in accordance with the Write Protect (W) signal.
The Status Register Write Disable (SRWD) bit and
Write Protect (W) signal allow the device to be put
in the Hardware Protected Mode (HPM). The Write
Status Register (WRSR) instruction is not execut-
ed once the Hardware Protected Mode (HPM) is
entered.
The Write Status Register (WRSR) instruction is
entered by driving Chip Select (S) Low, followed
by the instruction code and the data byte on Serial
Data Input (D).
The instruction sequence is shown in Figure 13..
The Write Status Register (WRSR) instruction has
no effect on b6, b5, b1 and b0 of the Status Reg-
ister. b6 and b5 are always read as 0.
Chip Select (S) must be driven High after the
eighth bit of the data byte has been latched in. If
not, the Write Status Register (WRSR) instruction
is not executed. As soon as Chip Select (S) is driv-
en High, the self-timed Write Status Register cycle
Figure 13. Write Status Register (WRSR) Instruction Sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
Instruction
Status
Register In
7
6
5
4
3
2
0
1
D
Q
High Impedance
MSB
AI02282D
17/39
M25P32
Table 7. Protection Modes
Memory Content
W
Signal
SRWD
Bit
Write Protection of the
Status Register
Mode
1
1
Protected Area
Unprotected Area
1
0
0
0
Status Register is Writable
(if the WREN instruction
has set the WEL bit)
The values in the SRWD,
BP2, BP1 and BP0 bits
can be changed
Software
Protected
(SPM)
Protected against Page
Program, Sector Erase
and Bulk Erase
Ready to accept Page
Program and Sector Erase
instructions
1
1
Status Register is
Hardware Hardware write protected
Protected The values in the SRWD,
Protected against Page
Program, Sector Erase
and Bulk Erase
Ready to accept Page
Program and Sector Erase
instructions
0
1
(HPM)
BP2, BP1 and BP0 bits
cannot be changed
Note: 1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 2..
The protection features of the device are summa-
rized in Table 7..
Status Register are rejected, and are not
accepted for execution). As a consequence,
all the data bytes in the memory area that are
software protected (SPM) by the Block Protect
(BP2, BP1, BP0) bits of the Status Register,
are also hardware protected against data
modification.
When the Status Register Write Disable (SRWD)
bit of the Status Register is 0 (its initial delivery
state), it is possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit has
previously been set by a Write Enable (WREN) in-
struction, regardless of the whether Write Protect
(W) is driven High or Low.
Regardless of the order of the two events, the
Hardware Protected Mode (HPM) can be entered:
When the Status Register Write Disable (SRWD)
bit of the Status Register is set to 1, two cases
need to be considered, depending on the state of
Write Protect (W):
–
by setting the Status Register Write Disable
(SRWD) bit after driving Write Protect (W) Low
–
or by driving Write Protect (W) Low after
setting the Status Register Write Disable
(SRWD) bit.
–
If Write Protect (W) is driven High, it is
possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit
has previously been set by a Write Enable
(WREN) instruction.
The only way to exit the Hardware Protected Mode
(HPM) once entered is to pull Write Protect (W)
High.
If Write Protect (W) is permanently tied High, the
Hardware Protected Mode (HPM) can never be
activated, and only the Software Protected Mode
(SPM), using the Block Protect (BP2, BP1, BP0)
bits of the Status Register, can be used.
–
If Write Protect (W) is driven Low, it is not
possible to write to the Status Register even if
the Write Enable Latch (WEL) bit has
previously been set by a Write Enable
(WREN) instruction. (Attempts to write to the
18/39
M25P32
Read Data Bytes (READ)
next higher address after each byte of data is shift-
ed out. The whole memory can, therefore, be read
with a single Read Data Bytes (READ) instruction.
When the highest address is reached, the address
counter rolls over to 000000h, allowing the read
sequence to be continued indefinitely.
The Read Data Bytes (READ) instruction is termi-
nated by driving Chip Select (S) High. Chip Select
(S) can be driven High at any time during data out-
put. Any Read Data Bytes (READ) instruction,
while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on
the cycle that is in progress.
The device is first selected by driving Chip Select
(S) Low. The instruction code for the Read Data
Bytes (READ) instruction is followed by a 3-byte
address (A23-A0), each bit being latched-in during
the rising edge of Serial Clock (C). Then the mem-
ory contents, at that address, is shifted out on Se-
rial Data Output (Q), each bit being shifted out, at
a maximum frequency f , during the falling edge of
R
Serial Clock (C).
The instruction sequence is shown in Figure 14..
The first byte addressed can be at any location.
The address is automatically incremented to the
Figure 14. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-Bit Address
23 22 21
MSB
3
2
1
0
D
Q
Data Out 1
Data Out 2
High Impedance
2
7
6
5
4
3
1
7
0
MSB
AI03748D
Note: Address bits A23 to A22 are Don’t Care.
19/39
M25P32
Read Data Bytes at Higher Speed
(FAST_READ)
next higher address after each byte of data is shift-
ed out. The whole memory can, therefore, be read
with a single Read Data Bytes at Higher Speed
(FAST_READ) instruction. When the highest ad-
dress is reached, the address counter rolls over to
000000h, allowing the read sequence to be contin-
ued indefinitely.
The Read Data Bytes at Higher Speed
(FAST_READ) instruction is terminated by driving
Chip Select (S) High. Chip Select (S) can be driv-
en High at any time during data output. Any Read
Data Bytes at Higher Speed (FAST_READ) in-
struction, while an Erase, Program or Write cycle
is in progress, is rejected without having any ef-
fects on the cycle that is in progress.
The device is first selected by driving Chip Select
(S) Low. The instruction code for the Read Data
Bytes at Higher Speed (FAST_READ) instruction
is followed by a 3-byte address (A23-A0) and a
dummy byte, each bit being latched-in during the
rising edge of Serial Clock (C). Then the memory
contents, at that address, is shifted out on Serial
Data Output (Q), each bit being shifted out, at a
maximum frequency f , during the falling edge of
C
Serial Clock (C).
The instruction sequence is shown in Figure 15..
The first byte addressed can be at any location.
The address is automatically incremented to the
Figure 15. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out
Sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
C
Instruction
24 BIT ADDRESS
23 22 21
3
2
1
0
D
Q
High Impedance
S
C
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
Dummy Byte
7
6
5
4
3
2
0
1
D
Q
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
MSB
MSB
MSB
AI04006
Note: Address bits A23 to A22 are Don’t Care.
20/39
M25P32
Page Program (PP)
rectly within the same page. If less than 256 Data
bytes are sent to device, they are correctly pro-
grammed at the requested addresses without hav-
ing any effects on the other bytes of the same
page.
Chip Select (S) must be driven High after the
eighth bit of the last data byte has been latched in,
otherwise the Page Program (PP) instruction is not
executed.
The Page Program (PP) instruction allows bytes to
be programmed in the memory (changing bits from
1 to 0). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write En-
able Latch (WEL).
The Page Program (PP) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, three address bytes and at least
one data byte on Serial Data Input (D). If the 8
least significant address bits (A7-A0) are not all
zero, all transmitted data that goes beyond the end
of the current page are programmed from the start
address of the same page (from the address
whose 8 least significant bits (A7-A0) are all zero).
Chip Select (S) must be driven Low for the entire
duration of the sequence.
As soon as Chip Select (S) is driven High, the self-
timed Page Program cycle (whose duration is t
)
PP
is initiated. While the Page Program cycle is in
progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit.
The Write In Progress (WIP) bit is 1 during the self-
timed Page Program cycle, and is 0 when it is
completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL)
bit is reset.
The instruction sequence is shown in Figure 16..
A Page Program (PP) instruction applied to a page
which is protected by the Block Protect (BP2, BP1,
BP0) bits (see Table 2. and Table 3.) is not execut-
ed.
If more than 256 bytes are sent to the device, pre-
viously latched data are discarded and the last 256
data bytes are guaranteed to be programmed cor-
Figure 16. Page Program (PP) Instruction Sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
C
D
Instruction
24-Bit Address
Data Byte 1
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
0
1
MSB
S
C
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Data Byte 2
Data Byte 3
Data Byte 256
7
6
5
4
3
2
0
7
6
5
4
3
2
0
7
6
5
4
3
2
0
1
1
1
D
MSB
MSB
MSB
AI04082B
Note: Address bits A23 to A22 are Don’t Care.
21/39
M25P32
Sector Erase (SE)
Chip Select (S) must be driven High after the
eighth bit of the last address byte has been latched
in, otherwise the Sector Erase (SE) instruction is
not executed. As soon as Chip Select (S) is driven
High, the self-timed Sector Erase cycle (whose du-
The Sector Erase (SE) instruction sets to 1 (FFh)
all bits inside the chosen sector. Before it can be
accepted, a Write Enable (WREN) instruction
must previously have been executed. After the
Write Enable (WREN) instruction has been decod-
ed, the device sets the Write Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, and three address bytes on Serial
Data Input (D). Any address inside the Sector (see
Table 3.) is a valid address for the Sector Erase
(SE) instruction. Chip Select (S) must be driven
Low for the entire duration of the sequence.
ration is t ) is initiated. While the Sector Erase cy-
SE
cle is in progress, the Status Register may be read
to check the value of the Write In Progress (WIP)
bit. The Write In Progress (WIP) bit is 1 during the
self-timed Sector Erase cycle, and is 0 when it is
completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL)
bit is reset.
A Sector Erase (SE) instruction applied to a page
which is protected by the Block Protect (BP2, BP1,
BP0) bits (see Table 2. and Table 3.) is not execut-
ed.
The instruction sequence is shown in Figure 17..
Figure 17. Sector Erase (SE) Instruction Sequence
S
0
1
2
3
4
5
6
7
8
9
29 30 31
C
D
Instruction
24 Bit Address
23 22
MSB
2
0
1
AI03751D
Note: Address bits A23 to A22 are Don’t Care.
22/39
M25P32
Bulk Erase (BE)
in, otherwise the Bulk Erase instruction is not exe-
cuted. As soon as Chip Select (S) is driven High,
the self-timed Bulk Erase cycle (whose duration is
The Bulk Erase (BE) instruction sets all bits to 1
(FFh). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write En-
able Latch (WEL).
The Bulk Erase (BE) instruction is entered by driv-
ing Chip Select (S) Low, followed by the instruction
code on Serial Data Input (D). Chip Select (S)
must be driven Low for the entire duration of the
sequence.
t
) is initiated. While the Bulk Erase cycle is in
BE
progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit.
The Write In Progress (WIP) bit is 1 during the self-
timed Bulk Erase cycle, and is 0 when it is com-
pleted. At some unspecified time before the cycle
is completed, the Write Enable Latch (WEL) bit is
reset.
The Bulk Erase (BE) instruction is executed only if
all Block Protect (BP2, BP1, BP0) bits are 0. The
Bulk Erase (BE) instruction is ignored if one, or
more, sectors are protected.
The instruction sequence is shown in Figure 18..
Chip Select (S) must be driven High after the
eighth bit of the instruction code has been latched
Figure 18. Bulk Erase (BE) Instruction Sequence
S
0
1
2
3
4
5
6
7
C
D
Instruction
AI03752D
23/39
M25P32
Deep Power-down (DP)
ture of the device to be output on Serial Data Out-
put (Q).
The Deep Power-down mode automatically stops
at Power-down, and the device always Powers-up
in the Standby Power mode.
The Deep Power-down (DP) instruction is entered
by driving Chip Select (S) Low, followed by the in-
struction code on Serial Data Input (D). Chip Se-
lect (S) must be driven Low for the entire duration
of the sequence.
Executing the Deep Power-down (DP) instruction
is the only way to put the device in the lowest con-
sumption mode (the Deep Power-down mode). It
can also be used as an extra software protection
mechanism, while the device is not in active use,
since in this mode, the device ignores all Write,
Program and Erase instructions.
Driving Chip Select (S) High deselects the device,
and puts the device in the Standby Power mode (if
there is no internal cycle currently in progress). But
this mode is not the Deep Power-down mode. The
Deep Power-down mode can only be entered by
executing the Deep Power-down (DP) instruction,
subsequently reducing the standby current (from
The instruction sequence is shown in Figure 19..
Chip Select (S) must be driven High after the
eighth bit of the instruction code has been latched
in, otherwise the Deep Power-down (DP) instruc-
tion is not executed. As soon as Chip Select (S) is
I
to I
, as specified in Table 13.).
CC1
CC2
driven High, it requires a delay of t
before the
DP
Once the device has entered the Deep Power-
down mode, all instructions are ignored except the
Release from Deep Power-down and Read Elec-
tronic Signature (RES) instruction. This releases
the device from this mode. The Release from
Deep Power-down and Read Electronic Signature
(RES) instruction also allows the Electronic Signa-
supply current is reduced to I
Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an
Erase, Program or Write cycle is in progress, is re-
jected without having any effects on the cycle that
is in progress.
and the Deep
CC2
Figure 19. Deep Power-down (DP) Instruction Sequence
S
tDP
0
1
2
3
4
5
6
7
C
D
Instruction
Stand-by Mode
Deep Power-down Mode
AI03753D
24/39
M25P32
Release from Deep Power-down and Read
Electronic Signature (RES)
progress, is not decoded, and has no effect on the
cycle that is in progress.
Once the device has entered the Deep Power-
down mode, all instructions are ignored except the
Release from Deep Power-down and Read Elec-
tronic Signature (RES) instruction. Executing this
instruction takes the device out of the Deep Pow-
er-down mode.
The device is first selected by driving Chip Select
(S) Low. The instruction code is followed by 3
dummy bytes, each bit being latched-in on Serial
Data Input (D) during the rising edge of Serial
Clock (C). Then, the old-style 8-bit Electronic Sig-
nature, stored in the memory, is shifted out on Se-
rial Data Output (Q), each bit being shifted out
during the falling edge of Serial Clock (C).
The instruction can also be used to read, on Serial
Data Output (Q), the old-style 8-bit Electronic Sig-
nature, whose value for the M25P32 is 15h.
The instruction sequence is shown in Figure 20..
Please note that this is not the same as, or even a
subset of, the JEDEC 16-bit Electronic Signature
that is read by the Read Identifier (RDID) instruc-
tion. The old-style Electronic Signature is support-
ed for reasons of backward compatibility, only, and
should not be used for new designs. New designs
should, instead, make use of the JEDEC 16-bit
Electronic Signature, and the Read Identifier
(RDID) instruction.
Except while an Erase, Program or Write Status
Register cycle is in progress, the Release from
Deep Power-down and Read Electronic Signature
(RES) instruction always provides access to the
old-style 8-bit Electronic Signature of the device,
and can be applied even if the Deep Power-down
mode has not been entered.
The Release from Deep Power-down and Read
Electronic Signature (RES) instruction is terminat-
ed by driving Chip Select (S) High after the Elec-
tronic Signature has been read at least once.
Sending additional clock cycles on Serial Clock
(C), while Chip Select (S) is driven Low, cause the
Electronic Signature to be output repeatedly.
When Chip Select (S) is driven High, the device is
put in the Standby Power mode. If the device was
not previously in the Deep Power-down mode, the
transition to the Standby Power mode is immedi-
ate. If the device was previously in the Deep Pow-
er-down mode, though, the transition to the
Standby Power mode is delayed by t
, and
RES2
Chip Select (S) must remain High for at least
(max), as specified in Table 14.. Once in the
t
RES2
Standby Power mode, the device waits to be se-
lected, so that it can receive, decode and execute
instructions.
Any Release from Deep Power-down and Read
Electronic Signature (RES) instruction while an
Erase, Program or Write Status Register cycle is in
Figure 20. Release from Deep Power-down and Read Electronic Signature (RES) Instruction
Sequence and Data-Out Sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38
C
tRES2
Instruction
3 Dummy Bytes
23 22 21
MSB
3
2
1
0
D
Q
Electronic Signature Out
High Impedance
7
6
5
4
3
2
0
1
MSB
Deep Power-down Mode
Stand-by Mode
AI04047C
Note: The value of the 8-bit Electronic Signature, for the M25P32, is 15h.
25/39
M25P32
Figure 21. Release from Deep Power-down (RES) Instruction Sequence
S
tRES1
0
1
2
3
4
5
6
7
C
D
Instruction
High Impedance
Q
Deep Power-down Mode
Stand-by Mode
AI04078B
Driving Chip Select (S) High after the 8-bit instruc-
tion byte has been received by the device, but be-
fore the whole of the 8-bit Electronic Signature has
been transmitted for the first time (as shown in Fig-
ure 21.), still ensures that the device is put into
Standby Power mode. If the device was not previ-
ously in the Deep Power-down mode, the transi-
tion to the Standby Power mode is immediate. If
the device was previously in the Deep Power-
down mode, though, the transition to the Standby
Power mode is delayed by t
(S) must remain High for at least t
, and Chip Select
RES1
(max), as
RES1
specified in Table 14.. Once in the Standby Power
mode, the device waits to be selected, so that it
can receive, decode and execute instructions.
26/39
M25P32
POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must
not be selected (that is Chip Select (S) must follow
–
–
t
t
after V
passed the V threshold
CC WI
PUW
VSL
after V passed the V (min) level
CC
CC
the voltage applied on V ) until V
reaches the
CC
CC
These values are specified in Table 8..
If the delay, t , has elapsed, after V has risen
above V (min), the device can be selected for
READ instructions even if the t
fully elapsed.
correct value:
VSL
CC
–
V
(min) at Power-up, and then for a further
CC
CC
delay of t
VSL
delay is not yet
PUW
–
V
at Power-down
SS
Usually a simple pull-up resistor on Chip Select (S)
can be used to ensure safe and proper Power-up
and Power-down.
To avoid data corruption and inadvertent write op-
erations during Power-up, a Power On Reset
(POR) circuit is included. The logic inside the de-
At Power-up, the device is in the following state:
–
The device is in the Standby Power mode (not
the Deep Power-down mode).
–
The Write Enable Latch (WEL) bit is reset.
vice is held reset while V is less than the Power
Normal precautions must be taken for supply rail
decoupling, to stabilize the V supply. Each de-
CC
On Reset (POR) threshold voltage, V – all oper-
WI
CC
ations are disabled, and the device does not re-
spond to any instruction.
Moreover, the device ignores all Write Enable
(WREN), Page Program (PP), Sector Erase (SE),
Bulk Erase (BE) and Write Status Register
vice in a system should have the V
rail decou-
CC
pled by a suitable capacitor close to the package
pins. (Generally, this capacitor is of the order of
0.1µF).
At Power-down, when V drops from the operat-
CC
(WRSR) instructions until a time delay of t
has
ing voltage, to below the Power On Reset (POR)
PUW
elapsed after the moment that V rises above the
threshold voltage, V , all operations are disabled
CC
WI
V
threshold. However, the correct operation of
and the device does not respond to any instruc-
tion. (The designer needs to be aware that if a
Power-down occurs while a Write, Program or
Erase cycle is in progress, some data corruption
can result.)
WI
the device is not guaranteed if, by this time, V is
CC
still below V (min). No Write Status Register,
CC
Program or Erase instructions should be sent until
the later of:
Figure 22. Power-up Timing
V
CC
V
(max)
CC
Program, Erase and Write Commands are Rejected by the Device
Chip Selection Not Allowed
V
(min)
CC
tVSL
Read Access allowed
Device fully
accessible
Reset State
of the
Device
V
WI
tPUW
time
AI04009C
27/39
M25P32
Table 8. Power-Up Timing and V Threshold
WI
Symbol
Parameter
Min.
30
Max.
Unit
µs
1
V
CC
(min) to S low
tVSL
1
Time delay to Write instruction
Write Inhibit Voltage
1
10
ms
V
tPUW
1
1.5
2.5
VWI
Note: 1. These parameters are characterized only.
INITIAL DELIVERY STATE
The device is delivered with the memory array
erased: all bits are set to 1 (each byte contains
FFh). The Status Register contains 00h (all Status
Register bits are 0).
28/39
M25P32
MAXIMUM RATING
Stressing the device outside the ratings listed in
Table 9. may cause permanent damage to the de-
vice. These are stress ratings only, and operation
of the device at these, or any other conditions out-
side those indicated in the Operating sections of
this specification, is not implied. Exposure to Ab-
solute Maximum Rating conditions for extended
periods may affect device reliability. Refer also to
the STMicroelectronics SURE Program and other
relevant quality documents.
Table 9. Absolute Maximum Ratings
Symbol
Parameter
Min.
Max.
Unit
°C
°C
V
T
Storage Temperature
–65
150
STG
1
TLEAD
VIO
Lead Temperature during Soldering
Input and Output Voltage (with respect to Ground)
Supply Voltage
See note
–0.6
–0.6
4.0
4.0
V
V
CC
2
VESD
–2000
2000
V
Electrostatic Discharge Voltage (Human Body model)
®
Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK 7191395 specification, and
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
29/39
M25P32
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 10. Operating Conditions
Symbol
Parameter
Min.
2.7
Max.
3.6
Unit
V
V
CC
Supply Voltage
Ambient Operating Temperature
TA
–40
85
°C
Table 11. AC Measurement Conditions
Symbol
Parameter
Min.
Max.
Unit
pF
ns
V
C
Load Capacitance
30
L
Input Rise and Fall Times
5
0.2V to 0.8V
Input Pulse Voltages
CC
CC
CC
0.3V to 0.7V
Input Timing Reference Voltages
Output Timing Reference Voltages
V
CC
V
/ 2
V
CC
Note: Output Hi-Z is defined as the point where data out is no longer driven.
Figure 23. AC Measurement I/O Waveform
Input Levels
Input and Output
Timing Reference Levels
0.8V
0.2V
CC
CC
0.7V
CC
CC
0.3V
CC
0.5V
AI07455
Table 12. Capacitance
Symbol
COUT
Parameter
Test Condition
= 0V
Min.
Max.
Unit
pF
Output Capacitance (Q)
V
8
6
OUT
CIN
Input Capacitance (other pins)
V
= 0V
pF
IN
Note: Sampled only, not 100% tested, at T =25°C and a frequency of 20MHz.
A
30/39
M25P32
Table 13. DC Characteristics
Test Condition
(in addition to those in Table 10.)
Symbol
Parameter
Min.
Max.
Unit
ILI
Input Leakage Current
Output Leakage Current
Standby Current
± 2
± 2
50
µA
µA
µA
µA
ILO
ICC1
ICC2
S = VCC, VIN = VSS or VCC
S = VCC, VIN = VSS or VCC
Deep Power-down Current
10
C = 0.1VCC / 0.9.VCC at 50MHz,
Q = open
8
4
mA
mA
ICC3
Operating Current (READ)
C = 0.1VCC / 0.9.VCC at 20MHz,
Q = open
ICC4
ICC5
ICC6
ICC7
VIL
S = VCC
S = VCC
S = VCC
S = VCC
Operating Current (PP)
Operating Current (WRSR)
Operating Current (SE)
Operating Current (BE)
Input Low Voltage
15
15
mA
mA
mA
mA
V
15
15
0.3VCC
VCC+0.4
0.4
– 0.5
VIH
0.7VCC
Input High Voltage
V
VOL
VOH
I
OL = 1.6mA
Output Low Voltage
V
Output High Voltage
IOH = –100µA
VCC–0.2
V
Table 14. AC Characteristics
Test conditions specified in Table 10. and Table 11.
Symbol
Alt.
Parameter
Min.
Typ.
Max.
Unit
Clock Frequency for the following instructions:
FAST_READ, PP, SE, BE, DP, RES,
WREN, WRDI, RDID, RDSR, WRSR
f
f
D.C.
50
20
MHz
C
C
f
Clock Frequency for READ instructions
Clock High Time
D.C.
9
MHz
ns
R
1
t
t
CLH
CH
1
t
Clock Low Time
9
ns
t
CL
CLL
2
3
0.1
V/ns
t
Clock Rise Time (peak to peak)
CLCH
2
3
0.1
5
V/ns
ns
t
Clock Fall Time (peak to peak)
CHCL
t
t
t
S Active Setup Time (relative to C)
S Not Active Hold Time (relative to C)
Data In Setup Time
SLCH
CSS
t
5
ns
CHSL
t
2
ns
DVCH
DSU
t
t
Data In Hold Time
5
ns
CHDX
DH
t
S Active Hold Time (relative to C)
S Not Active Setup Time (relative to C)
S Deselect Time
5
ns
CHSH
t
5
ns
SHCH
t
t
CSH
100
ns
SHSL
31/39
M25P32
Test conditions specified in Table 10. and Table 11.
Symbol
Alt.
Parameter
Output Disable Time
Min.
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
2
t
8
8
t
DIS
SHQZ
t
t
V
Clock Low to Output Valid
Output Hold Time
CLQV
t
t
0
5
5
5
5
CLQX
HO
t
HOLD Setup Time (relative to C)
HOLD Hold Time (relative to C)
HOLD Setup Time (relative to C)
HOLD Hold Time (relative to C)
HOLD to Output Low-Z
HLCH
t
CHHH
t
HHCH
t
CHHL
2
t
8
8
t
LZ
HHQX
2
4
4
t
HZ
HOLD to Output High-Z
ns
ns
ns
µs
t
HLQZ
Write Protect Setup Time
Write Protect Hold Time
20
t
t
WHSL
100
SHWL
2
S High to Deep Power-down Mode
3
t
DP
S High to Standby Power mode without
Electronic Signature Read
2
2
30
µs
µs
t
RES1
RES2
S High to Standby Power mode with Electronic
Signature Read
30
t
t
Write Status Register Cycle Time
Page Program Cycle Time
Sector Erase Cycle Time
Bulk Erase Cycle Time
5
1.4
1
15
5
ms
ms
s
W
t
PP
t
SE
3
t
BE
34
80
s
Note: 1. t + t must be greater than or equal to 1/ f (max)
CH
CL
C
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
32/39
M25P32
Figure 24. Serial Input Timing
tSHSL
S
tCHSL
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
D
Q
High Impedance
AI01447C
Figure 25. Write Protect Setup and Hold Timing during WRSR when SRWD=1
W
tSHWL
tWHSL
S
C
D
High Impedance
Q
AI07439
33/39
M25P32
Figure 26. Hold Timing
S
C
tHLCH
tCHHH
tCHHL
tHLQZ
tHHCH
tHHQX
Q
D
HOLD
AI02032
Figure 27. Output Timing
S
tCH
C
tCLQV
tCLQV
tCL
tSHQZ
tCLQX
tCLQX
LSB OUT
Q
D
tQLQH
tQHQL
ADDR.LSB IN
AI01449D
34/39
M25P32
PACKAGE MECHANICAL
Figure 28. MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm, Package Outline
D
E
E2
e
b
D2
A
L
L1
ddd
A1
VDFPN-02
Note: Drawing is not to scale.
Table 15. MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm, Package Mechanical Data
mm
inches
Min.
Symb.
Typ.
Min.
Max.
1.00
0.05
0.48
Typ.
Max.
A
A1
b
0.85
0.0335
0.0394
0.0020
0.0189
0.00
0.35
0.0000
0.0138
0.40
8.00
6.40
0.0157
0.3150
0.2520
D
D2
ddd
E
0.05
–
0.0020
6.00
4.80
1.27
0.2362
0.1890
0.0500
E2
e
–
–
–
K
0.20
0.45
0.0079
0.0177
L
0.50
0.60
0.15
0.0197
0.0236
0.0059
L1
N
8
8
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M25P32
Figure 29. SO16 wide – 16-lead Plastic Small Outline, 300 mils body width, Package Outline
D
h x 45˚
16
9
C
E
H
1
8
θ
A2
A
A1
L
ddd
B
e
SO-H
Note: Drawing is not to scale.
Table 16. SO16 wide – 16-lead Plastic Small Outline, 300 mils body width, Mechanical Data
mm
Min.
2.35
0.10
0.33
0.23
10.10
7.40
–
inches
Min.
Symb.
Typ.
Max.
2.65
0.30
0.51
0.32
10.50
7.60
–
Typ.
Max.
0.104
0.012
0.020
0.013
0.413
0.299
–
A
A1
B
0.093
0.004
0.013
0.009
0.398
0.291
–
C
D
E
e
1.27
0.050
H
10.00
0.25
0.40
0
10.65
0.75
1.27
8
0.394
0.010
0.016
0
0.419
0.030
0.050
8
h
L
q
ddd
0.10
0.004
36/39
M25P32
PART NUMBERING
Table 17. Ordering Information Scheme
Example:
M25P32
–
V
MF
6
T
P
Device Type
M25P = Serial Flash Memory for Code Storage
Device Function
32 = 32Mbit (4M x 8)
Operating Voltage
V = V = 2.7 to 3.6V
CC
Package
MF = SO16 (300 mil width)
ME = VDFPN8 8x6mm (MLP8)
Device Grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
blank = Standard SnPb plating
P = Lead-Free and RoHS compliant
G = Lead-Free, RoHS compliant, Sb O -free and TBBA-free
2
3
For a list of available options (speed, package,
etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Of-
fice.
37/39
M25P32
REVISION HISTORY
Table 18. Document Revision History
Date
Rev.
Description of Revision
28-Apr-2003
15-May-2003
20-Jun-2003
18-Jul-2003
24-Sep-2003
0.1 Target Specification Document written in brief form
0.2 Target Specification Document written in full
0.3 8x6 MLP8 and SO16(300 mil) packages added
t
, t and t revised
PP SE BE
0.4
0.5 SO16 package code changed. Output Timing Reference Voltage changed.
Table of contents, warning about exposed paddle on MLP8, and Pb-free options added.
Value of t
(min) V , t (typ) and t (typ) changed. Change of naming for VDFPN8
04-Dec-2003
0.6
VSL
WI PP BE
package.
10-Dec-2003
01-Apr-2004
05-Aug-2004
01-Oct-2004
1.0 Document promoted to Product Preview
Document promoted to Preliminary Data. Soldering temperature information clarified for RoHS
compliant devices. Device grade information clarified
2.0
3.0 Device grade information further clarified
Document promoted to mature datasheet. Footnotes removed from P and G options in
Ordering Information table. Minor wording improvements made.
4.0
38/39
M25P32
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
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39/39
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M25P32-VMN6G
4M X 8 FLASH 2.7V PROM, PDSO8, 0.150 INCH, ANTIMONY, TBBP-A FREE AND ROHS COMPLIANT, SOP-8
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