M24256-BRBN6 [STMICROELECTRONICS]
256Kbit and 128Kbit Serial I2C Bus EEPROM With Three Chip Enable Lines; 256Kbit和128Kbit的串行I2C总线的EEPROM采用三片选线
| 型号： | M24256-BRBN6 |
| 厂家： | 
ST |
| 描述： | 256Kbit and 128Kbit Serial I2C Bus EEPROM With Three Chip Enable Lines |
| 文件： | 总25页 (文件大小：456K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M24128-BW, M24128-BR
M24256-BW, M24256-BR
256Kbit and 128Kbit Serial I²C Bus EEPROM
With Three Chip Enable Lines
FEATURES SUMMARY
■
Compatible with I2C Extended Addressing
Figure 1. Packages
■
Two-Wire I2C Serial Interface
Supports 400kHz Protocol
■
Single Supply Voltage:
–
–
2.5 to 5.5V for M24128-BW, M24256-BW
1.8 to 5.5V for M24128-BR, M24256-BR
■
■
■
■
■
■
■
■
Hardware Write Control
BYTE and PAGE WRITE (up to 64 Bytes)
RANDOM and SEQUENTIAL READ Modes
Self-Timed Programming Cycle
Automatic Address Incrementing
Enhanced ESD/Latch-Up Protection
More than 1 Million Erase/Write Cycles
More than 40-Year Data Retention
8
1
PDIP8 (BN)
Table 1. Product List
Reference
8
Part Number
M24128-BW
1
128 Kbits
256 Kbits
M24128-BR
M24256-BW
M24256-BR
SO8 (MN)
150 mil width
8
1
SO8 (MW)
200 mil width
TSSOP8 (DW)
169 mil width
June 2005
1/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Power On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. DIP, SO and TSSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Clock (SCL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. Maximum RP Value versus Bus Parasitic Capacitance (C) for an I2C Bus . . . . . . . . . . . 5
Figure 5. I2C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Most Significant Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 5. Least Significant Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DEVICE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Stop Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 6. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Write Mode Sequences with WC=1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Write Mode Sequences with WC=0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. Write Cycle Polling Flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Minimizing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Read Mode Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Random Address Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Acknowledge in Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 7. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. Operating Conditions (M24128-BW, M24256-BW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 9. Operating Conditions (M24128-BR, M24256-BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 10. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 11. Input Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 12. DC Characteristics (M24128-BW, M24256-BW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 13. DC Characteristics (M24128-BR, M24256-BR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 14. AC Characteristics ( M24128-BW, M24256-BW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 15. AC Characteristics (M24128-BR, M24256-BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11.AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 19
Table 16. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 19
Figure 13.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 20
Table 17. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
20
Figure 14.SO8 wide – 8 lead Plastic Small Outline, 200 mils body width, Package Outline . . . . . . 21
Table 18. SO8 wide – 8 lead Plastic Small Outline, 200 mils body width, Package Mechanical Data
21
Figure 15.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 22
Table 19. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 22
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 20. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 21. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
ter. The Start condition is followed by a Device
SUMMARY DESCRIPTION
Select Code and Read/Write bit (RW) (as de-
scribed in Table 3.), terminated by an acknowl-
edge bit.
These I2C-compatible electrically erasable pro-
grammable memory (EEPROM) devices are orga-
nized as 32K x 8 bits (M24256-BW and M24256-
BR) and 16K x 8 bits (M24128-BW and M24128-
BR).
When writing data to the memory, the device in-
serts an acknowledge bit during the 9th bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Figure 2. Logic Diagram
V
CC
Power On Reset
In order to prevent inadvertent Write operations
during Power Up, a Power On Reset (POR) circuit
is implemented.
3
E0-E2
SCL
WC
SDA
At Power Up, the device will not respond to any in-
struction until VCC has reached the POR threshold
voltage (this threshold is lower than the VCC mini-
mum operating voltage defined in Table 8. and Ta-
ble 9.). In the same way, as soon as VCC drops
from the normal operating voltage, below the POR
threshold voltage, all the operations are disabled
and the device will not respond to any instruction.
Prior to selecting and issuing instructions to the
memory, a valid and stable VCC voltage must be
applied. This voltage must remain stable and valid
until the end of the transmission of the instruction
and, for a Write instruction, until the completion of
the internal write cycle (tW).
M24256-B
M24128-B
V
SS
AI02809
Table 2. Signal Names
E0, E1, E2
SDA
Chip Enable
Figure 3. DIP, SO and TSSOP Connections
Serial Data
Serial Clock
Write Control
Supply Voltage
Ground
SCL
M24256-B
M24128-B
WC
E0
E1
E2
1
2
3
4
8
V
CC
WC
V
V
CC
SS
7
6
5
SCL
SDA
I2C uses a two-wire serial interface, comprising a
bi-directional data line and a clock line. The devic-
es carry a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I2C bus definition.
V
SS
AI02810B
The device behaves as a slave in the I2C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are initiat-
ed by a Start condition, generated by the bus mas-
Note: See PACKAGE MECHANICAL section for package dimen-
sions, and how to identify pin-1.
4/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
SIGNAL DESCRIPTION
Serial Clock (SCL). This input signal is used to
strobe all data in and out of the device. In applica-
tions where this signal is used by slave devices to
synchronize the bus to a slower clock, the bus
master must have an open drain output, and a
pull-up resistor must be connected from Serial
Clock (SCL) to VCC. (Figure 4. indicates how the
value of the pull-up resistor can be calculated). In
most applications, though, this method of synchro-
nization is not employed, and so the pull-up resis-
tor is not necessary, provided that the bus master
has a push-pull (rather than open drain) output.
Serial Data (SDA). This bi-directional signal is
used to transfer data in or out of the device. It is an
open drain output that may be wire-OR’ed with
other open drain or open collector signals on the
bus. A pull up resistor must be connected from Se-
rial Data (SDA) to VCC. (Figure 4. indicates how
the value of the pull-up resistor can be calculated).
Chip Enable (E0, E1, E2). These input signals
are used to set the value that is to be looked for on
the three least significant bits (b3, b2, b1) of the 7-
bit Device Select Code. These inputs must be tied
to VCC or VSS, to establish the Device Select
Code. When not connected (left floating), these in-
puts are read as Low (0,0,0).
Write Control (WC). This input signal is useful
for protecting the entire contents of the memory
from inadvertent write operations. Write opera-
tions are disabled to the entire memory array when
Write Control (WC) is driven High. When uncon-
nected, the signal is internally read as VIL, and
Write operations are allowed.
When Write Control (WC) is driven High, Device
Select and Address bytes are acknowledged,
Data bytes are not acknowledged.
Figure 4. Maximum RP Value versus Bus Parasitic Capacitance (C) for an I2C Bus
V
CC
20
16
RP
RP
12
8
SDA
SCL
MASTER
C
fc = 100kHz
4
0
fc = 400kHz
C
10
100
C (pF)
1000
AI01665b
5/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
Figure 5. I2C Bus Protocol
SCL
SDA
SDA
Input
SDA
Change
START
Condition
STOP
Condition
1
2
3
7
8
9
SCL
SDA
ACK
MSB
START
Condition
1
2
3
7
8
9
SCL
SDA
MSB
ACK
STOP
Condition
AI00792B
Table 3. Device Select Code
1
2
RW
b0
Device Type Identifier
Chip Enable Address
b7
b6
0
b5
1
b4
0
b3
E2
b2
b1
Device Select Code
1
E1
E0
RW
Note: 1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
Table 4. Most Significant Byte
Table 5. Least Significant Byte
b15
b14
b13 b12 b11
b10 b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
6/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
DEVICE OPERATION
The device supports the I2C protocol. This is sum-
marized in Figure 5.. Any device that sends data
on to the bus is defined to be a transmitter, and
any device that reads the data to be a receiver.
The device that controls the data transfer is known
as the bus master, and the other as the slave de-
vice. A data transfer can only be initiated by the
bus master, which will also provide the serial clock
for synchronization. The M24xxx-B device is al-
ways a slave in all communication.
Data (SDA) Low to acknowledge the receipt of the
eight data bits.
Data Input
During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change only when Serial Clock (SCL) is driv-
en Low.
Start Condition
Memory Addressing
Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The device continuously
monitors (except during a Write cycle) Serial Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is given.
To start communication between the bus master
and the slave device, the bus master must initiate
a Start condition. Following this, the bus master
sends the Device Select Code, shown in Table 3.
(on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device
Type Identifier, and a 3-bit Chip Enable “Address”
(E2, E1, E0). To address the memory array, the 4-
bit Device Type Identifier is 1010b.
Up to eight memory devices can be connected on
a single I2C bus. Each one is given a unique 3-bit
code on the Chip Enable (E0, E1, E2) inputs.
When the Device Select Code is received, the de-
vice only responds if the Chip Enable Address is
the same as the value on the Chip Enable (E0, E1,
E2) inputs.
The 8th bit is the Read/Write bit (RW). This bit is
set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code, the
corresponding device gives an acknowledgment
on Serial Data (SDA) during the 9th bit time. If the
device does not match the Device Select code, it
deselects itself from the bus, and goes into Stand-
by mode.
Stop Condition
Stop is identified by a rising edge of Serial Data
(SDA) while Serial Clock (SCL) is stable and driv-
en High. A Stop condition terminates communica-
tion between the device and the bus master. A
Read command that is followed by NoAck can be
followed by a Stop condition to force the device
into the Stand-by mode. A Stop condition at the
end of a Write command triggers the internal EE-
PROM Write cycle.
Acknowledge Bit (ACK)
The acknowledge bit is used to indicate a success-
ful byte transfer. The bus transmitter, whether it be
bus master or slave device, releases Serial Data
(SDA) after sending eight bits of data. During the
9th clock pulse period, the receiver pulls Serial
Table 6. Operating Modes
1
Mode
RW bit
Bytes
Initial Sequence
WC
X
Current Address Read
1
0
1
1
0
0
1
START, Device Select, RW = 1
X
START, Device Select, RW = 0, Address
reSTART, Device Select, RW = 1
Similar to Current or Random Address Read
START, Device Select, RW = 0
Random Address Read
1
X
Sequential Read
Byte Write
X
≥ 1
1
VIL
VIL
Page Write
≤ 64
START, Device Select, RW = 0
Note: 1. X = VIH or VIL.
7/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
Figure 6. Write Mode Sequences with WC=1 (data write inhibited)
WC
ACK
ACK
ACK
NO ACK
DATA IN
BYTE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
R/W
WC
ACK
ACK
ACK
NO ACK
DATA IN 1 DATA IN 2
PAGE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
R/W
WC (cont'd)
NO ACK
NO ACK
PAGE WRITE
(cont'd)
DATA IN N
AI01120C
Write Operations
When the bus master generates a Stop condition
immediately after the Ack bit (in the “10th bit” time
slot), either at the end of a Byte Write or a Page
Write, the internal memory Write cycle is triggered.
A Stop condition at any other time slot does not
trigger the internal Write cycle.
After the Stop condition, the delay tW, and the suc-
cessful completion of a Write operation, the de-
vice’s internal address counter is incremented
automatically, to point to the next byte address af-
ter the last one that was modified.
Following a Start condition the bus master sends
a Device Select Code with the R/W bit (RW) reset
to 0. The device acknowledges this, as shown in
Figure 7., and waits for two address bytes. The de-
vice responds to each address byte with an ac-
knowledge bit, and then waits for the data byte.
Writing to the memory may be inhibited if Write
Control (WC) is driven High. Any Write instruction
with Write Control (WC) driven High (during a pe-
riod of time from the Start condition until the end of
the two address bytes) will not modify the memory
contents, and the accompanying data bytes are
not acknowledged, as shown in Figure 6..
During the internal Write cycle, Serial Data (SDA)
is disabled internally, and the device does not re-
spond to any requests.
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte (Ta-
ble 4.) is sent first, followed by the Least Signifi-
cant Byte (Table 5.). Bits b15 to b0 form the
address of the byte in memory.
Byte Write
After the Device Select code and the address
bytes, the bus master sends one data byte. If the
addressed location is Write-protected, by Write
Control (WC) being driven High, the device replies
8/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
with NoAck, and the location is not modified. If, in-
data starts to become overwritten in an implemen-
tation dependent way.
stead, the addressed location is not Write-protect-
ed, the device replies with Ack. The bus master
terminates the transfer by generating a Stop con-
dition, as shown in Figure 7..
The bus master sends from 1 to 64 bytes of data,
each of which is acknowledged by the device if
Write Control (WC) is Low. If Write Control (WC) is
High, the contents of the addressed memory loca-
tion are not modified, and each data byte is fol-
lowed by a NoAck. After each byte is transferred,
the internal byte address counter (the 6 least sig-
nificant address bits only) is incremented. The
transfer is terminated by the bus master generat-
ing a Stop condition.
Page Write
The Page Write mode allows up to 64 bytes to be
written in a single Write cycle, provided that they
are all located in the same ’row’ in the memory:
that is, the most significant memory address bits,
b15-b6, are the same. If more bytes are sent than
will fit up to the end of the row, a condition known
as ‘roll-over’ occurs. This should be avoided, as
Figure 7. Write Mode Sequences with WC=0 (data write enabled)
WC
ACK
ACK
ACK
ACK
BYTE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN
R/W
WC
ACK
ACK
ACK
ACK
PAGE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN 1
DATA IN 2
R/W
WC (cont'd)
ACK
ACK
PAGE WRITE
(cont'd)
DATA IN N
AI01106C
9/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
Figure 8. Write Cycle Polling Flowchart using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
NO
First byte of instruction
with RW = 0 already
decoded by the device
YES
Next
Operation is
Addressing the
Memory
NO
YES
Send Address
and Receive ACK
ReSTART
START
NO
YES
STOP
Condition
DATA for the
WRITE Operation
DEVICE SELECT
with RW = 1
Continue the
Continue the
Random READ Operation
WRITE Operation
AI01847C
Minimizing System Delays by Polling On ACK
–
–
Initial condition: a Write cycle is in progress.
During the internal Write cycle, the device discon-
nects itself from the bus, and writes a copy of the
data from its internal latches to the memory cells.
Step 1: the bus master issues a Start condition
followed by a Device Select Code (the first
byte of the new instruction).
The maximum Write time (t ) is shown in Table
w
–
Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the
bus master goes back to Step 1. If the device
has terminated the internal Write cycle, it
responds with an Ack, indicating that the
device is ready to receive the second part of
the instruction (the first byte of this instruction
having been sent during Step 1).
14. and Table 15., but the typical time is shorter.
To make use of this, a polling sequence can be
used by the bus master.
The sequence, as shown in Figure 8., is:
10/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
Figure 9. Read Mode Sequences
ACK
NO ACK
CURRENT
ADDRESS
READ
DEV SEL
DATA OUT
R/W
ACK
ACK
ACK
ACK
NO ACK
DATA OUT
RANDOM
ADDRESS
READ
DEV SEL *
BYTE ADDR
BYTE ADDR
DEV SEL *
R/W
R/W
ACK
ACK
ACK
NO ACK
SEQUENTIAL
CURRENT
READ
DEV SEL
DATA OUT 1
DATA OUT N
R/W
ACK
ACK
ACK
ACK
ACK
SEQUENTIAL
RANDOM
READ
DEV SEL *
BYTE ADDR
BYTE ADDR
DEV SEL * DATA OUT 1
R/W
R/W
ACK
NO ACK
DATA OUT N
AI01105C
st
th
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1 and 4 bytes) must be identical.
Read Operations
Read operations are performed independently of
the state of the Write Control (WC) signal.
puts the contents of the addressed byte. The bus
master must not acknowledge the byte, and termi-
nates the transfer with a Stop condition.
Current Address Read
After the successful completion of a Read opera-
tion, the device’s internal address counter is incre-
mented by one, to point to the next byte address.
For the Current Address Read operation, following
a Start condition, the bus master only sends a De-
vice Select Code with the R/W bit set to 1. The de-
vice acknowledges this, and outputs the byte
addressed by the internal address counter. The
counter is then incremented. The bus master ter-
minates the transfer with a Stop condition, as
shown in Figure 9., without acknowledging the
byte.
Random Address Read
A dummy Write is first performed to load the ad-
dress into this address counter (as shown in Fig-
ure 9.) but without sending a Stop condition. Then,
the bus master sends another Start condition, and
repeats the Device Select Code, with the RW bit
set to 1. The device acknowledges this, and out-
11/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
Sequential Read
Acknowledge in Read Mode
This operation can be used after a Current Ad-
dress Read or a Random Address Read. The bus
master does acknowledge the data byte output,
and sends additional clock pulses so that the de-
vice continues to output the next byte in sequence.
To terminate the stream of bytes, the bus master
must not acknowledge the last byte, and must
generate a Stop condition, as shown in Figure 9..
For all Read commands, the device waits, after
each byte read, for an acknowledgment during the
9th bit time. If the bus master does not drive Serial
Data (SDA) Low during this time, the device termi-
nates the data transfer and switches to its Stand-
by mode.
The output data comes from consecutive address-
es, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’,
and the device continues to output data from
memory address 00h.
INITIAL DELIVERY STATE
The device is delivered with all the memory array
bits set to 1 (each byte contains FFh).
12/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
MAXIMUM RATING
Stressing the device outside the ratings listed in
Table 7. may cause permanent damage to the de-
vice. These are stress ratings only, and operation
of the device at these, or any other conditions out-
side those indicated in the Operating sections of
this specification, is not implied. Exposure to Ab-
solute Maximum Rating conditions for extended
periods may affect device reliability. Refer also to
the STMicroelectronics SURE Program and other
relevant quality documents.
Table 7. Absolute Maximum Ratings
Symbol
Parameter
Ambient Operating Temperature
Min.
–40
–65
Max.
Unit
°C
°C
°C
V
T
A
125
T
Storage Temperature
150
STG
1
T
Lead Temperature during Soldering
Input or Output range
Supply Voltage
LEAD
See note
V
IO
–0.50
–0.50
–3000
6.5
6.5
V
V
CC
2
V
ESD
3000
V
Electrostatic Discharge Voltage (Human Body model)
®
Note: 1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK 7191395 specification, and
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω)
13/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 8. Operating Conditions (M24128-BW, M24256-BW)
Symbol
Parameter
Min.
2.5
Max.
5.5
Unit
V
V
Supply Voltage
Ambient Operating Temperature
CC
TA
–40
85
°C
Table 9. Operating Conditions (M24128-BR, M24256-BR)
Symbol
Parameter
Min.
1.8
Max.
5.5
Unit
V
V
Supply Voltage
Ambient Operating Temperature
CC
TA
–40
85
°C
Table 10. AC Measurement Conditions
Symbol
Parameter
Min.
Max.
Unit
pF
ns
V
C
Load Capacitance
100
L
Input Rise and Fall Times
Input Levels
50
0.2V to 0.8V
CC
CC
CC
0.3V to 0.7V
Input and Output Timing Reference Levels
V
CC
Figure 10. AC Measurement I/O Waveform
Input Levels
Input and Output
Timing Reference Levels
0.8V
CC
0.7V
CC
0.3V
CC
0.2V
CC
AI00825B
14/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
Table 11. Input Parameters
1,2
Symbol
CIN
Test Condition
Min.
Max.
Unit
pF
Parameter
Input Capacitance (SDA)
8
6
CIN
Input Capacitance (other pins)
pF
VIN < 0.3 V
ZL
30
kΩ
kΩ
CC
Input Impedance (WC)
VIN > 0.7V
ZH
500
CC
Pulse width ignored
(Input Filter on SCL and SDA)
tNS
Single glitch
100
ns
Note: 1. T = 25°C, f = 400kHz
A
2. Sampled only, not 100% tested.
Table 12. DC Characteristics (M24128-BW, M24256-BW)
Test Condition
(in addition to those in Table 8.)
Symbol
Parameter
Min.
Max.
Unit
Input Leakage Current
(SCL, SDA)
VIN = VSS or VCC
device in Stand-by mode
ILI
± 2
µA
ILO
Output Leakage Current
V
OUT = VSS or VCC, SDA in Hi-Z
± 2
µA
mA
mA
µA
µA
V
VCC =2.5V, f =400kHz (rise/fall time < 30ns)
1
c
ICC
Supply Current
VCC = 5V, f =400kHz (rise/fall time < 30ns)
2
2
c
V
IN = VSS or VCC , VCC = 2.5V
IN = VSS or VCC , VCC = 5V
ICC1
Stand-by Supply Current
V
10
VIL
VIH
VOL
Input Low Voltage (SCL, SDA)
–0.45
0.3VCC
Input High Voltage
(SCL, SDA, WC)
0.7VCC
VCC+1
0.4
V
V
Output Low Voltage
IOL = 2.1 mA, VCC = 2.5 V
Table 13. DC Characteristics (M24128-BR, M24256-BR)
Test Condition
(in addition to those in Table 9.)
Symbol
Parameter
Min.
Max.
Unit
Input Leakage Current
(SCL, SDA)
VIN = VSS or VCC
device in Stand-by mode
ILI
± 2
µA
ILO
ICC
Output Leakage Current
Supply Current
V
OUT = VSS or VCC, SDA in Hi-Z
± 2
0.8
µA
mA
µA
V
V
CC =1.8V, f =100kHz (rise/fall time < 30ns)
c
ICC1
Stand-by Supply Current
Input Low Voltage (SCL, SDA)
V
IN = VSS or VCC , VCC = 1.8 V
1
–0.45
–0.45
0.3 VCC
VIL
Input Low Voltage
(E2, E1, E0, WC)
0.5
V
Input High Voltage
(E2, E1, E0, SCL, SDA, WC)
VIH
0.7VCC
VCC+1
0.2
V
V
VOL
Output Low Voltage
IOL = 0.7 mA, VCC = 1.8 V
15/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
Table 14. AC Characteristics ( M24128-BW, M24256-BW)
Test conditions specified in Table 8.
Parameter
Symbol
fC
Alt.
fSCL
tHIGH
tLOW
tR
Min.
Max.
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Frequency
400
tCHCL
Clock Pulse Width High
Clock Pulse Width Low
Clock Rise Time
600
tCLCH
1300
tCH1CH2
tCL1CL2
300
300
300
300
tF
Clock Fall Time
2
tR
SDA Rise Time
20
20
tDH1DH2
2
tF
SDA Fall Time
tDL1DL2
tDXCX
tCLDX
tCLQX
tSU:DAT
tHD:DAT
tDH
Data In Set Up Time
100
0
Data In Hold Time
Data Out Hold Time
200
200
600
600
600
3
tAA
Clock Low to Next Data Valid (Access Time)
Start Condition Set Up Time
Start Condition Hold Time
Stop Condition Set Up Time
900
tCLQV
1
tSU:STA
tHD:STA
tSU:STO
tCHDX
tDLCL
tCHDH
Time between Stop Condition and Next Start
Condition
tDHDL
tW
tBUF
tWR
1300
ns
Write Time
5
ms
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
16/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
Table 15. AC Characteristics (M24128-BR, M24256-BR)
Test conditions specified in Table 9.
Parameter
Symbol
fC
Alt.
fSCL
tHIGH
tLOW
tR
Min.
Max.
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Frequency
400
tCHCL
Clock Pulse Width High
Clock Pulse Width Low
Clock Rise Time
600
tCLCH
1300
tCH1CH2
tCL1CL2
300
300
300
300
tF
Clock Fall Time
2
tR
SDA Rise Time
20
20
tDH1DH2
2
tF
SDA Fall Time
tDL1DL2
tDXCX
tCLDX
tCLQX
tSU:DAT
tHD:DAT
tDH
Data In Set Up Time
100
0
Data In Hold Time
Data Out Hold Time
200
200
600
600
600
3
tAA
Clock Low to Next Data Valid (Access Time)
Start Condition Set Up Time
Start Condition Hold Time
Stop Condition Set Up Time
900
tCLQV
1
tSU:STA
tHD:STA
tSU:STO
tCHDX
tDLCL
tCHDH
Time between Stop Condition and Next Start
Condition
tDHDL
tW
tBUF
tWR
1300
ns
Write Time
10
ms
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
17/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
Figure 11. AC Waveforms
tCHCL
tCLCH
SCL
tDLCL
SDA In
tCHDX
tCLDX
tDXCX
SDA
tCHDH tDHDL
Change
START
Condition
START
Condition
SDA
Input
STOP
Condition
SCL
SDA In
tCHDH
tCHDX
START
Condition
tW
Write Cycle
STOP
Condition
SCL
tCLQV
tCLQX
Data Valid
SDA Out
AI00795C
18/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
PACKAGE MECHANICAL
Figure 12. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline
E
b2
A2
A1
A
L
c
b
e
eA
eB
D
8
1
E1
PDIP-B
Note: Drawing is not to scale.
Table 16. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
mm
inches
Min.
Symb.
Typ.
Min.
Max.
Typ.
Max.
A
A1
A2
b
5.33
0.210
0.38
2.92
0.36
1.14
0.20
9.02
7.62
6.10
–
0.015
0.115
0.014
0.045
0.008
0.355
0.300
0.240
–
3.30
0.46
1.52
0.25
9.27
7.87
6.35
2.54
7.62
4.95
0.56
1.78
0.36
10.16
8.26
7.11
–
0.130
0.018
0.060
0.010
0.365
0.310
0.250
0.100
0.300
0.195
0.022
0.070
0.014
0.400
0.325
0.280
–
b2
c
D
E
E1
e
eA
eB
L
–
–
–
–
10.92
3.81
0.430
0.150
3.30
2.92
0.130
0.115
19/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
Figure 13. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline
h x 45˚
A
C
B
CP
e
D
N
E
H
1
A1
α
L
SO-a
Note: Drawing is not to scale.
Table 17. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
mm
Min.
1.35
0.10
0.33
0.19
4.80
3.80
–
inches
Min.
0.053
0.004
0.013
0.007
0.189
0.150
–
Symb.
Typ.
Max.
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ.
Max.
0.069
0.010
0.020
0.010
0.197
0.157
–
A
A1
B
C
D
E
e
1.27
0.050
H
h
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
L
α
N
CP
8
8
0.10
0.004
20/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
Figure 14. SO8 wide – 8 lead Plastic Small Outline, 200 mils body width, Package Outline
A2
A
C
B
CP
e
D
N
1
E
H
A1
α
L
SO-b
Note: Drawing is not to scale.
Table 18. SO8 wide – 8 lead Plastic Small Outline, 200 mils body width, Package Mechanical Data
mm
inches
Min.
Symb.
Typ.
Min.
Max.
2.03
0.25
1.78
0.45
–
Typ.
Max.
0.080
0.010
0.070
0.018
–
A
A1
A2
B
0.10
0.004
0.35
–
0.014
–
C
0.20
1.27
0.008
0.050
D
5.15
5.20
–
5.35
5.40
–
0.203
0.205
–
0.211
0.213
–
E
e
H
7.70
0.50
0°
8.10
0.80
10°
0.303
0.020
0°
0.319
0.031
10°
L
α
N
8
8
CP
0.10
0.004
21/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
Figure 15. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline
D
8
5
c
E1
E
1
4
α
A1
L
A
A2
L1
CP
b
e
TSSOP8AM
Note: Drawing is not to scale.
Table 19. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data
mm
inches
Min.
Symbol
Typ.
Min.
Max.
1.200
0.150
1.050
0.300
0.200
0.100
3.100
–
Typ.
Max.
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.1220
–
A
A1
A2
b
0.050
0.800
0.190
0.090
0.0020
0.0315
0.0075
0.0035
1.000
0.0394
c
CP
D
3.000
0.650
6.400
4.400
0.600
1.000
2.900
–
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
0.1142
–
e
E
6.200
4.300
0.450
6.600
4.500
0.750
0.2441
0.1693
0.0177
0.2598
0.1772
0.0295
E1
L
L1
α
0°
8°
0°
8°
22/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
PART NUMBERING
Table 20. Ordering Information Scheme
Example:
M24256
–
B
W MN
6
T
P
Device Type
2
M24 = I C serial access EEPROM
Device Function
256 = 256 Kbit (32K x 8)
128 = 128 Kbit (16K x 8)
Operating Voltage
3
W = V = 2.5 to 5.5V
CC
1
R = V = 1.8 to 5.5V
CC
Package
BN = PDIP8
MN = SO8 (150 mil width)
MW = SO8 (200 mil width)
DW = TSSOP8 (169 mil width)
Device Grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
blank = Standard SnPb plating
P or G = Lead-Free and RoHS compliant
For a list of available options (speed, package, etc.) or for further information on any aspect of this device,
please contact your nearest ST Sales Office.
23/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
REVISION HISTORY
Table 21. Document Revision History
Date
Rev.
Description of Revision
28-Dec-1999
2.1 TSSOP8 package added
E2, E1, E0 must be tied to Vcc or Vss
Low Pass Filter Time Constant changed to Glitch Filter
24-Feb-2000
22-Nov-2000
2.2
2.3 -V voltage range added
-V voltage range changed to 2.5V to 3.6V
Lead Soldering Temperature in the Absolute Maximum Ratings table amended
Write Cycle Polling Flow Chart using ACK illustration updated. SO8(wide) package added
References to PSDIP8 changed to PDIP8, and Package Mechanical data updated
30-Jan-2001
01-Jun-2001
2.4
-R voltage range added. Package mechanical data updated for TSSOP8 and TSSOP14
2.5 packages according to JEDEC\MO-153
Document promoted from “Preliminary Data” to “Full Data Sheet”
TSSOP14 package removed
Absolute Max Ratings and DC characteristics updated for M24256-BV
16-Oct-2001
09-Nov-2001
21-Mar-2002
2.6
2.7 Specification of Test Condition for Leakage Currents in the DC Characteristics table improved
1 million Erase/Write cycle endurance for M24256-B and M24256-BW products with process
letter "V"
2.8
Document reformatted. Parameters changed are: 1 million Erase/Write cycle endurance and 5
ms write time for M24128-B and M24128-BW products with process letter "B".
18-Oct-2002
20-Nov-2002
02-Jun-2003
3.0
Superfluous (and incorrectly present) 100kHz AC Characteristics table for M24256-BR
removed.
3.1
Initial delivery state specified. -R and -S ranges are no longer Preliminary Data. Package
mechanical data for unavailable package removed.
3.2
Table of contents, and Pb-free options added. Minor wording changes in Summary
Description, Power-On Reset, Memory Addressing, Write Operations, Read Operations.
V (min) improved to -0.45V.
22-Oct-2003
16-Apr-2004
4.0
5.0
IL
SO8W package added. Absolute Maximum Ratings for V (min) and V (min) changed.
IO
CC
Soldering temperature information clarified for RoHS compliant devices.
M24xxx-B, M24xxx-BV and M24xxx-BS removed from the datasheet.
Product List summary table added.
Power On Reset paragraph updated.
Figure 4., Maximum RP Value versus Bus Parasitic Capacitance (C) for an I2C Bus updated.
13-Jun-2005
6.0
Z and Z definition changed.
L
H
I
and I
updated in Table 12., DC Characteristics (M24128-BW, M24256-BW).
CC
CC1
Device Grade information further clarified to Table 20., Ordering Information Scheme.
24/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
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SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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