LD49150XX10 [STMICROELECTRONICS]
1.5 A very low drop for low output voltage regulator; 1.5一个非常低的压降为低输出电压稳压器
| 型号： | LD49150XX10 |
| 厂家： | 
ST |
| 描述： | 1.5 A very low drop for low output voltage regulator |
| 文件： | 总22页 (文件大小：710K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LD49150XX08
LD49150XX10, LD49150XX12
1.5 A very low drop for low output voltage regulator
Features
■ Input voltage range:
– V = 1.4 V to 5.5 V
I
– V
= 3 V to 6 V
BIAS
■ Stable with ceramic capacitor
1.5 ꢀ initial tolerance
■ Maximum dropout voltage (V - V ) of 200 mV
■
I
O
DFN6 (3x3 mm)
PPAK
over temperature
■ Adjustable output voltage down to 0.8 V
■ Ultra fast transient response (up to 10 MHz
Description
bandwidth)
The LD49150xx is a high-bandwidth, low-dropout,
1.5 A voltage regulator, ideal for powering core
voltages of low-power microprocessors. The
LD49150xx implements a dual supply
■ Excellent line and load regulation
specifications
■ Logic controlled shutdown option
■ Thermal shutdown and current limit protection
■ Junction temperature range: - 25 °C to 125 °C
configuration allowing for very low output
impedance and very fast transient response. The
LD49150xx requires a bias input supply and a
main input supply, allowing for ultra-low input
voltages on the main supply rail. The input supply
operates from 1.4 V to 5.5 V and the bias supply
requires between 3 V and 6 V for proper
operation. The LD49150xx offers fixed output
voltages from 0.8 V to 1.8 V and adjustable output
voltages down to 0.8 V. The LD49150xx requires a
minimum output capacitance for stability, and
work optimally with small ceramic capacitors.
Applications
■ Graphics processors
■ PC add-in cards
■ Microprocessor core voltage supply
■ Low voltage digital ICs
■ High efficiency linear power supplies
■ SMPS post regulators
Table 1.
Device summary
Order codes
Output voltages
PPAK (tape and reel)
DFN6 (tape and reel) (1)
LD49150PT08R
LD49150PT10R
LD49150PT12R
0.8 V (2)
1.0 V
LD49150PU10R
LD49150PU12R
1.2 V
1. Available on request.
2. Adjustable version.
June 2010
Doc ID 13446 Rev 3
1/22
www.st.com
22
Contents
LD49150XX08, LD49150XX10, LD49150XX12
Contents
1
2
3
4
5
6
7
8
Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Alternative application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
Input supply voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bias supply voltage (VBIAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Minimum load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power sequencing recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power dissipation/heatsinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Heatsinking PPAK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Adjustable regulator design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.10 Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9
10
2/22
Doc ID 13446 Rev 3
LD49150XX08, LD49150XX10, LD49150XX12
Typical application circuits
1
Typical application circuits
Figure 1.
Adjustable version
Figure 2.
Fixed version with Enable
Doc ID 13446 Rev 3
3/22
Alternative application circuits
LD49150XX08, LD49150XX10, LD49150XX12
2
Alternative application circuits
Figure 3.
Single supply voltage solution
Figure 4.
LD49150xx plus DC-DC pre-regulator to reduce power dissipation
4/22
Doc ID 13446 Rev 3
LD49150XX08, LD49150XX10, LD49150XX12
Pin configuration
3
Pin configuration
Figure 5.
Pin connections (top view for PPAK, bottom view for DFN)
PPAK
DFN6 (3 x 3 mm)
Pin description
Table 2.
Pin n° for Pin n° for
Symbol
Note
PPAK
DFN
For fixed versions: Enable (Input) - Logic High = Enable, Logic Low =
Shutdown.
EN
1
2
For adjustable versions: Adjustable regulator feedback input. Connect to
resistor voltage divider.
ADJ
2
3
4
3
1
4
VIN
Input voltage which supplies current to the output power device.
Ground (TAB is connected to ground).
Regulator output.
GND
VOUT
Input bias voltage for powering all circuitry on the regulator with the
exception of the output power device.
5
6
5
VBIAS
N.C.
Not connect.
Doc ID 13446 Rev 3
5/22
Diagram
4
LD49150XX08, LD49150XX10, LD49150XX12
Diagram
Figure 6.
Block diagram
6/22
Doc ID 13446 Rev 3
LD49150XX08, LD49150XX10, LD49150XX12
Maximum ratings
5
Maximum ratings
(1)
Table 3.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
VIN
Supply voltage
Output voltage
-0.3 to 7
V
-0.3 to VIN + 0.3
-0.3 to VBIAS + 0.3
VOUT
V
VBIAS
VEN
PD
BIAS supply voltage
Enable input voltage
Power dissipation
-0.3 to 7
-0.3 to 7
V
V
Internally limited
-50 to 150
TSTG
Storage temperature range
°C
1. All the values are referred to ground.
Note:
Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied.
Table 4.
Operating ratings
Symbol
Parameter
Value
Unit
VIN
VOUT
VBIAS
VEN
TJ
Supply voltage
1.4 to 5.5
0.8 to 4.5
3 to 6
V
V
Output voltage
BIAS supply voltage
Enable input voltage
V
0 to VBIAS
-25 to 125
V
Junction temperature range
°C
Doc ID 13446 Rev 3
7/22
Electrical characteristics
LD49150XX08, LD49150XX10, LD49150XX12
6
Electrical characteristics
(1)
(2)
T = - 25 °C to 125 °C, V
= V + 2.1 V ; V = V +1 V; V = V
, I = 10 mA; C =
J
BIAS
O
I
O
EN
BIAS
O
I
1 µF; C = 10 µF; C
= 1 µF; unless otherwise specified.
O
BIAS
Typical values are referred to T = 25 °C.
J
Table 5.
Symbol
Electrical characteristics
Parameter
Test conditions
Min.
Typ.
Max. Unit
TJ = 25 °C, fixed voltage options
Over temperature range
VI = VO + 1 V to 5.5 V
IL = 0 mA to 3 A, VBIAS ≥ 3 V
IL = 1.5 A
-1.5
-3
1.5
ꢀ
3
VO
Output voltage accuracy
VLINE
VLOAD
VDROP
VDROP
Line regulation
-0.1
0.1
1
ꢀ/V
ꢀ
Load regulation
Dropout voltage (VI - VO)
Dropout voltage (VBIAS- VO)
200
2.1
6
mV
V
IL = 1.5 A (1)
1.5
4
IL = 0 mA
IGND
Ground pin current
mA
µA
mA
A
IL = 1.5 A
4
6
IGND_SHD Ground pin current in shutdown VEN ≤ 0.4 V (2)
5
IL = 0 mA
3
3
5
IVBIAS
Current through VBIAS
IL = 1.5 A
VO = 0 V
5
IL
Current limit
2.5
1.4
Enable input (2)
Regulator Enable
Enable input threshold (fixed
voltage only)
VEN
V
Regulator Shutdown
0.4
1
IEN
Enable pin input current
0.1
µA
Reference
TJ = 25 °C
0.788
0.776
0.8
0.8
0.812
0.824
VREF
SVR
Reference voltage
V
Over temperature range
VI = 2.5 V 0.5 V, VO = 1 V,
F = 120 Hz, VBIAS = 3.3 V
Supply voltage rejection
68
dB
1. For VO ≤ 1 V, VBIAS dropout specification does not apply due to a minimum 3 V VBIAS input.
2. Fixed output voltage version only.
8/22
Doc ID 13446 Rev 3
LD49150XX08, LD49150XX10, LD49150XX12
Typical characteristics
7
Typical characteristics
Figure 7.
Reference voltage vs. temperature Figure 8.
Output voltage vs. temperature
Figure 9.
Load regulation vs. temperature
Figure 10. Line regulation vs. temperature
Figure 11. Output voltage vs. input voltage
Figure 12. Dropout voltage (V -V
) vs.
IN OUT
temperature
Doc ID 13446 Rev 3
9/22
Typical characteristics
LD49150XX08, LD49150XX10, LD49150XX12
Figure 13. Dropout voltage (V -V
) vs.
Figure 14. V
pin current vs. temperature
IN OUT
BIAS
temperature
Figure 15. Noise vs. frequency
Figure 16. Quiescent current vs. temperature
Figure 17. Supply voltage rejection vs. output Figure 18. Stability region vs. C
& High
OUT
current
ESR
10/22
Doc ID 13446 Rev 3
LD49150XX08, LD49150XX10, LD49150XX12
Typical characteristics
Figure 19. Stability region vs. C
& low ESR Figure 20. V
& V start up transient
BIAS IN
OUT
response (V and V
start up at
IN
BIAS
the same time)
VIN=VBIAS=VINH=3.1V, VOUT=1V, COUT=1µF
Figure 21. V start up transient response
Figure 22. V start up transient response
IN
IN
(V
start up before V )
(V
start up before V )
BIAS
IN
BIAS IN
VIN=2.5V, VBIAS=VINH=3.1V, VOUT=1V, COUT=1µF
VIN=2.5V, VBIAS=VINH=3.1V, VOUT=1V, COUT=1µF
Doc ID 13446 Rev 3
11/22
Typical characteristics
LD49150XX08, LD49150XX10, LD49150XX12
Figure 23. V start up transient response
IN
(V
start up before V and
=V )
IN
BIAS
INH
IN
V
VIN=VINH=2.5V, VBIAS=3.1V, VOUT=1V, COUT=1µF
12/22
Doc ID 13446 Rev 3
LD49150XX08, LD49150XX10, LD49150XX12
Application hints
8
Application hints
The LD49150xx is an ultra-high performance, low dropout linear regulator, designed for high
current application that requires fast transient response. The LD49150xx operates from two
input voltages, to reduce dropout voltage. The LD49150xx is designed so that a minimum of
external component are necessary.
8.1
8.2
Input supply voltage (VIN)
V
provides the power input current to the LD49150xx. The minimum input voltage can be
IN
as low as 1.4 V, allowing conversion from very low voltage supplies to achieve low output
voltage levels with very low power dissipation.
Bias supply voltage (VBIAS
)
The LD49150xx control circuitry is supplied the V
pin which requires a very low bias
BIAS
current (3 mA typ.) even at the maximum output current level (1.5 A). A bypass capacitor on
the bias pin is recommended to improve the performance of the LD49150xx during line and
load transient. The small ceramic capacitor from V
to ground reduces high frequency
BIAS
noise that could be injected into the control circuitry from the bias rail. In typical applications
a 1 µF ceramic chip capacitor may be used. The V input voltage must be 2.1 V above
BIAS
the output voltage, with a minimum V
input voltage of 3 V.
BIAS
8.3
8.4
External capacitors
To assure regulator stability, input and output capacitors are required as shown in the 1:
Typical application circuits.
Output capacitor
The LD49150xx requires a minimum output capacitance to maintain stability. A ceramic chip
capacitor of at least 1 µF is required. However, specific capacitor selection could be needed
to ensure the transient response. A 1 µF ceramic chip capacitor satisfies most applications
but 10 µF is recommended to ensure better transient performances. In applications where
the V level is close to the maximum operating voltage (V > 4 V), it is strongly
IN
IN
recommended to use an output capacitors of, at least, 10 µF in order to avoid over-voltage
stress on the Input/output power pins during short circuit conditions due to parasitic
inductive effect. The output capacitor must be located as close as possible to the output pin
of the LD49150xx. The ESR (equivalent series resistance) of the output capacitor must be
within the "stable" region as shown in the typical characteristics figures. Both ceramic and
tantalum capacitors are suitable.
8.5
Minimum load current
The LD49150xx does not require a minimum load to maintain output voltage regulation.
Doc ID 13446 Rev 3
13/22
Application hints
LD49150XX08, LD49150XX10, LD49150XX12
8.6
Power sequencing recommendations
In order to ensure the correct biasing and settling of the regulator internal circuitry during the
startup phase, as well as to avoid overvoltage spikes at the output, it is recommended to
provide for the correct power sequencing.
As a general rule the V and V
signals timings at startup should be chosen properly, so
IN
INH
that they are applied to the device after the V
voltage is already settled at its minimum
BIAS
operative value (see paragraph 8.2: Bias supply voltage (VBIAS)). This can be achieved, for
instance, by avoiding too slow V rising edges (T >10 ms).
BIAS
r
Provided that the above condition is satisfied, when fast V transient input (T < 100 µs) is
IN
r
present, a smooth startup, with limited overvoltage on the output, can be obtained by
applying V voltage at the same time as the V
voltage (refer to Figure 20, Figure 21
IN
BIAS
and Figure 22 on page 11).
In the fixed voltage versions it is possible to reduce overvoltage spikes during very fast
startup (T << 100 µs) by pulling the V pin up to V voltage (see Figure 23 on page 12).
r
INH
IN
8.7
Power dissipation/heatsinking
A heatsink may be required depending on the maximum power dissipation and maximum
ambient temperature of the application. Under all possible conditions, the junction
temperature must be within the range specified under operating conditions. The total power
dissipation of the device is given by:
P = V x I + V
x I
- V
x I
D
IN
IN
BIAS
BIAS
OUT OUT
Where:
●
●
●
●
V , input supply voltage
IN
V
, bias supply voltage
BIAS
V
, output voltage
OUT
I
, load current
OUT
From this data, we can calculate the thermal resistance (θSA) required for the heat sink
using the following formula:
θSA = (T - T /P ) - (θJC + θCS
)
J
A
D
The maximum allowed temperature rise (T
) depends on the maximum ambient
Rmax
temperature (T
) of the application, and the maximum allowable junction temperature
Amax
(T
):
Jmax
T
= T
- T
Jmax Amax
Rmax
The maximum allowable value for junction to ambient thermal resistance, θJA, can be
calculated using the formula:
θJAmax = T
/ P
D
Rmax
This part is available for the PPAK package.
The thermal resistance depends on the amount of copper area or heat sink, and on air flow.
If the maximum allowable value of θJA calculated above is ≥ 100 °C/W for the PPAK
package, no heatsink is needed since the package can dissipate enough heat to satisfy
these requirements. If the value for allowable θJA falls below these limits, a heat sink is
required as described below.
14/22
Doc ID 13446 Rev 3
LD49150XX08, LD49150XX10, LD49150XX12
Application hints
8.8
Heatsinking PPAK package
The PPAK package uses the copper plane on the PCB as a heatsink. The tab of these
packages is soldered to the copper plane for heat sinking. It is also possible to use the PCB
ground plane a heatsink. This area can be the inner GND layer of a multi-layer PCB, or, in a
dual layer PCB, it can be an unbroken GND area on the opposite side where the IC is
situated with a dissipating area thermally connected through vias holes, filled by solder.
Figure 26 shows a curve for θJA of the PPAK package for different copper area sizes, using
a typical PCB with 1/16 in thick G10/FR4.
Figure 24. θJA vs. copper area for PPAK package
8.9
Adjustable regulator design
The LD49150xx adjustable version allows fixing output voltage anywhere between 0.8 V and
4.5 V using two resistors as shown in the typical application circuit. For example, to fix the
R resistor value between V
and the ADJ pin, the resistor value between ADJ and GND
1
OUT
(R ) is calculated by:
2
R = R [0.8/(V - 0.8)]
OUT
2
1
Where V
is the desired output voltage.
OUT
It is suggested to use R1 values lower than 10 kΩ to obtain better load transient
performances. Even, higher values up to 100 kΩ are suitable.
8.10
Enable
The fixed output voltage versions of LD49150xx feature an active high Enable input (EN)
that allows on-off control of the regulator. The EN input threshold is guaranteed between 0.4
V and 1.4 V, for simple logic interfacing. The regulator is set in shut down mode when V
<
EN
0.4 V and it is in operating mode (V
activated) when V > 1.4 V. If not in use, the EN pin
OUT
EN
must be tied directly to the V to keep the regulator continuously activated. The En pin must
IN
not be left at high impedance.
Doc ID 13446 Rev 3
15/22
Package mechanical data
LD49150XX08, LD49150XX10, LD49150XX12
9
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
16/22
Doc ID 13446 Rev 3
LD49150XX08, LD49150XX10, LD49150XX12
Package mechanical data
PPAK mechanical data
mm.
Typ.
inch.
Dim.
Min.
Max.
Min.
Typ.
Max.
A
A1
A2
B
2.2
0.9
2.4
1.1
0.23
0.6
5.4
0.6
0.6
6.2
0.086
0.035
0.001
0.015
0.204
0.017
0.019
0.236
0.094
0.043
0.009
0.023
0.212
0.023
0.023
0.244
0.03
0.4
5.2
B2
C
0.45
0.48
6
C2
D
D1
E
5.1
0.201
6.4
6.6
0.252
0.260
E1
e
4.7
0.185
1.27
0.050
G
4.9
5.25
2.7
10.1
1
0.193
0.093
0.368
0.206
0.106
0.397
0.039
0.039
G1
H
2.38
9.35
L2
L4
L5
L6
0.8
2.8
0.031
0.6
1
1
0.023
0.039
0.110
0078180-E
Doc ID 13446 Rev 3
17/22
Package mechanical data
LD49150XX08, LD49150XX10, LD49150XX12
DFN6 (3x3 mm) mechanical data
mm.
Typ.
0.90
inch.
Typ.
Dim.
Min.
Max.
1.00
0.05
Min.
0.031
0
Max.
0.039
0.002
A
A1
A3
b
0.80
0.035
0
0.02
0.20
0.30
3.00
2.38
3.00
1.65
0.95
0.40
0.001
0.008
0.012
0.118
0.094
0.118
0.065
0.037
0.016
0.23
2.90
2.23
2.90
1.50
0.38
3.10
2.48
3.10
1.75
0.009
0.114
0.088
0.114
0.059
0.015
0.122
0.098
0.122
0.069
D
D2
E
E2
e
L
0.30
0.50
0.012
0.020
7946637A
18/22
Doc ID 13446 Rev 3
LD49150XX08, LD49150XX10, LD49150XX12
Package mechanical data
Tape & reel DPAK-PPAK mechanical data
mm.
Typ.
inch.
Dim.
Min.
Max.
330
Min.
Typ.
Max.
12.992
0.519
A
C
12.8
20.2
60
13.0
13.2
0.504
0.795
2.362
0.512
D
N
T
22.4
7.00
10.60
2.75
4.1
0.882
0.2.76
0.417
0.105
0.161
0.319
Ao
Bo
Ko
Po
P
6.80
10.40
2.55
3.9
6.90
10.50
2.65
4.0
0.268
0.409
0.100
0.153
0.311
0.272
0.413
0.104
0.157
0.315
7.9
8.0
8.1
Doc ID 13446 Rev 3
19/22
Package mechanical data
LD49150XX08, LD49150XX10, LD49150XX12
Tape & reel QFNxx/DFNxx (3x3) mechanical data
mm.
Typ.
inch.
Typ.
Dim.
Min.
Max.
180
Min.
Max.
7.087
0.519
A
C
D
12.8
20.2
60
13.2
0.504
0.795
2.362
N
T
14.4
0.567
Ao
Bo
Ko
Po
P
3.3
3.3
1.1
4
0.130
0.130
0.043
0.157
0.315
8
20/22
Doc ID 13446 Rev 3
LD49150XX08, LD49150XX10, LD49150XX12
Revision history
10
Revision history
Table 6.
Document revision history
Revision
Date
Changes
18-Apr-2007
12-Jan-2009
29-Jun-2010
1
2
3
Initial release.
Added new package DFN6 (3x3 mm) and mechanical data.
Modified Section 8.6: Power sequencing recommendations on page 14.
Doc ID 13446 Rev 3
21/22
LD49150XX08, LD49150XX10, LD49150XX12
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