L6910_05_技术文档

L6910

L6910A

ADJUSTABLE STEP DOWN CONTROLLER

WITH SYNCHRONOUS RECTIFICATION

Figure 1. Packages

1 FEATURES

■ OPERATING SUPPLY VOLTAGE FROM 5V

TO 12V BUSES

■ UP TO 1.3A GATE CURRENT CAPABILITY

■ ADJUSTABLE OUTPUT VOLTAGE

■ N-INVERTING E/A INPUT AVAILABLE

■ 0.9V 1.5% VOLTAGE REFERENCE

■ VOLTAGE MODE PWM CONTROL

■ VERY FAST LOAD TRANSIENT RESPONSE

■ 0% TO 100% DUTY CYCLE

HTSSOP16 (Exposed Pad)

SO-16 (Narrow)

Table 1. Order Codes

Part Number

L6910

Package

SO-16

■ POWER GOOD OUTPUT

L6910TR

L6910A

SO-16 in Tape & Reel

HTSSOP16

■ OVERVOLTAGE PROTECTION

■ HICCUP OVERCURRENT PROTECTION

■ 200kHz INTERNAL OSCILLATOR

■ OSCILLATOR EXTERNALLY ADJUSTABLE

FROM 50kHz TO 1MHz

L6910ATR

HTSSOP16 in Tape & Reel

dc-dc conversion from 3.3V, 5V and 12V buses.

The output voltage is adjustable down to 0.9V;

higher voltages can be obtained with an external

voltage divider.

■ SOFT START AND INHIBIT

■ PACKAGES: SO-16 & HTSSOP16

High peak current gate drivers provide for fast switch-

ing to the external power section, and the output

current can be in excess of 20A.

2 APPLICATIONS

■ SUPPLY FOR MEMORIES AND TERMI-

NATIONS

The device assures protections against load overcur-

rent and overvoltage. An internal crowbar is also pro-

vided turning on the low side mosfet as long as the

over-voltage is detected. In case of over-current de-

tection, the soft start capacitor is discharged and the

system works in HICCUP mode.

■ COMPUTER ADD-ON CARDS

■ LOW VOLTAGE DISTRIBUTED DC-DC

■ MAG-AMP REPLACEMENT

3 DESCRIPTION

The device is a pwm controller for high performance

Figure 2. Block Diagram

V_in5V to 12V

VCC

OCSET

PGOOD

MONITOR

BOOT

PROTECTION

VREF

SS

&

REF

UGATE

V_O

OSC

BOOT

OSC

R

T

PWM

-

E/A

LGATE

PGND

EAREF

+

-

+

GND

VFB

COMP

D03IN1509

Rev. 9

1/29

May 2005

L6910 - L6910A

Table 2. Absolute Maximum Ratings

Symbol

Parameter

Value

15

Unit

V

Vcc

Vcc to GND, PGND

Boot Voltage

V

-

15

V

BOOT

V

PHASE

V

-

15

V

HGATE

V

PHASE

OCSET, LGATE, PHASE

-0.3 to Vcc+0.3

V

SS, FB, PGOOD, VREF, EAREF, RT

COMP

7

6.5

V

T

Junction Temperature Range

Storage temperature range

Maximum power dissipation at Tamb = 25°C

-40 to 150

1

°C

W

j

T

stg

P

tot

Table 3. Thermal Data

Symbol

Parameter

SO-16

HTSSOP16 HTSSOP16 (*)

Unit

R

Thermal Resistance Junction to Ambient

120

110

50

°C/W

th j-amb

(*) Device soldered on 1 S2P PC board

Figure 3. Pins Connection (Top view)

VREF

OSC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

VCC

VREF

OSC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

N.C.

LGATE

PGND

VCC

OCSET

SS/INH

N.C.

OCSET

SS/INH

COMP

FB

LGATE

PGND

BOOT

HGATE

PHASE

PGOOD

BOOT

HGATE

PHASE

PGOOD

EAREF

COMP

FB

GND

EAREF

D03IN1510

D03IN1511

2/29

L6910 - L6910A

Table 4. Pins Function

SO HTSSOP Name

Description

1

VREF Internal 0.9V 1.5% reference is available for external regulators or for the internal error

amplifier (connecting this pin to EAREF) if external reference is not available.

A minimum 1nF capacitor is required.

If the pin is forced to a voltage lower than 70%, the device enters the hiccup mode.

2

OSC

Oscillator switching frequency pin. Connecting an external resistor (R ) from this pin to

T

GND, the external frequency is increased according to the equation:

4.94 ⋅ 10⁶

f_OSC,RT= 200KHz + -------------------------

R_T(KΩ)

Connecting a resistor (R_T) from this pin to Vcc (12V), the switching frequency is reduced

according to the equation:

4.306 ⋅ 10⁷

f_OSC,RT= 200KHz – ----------------------------

R_T(KΩ)

If the pin is not connected, the switching frequency is 200KHz.

The voltage at this pin is fixed at 1.23V. Forcing a 50µA current into this pin, the built in

oscillator stops to switch.

In Over Voltage condition this pin goes over 3V until that conditon is removed.

3

4

3

4

OCSET A resistor connected from this pin and the upper Mos Drain sets the current limit

protection.

The internal 200µA current generator sinks a constant current through the external

resistor. The Over-Current threshold is due to the following equation:

I

⋅ R_OCSET

R_DSon

I_P= --^O----^C----^S----^E---^T----------------------------

SS/INH The soft start time is programmed connecting an external capacitor from this pin and

GND. The internal current generator forces through the capacitor 10µA.

This pin can be used to disable the device forcing a voltage lower than 0.4V

5

6

7

COMP This pin is connected to the error amplifier output and is used to compensate the voltage

control feedback loop.

FB

This pin is connected to the error amplifier inverting input and is used to compensate the

voltage control feedback loop.

Connected to the output resistor divider, if used, or directly to Vout, it manages also over-

voltage conditions and the PGOOD signal

7

8

9

GND

All the internal references are referred to this pin. Connect it to the PCB signal ground.

EAREF Error amplifier non-inverting input. Connect to this pin an external reference (from 0.9V to

3V) for the PWM regulation or short it to VREF pin to use the internal reference.

If this pin goes under 650mV (typ), the device shuts down.

9

10

11

PGOOD This pin is an open collector output and it is pulled low if the output voltage is not within the

above specified thresholds. If not used it may be left floating.

10

PHASE This pin is connected to the source of the upper mosfet and provides the return path for the

high side driver. This pin monitors the drop across the upper mosfet for the current limit

together with OCSET.

11

12

13

HGATE High side gate driver output.

BOOT Bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper

mosfet. Connect through a capacitor to the PHASE pin and through a diode to Vcc

(cathode vs. boot).

13

14

PGND Power ground pin. This pin has to be connected closely to the low side mosfet source in

order to reduce the noise injection into the device

14

15

5

LGATE This pin is the lower mosfet gate driver output

16

VCC

Device supply voltage. The operative supply voltage ranges is from 5V to 12V.

DO NOT CONNECT V TO A VOLTAGE GREATER THAN V

.

CC

IN

16

5

N.C.

This pin is not internally bonded. It may be left floating or connected to GND.

3/29

L6910 - L6910A

Table 5. Electrical Characteristics (V_cc= 12V, T_J=25°C unless otherwise specified)

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

V

cc

SUPPLY CURRENT

Icc

Vcc Supply current

OSC = open; SS to GND

4

7

9

mA

POWER-ON

Turn-On Vcc threshold

Turn-Off Vcc threshold

VOCSET = 4V

4.0

3.8

4.3

4.1

4.6

4.4

1.4

750

V

Rising V

threshold

1.24

650

V

OCSET

Turn On EAREF threshold

SOFT START AND INHIBIT

VOCSET = 4V

mV

Iss

Soft start Current

S.S. current in INH condition

SS = 2V

SS = 0 to 0.4V

6

10

35

14

60

µA

OSCILLATOR

f

Initial Accuracy

OSC = OPEN

OSC = OPEN; T = 0° to 125°

180

170

200

1.9

220

230

KHz

kHz

OSC

j

f

Total Accuracy

16 KΩ < R to GND < 200 KΩ

-15

15

%

V

OSC,RT

T

∆Vosc

Ramp amplitude

REFERENCE

V

Output Voltage Accuracy

Reference Voltage

V

= V ; V

= V

REF

0.886

-2

0.900

0.913

+2

V

OUT

FB EAREF

V

C

= 1nF; I

= 0 to 100µA

REF

Reference Voltage

= 1nF; T = 0 to 125°C

%

J

ERROR AMPLIFIER

I

N.I. bias current

V

= 3V

10

µA

kΩ

µA

V

EAREF

EAREF Input Resistance

I.I. bias current

Vs. GND

300

0.01

I

FB

V

= 0V to 3V

FB

0.5

3

V

Common Mode Voltage

Output Voltage

0.8

0.5

70

CM

V

4

V

COMP

G

Open Loop Voltage Gain

85

10

dB

MHz

V/µs

V

GBWP Gain-Bandwidth Product

SR Slew-Rate

GATE DRIVERS

COMP = 10pF

I

High Side

Source Current

V

- V = 12V

PHASE

1

1.3

2

A

HGATE

BOOT

- V

= 6V

PHASE

HGATE

R

High Side

Sink Resistance

V

BOOT

- V = 12V

PHASE

4

Ω

HGATE

I

Low Side Source Current

Low Side Sink Resistance

Output Driver Dead Time

Vcc = 12V; V

Vcc = 12V

= 6V

0.9

1.1

1.5

A

Ω

LGATE

R

3

LGATE

PHASE connected to GND

90

210

ns

PROTECTIONS

OCSET Current Source

I

V

= 4V

170

200

117

30

230

120

µA

%

OCSET

Over Voltage Trip (V / V

)

Rising

FB

EAREF

FB

I

OSC Sourcing Current

> OVP Trip

15

mA

OSC

POWER GOOD

Upper Threshold (V / V

)

V

Rising

Falling

108

88

110

90

112

92

%

V

FB

EAREF

FB

Lower Threshold (V / V

)

FB

EAREF

FB

Hysteresis (V / V

)

Upper and Lower threshold

2

FB

EAREF

V

I

PGOOD Voltage Low

I

= -4mA

= 6V

PGOOD

0.4

0.2

PGOOD

Output Leakage Current

V

1

µA

PGOOD

4/29

L6910 - L6910A

4 DEVICE DESCRIPTION

The device is an integrated circuit realized in BCD technology. The controller provides complete con-

trol logic and protection for a high performance step-down DC-DC converter. It is designed to drive N

Channel Mosfets in a synchronous-rectified buck topology. The output voltage of the converter can be

precisely regulated down to 900mV with a maximum tolerance of 1.5% when the internal reference is

used (simply connecting together EAREF and VREF pins). The device allows also using an external

reference (0.9V to 3V) for the regulation. The device provides voltage-mode control with fast transient

response. It includes a 200kHz free-running oscillator that is adjustable from 50kHz to 1MHz. The er-

ror amplifier features a 10MHz gain-bandwidth product and 10V/µs slew rate that permits to realize

high converter bandwidth for fast transient performance. The PWM duty cycle can range from 0% to

100%. The device protects against over-current conditions entering in HICCUP mode. The device

monitors the current by using the r_DS(ON)of the upper MOSFET(s) that eliminates the need for a cur-

rent sensing resistor. The device is available in SO16 narrow package.

4.1 Oscillator

The switching frequency is internally fixed to 200kHz. The internal oscillator generates the triangular waveform

for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the

oscillator is typically 50µA (F = 200KHz) and may be varied using an external resistor (R ) connected between

s

w

T

OSC pin and GND or V . Since the OSC pin is maintained at fixed voltage (typ. 1.235V), the frequency is var-

CC

ied proportionally to the current sunk (forced) from (into) the pin.

In particular connecting R vs. GND the frequency is increased (current is sunk from the pin), according to the

T

following relationship:

6

4.94 ⋅ 10

f

= 200KHz + -------------------------

OSC,RT

R (KΩ)

T

Connecting R to V = 12V or to V = 5V the frequency is reduced (current is forced into the pin), according

T

CC

to the following relationships:

7

4.306 ⋅ 10

f

= 200KHz – ----------------------------

V

= 12V

CC

OSC,RT

R (KΩ)

T

6

15 ⋅ 10

f

= 200KHz – ---------------------

V

= 5V

CC

OSC,RT

R (KΩ)

T

Switching frequency variation vs. RT are repeated in Fig. 4.

Note that forcing a 50

oscillator.

µ

A current into this pin, the device stops switching because no current is delivered to the

Figure 4.

10000

1000

100

RT to GND

10

RT to VCC=12V

RT to VCC=5V

10

100

1000

Frequency [kHz]

5/29

L6910 - L6910A

4.2 Reference

A precise 1.5% 0.9V reference is available. This reference must be filtered with 1nF ceramic capacitor to avoid

instability in the internal linear regulator. It is able to deliver up to 100µA and may be used as reference for the

device regulation and also for other devices. If forced under 70% of its nominal value, the device enters in Hic-

cup mode until this condition is removed.

Through the EAREF pin the reference for the regulation is taken. This pin directly connects the non-inverting

input of the error amplifier. An external reference (or the internal 0.9V 1.5%) may be used. The input for this

pin can range from 0.9V to 3V. It has an internal pull-down (300k

no reference is connected (pin floating). However the device is shut down if the voltage on the EAREF pin is

lower than 650mV (typ).

Ω resistor) that forces the device shutdown if

4.3 Soft Start

At start-up a ramp is generated charging the external capacitor C with an internal current generator. The initial

SS

value for this current is of 35

10 A until the final charge value of approximatively 4V.

When the voltage across the soft start capacitor (V ) reaches 0.5V the lower power MOS is turned on to dis-

µA and speeds-up the charge of the capacitor up to 0.5V. After that it becames

µ

SS

charge the output capacitor. As V reaches 1.1V (i.e. the oscillator triangular wave inferior limit) also the upper

SS

MOS begins to switch and the output voltage starts to increase.

No switching activity is observable if SS is kept lower than 0.5V and both mosfets are off.

If VCC and OCSET pins are not above their own turn-on thresholds and V

is not above 650mV, the Soft-

EAREF

Start will not take place, and the relative pin is internally shorted to GND. During normal operation, if any under-

voltage is detected on one of the two supplies, the SS pin is internally shorted to GND and so the SS capacitor

is rapidly discharged.

Figure 5. Soft Start (with Reference Present)

Vcc Turn-on threshold

Vcc

Vin

Vin Turn-on threshold

1V

Vss

LGATE

Vout

to GND

0.5V

Acquisition: CH1 = PHASE; CH2 = V

;

out

Timing Diagram

CH3 = PGOOD; CH4 = V

ss

4.4 Driver Section

The driver capability on the high and low side drivers allows using different types of power MOS (also multiple

MOS to reduce the R ), maintaining fast switching transition.

DSON

The low-side mos driver is supplied directly by Vcc while the high-side driver is supplied by the BOOT pin.

Adaptative dead time control is implemented to prevent cross-conduction and allow to use several kinds of mos-

fets. The upper mos turn-on is avoided if the lower gate is over about 200mV while the lower mos turn-on is

6/29

L6910 - L6910A

avoided if the PHASE pin is over about 500mV. The lower mos is in any case turned-on after 200ns from the

high side turn-off.

The peak current is shown for both the upper (fig. 6) and the lower (fig. 7) driver at 5V and 12V. A 3.3nF capac-

itive load has been used in these measurements.

For the lower driver, the source peak current is 1.1A @ V = 12V and 500mA @ V = 5V, and the sink peak

CC

current is 1.3A @ V = 12V and 500mA @ V = 5V.

CC

Similarly, for the upper driver, the source peak current is 1.3A @ Vboot-Vphase = 12V and 600mA @ Vboot-

Vphase = 5V, and the sink peak current is 1.3A @ Vboot-Vphase =12V and 550mA @ Vboot-Vphase = 5V.

Figure 6. High Side Driver Peak Current. Vboot-Vphase = 12V (right) Vboot-Vphase = 5V (left)

CH1 = High Side Gate CH4 = Gate Current

Figure 7. Low Side Driver Peak Current. V_CC= 12V (right) V_CC= 5V (left)

CH1 = Low Side Gate CH4 = Gate Current

4.5 Monitoring and Protections

The output voltage is monitored by means of pin FB. If it is not within 10% (typ.) of the programmed value, the

powergood output is forced low.

The device provides overvoltage protection, when the voltage sensed on pin FB reaches a value 17% (typ.)

greater than the reference the OSC pin is forced high (3V typ.) and the lower driver is turned on as long as the

over-voltage is detected.

7/29

L6910 - L6910A

Overcurrent protection is performed by the device comparing the drop across the high side MOS, due to the

R

, with the voltage across the external resistor (R ) connected between the OCSET pin and drain of the

DSON OCS

upper MOS. Thus the overcurrent threshold (I ) can be calculated with the following relationship:

P

R

⋅ I

OCS OCS

I

= --------------------------------

P

R

dsON

Where the typical value of I

is 200

µ

A. To calculate the R

value it must be considered the maximum

OCS

R

(also the variation with temperature) and the minimum value of I

. To avoid undesirable trigger of

OCS

dsON

overcurrent protection this relationship must be satisfied:

∆I

+ ---- = I

PEAK

I ≥ I

P

OUTMAX

2

Where

∆

I is the inductance ripple current and I

is the maximum output current.

OUTMAX

In case of over current detectionthe soft start capacitor is discharged with constant current (10

µ

A typ.) and when

the SS pin reaches 0.5V the soft start phase is restarted. During the soft start the over-current protection is al-

ways active and if such kind of event occurs, the device turns off both mosfets, and the SS capacitor is dis-

charged again (after reaching the upper threshold of about 4V). The system is now working in HICCUP mode,

as shown in figure 8. After removing the cause of the over-current, the device restart working normally without

power supplies turn off and on.

Figure 8. Hiccup Mode

Figure 9. Inductor Ripple Current vs. Vout

9

L=1.5µH, Vin=12V

8

L=2µH,

Vin=12V

7

6

L=3µH,

Vin=12V

5

4

3

2

1

0

L=1.5µH,

Vin=5V

L=2µH,

Vin=5V

L=3µH, Vin=5V

0.5

1.5

2.5

3.5

Output Voltage [V]

CH1 = SS; CH4 = Inductor current

4.6 Inductor Design

The inductance value is defined by a compromise between the transient response time, the efficiency, the cost

and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain

the ripple current

culated with this relationship:

∆I between 20% and 30% of the maximum output current. The inductance value can be cal-

L

V

– V

V

OUT OUT

IN

------------------------------ --------------

L =

is the switching frequency, V is the input voltage and V is the output voltage. Figure 9 shows

OUT

⋅

f

⋅ ∆I

V

IN

sw

L

Where f

SW

IN

the ripple current vs. the output voltage for different values of the inductor, with V = 5V and V = 12V.

IN

Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter

response time to a load transient. If the compensation network is well designed, the device is able to open or

close the duty cycle up to 100% or down to 0%. The response time is now the time required by the inductor to

change its current from initial to final value. Since the inductor has not finished its charging time, the output cur-

rent is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance

required.

8/29

L6910 - L6910A

The response time to a load transient is different for the application or the removal of the load: if during the ap-

plication of the load the inductor is charged by a voltage equal to the difference between the input and the output

voltage, during the removal it is discharged only by the output voltage. The following expressions give approx-

imate response time for ∆I load transient in case of enough fast compensation network response:

L ⋅ ∆I

------------------------------

IN

L ⋅ ∆I

t

=

t

= --------------

application

removal

V

– V

OUT

V

OUT

The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst

case is the response time after removal of the load with the minimum output voltage programmed and the max-

imum input voltage available.

4.7 Output Capacitor

The output capacitor is a basic component for the fast response of the power supply. In fact, during load tran-

sient, for first few microseconds they supply the current to the load. The controller recognizes immediately the

load transient and sets the duty cycle at 100%, but the current slope is limited by the inductor value. The output

voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the ESL):

∆V

= ∆I

⋅ ESR

OUT

A minimum capacitor value is required to sustain the current during the load transient without discharge it. The

voltage drop due to the output capacitor discharge is given by the following equation:

2

∆I

⋅ L

OUT

∆V

= ---------------------------------------------------------------------------------------------

OUT

2 ⋅ C

⋅ (V

⋅ D

– V

)

OUT

INMIN

MAX

Where D

is the maximum duty cycle value that is 100%. The lower is the ESR, the lower is the output drop

MAX

during load transient and the lower is the output voltage static ripple.

4.8 Input Capacitor

The input capacitor has to sustain the ripple current produced during the on time of the upper MOS, so it must

have a low ESR to minimize the losses. The rms value of this ripple is:

I

= I

D ⋅ (1 – D)

OUT

rms

Where D is the duty cycle. The equation reaches its maximum value with D = 0.5. The losses in worst case are:

2

P = ESR ⋅ I

rms

4.9 Compensation Network Design

The control loop is a voltage mode (figure 10). The output voltage is regulated to the input Reference voltage

level (EAREF). The error amplifier output V

is then compared with the oscillator triangular wave to provide

COMP

a pulse-width modulated (PWM) wave with an amplitude of V at the PHASE node. This wave is filtered by the

IN

output filter. The modulator transfer function is the small-signal transfer function of V

/V

. This function

OUT COMP

has a double pole at frequency F depending on the L-C resonance and a zero at F depending on the

LC

out

ESR

output capacitor ESR. The DC Gain of the modulator is simply the input voltage V divided by the peak-to-peak

IN

oscillator voltage

∆

V

.

OSC

9/29

L6910 - L6910A

Figure 10. Compensation Network

V_IN

∆V_OSC

L

V_OUT

ESR

C_OUT

PWM

COMPARATOR

C18

C19

R5

R3

C20

R4

EAREF

-

V_COMP

D03IN1512

+

The compensation network consists in the internal error amplifier and the impedance networks Z (R3, R4 and

IN

C20) and Z (R5, C18 and C19). The compensation network has to provide a closed loop transfer function with

FB

the highest 0dB crossing frequency to have fast response (but always lower than fsw/10) and the highest gain

in DC conditions to minimize the load regulation.

A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45°. Include

worst-case component variations when determining phase margin.

To locate poles and zeroes of the compensation networks, the following suggestions may be used:

Modulator singularity frequencies:

1

---------------------------

ω

=

ω

= --------------------------------

LC

ESR

ESR ⋅ C

L ⋅ C

OUT

Compensation network singularity frequency:

1

-----------------------------------------------

ω

=

ω

= -----------------------

P1

P2

R4 ⋅ C20

C18 ⋅ C19

⎛

⎞

----------------------------

R5 ⋅

⎝

⎠

C18 + C19

1

-----------------------

ω

=

ω

= ------------------------------------------

Z1

Z2

R5 ⋅ C19

(R3 + R4) ⋅ C20

– Put the gain R5/R3 in order to obtain the desired converter bandwidth;

– Place ω_Z1before the output filter resonance ω_LC

– Place ω_Z2at the output filter resonance ω_LC

;

– Place ω_P1at the output capacitor ESR zero ω_ESR

– Place ω_P2at one half of the switching frequency;

;

– Check the loop gain considering the error amplifier open loop gain.

10/29

L6910 - L6910A

Figure 11. Asymptotic Bode Plot of Converter's Gain

dB

Error Amplifier

R5/R3

ωΖ1

ω_LC

ωΖ2

ω_P1

ω_P2

ω

Modulator Gain

ω^ESR

Compensation Network Gain

Error Amplifier

Closed Loop Gain

5 15A DEMO BOARD DESCRIPTION

The demo board shows the operation of the device in a general purpose application. This evaluation board al-

lows voltage adjustability from 0.9V to 5V through the switches S2-S5 according to the reported table when the

internal 0.9V reference is used (G1 closed). Output current in excess of 20A can be reached dependently on

the kind of mosfet used: up to three SO8 mosfet may be used for both High side and Low side switches. External

reference may be used for the regulation simply leaving open G1 and the switches S2-S5. The device may also

be disabled with the switch S1. The V input rail supplies the device while the power conversion starts from

CC

the V input rail. The device is also able to operate with a single supply voltage; in this case the jumper G2 has

IN

to be closed and a 5V to 12V input can be directly connected to the V input. The four layers demo board's

IN

copper thickness is of 70µm in order to minimize conduction losses considering the high current that the circuit

is able to deliver.The PGOOD signal is used as a logic level and it's been pulled up to V because there's no

IN

other appropriate voltage available on the demo board. In case of input voltage higher than 7V (PGOOD Pin

Maximum Absolute Rating) a 5V reference is required. Figure 12 shows the demo board's schematic circuit

Figure 12. 15A Demo Board Schematic

L1

F1

VIN

GNDIN

R7

C14

C13

C1-C3

G2

D1

V_CC

BOOT

OCSET

Q1-3

Q4-6

R6

UGATE

12

3

VCC

15

11

10

14

13

L2

GNDCC

C17

C15

PHASE

LGATE

PGND

V_OUT

7

8

GND

C4-

11

R2

D2

R8

EAREF

REFIN

GNDOUT

PWRGD

GNDREFIN

C16

G1

PGOOD

VREF

9

+VREF

1

GNDREF

C12

R9

SS

4

2

C21

OSC

C22

R1

5

6

COMP

VFB

C19

V_OUT

S2 S3 S4 S5

Open Open Open Open

ON Open Open Open

Open ON Open Open

ON ON Open Open

Open Open ON Open

Open Open Open ON

Open Open ON ON

R5

R3

R4

0.9

1.2

1.5

1.8

2.5

3.3

5.0

C20

S1

S2

S3

S4

S5

C18

R10

R11

SR12

SR13

D03IN1513

11/29

L6910 - L6910A

Table 6. Part List

Reference

R1

Description

Manufacturer

NEOHM

N.C

R2

10K

5% 125mW

SMD 0805

R3

4.7K

R4

1KOhm 5% 125mW

2.7K 5% 125mW

R5

R6

10Ohm 5% 125mW

510Ohm 5% 125mW

N.C

R7

R8

R9

0 Ohm

SMD 0805

R10

R11

R12

R13

C1, C3

C9, C10

14K

5% 125mW

5 5% 125mW

NEOHM

6.98K

2.61K

1.74K

SMD 0805

NEOHM

SMD 0805

NEOHM

SMD 0805

100µF - 20V

OSCON 20SA100M

POSCAP 6TPB330M

KEMET

RADIAL 10X10.5

SMD7343

330µF - 6.3V

C12, C13,

C15, C21

100nF

SMD0805

C14

C16

1nF

KEMET

AUX

SMD0805

100nF

C17

4.7µF - 16V

SMA6032

SMD0805

C18

1.5nF

KEMET

C19

15nF

C20

47nF

N.C

C22

L1

Short

L2

3µH (T50-52B Core, 7T AWG15)

STS11NF30L

1N4148

MICROMETALS

ST

Q2,Q3,Q4,Q6

D1

SO8

SOT23

D2

STPS2L25U

Device L6910

Short

ST

SMB

U1

SO16Narrow

F1

SWITCH

DIP SWITCH 6 POS.

Table 7. Other Inductor Manufacturer

Manufacturer

WÜRTH ELEKTRONIK

PANASONIC

Series

Inductor Value (µH)

Saturation Current (A)

744318

1.8 to 2.7

1.8

16 to 20

20

ETQP6F1R8FA

CDEP134-2R7MC-H

SUMIDA

2.7

15

12/29

L6910 - L6910A

Figure 13. PCB and Components Layouts

Component Side

Internal Signal GND Layer

Figure 14. PCB and Components Layouts

Internal Power GND Layer

Solder Side

Figure 15. Efficiency vs Output Current

100

95

Vo=3.3V

Vo=2.5V

90

Vo=1.8V

Vo=1.5V

85

Vo=1.2V

Vo=0.9V

15

Vin=Vcc=5V

80

Fsw=200KHz

75

1

3

5

7

9

11

13

17

Output Current (A)

13/29

L6910 - L6910A

Figure 16. Efficiency vs Output Current

100

95

90

85

80

75

70

65

Vo=5V

Vo=3.3V

Vo=1.5V

Vo=1.8V

Vo=2.5V

Vo=1.2V

Vo=0.9V

Vin=Vcc=12V

Fsw.=200KHZ

60

55

50

1

3

5

7Output Cur9rent (A) 11

13

15

17

Output Current (A)

6 COMPONENTS SELECTION

6.1 Inductor Selection

To select the right inductor value, the application conditions must be fixed. For example we can consider:

Vin=12V Vout =3.3V Iout=15A

Considering a ripple of approximately 25% to 30% of Iout, the inductor value will be L=3

An iron powder core (TO50-52B) with 7 windings has been chosen.

µH.

6.2 Output Capacitors

2 POSCAP capacitors, model 6TPB330M, have been chosen, with a maximum ERS equal to 40m

Ω each.

Therefore, the resultant ESR is of 20m

Ω

. Considering a current ripple of 4A, the output voltage ripple is:

∆

Vout = 4 · 0.02 = 80mV

6.3 Input Capacitors

For I

= 15A and D = 0.5 (worst case for input current ripple), the RMS current of the input capacitor is equal

OUT

to 7.5A.

Two OSCON electrolytic capacitors 6SP680M, with a maximum ESR equal to 13m

tain the ripple. Therefore, the resultant ESR is equal to 13mΩ/2 = 6.5mΩ. The losses, in worst case, are:

Ω

, have been chosen to sus-

2

P = ESR · I rms = 366mW

6.4 Over-Current Protection

The current limit can be set to approximately 20A. Substituting the demo board parameters in the relation-

ship reported in the relative section, (I_OSCMIN=170µA; IP = 20A; R_DSONMAX= 9mΩ / 2=4.5mΩ) it results

that R_OCS= 510Ω

14/29

L6910 - L6910A

6.5 APPLICATION SUGGESTIONS FOR HIGHER CURRENTS

For higher output currents, up to 20A, the following configuration can be used (with reference to the demo board

schematic):

Q1,Q2,Q3: STS11NF30L

Q4,Q5,Q6: STS17NF3LL

L: 2.5µH Magnetic 77121A7 Core 7T 2x AWG16

In these conditions, the following performance have been achieved:

Table 8.

V

(V)

V

OUT

(V)

I

(A)

V

(V)

V

OUT

(V)

I

(A)

OUT

η (%)

81

η (%)

80

IN

OUT

IN

5

1.2

1.5

1.8

2.5

3.3

20

12

1.2

1.5

1.8

2.5

3.3

5

20

5

20

83

12

20

83

85

89

88

91

93

For currents higher than 20A, bigger mosfets should be selected (e.g. STS25NH3LL) both for the high side and

low side (depending on the duty cycle and input voltage).

7 6A DEMO BOARD DESCRIPTION

A compact demo board has been realized to manage currents in the range of 5A-6A .

The external power mosfets are included in a single SO8 package to save space and increase power density.

Two separate rails are provided, for V and V . They can be connected together by shorting the jumper J1.

CC

IN

The PGOOD signal is used as a logic level and it's been pulled up to V because there's no other appropriate

IN

voltage available on the demo board. In case of input voltage higher than 7V (PGOOD Pin Maximum Ab-

solute Rating) a 5V reference is required.

Figure 17. 6A Demo Board Schematic

VIN

R7

C7

J1

GNDIN

D1

C6

UGATE

PHASE

LGATE

PGND

C1-C2

BOOT

OCSET

12

R8

R9

R6

VCC

3

15

11

VCC

L1

Q1/Q1

Q2/Q1

C5

10

14

13

9

VOUT

GND

GNDCC

7

R11

C10

R2

U1

L6910

D2

SS

OSC

C3-4

4

2

8

GNDOUT

PWRGD

C9

C8

PGOOD

VREF

EAREF

1

5

6

VFB

COMP

R10

R3

R5

C19

C20

R4

C18

R1

15/29

L6910 - L6910A

Table 9. Part List

Reference

Resistor

R1

Description

Manufacturer

2K7 Ohm 0805 5% 125mW

1K8 Ohm 0805 5% 125mW

1K Ohm 0805 5% 125mW

10K 5% 125mW

NEOHM

(Vout = 2.5V)

(Vout = 3.3V)

(Vout = 5V)

SMD 0805

R2

R3

4K7 5% 125mW

2K7 5% 125mW

10 Ohm 5% 125mW

680 Ohm 5% 125mW

2.2 Ohm 5% 125mW

N.C

R4

R5

R6

R7

R8 R9

R10

R11

N.C

Capacitors

C1,C2

C3,C4

C5,C6,C9

C7,C8

C10

10µF 25V

100µF - 6.3V

100nF

1nF

TOKIN

POSCAP 6TPB100M

KEMET

C34Y5U1E106ZTE12

SMD7343

SMD0805

KEMET

SMD0805

N.C

C18

1.5nF

KEMET

SMD0805

C19

15nF

C20

47nF

Magnetics

L1

Transistor

Q1

7µH (T50-52B Core, 12T AWG 21)

STS8DNF3LL

MICROMETALS

ST

Diodes

D1

1N4148

SOT23

SMB

D2

STPS2L25U

ST

Device

U1

Device L6910

SO16Narrow

Table 10. Other inductor manufacturer

Manufacturer

WÜRTH ELEKTRONIK

PANASONIC

Series

744 382

Inductor Value (µH)

Saturation Current (A)

4.8 to 5.8

4.6 to 6.4

6 to 8

7.5 to 8

9.3 to 7.9

7.2 to 9.6

5.4

ETQP6F

SUMIDA

CDEP134-H

DO3316P-472HC

DO3340P

COILCRAFT

4.7

10 to 22

8.2

8 to 5.5

7.8

COILTRONICS

16/29

DR125-8R2

L6910 - L6910A

Figure 18. PCB and Components Layouts

Component Side

Solder Side

7.1 Compact Demo Board Performances

Figures 19, 20 show the measured efficiency versus load current for different values of output voltage. The mea-

sure has been done at 5V and 12V input. Output voltage has been changed modifying the value of R1 in the

demo board as reported in the part list.

Figure 19. Efficiency vs. Output Current

100

95

Vo=3.3V

90

Vo=2.5V

85

Vo=1.8V

80

Vo=1.5V

Vin=Vcc=5V

Fsw=200KHz

75

Vo=1.2V

70

1

2

3

4

5

6

7

8

Output Current (A)

Figure 20. Efficiency vs. Output Current

95

90

85

80

Vo=5V

Vo=3.3V

Vo=2.5V

Vo=1.8V

Vo=1.5V

Vin=Vcc=12V

Fsw=200KHz

75

Vo=1.2V

70

1

2

3

4

5

6

7

8

Output Current (A)

17/29

L6910 - L6910A

8 15A HTSSOP16 DEMO BOARD DESCRIPTION

A specific Demo Board has been realized for the HTSSOP16 package. The features are the same of the 15A

Demo Board previously described but thermal performance are improved. The PGOOD signal is used as a logic

level and it's been pulled up to V because there's no other appropriate voltage available on the demo board.

IN

In case of input voltage higher than 7V (PGOOD Pin Maximum Absolute Rating) a 5V reference is re-

quired

.

Figure 21. 15A HTSSOP16 Demo Board Schematic

L1

F1

VIN

R7

C14

G2

GNDIN

D1

C13

UGATE

PHASE

LGATE

PGND

C1-C3

BOOT

OCSET

R14

R15

13

3

R6

VCC

12

16

8

L2

Q1-3

Q4-6

C17

C15

VOUT

11

15

GND

GNDCC

R16

C23

U1

L6910A

D2

R2

SS

OSC

C4 -11

4

2

GNDOUT

PWRGD

14

10

1

PGOOD

VREF

EAREF

Ref IN

9

+Vref

C12

6

7

C16

GNDref

R8

C21

GNDRef

R1

R3

R9

R5

C19

C20

R4

C22

C18

S1

S2

S3

S4

S5

Vout

S2 S3 S4 S5

R10

0.9

1.2

1.5

1.8

2.5

3.3

5.0

R11

R12

R13

Open Open Open Open

ON

Open Open Open

ON

Open

Open Open

ON ON

ON

Open Open

Open

ON

Open Open Open

ON ON

Open Open

Table 11. Part List

Reference

R1

Description

Manufacturer

N.C

R2

R3

R4

R5

R6

R7

10K

4.7K

1K Ohm

2.7K

10 Ohm

560 Ohm

5% 125mW

NEOHM

SMD 0805

R8

R9

N.C

0 Ohm

5% 125mW

NEOHM

SMD 0805

R10

R11

R12

R13

R14

R15

R16

C1,C3

14K

6.98K

2.61K

1.74K

5% 125mW

0 Ohm

N.C

100uF 20V

OSCON

20SA100M

POSCAP

RADIAL 10X10.5

SMD7343

C9,C10

330uF - 6.3V

6TPB330M

18/29

L6910 - L6910A

Table 11. Part List (continued)

Reference

Description

Manufacturer

C12,C13,

100nF

KEMET

SMD0805

C15,C21,C16

C14

C17

C18

C19

C20

C22

C23

L1

1nF

4.7uF - 16V

1.5nF

15nF

KEMET

AVX

KEMET

SMD0805

SMA6032

SMD0805

47nF

N.C

Short

L2

3uH T50-52B Core, 7T AWG15

STS11NF30L

1N4148

MICROMETALS

SO8

SOT23

SMB

HTSSOP16

Q2,Q3,Q4,Q6

ST

D1

D2

U1

STPS340U

Device L6910

Short

ST

F1

SWITCH

DIP SWITCH

Table 12. Other inductor manufacturer

Manufacturer

WÜRTH ELEKTRONIK

PANASONIC

Series

744318

Inductor Value (µH)

Saturation Current (A)

1.8 to 2.7

16 to 20

20

ETQP6F1R8FA

CDEP134-2R7MC-H

1.8

SUMIDA

2.7

15

Figure 22. PCB and Components Layout

Component Side

Internal Power GND Layer

Solder Side

Internal Signal GND Layer

19/29

L6910 - L6910A

9 APPLICATION IDEA 1: DDR MEMORY AND TERMINATION SUPPLY

Double Data Rate (DDR) Memories require a particular Power Management Architecture. This is due to the fact

that the trace between the driving chipset and the memory input must be terminated with resistors.

Since the Chipset driving the Memory has a push pull output buffer, the Termination voltage must be capable

of sourcing and sinking current.

Moreover, the Termination voltage must be equal to one half of the memory supply (the input of the memory is

a differential stage requiring a reference bias midpoint) and in tracking with it. For DDRI the Memory Supply is

2.5V and the Termination voltage is 1.25V while, for DDRII, the Memory Supply is 1.8V and the Termination

voltage is 0.9V. Fig. 23 shows a complete DDRI Memory and Termination Power Supply realized by using 2 x

L6910. The 2.5V section is powering the memory while the 1.25V section is providing the termination voltage.

The tracking between the two sections is realized by providing the EAREF voltage of the 1.25V section through

a resistor divider connected to the 2.5V.

Figure 23. Application idea : DDR Memory Supply

VIN

12V

BOOT

OCSET

11

12

15

3

VCC

GND

UGATE

PHASE

LGATE

STS11NF3LL

DDR

VREF

10

14

7

MEMORY

V_DDQ

U1

STS11NF3LL

PGND

SS

OSC

4

2

8

2.5V@15A

PWRGD

L6910

13

9

PGOOD

VREF

EAREF

TERMINATION

NETWORK

1

6

5

VIN

12V

STS8DNF3LL

BOOT

12

OCSET

11

3

VCC

UGATE

PHASE

LGATE

PGND

15

CHIPSET

10

GND

7

U2

L6910

14

V_TT

SS

OSC

4

2

8

13

9

+

1.25V@ - 5A

PWRGD

R

PGOOD

VREF

EAREF

1

6

5

R

-

+

The current required by the memory and the termination supply, depends on the memory type and size.

The figure 24, 25 shows the efficiency of the L6910 for the termination section of the application shown in fig.

23, in sink and source mode. The figures show the efficiency values also when the input voltage is coming di-

rectly from the 12V rail.

20/29

L6910 - L6910A

Figure 24. Efficiency vs Output Current Source

Mode

Figure 27. Efficiency vs Output Current Sink

Mode

95

90

100

90

Vin=2.5V

85

Vin=1.8V

80

70

Vin=12V

75

Vcc=12V

70

60

Vcc=12V

Vout=0.9V

Fsw=200KHz

Vout=1.25V

Fsw=200KHz

50

65

60

40

1

2

3

4

5

6

7

1

3

5

7

9

11 13 15 17

8

Output Current (A)

Figure 25. Efficiency vs Output Current Sink

Mode

Figure 28. Efficiency vs Output Current Source

Mode

95

90

85

100

Vout=2.5V

90

Vin=2.5V

80

75

Vout=12V

70

65

60

Vcc=12V

Vout=1.25V

Fsw=200KHz

Vcc=12V

Vout=1.25V

Fsw=200KHz

Vin=12V

60

1

2

3

4

5

6

7

8

50

Output Current (A)

1

3

5

7

9

11 13 15 17

Output Current (A)

For very big systems (e.g. servers), the DDR memory

termination can require much higher currents, in the

range of 10A-15A and more.

Figures 26, 27 and 28, 29 show the efficiency of the

L6910 in sink and source mode, up to 17A both for DDRI

and DDRII memories.The measurements have been re-

alized with the 15A demo board. (See pag.11 )

Figure 29. Efficiency vs Output Current Source

Mode

100

90

Figure 26. Efficiency vs Output Current Sink

Mode

Vin=1.8V

80

Vin=12V

100

70

90

Vin=12V

Vout=0.9V

60

Vin=2.5V

Fsw=200KHz

80

Vin=12V

50

1

3

5

7

9

11 13 15 17

70

Vcc=12V

Vout=1.25V

Output Current (A)

60

Fsw=200KHz

50

1

3

5

7

9

11 13 15 17

Output Current (A)

21/29

L6910 - L6910A

10 APPLICATION IDEA 2: POSITIVE BUCK-BOOST REGULATOR 3V TO 13.2V

INPUT / 5V 2.5A OUTPUT

In some applications the input voltage changes in a very wide range while the output must be regulated to a

fixed value. In this case a Buck-Boost topology can be required in order to keep the output voltage in regulation.

The schematic below shows how to implement a Buck-Boost regulating 5V at the output from both 3.3V and 5V

and 12V input buses.

In a Buck-Boost topology the current is delivered to the output during the OFF phase only. So, for a given current

limit, the maximum output current depends strongly on the duty cycle. Assuming a 100% efficiency and neglect-

ing the current ripple across the inductor, the relationship betweent the current limit and the maximum output

current is the following:

I_OMAX= I_LIM⋅ (1 – D)

Where I

is the current limit and D is the duty cycle of the application.

LIM

The worst case is with D

. Since, in a Buck-Boost application, D is given by the following formula:

MAX

V_O

D = ----------------------

V

_IN+ V_O

The worst case is with V

.

INMIN

Obviously, since the efficiency is lower than 100% and the ripple is usually not negligible, the maximum output

current is always lower than the value calculated in the above formula

Figure 30. Positive buck-boost regulator 3V to 13.2V input / 5V 2.5A Output Circuit

VIN (3.3V-5V-12V BUSES)

C3

R1

G1

GNDIN

D1

C4

C1-C2

Q4

BOOT

OCSET

12

R7

VCC (12V BUS)

3

VCC

UGATE

15

11

10

14

13

9

L1

Q1

Q2

C6

C5

VOUT ( 5V 2.5A )

PHASE

LGATE

PGND

GND

GNDCC

7

R2

U1

L6910/A

D2

SS

OSC

Q3

C13-14

4

2

8

GNDOUT

PGOOD

VREF

EAREF

1

C8

C7

5

6

C12

R3

R5

C9

C11

R4

C10

R6

22/29

L6910 - L6910A

Table 13. Part List

Reference

R1

Description

910 Ohm 5% 125mW

10K 5% 125mW

4.7K 5% 125mW

1K 5% 125mW

2.7K 5% 125mW

1K1

Manufacturer

NEOHM

SMD 0805

RADIAL 10X10.5

SMD7343

R2

NEOHM

R3

NEOHM

R4

NEOHM

R5

NEOHM

R6

NEOHM

R7

10 Ohm 125mW

100µF - 20V

330µF - 6.3V

100nF

NEOHM

C1,C2

C13,C14

C12,C5,C8

C3

OSCON 20SA100M

POSCAP 6TPB330M

KEMET

SMD0805

1nF

KEMET

SMD0805

C4

470nF

KEMET

SMD0805

C6

4.7µF - 16V

100nF

AUX

SMA6032

C7

KEMET

C9

15nF

KEMET

SMD0805

C10

C11

G1

1.5nF

KEMET

47nF

KEMET

Open

Jumper

L1

Q1,Q2,Q3

Q4

2.5µH (77121A7 Core, Double winding 7 AWG16)

MAGNETICS

ST

STS11NF30L

STS5P30L

SO8

ST

D1

1N4148

SOT23

D2

STPS3L25U (STPS340U)

Device L6910

ST

SMB (D0144)

SO16 Narrow

U1

Figure 31. Efficiency vs. Output Current

90

Vin=5V

85

Vin=12V

80

75

Vin=3.3V

Vcc=5V

70

Vout=5V

Fsw=200KHz

65

1

1.5

2

2.5

3

3.5

Output Current (A)

23/29

L6910 - L6910A

11 APPLICATION IDEA 3: BUCK-BOOST REGULATOR 3V TO 5.5V INPUT/-5V

3A OUTPUT

In applications where a negative output voltage is required, a standard Buck-Boost topology can be implement-

ed. The considerations related to the maximum output current are the same of the "Positive Buck-Boost" (Ap-

plication Idea 2).

A particularity of this topology is that the device undergoes a voltage that is the sum of V and V

. So, con-

IN

OUT

verting 5V to -5V, the device undergoes 10V voltage. It must be checked that the sum of the input and output

voltage is lower than the maximum operating input voltage of the device.

Figure 32. buck-boost regulator 3V to 5.5V input / -5V 3A Output Circuit

VIN (3V to 5.5V )

R1

G1

C3

C1-C2

GNDIN=GNDOUT

D1

C4

BOOT

12

OCSET

3

R7

VCC

C5

UGATE

PHASE

LGATE

PGND

15

7

11

VCC (5V)

GNDCC

L1

Q1

Q2

C6

10

14

13

9

GNDOUT

GND

C13 14

U1

L6910/A

D2

-

SS

OSC

VOUT (-5V 3A)

4

2

8

PGOOD

VREF

EAREF

1

C7

5

6

C8

C12

R3

R5

C9

C11

R4

C10

R6

Table 14. Part List

Reference

Description

Manufacturer

NEOHM

R1

910 Ohm 5% 125mW

10K 5% 125mW

4.7K 5% 125mW

1K Ohm 5% 125mW

2.7K 5% 125mW

1K 5% 125mW

10 Ohm 5% 125mW

100µF - 20V

SMD 0805

RADIAL 10X10.5

SMD7343

R2

R3

R4

R5

R6

R7

C1,C2

C13,C14

C12,C4,C5,C8

C3

OSCON 20SA100M

POSCAP 6TPB330M

KEMET

330µF - 6.3V

100nF

SMD0805

1nF

KEMET

SMD0805

C6

4.7µF - 16V

AUX

SMA6032

C7

100nF

KEMET

24/29

L6910 - L6910A

Table 14. Part List (continued)

C9

C10

15nF

1.5nF

KEMET

SMD0805

Reference

C11

Description

47nF

Manufacturer

KEMET

SMD0805

G1

Open

Jumper

L1

Q1,Q2

D1

2.5µH (77121A7 Core, Double winding 7 AWG16)

MAGNETICS

ST

STS11NF30L

1N4148

SO8

SOT23

D2

STPS3L25U ( STPS340U)

Device L6910

ST

SMB (D0144)

SO16 Narrow

U1

Figure 33. Efficiency vs. Output Current

94

92

90

88

Vin=5V

Vin=3.3V

86

Vcc=5V

Vout= -5V

Fsw=200KHz

84

82

1

1.5

2

2.5

3

Output Current (A)

25/29

L6910 - L6910A

Figure 34. HTSSOP16 (Exposed pad) Mechanical Data & Package Dimensions

mm

inch

DIM.

OUTLINE AND

MECHANICAL DATA

MIN. TYP. MAX. MIN.

TYP. MAX.

0.047

A

A1

A2

b

1.2

0.15

0.006

0.8

0.19

0.09

4.9

1.0

5.0

1.05 0.031 0.039 0.041

0.3

0.2

5.1

0.007

0.003

0.012

0.008

c

D (*)

D1

E

0.192 0.197 0.200

0.067

1.7

6.2

6.4

4.4

6.6

4.5

0.244 0.252 0.260

0.169 0.173 0.177

0.059

E1 (*)

E2

e

4.3

1.5

0.65

0.6

0.026

L

0.45

0.75 0.018 0.024 0.029

0.039

L1

k

1.0

0˚ (min), 8˚ (max)

aaa

0.10

0.004

HTSSOP16

(Exposed Pad)

(*) Dimensions D and E1 does not include mold flash or

protusions. Mold flash or protusions shall not exeed

0.15mm per side.

7419276

26/29

L6910 - L6910A

Figure 35. SO-16 (Narrow) Mechanical Data & Package Dimensions

mm

inch

DIM.

OUTLINE AND

MECHANICAL DATA

MIN. TYP. MAX. MIN.

TYP. MAX.

0.069

A

a1

a2

b

1.75

0.1

0.25 0.004

1.6

0.009

0.063

0.35

0.19

0.46 0.014

0.25 0.007

0.018

b1

C

0.010

0.5

0.020

c1

45°

(typ.)

0.386

(1)

D

9.8

5.8

10

0.394

E

e

6.2

0.228

0.244

0.050

1.27

8.89

e3

0.350

(1)

F

3.8

4.0

0.150

0.157

G

L

4.60

0.4

5.30 0.181

1.27 0.150

0.62

0.208

0.050

0.024

M

S

8 ° (max.)

SO16 (Narrow)

(1) "D" and "F" do not include mold flash or protrusions - Mold

flash or protrusions shall not exceed 0.15mm (.006inc.)

0016020 D

27/29

L6910 - L6910A

Table 1. Revision History

Date

Revision

Description of Changes

Migration from ST-Press to EDOCS dms.

January 2004

August 2004

7

8

Changed any figures and textes; add. the section “15A HTSSOP16

Demo Board Description”.

Changed the style-look following the new “Corporate Technical

Pubblications Design Guide” rules; and figs 23, 30, 32

May 2005

9

Changed the figure 30.

28/29

L6910 - L6910A

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

STMicroelectronics group of companies

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www.st.com

29/29


型号：	L6910_05
厂家：	ST
描述：	ADJUSTABLE STEP DOWN CONTROLLER WITH SYNCHRONOUS RECTIFICATION 采用同步整流可调降压控制器控制器
文件：	总29页 (文件大小：683K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

L6910_05 [STMICROELECTRONICS]

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