L6910ATR_技术文档

L6910

L6910A

ADJUSTABLE STEP DOWN CONTROLLER

WITH SYNCHRONOUS RECTIFICATION

FEATURE

■ OPERATING SUPPLY VOLTAGE FROM 5V

TO 12V BUSES

■ UP TO 1.3A GATE CURRENT CAPABILITY

■ ADJUSTABLE OUTPUT VOLTAGE

■ N-INVERTING E/A INPUT AVAILABLE

■ 0.9V ±1.5% VOLTAGE REFERENCE

■ VOLTAGE MODE PWM CONTROL

■ VERY FAST LOAD TRANSIENT RESPONSE

■ 0% TO 100% DUTY CYCLE

SO-16 (Narrow)

ORDERING NUMBERS:

(SO-16) L6910A

HTSSOP16 (Exposed Pad)

L6910

(HTSSOP16)

L6910TR (Tape & Reel) L6910ATR (Tape & Reel)

■ POWER GOOD OUTPUT

■ OVERVOLTAGE PROTECTION

■ HICCUP OVERCURRENT PROTECTION

■ 200kHz INTERNAL OSCILLATOR

■ OSCILLATOR EXTERNALLY ADJUSTABLE

FROM 50kHz TO 1MHz

DESCRIPTION

The device is a pwm controller for high performance

dc-dc conversion from 3.3V, 5V and 12V buses.

The output voltage is adjustable down to 0.9V; higher

voltages can be obtained with an external voltage di-

vider.

■ SOFT START AND INHIBIT

■ PACKAGES: SO-16 & HTSSOP16

High peak current gate drivers provide for fast switch-

ing to the external power section, and the output

current can be in excess of 20A.

APPLICATIONS

■ SUPPLY FOR MEMORIES AND TERMI-

NATIONS

■ COMPUTER ADD-ON CARDS

■ LOW VOLTAGE DISTRIBUTED DC-DC

■ MAG-AMP REPLACEMENT

The device assures protections against load overcur-

rent and overvoltage. An internal crowbar is also pro-

vided turning on the low side mosfet as long as the

over-voltage is detected. In case of over-current de-

tection, the soft start capacitor is discharged and the

system works in HICCUP mode.

BLOCK DIAGRAM

Vin 5V to12V

PGOOD

VCC

OCSET

BOOT

VREF

SS

Monitor

UGATE

Protection and Ref

OSC

PHASE

OSC

Vo

RT

LGATE

L6910

PGND

-

+

EAREF

E/A

PWM

+

-

GND

VFB

300k

COMP

July 2003

1/21

L6910A L6910

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

15

Unit

V

Vcc

Vcc to GND, PGND

Boot Voltage

V

-

15

V

BOOT

V

PHASE

V

-

15

V

HGATE

V

PHASE

OCSET, LGATE, PHASE

-0.3 to Vcc+0.3

V

SS, FB, PGOOD, VREF, EAREF, RT

COMP

7

6.5

V

T

Junction Temperature Range

Storage temperature range

Maximum power dissipation at Tamb = 25°C

-40 to 150

1

°C

W

j

T

stg

P

tot

THERMAL DATA

Symbol

Parameter

SO-16

HTSSOP16 HTSSOP16 (*)

Unit

R

Thermal Resistance Junction to Ambient

120

110

50

°C/W

th j-amb

(*) Device soldered on 1 S2P PC board

PINS CONNECTION (Top view)

VREF

OSC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

N.C.

VREF

OSC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

VCC

LGATE

PGND

BOOT

OCSET

SS/INH

COMP

FB

LGATE

PGND

BOOT

HGATE

PHASE

PGOOD

OCSET

SS/INH

N.C.

HGATE

PHASE

PGOOD

EAREF

COMP

FB

GND

EAREF

GND

SO16

HTSSOP-16

2/21

L6910A L6910

PINS FUNCTION

SO HTSSOP Name

Description

1

VREF Internal 0.9V ±1.5% reference is available for external regulators or for the internal error

amplifier (connecting this pin to EAREF) if external reference is not available.

A minimum 1nF capacitor is required.

If the pin is forced to a voltage lower than 70%, the device enters the hiccup mode.

2

OSC

Oscillator switching frequency pin. Connecting an external resistor (R ) from this pin to

T

GND, the external frequency is increased according to the equation:

4.94 10⁶

f_OSC,RT= 200KHz + -------------------------

R_T(KΩ)

Connecting a resistor (R ) from this pin to Vcc (12V), the switching frequency is reduced

T

according to the equation:

4.306 10⁷

f _OSC,RT= 200KHz – ----------------------------

R_T(KΩ)

If the pin is not connected, the switching frequency is 200KHz.

The voltage at this pin is fixed at 1.23V. Forcing a 50µA current into this pin, the built in

oscillator stops to switch.

In Over Voltage condition this pin goes over 3V until that conditon is removed.

3

4

3

4

OCSET A resistor connected from this pin and the upper Mos Drain sets the current limit

protection.

The internal 200µA current generator sinks a constant current through the external

resistor. The Over-Current threshold is due to the following equation:

I

R_OCSET

I _P= --^O----^C----^S----^E---^T----------------------------

R_DSon

SS/INH The soft start time is programmed connecting an external capacitor from this pin and

GND. The internal current generator forces through the capacitor 10µA.

This pin can be used to disable the device forcing a voltage lower than 0.4V

5

6

7

COMP This pin is connected to the error amplifier output and is used to compensate the voltage

control feedback loop.

FB

This pin is connected to the error amplifier inverting input and is used to compensate the

voltage control feedback loop.

Connected to the output resistor divider, if used, or directly to Vout, it manages also over-

voltage conditions and the PGOOD signal

7

8

9

GND

All the internal references are referred to this pin. Connect it to the PCB signal ground.

EAREF Error amplifier non-inverting input. Connect to this pin an external reference (from 0.9V to

3V) for the PWM regulation or short it to VREF pin to use the internal reference.

If this pin goes under 650mV (typ), the device shuts down.

9

10

11

PGOOD This pin is an open collector output and it is pulled low if the output voltage is not within the

above specified thresholds. If not used it may be left floating.

10

PHASE This pin is connected to the source of the upper mosfet and provides the return path for the

high side driver. This pin monitors the drop across the upper mosfet for the current limit

together with OCSET.

11

12

13

HGATE High side gate driver output.

12

BOOT Bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper

mosfet. Connect through a capacitor to the PHASE pin and through a diode to Vcc

(cathode vs. boot).

13

14

PGND Power ground pin. This pin has to be connected closely to the low side mosfet source in

order to reduce the noise injection into the device

14

15

‘5

LGATE This pin is the lower mosfet gate driver output

16

VCC

Device supply voltage. The operative supply voltage ranges is from 5V to 12V.

DO NOT CONNECT V TO A VOLTAGE GREATER THAN V

.

CC

IN

16

5

N.C.

This pin is not internally bonded. It may be left floating or connected to GND.

3/21

L6910A L6910

ELECTRICAL CHARACTERISTICS (V = 12V, T =25°C unless otherwise specified)

cc

J

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

V

SUPPLY CURRENT

cc

Icc

Vcc Supply current

OSC = open; SS to GND

4

7

9

mA

POWER-ON

Turn-On Vcc threshold

Turn-Off Vcc threshold

VOCSET = 4V

4.0

3.8

4.3

4.1

4.6

4.4

1.4

750

V

Rising V

threshold

1.24

650

V

OCSET

Turn On EAREF threshold

SOFT START AND INHIBIT

VOCSET = 4V

mV

Iss

Soft start Current

S.S. current in INH condition

SS = 2V

SS = 0 to 0.4V

6

10

35

14

60

µA

OSCILLATOR

f

Initial Accuracy

OSC = OPEN

OSC = OPEN; T = 0° to 125°

180

170

200

1.9

220

230

KHz

kHz

OSC

j

f

Total Accuracy

16 KΩ < R to GND < 200 KΩ

-15

15

%

V

OSC,RT

T

∆Vosc Ramp amplitude

REFERENCE

V

OUT

V

REF

V

REF

Output Voltage Accuracy

Reference Voltage

V

OUT

C

REF

C

REF

= V ; V

= V

REF

0.886

-2

0.900

0.913

+2

V

FB

EAREF

= 1nF; I

= 0 to 100µA

REF

Reference Voltage

= 1nF; T = 0 to 125°C

%

J

ERROR AMPLIFIER

I

N.I. bias current

V

= 3V

10

µA

kΩ

µA

V

EAREF

EAREF Input Resistance

I.I. bias current

Vs. GND

= 0V to 3V

300

0.01

I

V

0.5

3

FB

V

Common Mode Voltage

Output Voltage

0.8

0.5

70

CM

V

4

V

COMP

G

Open Loop Voltage Gain

85

10

dB

V

GBWP Gain-Bandwidth Product

SR Slew-Rate

GATE DRIVERS

MHz

V/µs

COMP = 10pF

I

High Side

Source Current

V

- V = 12V

PHASE

1

1.3

2

A

HGATE

BOOT

- V

= 6V

HGATE

PHASE

R

High Side

V

- V = 12V

PHASE

4

Ω

HGATE

BOOT

Sink Resistance

I

Low Side Source Current

Low Side Sink Resistance

Output Driver Dead Time

Vcc = 12V; V

Vcc = 12V

= 6V

0.9

1.1

1.5

A

Ω

LGATE

R

3

LGATE

PHASE connected to GND

90

210

ns

PROTECTIONS

OCSET Current Source

I

V

= 4V

OCSET

170

200

117

30

230

120

µA

%

OCSET

Over Voltage Trip (V / V

)

Rising

FB

EAREF

FB

I

OSC Sourcing Current

> OVP Trip

15

mA

OSC

POWER GOOD

Upper Threshold (V / V

)

V

Rising

Falling

108

88

110

90

2

112

92

%

V

FB

EAREF

FB

Lower Threshold (V / V

FB

Hysteresis (V / V

)

EAREF

Upper and Lower threshold

FB

V

PGOOD Voltage Low

I

= -4mA

= 6V

0.4

0.2

PGOOD

I

Output Leakage Current

V

1

µA

PGOOD

4/21

L6910A L6910

Device Description

The device is an integrated circuit realized in BCD technology. The controller provides complete control logic and

protection for a high performance step-down DC-DC converter. It is designed to drive N Channel Mosfets in a

synchronous-rectified buck topology. The output voltage of the converter can be precisely regulated down to

900mV with a maximum tolerance of ±1.5% when the internal reference is used (simply connecting together

EAREF and VREF pins). The device allows also using an external reference (0.9V to 3V) for the regulation. The

device provides voltage-mode control with fast transient response. It includes a 200kHz free-running oscillator that

is adjustable from 50kHz to 1MHz. The error amplifier features a 10MHz gain-bandwidth product and 10V/µs slew

rate that permits to realize high converter bandwidth for fast transient performance. The PWM duty cycle can

range from 0% to 100%. The device protects against over-current conditions entering in HICCUP mode. The de-

vice monitors the current by using the r

of the upper MOSFET(s) that eliminates the need for a current

DS(ON)

sensing resistor. The device is available in SO16 narrow package.

Oscillator

The switching frequency is internally fixed to 200kHz. The internal oscillator generates the triangular waveform

for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the

oscillator is typically 50µA (F = 200KHz) and may be varied using an external resistor (R ) connected between

sw T

OSC pin and GND or V . Since the OSC pin is maintained at fixed voltage (typ. 1.235V), the frequency is var-

CC

ied proportionally to the current sunk (forced) from (into) the pin.

In particular connecting R vs. GND the frequency is increased (current is sunk from the pin), according to the

T

following relationship:

6

4.94 10

f

= 200KHz + -------------------------

OSC,RT

R (KΩ)

T

Connecting R to V = 12V or to V = 5V the frequency is reduced (current is forced into the pin), according

T

CC

to the following relationships:

7

4.306 10

f

= 200KHz – ----------------------------

V

CC

= 12V

OSC,RT

R (KΩ)

T

6

15 10

f

= 200KHz – ---------------------

V

CC

= 5V

OSC,RT

R (KΩ)

T

Switching frequency variation vs. RT are repeated in Fig. 1.

Note that forcing a 50

µ

A current into this pin, the device stops switching because no current is delivered to the

oscillator.

Figure 1.

Reference

A precise ±1.5% 0.9V reference is available. This ref-

erence must be filtered with 1nF ceramic capacitor to

avoid instability in the internal linear regulator. It is

10000

able to deliver up to 100µA and may be used as ref-

1000

100

10

erence for the device regulation and also for other de-

vices. If forced under 70% of its nominal value, the

device enters in Hiccup mode until this condition is

removed.

Through the EAREF pin the reference for the regula-

tion is taken. This pin directly connects the non-in-

verting input of the error amplifier. An external

reference (or the internal 0.9V ±1.5%) may be used.

The input for this pin can range from 0.9V to 3V. It

RT to GND

RT to VCC=12V

RT to VCC=5V

has an internal pull-down (300kΩ resistor) that forces

the device shutdown if no reference is connected (pin

floating). However the device is shut down if the volt-

age on the EAREF pin is lower than 650mV (typ).

10

100

1000

Frequency [kHz]

5/21

L6910A L6910

Soft Start

At start-up a ramp is generated charging the external capacitor C with an internal current generator. The initial

SS

value for this current is of 35µA and speeds-up the charge of the capacitor up to 0.5V. After that it becames

10 A until the final charge value of approximatively 4V.

µ

When the voltage across the soft start capacitor (V ) reaches 0.5V the lower power MOS is turned on to dis-

SS

charge the output capacitor. As V reaches 1.1V (i.e. the oscillator triangular wave inferior limit) also the upper

SS

MOS begins to switch and the output voltage starts to increase.

No switching activity is observable if SS is kept lower than 0.5V and both mosfets are off.

If VCC and OCSET pins are not above their own turn-on thresholds and V

is not above 650mV, the Soft-

EAREF

Start will not take place, and the relative pin is internally shorted to GND. During normal operation, if any under-

voltage is detected on one of the two supplies, the SS pin is internally shorted to GND and so the SS capacitor

is rapidly discharged.

Figure 2. Soft Start (with Reference Present)

Vcc Turn-on threshold

Vcc

Vin

Vin Turn-on threshold

1V

Vss

LGATE

Vout

to GND

0.5V

Acquisition: CH1 = PHASE; CH2 = V

;

out

Timing Diagram

CH3 = PGOOD; CH4 = V

ss

Driver Section

The driver capability on the high and low side drivers allows using different types of power MOS (also multiple

MOS to reduce the R ), maintaining fast switching transition.

DSON

The low-side mos driver is supplied directly by Vcc while the high-side driver is supplied by the BOOT pin.

Adaptative dead time control is implemented to prevent cross-conduction and allow to use several kinds of mos-

fets. The upper mos turn-on is avoided if the lower gate is over about 200mV while the lower mos turn-on is

avoided if the PHASE pin is over about 500mV. The lower mos is in any case turned-on after 200ns from the

high side turn-off.

The peak current is shown for both the upper (fig. 3) and the lower (fig. 4) driver at 5V and 12V. A 3.3nF capac-

itive load has been used in these measurements.

For the lower driver, the source peak current is 1.1A @ V = 12V and 500mA @ V = 5V, and the sink peak

CC

current is 1.3A @ V = 12V and 500mA @ V = 5V.

CC

Similarly, for the upper driver, the source peak current is 1.3A @ Vboot-Vphase = 12V and 600mA @ Vboot-

Vphase = 5V, and the sink peak current is 1.3A @ Vboot-Vphase =12V and 550mA @ Vboot-Vphase = 5V.

6/21

L6910A L6910

Figure 3. High Side driver peak current. Vboot-Vphase = 12V (right) Vboot-Vphase = 5V (left)

CH1 = High Side Gate CH4 = Gate Current

Figure 4. Low Side driver peak current. V = 12V (right) V = 5V (left)

CC

CH1 = Low Side Gate CH4 = Gate Current

Monitoring and Protections

The output voltage is monitored by means of pin FB. If it is not within ±10% (typ.) of the programmed value, the

powergood output is forced low.

The device provides overvoltage protection, when the voltage sensed on pin FB reaches a value 17% (typ.)

greater than the reference the OSC pin is forced high (3V typ.) and the lower driver is turned on as long as the

over-voltage is detected.

Overcurrent protection is performed by the device comparing the drop across the high side MOS, due to the

R , with the voltage across the external resistor (R ) connected between the OCSET pin and drain of the

DSON OCS

upper MOS. Thus the overcurrent threshold (I ) can be calculated with the following relationship:

P

R

I

OCS OCS

I

= --------------------------------

P

R

dsON

Where the typical value of I

is 200

µ

A. To calculate the R

value it must be considered the maximum

OCS

R

dsON

(also the variation with temperature) and the minimum value of I . To avoid undesirable trigger of

OCS

overcurrent protection this relationship must be satisfied:

7/21

L6910A L6910

∆I

I ≥ I

+ ---- = I

2

P

OUTMAX

PEAK

Where

∆

I is the inductance ripple current and I

is the maximum output current.

OUTMAX

In case of over current detectionthe soft start capacitor is discharged with constant current (10

µ

A typ.) and when

the SS pin reaches 0.5V the soft start phase is restarted. During the soft start the over-current protection is al-

ways active and if such kind of event occurs, the device turns off both mosfets, and the SS capacitor is dis-

charged again (after reaching the upper threshold of about 4V). The system is now working in HICCUP mode,

as shown in figure 5. After removing the cause of the over-current, the device restart working normally without

power supplies turn off and on.

Figure 5. Hiccup Mode

Figure 6. Inductor ripple current vs. Vout

9

L=1.5µH, Vin=12V

8

L=2µH,

Vin=12V

7

6

L=3µH,

Vin=12V

5

4

L=1.5µH,

Vin=5V

3

µ

L=2 H,

Vin=5V

2

1

0

L=3µH, Vin=5V

0.5

1.5

2.5

3.5

Output Voltage [V]

CH1 = SS; CH4 = Inductor current

Inductor design

The inductance value is defined by a compromise between the transient response time, the efficiency, the cost

and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain

the ripple current

∆I between 20% and 30% of the maximum output current. The inductance value can be cal-

L

culated with this relationship:

V

– V

V

OUT OUT

IN

L = ------------------------------ --------------

∆I

f

V

IN

sw

L

Where f

is the switching frequency, V is the input voltage and V

is the output voltage. Figure 6 shows

SW

IN

OUT

the ripple current vs. the output voltage for different values of the inductor, with V = 5V and V = 12V.

IN

Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter

response time to a load transient. If the compensation network is well designed, the device is able to open or

close the duty cycle up to 100% or down to 0%. The response time is now the time required by the inductor to

change its current from initial to final value. Since the inductor has not finished its charging time, the output cur-

rent is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance

required.

The response time to a load transient is different for the application or the removal of the load: if during the ap-

plication of the load the inductor is charged by a voltage equal to the difference between the input and the output

voltage, during the removal it is discharged only by the output voltage. The following expressions give approx-

imate response time for ∆I load transient in case of enough fast compensation network response:

L ∆I

= ------------------------------

L ∆I

t

= --------------

application

removal

V

– V

V

IN

OUT

The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst

case is the response time after removal of the load with the minimum output voltage programmed and the max-

imum input voltage available.

8/21

L6910A L6910

Output Capacitor

The output capacitor is a basic component for the fast response of the power supply. In fact, during load tran-

sient, for first few microseconds they supply the current to the load. The controller recognizes immediately the

load transient and sets the duty cycle at 100%, but the current slope is limited by the inductor value. The output

voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the ESL):

∆V

= ∆I

ESR

OUT

A minimum capacitor value is required to sustain the current during the load transient without discharge it. The

voltage drop due to the output capacitor discharge is given by the following equation:

2

∆I

L

OUT

∆V

= ---------------------------------------------------------------------------------------------

OUT

2 C

(V

D

– V

)

OUT

INMIN

MAX

Where D

is the maximum duty cycle value that is 100%. The lower is the ESR, the lower is the output drop

MAX

during load transient and the lower is the output voltage static ripple.

Input Capacitor

The input capacitor has to sustain the ripple current produced during the on time of the upper MOS, so it must

have a low ESR to minimize the losses. The rms value of this ripple is:

I

= I

D (1 – D)

OUT

rms

Where D is the duty cycle. The equation reaches its maximum value with D = 0.5. The losses in worst case are:

2

rms

P = ESR I

Compensation network design

The control loop is a voltage mode (figure 7). The output voltage is regulated to the input Reference voltage

level (EAREF). The error amplifier output V

is then compared with the oscillator triangular wave to provide

COMP

a pulse-width modulated (PWM) wave with an amplitude of V at the PHASE node. This wave is filtered by the

IN

output filter. The modulator transfer function is the small-signal transfer function of V

/V

. This function

OUT COMP

has a double pole at frequency F depending on the L-C resonance and a zero at F depending on the

LC

out

ESR

output capacitor ESR. The DC Gain of the modulator is simply the input voltage V divided by the peak-to-peak

IN

oscillator voltage

∆V

.

OSC

9/21

L6910A L6910

Figure 7. Compensation Network

Vin

∆

Vosc

L

Vout

ESR

PWM

Comparator

Cout

C18

R5

C19

R3

C20

R4

-

Vcomp

EAREF

+

The compensation network consists in the internal error amplifier and the impedance networks Z (R3, R4 and

IN

C20) and Z (R5, C18 and C19). The compensation network has to provide a closed loop transfer function with

FB

the highest 0dB crossing frequency to have fast response (but always lower than fsw/10) and the highest gain

in DC conditions to minimize the load regulation.

A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45°. Include

worst-case component variations when determining phase margin.

To locate poles and zeroes of the compensation networks, the following suggestions may be used:

Modulator singularity frequencies:

1

ω

= ---------------------------

ω

= --------------------------------

LC

ESR

ESR C

L C

OUT

Compensation network singularity frequency:

1

ω

= -----------------------------------------------

ω

= -----------------------

P1

P2

R4 C20

C18 C19

R5 ----------------------------

C18 + C19

1

ω

= -----------------------

ω

= ------------------------------------------

Z1

Z2

R5 C19

(R3 + R4) C20

– Put the gain R5/R3 in order to obtain the desired converter bandwidth;

– Place ω before the output filter resonance ω

;

LC

Z1

– Place ω at the output filter resonance ω

;

LC

Z2

– Place ω at the output capacitor ESR zero ω

;

ESR

P1

– Place ω at one half of the switching frequency;

P2

– Check the loop gain considering the error amplifier open loop gain.

10/21

L6910A L6910

Figure 8. Asymptotic Bode plot of Converter's gain

dB

Error Amplifier

R5/R3

Ζ1

P1

ω

LC

P2

ω

Ζ2

ω

Modulator Gain

ESR

ω

Compensation Network Gain

Error Amplifier Closed Loop Gain

20A Demo Board Description

The demo board shows the operation of the device in a general purpose application. This evaluation board al-

lows voltage adjustability from 0.9V to 5V through the switches S2-S5 according to the reported table when the

internal 0.9V reference is used (G1 closed). Output current in excess of 20A can be reached dependently on

the kind of mosfet used: up to three SO8 mosfet may be used for both High side and Low side switches. External

reference may be used for the regulation simply leaving open G1 and the switches S2-S5. The device may also

be disabled with the switch S1. The 12V input rail supplies the device while the power conversion starts from

the 5V input rail. The device is also able to operate with a single supply voltage; in this case the jumper G2 has

to be closed and a 5V to 12V input can be directly connected to the V input. The four layers demo board's

IN

copper thickness is of 70µm in order to minimize conduction losses considering the high current that the circuit

is able to deliver. Figure 9 shows the demo board's schematic circuit

Figure 9. 20A Demo Board Schematic

L1

F1

VIN

R7

C14

G2

GNDIN

D1

C13

C1-C3

BOOT

OCSET

12

15

VCC

UGATE

R6

3

VCC

11

Q1-3

Q4-6

L2

PHASE

LGATE

PGND

C17

C15

VOUT

10

14

13

9

GND

GNDCC

7

U1

L6910

SS

R2

D2

C4-11

4

2

8

GNDOU T

PWRGD

OSC

PGOOD

VREF

EAREF

Ref

IN

+Vref

1

C16

5

6

C12

GNDref

GNDRef

IN

C21

R1

R3

C19

R5

C20

R4

C18

G1

S1

S2

S3

S4

S5

Vout

S2 S3 S4 S5

R10

Open Open Ope n Open

0.9

1.2

1.5

1.8

2.5

3.3

5.0

R11

R12

R13

ON

Open Open Open

ON

Open

Open Open

ON ON

ON

Open Open

Open

ON

Open Open Open

ON ON

Open Open

11/21

L6910A L6910

Figure 10. PCB and Components Layouts

Component Side

Internal Signal GND Layer

Figure 11. PCB and Components Layouts

Internal Power GND Layer

Solder Side

Figures 10 and 11 show the demo board layout.

Considering the flexibility in the power mosfet configuration (up to three mosfet for both high side and low side),

it is possible to obtain different application idea with the same board.

In the following paragraphs, it will be described the standard demo-board configuration (8A) and the high current

configuration.

APPLICATION IDEA: 5V TO 12V INPUT; 0.9V TO 5V / 8A OUTPUT

This is a typical bus termination application in which the output voltage is programmed by the switch to 1.2V typ

(it can range from 0.9V to 5V) and the maximum output current is of 8A DC. The power mosfet are configured

with one STS12NF30L (30V, 10mΩ typ @ Vgs=4.5V ) for both hgih side and low side.

Inductor selection

Since the maximum output current is 8A, to have a 15% ripple (1A) in worst case the inductor chosen is 4.1

µH.

SUMIDA CEE125 series inductor has been chosen with a 4.2 A typical value.

µ

12/21

L6910A L6910

Output Capacitor

In the demo 5 POSCAP capacitors, model 6TPB330M, are used, with a maximum ESR equal to 40m

Therefore the resultant ESR is of 8m . For load transient of 8A in the worst case the voltage drop is of:

= 8 · 0.008 = 64mV

Ω

each.

Ω

∆

V

out

The voltage drop due to the capacitor discharge during load transient, considering that the maximum duty cycle

is equal to 100% results in 16.4mV with 1.2V of programmed output.

Input Capacitor

For I

= 8A and D=0.5 (worst case for input ripple current), Irms is equal to 4A. Three OSCON electrolytic

OUT

capacitors 20SA100M, with a maximum ESR equal to 30mΩ, are chosen to sustain the ripple. Therefore, the

resultant ESR is equal to 30m

Ω

/3 = 10m

Ω

. So the losses in worst case are:

2

rms

P = ESR ·

I

= 160mW

Over-Current Protection

The peak current is in this case equal to 12A, substituting the demo board parameters in the relationship report-

ed in the relative section, (I

= 170

µ

A; I = 12A; R

= 9mΩ

) it results that R

= 620Ω.

OCSMIN

P

DSONMAX

OCS

Table 1. Part List

R2

10k

SMD 0805

R3

4.7k

47k

1%

R5

R6

10

R7

620

R10

14k

E96 1%

R11

6.98k

2.61k

1.74k

100µ

330µ

100n

1n

E96 1% (optional)

OSCON - 20SA100M

POSCAP - 6TPB330M

Ceramic

R12

R13

C1

Radial 10x10.5mm

SMD 7343

C4…C11

C12, C13, C15, C21

SMD 0805

C14

C19

L1

Ceramic

SMD 0805

56n

Ceramic

SMD 0805

1.5µ

4.2µ

L6910

T44-52 Core, 7T-18AWG

SUMIDA CEE125 series

STMicroelectronics

Littlefuse

L2

U1

SO16 NARROW

SO8

Q1, Q4

D1

STS12NF30L

1N4148

SOT23

D2

STPS3340U

251015A-15°

SMB

F1

AXIAL

Efficiency

Figure 12 shows the measured efficiency versus load current for different values of output voltage. The measure

was done at V = 5V for different values of the output voltage (0.9V, 1.2V, 1.5V, 1.8V, 2.5V and 3.3V). IC supply

in

voltage is of 12V.

In the application one mosfets STS12NF30L (30V, 10mΩ typ @ V = 4.5V) is used for both the low and the

gs

high side.

Since the board has been layed out with the possibility to use up to three SO8 mosfets for both high and low

side switch, to increase efficiency at low output voltages, an additional mosfet on the low side can be considered

because of the duty cycle.

13/21

L6910A L6910

Figure 12. Demo Board Efficiency @ V = 5V

in

95

90

85

80

75

Vout = 0.9V

Vout = 1.2V

Vout = 1.8V

Vout = 3.3V

70

65

60

Vout = 1.5V

Vout = 2.5V

0

2

4

6

8

10

Output Current [A]

APPLICATION IDEA: 5V TO 12V INPUT; 3.3V / 25A OUTPUT

This is a typical application to replace the mag-amp in the silver box. The output voltage is programmed by the

switch to 3.3V and the maximum output current is of 25A DC. The power mosfet are configured with three

STS11NF30L (30V, 9m

Ω typ @ V = 10V ) for high side and two of them for the low side.

gs

Inductor selection

Since the maximum output current is 25A, to have a 20% ripple (5A) in worst case the inductor chosen is 1.1

µH.

An iron powder core (TO50-52B) with 6 windings has been chosen.

Output Capacitor

4 POSCAP capacitors, model 6TPB330M, are used, with a maximum ESR equal to 40m

Ω

each. Therefore the

resultant ESR is of 10mΩ. For load transient of 20A in the worst case the voltage drop is lower than 5%:

∆

V

out

= 20 · 0.01 = 200mV

Input Capacitor

For I

= 25A and D = 0.5 (worst case for input ripple current), Irms is equal to 12.5A. Three OSCON electro-

OUT

lytic capacitors 6SP680M, with a maximum ESR equal to 13mΩ, are chosen to sustain the ripple. Therefore,

the resultant ESR is equal to 13m

Ω

/3 = 4.3m

Ω

. So the losses in worst case are:

2

rms

P = ESR ·

I

= 670mW

Over-Current Protection

The peak current is in this case equal to 30A, substituting the demo board parameters in the relationship report-

ed in the relative section, (I = 170 A; I = 30A; R = 3m ) it results that R = 530

µ

Ω

Ω.

OCSMIN

P

DSONMAX

OCS

14/21

L6910A L6910

Table 2. Part List

R2

10k

SMD 0805

R3

4.7k

1%

SMD 0805

Radial 10x10.5mm

SMD 7343

SMD 0805

R4

220

R5

10k

R6

10

R7

620

R9

0

R10

1.74k

680µ

330µ

100n

1n

1%

C1,C2, C3

C4 to C8

C13, C15

C14, C16

C18

OSCON - 6SP680M

POSCAP - 6TPB330M

Ceramic

2.2n

Ceramic

C19

3.3n

Ceramic

C20

6.8n

Ceramic

L1

1.5µ

T44-52 Core, 7T-18AWG

T50-52B Core, 6T

STMicroelectronics

Littlefuse

L2

1.1µ

U1

L6910

STS11NF30L

1N4148

STPS340U

251015A-15°

SO16 NARROW

SO8

Q1 to Q5

D1

SOT23

D2

SMB

F1

AXIAL

Efficiency

Figure 13 shows the measured efficiency versus load current at Vin=5V.

In the application three mosfets STS11NF30L (30V, 9m

Ω

typ @ V = 10V) are used for high side swith while

gs

two of them are used for the low side..

Figure 13. Demo Board Efficiency @ V = 5V & V

= 3.3V

in

out

97

95

93

91

89

87

85

0

5

10

15

20

25

Output current

15/21

L6910A L6910

5A Demo Board Description

The demo board shows the operation of the device in a general purpose application. The interanl reference is

used for the regulation. The external power mosfets are included in one SO8 package to save space and in-

crease power density.The 12V input rail supplies the device while the power conversion starts from the 5V input

rail. The device is also able to operate with a single supply voltage; in this case the jumper J1on the board bot-

tom has to be closed and a 5V to 12V input can be directly connected to the V input.

IN

Figure 14. 5A Demo Board Schematic

VIN (+5V)

R7

C7

J1

GNDIN

D1

C6

C1,C2

BOOT

OCSET

12

VCC

UGATE

R6

3

R8

R9

VCC (+12V)

GNDCC

15

11

Q1/1

Q1/2

L1

PHASE

LGATE

PGND

C5

10

14

13

9

VOUT

GND

7

R11

C10

D2

C3, C4

U1

L6910

SS

OSC

R2

4

2

8

GNDOUT

PWRGD

C9

PGOOD

VREF

EAREF

1

C8

5

6

COMP

VFB

R10

R3

C19

R5

C18

C20

R4

R1

Figure 15. PCB and Components Layouts

Component Side

Solder Side

Efficiency

Figure 16 shows the measured efficiency versus load current for different values of output voltage. The measure

was done at 5V and 12V input for different values of the output voltage (2.5V, 3.3V and 5V only when Vin=12V).

Output voltage has been changed modifying the value of R1 in the demo board as reported in the part list.

16/21

L6910A L6910

Figure 16. Demoboard efficiency with V

= V = 5V (left), and with V = V = 12V (right).

IN CC IN

CC

95

90

85

80

75

70

65

60

95

94

93

92

91

90

89

88

87

86

85

Vout=2.5V

Vout=3.3V

Vout=2.5V

Vout=3.3V

Vout=5V

0

1

2

3

4

5

0

1

2

3

4

5

Output Current [A]

Part List

Resistors

R1

560

375

220

1%; (Vout = 2.5V)

1%; (Vout = 3.3V)

1%; (Vout = 5V)

SMD 0805

R2

10K

1K

SMD 0805

R3

R4

33

R5

2.7K

10

R6

R7

680

2.2

R8, R9

Capacitors

C1,C2

C3, C4

10µF

TOKIN C34Y5U1E106ZTE12

POSCAP 6TPB100M

SMD 7343

100 µF – 6.3V

C5,C6,C9

C7, C8

C18

100nF

1nF

SMD 0805

1.5n

15n

C19

C20

47n

Magnetics

L1

10µH

T50-52B Core, 12T

STMicroelectronics

Transistors

Q1

STS7DNF30L

SO8

Diodes

D1

1N4148

SOT23

SMA

D2

STPS125A

STMicroelectronics

Ics

U1

L6910

SO16Narrow

17/21

L6910A L6910

APPLICATION IDEA: BUCK-BOOST CONVERTER 3V TO 10V INPUT / 5V 2A OUTPUT

Figure 17. buck-boost converter 3V to 10V input / 5V 2A Output Circuit

VIN (+2.5V to +12V)

R7

C7

GNDIN

D1

C6

C1,C2

BOOT

OCSET

12

VCC

UGATE

R6

3

R8

VCC (+12V)

GNDCC

15

7

11

Q1/1

D3

L1

PHASE

LGATE

PGND

C5

10

14

13

9

VOUT

GND

R9 Q1/2

D2

Q2/1

C3, C4

U1

L6910

SS

OSC

Q2/2

R2

4

2

8

GNDOUT

PWRGD

C9

PGOOD

VREF

EAREF

1

C8

5

6

VFB

COMP

R10

R3

C19

R5

C20

R4

C18

R1

18/21

L6910A L6910

mm

inch

DIM.

OUTLINE AND

MECHANICAL DATA

MIN. TYP. MAX. MIN. TYP. MAX.

A

a1

a2

b

1.75

0.069

0.009

0.063

0.018

0.010

0.1

0.25 0.004

1.6

Weight: 0.20gr

0.35

0.19

0.46 0.014

0.25 0.007

b1

C

0.5

0.020

c1

D (1)

E

45˚ (typ.)

9.8

5.8

10

0.386

0.228

0.394

0.244

6.2

e

1.27

8.89

0.050

0.350

e3

F (1)

G

3.8

4.6

0.4

4

0.150

0.181

0.157

0.209

0.050

0.024

5.3

L

1.27 0.016

0.62

M

SO16 Narrow

8˚(max.)

S

(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).

0016020

19/21

L6910A L6910

mm

inch

DIM.

OUTLINE AND

MECHANICAL DATA

MIN. TYP. MAX. MIN.

TYP. MAX.

0.047

A

A1

A2

b

1.2

0.15

0.006

0.8

0.19

0.09

4.9

1.0

5.0

1.05 0.031 0.039 0.041

0.3

0.2

5.1

3.0

6.6

4.5

0.007

0.003

0.012

0.008

c

D (*)

D1

E

0.192 0.197 0.200

0.067

1.7

0.118

6.2

6.4

4.4

0.244 0.252 0.260

0.169 0.173 0.177

E1 (*)

E2

e

4.3

1.5

3.0 0.059

0.118

0.65

0.6

0.026

L

0.45

0.75 0.018 0.024 0.029

0.039

L1

k

1.0

0˚ (min), 8˚ (max)

aaa

0.10

0.004

HTSSOP16

(Exposed Pad)

(*) Dimensions D and E1 does not include mold flash or

protusions. Mold flash or protusions shall not exeed

0.15mm per side.

7419276

20/21

L6910A L6910

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco -

Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.

http://www.st.com

21/21


型号：	L6910ATR
厂家：	ST
描述：	ADJUSTABLE STEP DOWN CONTROLLER WITH SYNCHRONOUS RECTIFICATION 采用同步整流可调降压控制器控制器
文件：	总21页 (文件大小：455K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

L6910ATR [STMICROELECTRONICS]

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