L6491DTR [STMICROELECTRONICS]
Power supply unit;
ST 
L6491
High voltage high and low-side 4 A gate driver
Datasheet - production data
Applications
Motor driver for home appliances, factory
automation, industrial drives and fans
HID ballasts
Power supply unit
Induction heating
Wireless chargers
Industrial inverters
UPS
SO-14
Features
High voltage rail up to 600 V
dV/dt immunity ± 50 V/ns in full temperature
Description
range
The L6491 is a high voltage device manufactured
with the BCD6 “OFF-LINE” technology. It is
a single-chip half-bridge gate driver for N-channel
power MOSFET or IGBT.
Driver current capability: 4 A source/sink
Switching times 15 ns rise/fall with 1 nF load
3.3 V, 5 V TTL/CMOS inputs with hysteresis
Integrated bootstrap diode
The high-side (floating) section is designed to
stand a voltage rail up to 600 V. The logic inputs
are CMOS/TTL compatible down to 3.3 V for easy
interfacing microcontroller/DSP.
Comparator for fault protections
Smart shutdown function
Adjustable deadtime
An integrated comparator is available for fast
protection against overcurrent, overtemperature,
etc.
Interlocking function
Compact and simplified layout
Bill of material reduction
Table 1. Device summary
Effective fault protection
Order code
Package
Packaging
Flexible, easy and fast design
L6491D
SO-14
SO-14
Tube
L6491DTR
Tape and reel
March 2015
DocID024832 Rev 1
1/24
This is information on a product in full production.
www.st.com
Contents
L6491
Contents
1
2
3
4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1
4.2
4.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1
5.2
AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
6
7
8
9
Waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10
11
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2/24
DocID024832 Rev 1
L6491
Block diagram
1
Block diagram
Figure 1. Block diagram
VCC
PGND
DocID024832 Rev 1
3/24
24
Pin connection
L6491
2
Pin connection
Figure 2. Pin connection (top view)
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Table 2. Pin description
Type
Pin
number
Pin name
Function
1
2
LIN
I
Low-side driver logic input (active low)
Shutdown logic input (active low)/open-drain
comparator output
SD/OD(1)
I/O
3
4
HIN
VCC
DT
I
P
I
High-side driver logic input (active high)
Lower section supply voltage
Deadtime setting
5
6
SGND
PGND
LVG(1)
CP-
P
P
O
I
Signal ground
7
Power ground
8
Low-side driver output
Comparator negative input
Comparator positive input
Not connected
9
10
11
12
13
14
CP+
I
NC
OUT
HVG(1)
BOOT
P
O
P
High-side (floating) common voltage
High-side driver output
Bootstrapped supply voltage
1. The circuit guarantees less than 1 V on the LVG and HVG pins (at Isink = 10 mA), with VCC > 3 V. This
allows omitting the “bleeder” resistor connected between the gate and the source of the external MOSFET
normally used to hold the pin low.
When the SD is set low, gate driver outputs are forced low and assure low impedance.
4/24
DocID024832 Rev 1
L6491
Truth table
3
Truth table
Table 3. Truth table
HIN
Input
LIN
Output
SD
LVG
HVG
L
X(1)
H
X(1)
L
L
L
L
H
L
L
L
L
L
H
H
H
L
H
H
H
L
L
H
H
1. X: don't care.
DocID024832 Rev 1
5/24
24
Electrical data
L6491
4
Electrical data
4.1
Absolute maximum ratings
(1)
Table 4. Absolute maximum ratings
Value
Symbol
Parameter
Unit
Min.
Max.
VCC
Supply voltage
-0.3
VCC - 21
Vboot - 21
-0.3
21
VCC + 0.3
Vboot + 0.3
620
V
V
VPGND Low-side driver ground
Vout
Vboot
Vhvg
Vlvg
Vcp-
Vcp+
Vi
Output voltage
V
Bootstrap voltage
V
High-side gate output voltage
Low-side gate output voltage
Comparator negative input voltage(2)
Comparator positive input voltage(2)
Logic input voltage
Vout - 0.3
PGND - 0.3
-0.3
Vboot + 0.3
VCC + 0.3
5.5
V
V
V
-0.3
5.5
V
-0.3
15
V
VOD
Open-drain voltage
-0.3
15
V
dvout / dt Allowed output slew rate
50
V/ns
W
°C
°C
kV
Ptot
TJ
Total power dissipation (TA = 25 °C)
1.0
Junction temperature
Storage temperature
Human body model
150
Tstg
ESD
-50
150
2
1. Each voltage referred to SGND unless otherwise specified.
2. Spikes up to 20 V can be tolerated if the duration is shorter than 50 ns (fSW = 120 kHz).
4.2
Thermal data
Table 5. Thermal data
Symbol
Parameter
SO-14
Unit
Rth(JA)
Thermal resistance junction to ambient
120
°C/W
6/24
DocID024832 Rev 1
L6491
Electrical data
4.3
Recommended operating conditions
Table 6. Recommended operating conditions
Parameter Test conditions
Supply voltage
Symbol
Pin
Min.
Max.
Unit
VCC
4
10
-1.5
9.3
20
+1.5
20
V
V
V
V
(1)
VPS
7 - 6 Low-side driver ground
14 - 12 Floating supply voltage
(2)
VBO
Vout
12
9
DC output voltage
- 9(3)
580
Comparator negative
input pin voltage
VCP-
VCP+ 2.5 V
5(4)
5(4)
V
V
Comparator positive
input pin voltage
VCP+
10
VCP- 2.5 V
fsw
TJ
Switching frequency
Junction temperature
HVG, LVG load CL = 1 nF
800
125
kHz
°C
-40
1. VPS = VPGND - SGND.
2. VBO = Vboot - Vout
3. LVG off. VCC = 12.5 V. Logic is operational if Vboot > 5 V.
4. At least one of the comparator's inputs must be lower than 2.5 V to guarantee proper operation.
.
DocID024832 Rev 1
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24
Electrical characteristics
L6491
5
Electrical characteristics
5.1
AC operation
Table 7. AC operation electrical characteristics (VCC = 15 V; PGND = SGND; T = +25 °C)
J
Symbol
Pin
Parameter
Test conditions
Min. Typ. Max. Unit
High/low-side driver turn-on
propagation delay
ton
85 120 ns
OUT = 0 V
1 vs. 8
3 vs 13
BOOT = VCC
CL = 1 nF
High/low-side driver turn-off
propagation delay
toff
tsd
85 120 ns
85 120 ns
Vi = 0 to 3.3 V
see Figure 3
2 vs. Shutdown to high/low-side
8, 13 driver propagation delay
Comparator triggering to
high/low-side driver turn-off
propagation delay
Measured applying a voltage step from
0 V to 3.3 V to pin CP+; CP- = 0.5 V
tisd
175 220 ns
Delay matching, HS and LS
turn-on/off(1)
MT
30
ns
RDT = 0 , CL = 1 nF
0.12 0.18 0.24 µs
Deadtime setting range
DT
5
RDT = 100 k, CL = 1 nF, CDT = 100 nF 1.2 1.4 1.6
µs
µs
ns
see Figure 4
RDT = 200 k, CL = 1 nF, CDT = 100 nF 2.2
DT = 0 , CL = 1 nF
2.6
3
R
50
MDT
Matching deadtime(2)
RDT = 100 k, CL = 1 nF, CDT = 100 nF
RDT = 200 k, CL = 1 nF, CDT = 100 nF
CL = 1 nF
165 ns
260 ns
tr
tf
Rise time
8,13
15
15
40
40
ns
ns
Fall time
CL = 1 nF
1. MT = max. (|ton(LVG) - toff(LVG)|, |ton(HVG) - toff(HVG)|, |toff(LVG) - ton(HVG)|, |toff(HVG) - ton(LVG)|).
2. MDT = | DTLH - DTHL | (see Figure 5 on page 14).
8/24
DocID024832 Rev 1
L6491
Electrical characteristics
Figure 3. Timing
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DocID024832 Rev 1
9/24
24
Electrical characteristics
L6491
Figure 4. Typical deadtime vs. DT resistor value
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10/24
DocID024832 Rev 1
L6491
Electrical characteristics
5.2
DC operation
Table 8. DC operation electrical characteristics
(VCC = 15 V; PGND = SGND; T = + 25 °C)
J
Symbol
Pin
Parameter
Test conditions
Min. Typ. Max.
Unit
Vcc_hys
Vcc_thON
Vcc_thOFF
VCC UV hysteresis
0.5
8.7
8.2
0.6
9.3
8.7
0.72
9.8
V
V
V
VCC UV turn-ON threshold
VCC UV turn-OFF threshold
9.2
VCC = 8 V
SD = 5 V; LIN = 5 V;
HIN = SGND;
Undervoltage quiescent
supply current
Iqccu
160
540
210
700
A
A
4
RDT = 0 ;
CP+ = SGND; CP- = 5 V
VCC = 15 V
SD = 5 V; LIN = 5 V;
HIN = SGND;
Iqcc
Quiescent current
RDT = 0 ;
CP+ = SGND; CP- = 5 V
Bootstrapped supply voltage section(1)
VBO_hys
VBO_thON
VBO_thOFF
VBO UV hysteresis
0.48
8
0.6
8.6
8.0
0.7
9.1
8.5
V
V
V
VBO UV turn-ON threshold
VBO UV turn-OFF threshold
7.5
VCC = VBO = 7 V
SD = 5 V; LIN and
HIN = 5 V;
Undervoltage VBO quiescent
current
IQBOU
20
30
A
A
14-12
RDT = 0 ;
CP+ = SGND; CP- = 5 V
VBO = 15 V
SD = 5 V; LIN and
HIN = 5 V;
IQBO
VBO quiescent current
90
120
8
RDT = 0 ;
CP+ = SGND; CP- = 5 V
ILK
High voltage leakage current BOOT = HVG = OUT = 600 V
A
Bootstrap driver on
resistance(2)
RDS(on)
175
DocID024832 Rev 1
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24
Electrical characteristics
L6491
Unit
Table 8. DC operation electrical characteristics
(VCC = 15 V; PGND = SGND; T = + 25 °C) (continued)
J
Symbol
Pin
Parameter
Test conditions
Min. Typ. Max.
Driving buffer section
LVG/HVG ON
TJ = 25 °C
3.5
2.5
3.5
2.5
4
4
A
A
A
A
High/low-side source peak
current
Iso
Full temperature range
8, 13
LVG/HVG OFF
TJ = 25 °C
High/low-side sink peak
current
Isi
Full temperature range
Logic inputs
Vil
Low level logic threshold
0.95
2
1.45
2.5
0.8
0.8
V
V
V
V
1, 2, 3
High level logic threshold
voltage
Vih
VSSD
Vil_S
2
SmartSD unlatch threshold
Single input voltage
1, 3
LIN and HIN connected
together and floating
HIN logic “1” input bias
current
IHINh
IHINl
ILINl
ILINh
ISDh
ISDl
HIN = 15 V
HIN = 0 V
LIN = 0 V
LIN = 15 V
SD = 15 V
SD = 0 V
120
5
200
10
260
1
A
A
A
A
A
A
3
1
2
HIN logic “0” input bias
current
LIN logic “0” input bias
current
15
1
LIN logic “1” input bias
current
SD logic “1” input bias
current
20
40
60
1
SD logic “0” input bias
current
1. VBO = Vboot - Vout
.
2. RDS(on) is tested in the following way:
RDS(on) = [(VCC - VBOOT1) - (VCC - VBOOT2)] / [I1(VCC, VBOOT1) - I2(VCC, VBOOT2)] where I1 is pin 14 current when
BOOT = VBOOT1, I2 when VBOOT = VBOOT2
V
.
12/24
DocID024832 Rev 1
L6491
Electrical characteristics
(1)
Table 9. Sense comparator (V = 15 V, T = +25 °C)
CC
J
Symbol
Pin
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Vio
Iib
9, 10 Input offset voltage
9, 10 Input bias current
-15
15
1
mV
VCP+ = 1 V, VCP- = 1 V
A
Open-drain low level sink
current
SD\OD = 400 mV, VCP+ = 1
V; VCP - = 0.5 V;
I
2
13
20
27
mA
ns
OD
Rpu = 100 k to 5 V;
VCP - = 0.5 V;
td_comp
Comparator delay
100
155
voltage step on CP+ = 0 to
3.3 V; 50% CP+ to 90% SD
CL = 10 nF;
SR
2
Slew rate
Rpu = 5 k to 5 V;
90% SD to 10% SD
10
V/s
1. Comparator is disabled when VCC is in UVLO condition.
DocID024832 Rev 1
13/24
24
Waveform definitions
L6491
6
Waveform definitions
Figure 5. Deadtime and interlocking waveform definitions
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14/24
DocID024832 Rev 1
L6491
Smart shutdown function
7
Smart shutdown function
The L6491 device integrates a comparator committed to the fault sensing function. The
comparator input can be connected to an external shunt resistor in order to implement
a simple overcurrent detection function.
The output signal of the comparator is fed to an integrated MOSFET with the open-drain
output available on pin 2, shared with the SD input. When the comparator triggers, the
device is set in shutdown state and both its outputs are set to low level leaving the half-
bridge in 3-state.
Figure 6. Smart shutdown timing waveforms
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DocID024832 Rev 1
15/24
24
Smart shutdown function
L6491
In common overcurrent protection architectures, the comparator output is usually connected
to the SD input and an RC network is connected to this SD/OD line in order to provide
a monostable circuit, which implements a protection time following the fault condition.
Differently from the common fault detection systems, the L6491 smart shutdown
architecture allows immediate turn-off of the output gate driver in case of fault, by minimizing
the propagation delay between the fault detection event and the current output switch-off. In
fact the time delay between the fault and the output turn-off is no longer dependent on the
RC value of the external network connected to the SD/OD pin. In the smart shutdown
circuitry, the fault signal has a preferential path which directly switches off the outputs after
the comparator triggering. At the same time, the internal logic turns on the open-drain output
and holds it on until the SD voltage goes below the smartSD unlatch threshold V
. When
SSD
such threshold is reached, the open-drain output is turned off, allowing the external pull-up
to recharge the capacitor. The driver outputs restart following the input pins as soon as the
voltage at the SD/OD pin reaches the higher threshold of the SD logic input. The smart
shutdown system gives the possibility to increase the time constant of the external RC
network (that determines the disable time after the fault event) up to very large values
without increasing the delay time of the protection.
Any external signal provided to the SD pin is not latched and can be used as control signal
in order to perform, for instance, PWM chopping through this pin. In fact when a PWM signal
is applied to the SD input and the logic inputs of the gate driver are stable, the outputs
switch from the low level to the state defined by the logic inputs and vice versa.
16/24
DocID024832 Rev 1
L6491
Typical application diagram
8
Typical application diagram
Figure 7. Typical application diagram
BOOTSTRAP DRIVER
FLOATING STRUCTURE
VCC
+
VCC
HIN
LIN
BOOT
14
4
3
CVCC1
H.V.
Cboot
Rg
HVG
DRIVER
13 HVG
FROM CONTROLLER
FROM CONTROLLER
LEVEL
SHIFTER
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5V
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PREVENTION
1
OUT
LVG
12
8
Rfilt
Cfilt
TO LOAD
VCC
LVG
Vpu
RSD
DRIVER
Rg
FROM/TO
SD/OD
CONTROLLER
2
PGND
5V
SMART
SD
CSD
COMPARATOR
RLP
CP+
10
9
+
-
CLP
CP-
VCC
Vpu
Rp1
Rp2
DEAD
TIME
DT
5
6
CVCC2
Rshunt
7
RDT
CDT
SGND
Cp2
PGND
System power ground
Figure 8. Suggested PCB layout
Vpu
SD/OD
C
BOOT
LIN
Rfilt
R
SD
Cfilt
CSD
Cfilt
HIN
Rfilt
VCC
C
C
LP
p2
C
VCC1
RDT
C
DT
Rg
Vpu
C
VCC2
Rp2
R
p1
RLP
uC Signal GROUND
Rshunt
POWER GROUND
BOTTOM layer
TOP layer
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Bootstrap driver
L6491
9
Bootstrap driver
A bootstrap circuitry is needed to supply the high voltage section. This function is usually
accomplished by a high voltage fast recovery diode (Figure 9). In the L6491 an integrated
structure replaces the external diode.
CBOOT selection and charging
To choose the proper CBOOT value the external MOS can be seen as an equivalent
capacitor. This capacitor CEXT is related to the MOS total gate charge:
Equation 1
Qgate
CEXT = -------------
Vgate
The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss.
It has to be:
Equation 2
CBOOT>>>CEXT
if Qgate is 30 nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop is 300 mV.
If HVG has to be supplied for a long time, the CBOOT selection has also to take into account
the leakage and quiescent losses.
HVG steady-state consumption is lower than 120 A, so if HVG TON is 5 ms, CBOOT has to
supply CEXT with 0.6 C. This charge on a 1 F capacitor means a voltage drop of 0.6 V.
The internal bootstrap driver gives a great advantage: the external fast recovery diode can
be avoided (it usually has great leakage current).
This structure can work only if VOUT is close to SGND (or lower) and in the meanwhile the
LVG is on. The charging time (Tcharge) of the CBOOT is the time in which both conditions are
fulfilled and it has to be long enough to charge the capacitor.
The bootstrap driver introduces a voltage drop due to the DMOS RDS(on) (typical value:
175 ). At low frequency this drop can be neglected. Anyway, the rise of frequency has to
take into account.
The following equation is useful to compute the drop on the bootstrap DMOS:
Equation 3
Qgate
Vdrop = IchargeRDSon Vdrop = ------------------ RDSon
Tcharge
where Qgate is the gate charge of the external power MOS, RDS(on) is the on resistance of
the bootstrap DMOS and Tcharge is the charging time of the bootstrap capacitor.
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L6491
Bootstrap driver
For example: using a power MOS with a total gate charge of 30 nC the drop on the
bootstrap DMOS is about 1 V, if the Tcharge is 5 s. In fact:
Equation 4
30nC
5s
V
= -------------- 175 1V
drop
Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop
is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode
can be used.
Figure 9. Bootstrap driver with external high voltage fast recovery diode
DBOOT
VCC
BOOT
H.V.
HVG
OUT
CBOOT
TO LOAD
LVG
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Package information
L6491
10
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
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L6491
Package information
Figure 10. SO-14 package outline
ꢇꢇꢁꢋꢇꢁꢈB(
Table 10. SO-14 package mechanical data
Dimensions (mm)
Symbol
Min.
Typ.
Max.
A
A1
A2
B
1.35
0.10
1.10
0.33
0.19
8.55
3.80
1.75
0.25
1.65
0.51
0.25
8.75
4.00
C
D
E
e
1.27
H
5.80
0.25
0.40
0
6.20
0.50
1.27
8
h
L
k
ddd
0.10
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Package information
L6491
Figure 11. SO-14 package suggested land pattern
4.0
6.7
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L6491
Revision history
11
Revision history
Table 11. Document revision history
Changes
Date
Revision
11-Mar-2015
1
Initial release.
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L6491
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