L5150CJ [STMICROELECTRONICS]
5 V low dropout voltage regulator;
| 型号： | L5150CJ |
| 厂家： | 
ST |
| 描述： | 5 V low dropout voltage regulator 信息通信管理 光电二极管 输出元件 调节器 |
| 文件： | 总34页 (文件大小：664K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L5150CJ
L5150CS
5 V low dropout voltage regulator
Datasheet
−
production data
Features
Max DC supply voltage
Max output voltage tolerance
Max dropout voltage
Output current
VS
ΔVo
Vdp
Io
40 V
+/-2%
*$3*36ꢀꢁꢂꢃꢄ
*$3*36ꢀꢁꢂꢃꢂ
500 mV
150 mA
55 µA(1)
SO-8
PowerSSO-12
Quiescent current
Iqn
1. Typical value
Description
■
Operating DC supply voltage range
5.6 V to 40 V
L5150CJ and L5150CS are low dropout linear
regulators with microprocessor control functions
such as power on reset, low voltage reset, early
warning.
■
■
■
■
■
Low dropout voltage
Low quiescent current consumption
Precision output voltage 5 V +/- 2%
Typical quiescent current is 55 µA at very low
output current.
Reset circuit sensing the output voltage
On chip trimming results in high output voltage
accuracy (2%). Accuracy is kept over wide
temperature range, line and load variation. Early
warning circuit monitors the input voltage and
compares it with an internal voltage reference.
Programmable reset pulse delay with external
capacitor
■
■
■
Adjustable reset threshold
Early warning
Very wide stability range with low value output
capacitor
Output voltage reset threshold can be adjusted
down to 3.5 V by means of an external voltage
divider.
■
■
Thermal shutdown and short-circuit protection
Wide temperature range (Tj = -40 °C to 150 °C)
The maximum input voltage is 40 V. The max
output current is internally limited. Internal
temperature protection disables the voltage
regulator output. In addition, only low-value
ceramic capacitor on output is required for
stability.
Table 1.
Device summary
Package
Order codes
Tape & reel
Tube
PowerSSO-12
SO-8
L5150CJ
L5150CS
L5150CJTR
L5150CSTR
September 2013
Doc ID 15542 Rev. 15
1/34
This is information on a product in full production.
www.st.com
1
Contents
L5150CJ / L5150CS
Contents
1
2
Block diagram and pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2.2
2.3
2.4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1
3.2
3.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Early warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4
5
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1
4.2
PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
®
5.1
5.2
5.3
5.4
5.5
ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PowerSSO-12 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SO-8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2/34
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Early warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PowerSSO-12 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SO-8 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Doc ID 15542 Rev. 15
3/34
List of figures
L5150CJ / L5150CS
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Output voltage vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output voltage vs. VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Drop voltage vs. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current consumption vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current consumption vs. output current (at light load condition). . . . . . . . . . . . . . . . . . . . . 11
Current consumption vs. input voltage (Io = 0.1 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current consumption vs. input voltage (Io = 75 mA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. Current limitation vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. Current limitation vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 12. Short-circuit current vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 13. Short-circuit current vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 14.
Figure 15.
Figure 16.
Figure 17.
V
V
V
V
Rhth vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Rlth vs. Tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
EWi_thh vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
EWi_thl vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 18. Icr vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 19. dr vs. Tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I
Figure 20. PSRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 21. Application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 22. Stability region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 23. Maximum load variation response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 24. Reset time diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 25. Early warning time diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 26. PowerSSO-12 PC board(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 27. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 19
Figure 28. PowerSSO-12 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 20
Figure 29. Thermal fitting model of Vreg in PowerSSO-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 30. SO-8 PC board(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 31. Rthj-amb vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 22
Figure 32. SO-8 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 33. Thermal fitting model of Vreg in in SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 34. PowerSSO-12 package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 35. SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 36. PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 37. PowerSSO-12 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 38. SO-8 tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 39. SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4/34
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
Block diagram and pins description
1
Block diagram and pins description
Figure 1.
Block diagram
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Figure 2.
Configuration diagram (top view)
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Doc ID 15542 Rev. 15
5/34
Block diagram and pins description
L5150CJ / L5150CS
Table 2.
Pin name
Pins description
PowerSSO-12
pin #
SO-8
pin #
Function
Reset adjustable threshold. Connected to an
appropriate external voltage divider, it allows to
properly set the reset threshold down to 3.5 V.
Connect to GND if not needed.
Res_Adj
1
8
Reset output. Internally connected to Vo through a
20 KΩ pull up resistor. This pin is pulled low when
Vo < Vo_th. Keep open if not needed.
Res
2
3
1
2
Reset delay. Connect an external capacitor between
Vcr pin and ground to adjust the reset delay time.
Keep open if not needed.
Vcr
GND
NC
4
3
-
Ground reference.
Not connected.
5, 11, 8, 9
5 V regulated output. Block to GND with a ceramic
capacitor (Co ≥ 220 nF for regulator stability).
Vo
6
7
4
5
Supply voltage, block directly to GND on the IC with a
capacitor.
VS
Early warning input. This pin monitors the VS voltage
level through a resistor divider. Connect to VS if not
needed.
EWi
EWo
TAB
10
12
-
6
7
-
Early warning output. Internally connected to Vo
through 20 KΩ pull up resistor. This pin is pulled low
when EWi is below bandgap reference voltage. Keep
open if not needed.
TAB is connected to the substrate of the chip: connect
toGND or leave open (see Figure 2 for PowerSSO-12
only).
6/34
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
Electrical specifications
2
Electrical specifications
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the Table 3: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 3.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
V
sdc
DC supply voltage
-0.3 to 40
V
I
sdc
Input current
internally limited
-0.3 to 6
Vodc
Iodc
DC output voltage
V
V
DC output current
internally limited
-0.3 to Vodc + 0.3
internally limited
-0.3 to Vodc + 0.3
-0.3 to Vodc + 0.3
internally limited
Vod Res
Iod Res
VRes_adj
Vod EWo
Iod EWo
Vcr
Open drain output voltage Res
Open drain output current Res
VRes_adj voltage
V
V
Open drain output voltage EWo
Open drain output current EWo
Vcr voltage
-0.3 to V
o
+ 0.3
V
V
VEWi
Early warning input voltage
Junction temperature
-0.3 to 40
-40 to 150
+/- 2
Tj
°C
kV
V
VESD HBM
ESD HBM voltage level (HBM-MIL STD 883C)
ESD CDM voltage level (CDM- )
V
ESD CDM
+/- 750
Doc ID 15542 Rev. 15
7/34
Electrical specifications
L5150CJ / L5150CS
2.2
Thermal data
Table 4.
Thermal data
Value
Symbol
Parameter
Unit
PowerSSO-12
SO-8
Rthj-case
Rthj-lead
Thermal resistance junction to case:
Thermal resistance junction to lead:
Thermal resistance junction to ambient:
8
°K/W
°K/W
°K/W
40
(1)
Rthj-amb
52
112
1. PowerSSO-12: The values quoted are for PCB 77 mm x 86 mm x 1.6 mm, FR4, double copper layer with
2
single heatsink layer, copper thickness 70 µm, thermal vias, copper area 2 cm .
SO-8: The values quoted are for PCB 48 mm x 48 mm x 2 mm, FR4, double copper layer with single
2
heatsink layer, copper thickness 35 µm, copper area 2 cm .
2.3
Electrical characteristics
Values specified in this section are for VS = 5.6 V to 31 V, Tj = -40 °C to +150 °C unless
otherwise stated.
Table 5.
Pin
General
Symbol
Parameter
Test condition
Min. Typ. Max. Unit
VS = 8 V to 18 V
Vo
Vo
Vo
Vo_ref
Vo_ref
Vo_ref
Output voltage
4.9 5.0 5.1
4.85 5.0 5.15
V
V
Io = 8 mA to 150 mA
VS = 5.6 V to 31 V
Output voltage
Io = 8 mA to 150 mA
VS = 5.6 V to 31 V
Io = 0.1 mA to 8 mA
Output voltage
4.75 5.0 5.25
0.65 0.95 1.25
V
A
Vo
Vo
Ishort
Ilim
Short-circuit current
VS = 13.5 V
Output current capability (1) VS = 13.5 V
280 470 660 mA
VS = 6 V to 28 V
VS, Vo
Vline
Line regulation voltage
Load regulation voltage
40
55
mV
mV
Io = 30 mA
VS = 8 V to 18 V,
Io = 8 mA to 150 mA
Vo
Vload
VS = 13.5 V,
Tj = 25 °C
40
Io = 8 mA to 150 mA
VS, Vo
VS, Vo
Vdp
Drop voltage (2)
Ripple rejection
Io = 150 mA
500 mV
dB
SVR
fr = 100 Hz(3)
60
Normal consumption mode
output current
Vo
Vo
Vo
Ioth_H
Ioth_L
VS = 8 V to 18 V
VS = 8 V to 18 V
8
mA
Very low consumption mode
output current
1.1
mA
mA
VS = 13.5 V
Tj = 25 °C
Output current switching
threshold hysteresis
Ioth_Hyst
0.8
8/34
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
Electrical specifications
Min. Typ. Max. Unit
Table 5.
Pin
General (continued)
Symbol
Parameter
Test condition
VS = 13.5 V,
Io = 0.1 mA to 1 mA,
Tj = 25 °C
55
80
Current consumption
VS, Vo
Iqn_1
µA
Iqn_1 = IVs
– Io
VS = 13.5 V,
95
4.2
190
Io = 0.1 mA to 1 mA,
Current consumption
Iqn_150 = IVs Io
VS = 13.5 V
Io = 150 mA
VS, Vo Iqn_150
3
mA
°C
–
Thermal protection
temperature
Tw
150
Thermal protection
temperature hysteresis
Tw_hy
10
°C
1. Measured Output Current when the output voltage has dropped 100 mV from its nominal Value obtained at
13.5 V and I =75 mA.
o
2. Vs - V Measured Dropout when the output voltage has dropped 100 mV from its nominal Value obtained
o
at 13.5 V and I =75 mA.
o
3. Guaranteed by design.
Table 6.
Pin
Reset
Symbol
Parameter
Test condition
Min. Typ. Max.
Unit
Rext = 5 kΩ
Vo > 1 V
Reset output low
voltage
Res
Res
Vres_l
IRes_lkg
RRes
0.4
V
Reset output high
leakage current
V
Res = 5 V
1
µA
Pull up internal
resistance
Res
Versus Vo
10
6
20
8
40
10
kΩ
Vo out of regulation
threshold
Vres_adj < 0.2 V,
% Below
Vo_ref
Res
Vo_th
Vo decreasing
Reset adjustable
switching threshold
Res_adj
Res_adj
Res_adj
Vcr
Vres_adj
VRes_adjl
Res_adj_lkg
VRlth
2.35
0.4
-1
2.5
0.9
2.65
1.3
1
V
V
Reset adjustable
low voltage
Reset adjustable
leakage current
I
V
res_adj = 2.5 V
µA
Reset timing low
threshold
VS = 13.5 V
15
47
18
50
22
% Vo_ref
% Vo_ref
Reset timing high
threshold
Vcr
VRhth
VS =13.5 V
VS = 13.5 V
53
Vcr
Vcr
Icr
Idr
Charge current
10
10
20
20
30
30
µA
µA
Discharge current VS = 13.5 V
Doc ID 15542 Rev. 15
9/34
Electrical specifications
L5150CJ / L5150CS
Table 6.
Pin
Reset (continued)
Symbol
Parameter
Test condition
Min. Typ. Max.
Unit
Res
Res
Trr
Reset reaction time
Reset delay time
2
µs
VS = 13.5 V;
Ctr = 1000 pF
Trd
2
4
11
ms
Table 7.
Early warning
Pin
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
EW input low threshold
voltage
EWi
VEWi_thl
2.35
2.50
2.65
V
EW input high
threshold voltage
EWi
EWi
EWi
EWo
VEWi_thh
VEWi_thhyst
IEWi_lkg
2.42
2.57
70
2.72
V
EW input threshold
hysteresis
mV
µA
kΩ
EW input leakage
current
VEWi = 2.5 V,
VS > 4 V
-1
1
Pull up internal
resistance
REWo
Versus Vo
10
20
40
V
EWi < 2.35 V;
EW output low voltage
(with external pull up)
EWo
EWo
VEWo_lv
VS > 4 V;
Rext = 5 kΩ
0.4
1
V
EW output leakage
current
IEWo_lkg
V
EWo = 5 V
µA
10/34
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
Electrical specifications
2.4
Electrical characteristics curves
Figure 3.
Output voltage vs. Tj
Figure 4. Output voltage vs. VS
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Drop voltage vs. output current
Figure 6.
Current consumption vs. output
current
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Figure 7.
Current consumption vs. output
current (at light load condition)
Figure 8.
Current consumption vs. input
voltage (Io = 0.1 mA)
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Doc ID 15542 Rev. 15
11/34
Electrical specifications
L5150CJ / L5150CS
Figure 9.
Current consumption vs. input
voltage (Io = 75 mA)
Figure 10. Current limitation vs. Tj
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Figure 11. Current limitation vs. input voltage Figure 12. Short-circuit current vs. Tj
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Figure 13. Short-circuit current vs. input
voltage
Figure 14. VRhth vs. Tj
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12/34
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
Electrical specifications
Figure 15. VRlth vs. Tj
Figure 16. VEWi_thh vs. Tj
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Figure 17. VEWi_thl vs. Tj
Figure 18. Icr vs. Tj
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Figure 19. Idr vs. Tj
Figure 20. PSRR
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Doc ID 15542 Rev. 15
13/34
Application information
L5150CJ / L5150CS
3
Application information
3.1
Voltage regulator
The voltage regulator uses a p-channel mos transistor as a regulating element. With this
structure a very low dropout voltage at current up to 150 mA is obtained. The output voltage
is regulated up to input supply voltage of 40 V. The high-precision of the output voltage (2%)
is obtained with a pre-trimmed reference voltage. The voltage regulator automatically
adapts its own quiescent current to the output current level. In light load conditions the
quiescent current goes to 55 µA only (low consumption mode). This procedure features a
certain hysteresis on the output current (see Figure 7). Short-circuit protection to GND and a
thermal shutdown are provided.
Figure 21. Application schematic
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The input capacitor C1 ≥ 100 µF is necessary as backup supply for negative pulses which
may occur on the line. The second input capacitor C2 ≥ 220 nF is needed when the C1 is too
distant from the VS pin and it compensates smooth line disturbances. The C0 ceramic
capacitor, connected to the output pin, is for bypassing to GND the high-frequency noise
and it guarantees stability even during sudden line and load variations. Suggested value is
C0 = 220
ESR ≥ 100
nF?with
mΩ .
Stability region is reported in Figure 22.
14/34
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
Application information
Figure 22. Stability region
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Note: The curve which describes the minimum ESR is derived from characterization data on the regulator
with connected ceramic capacitors which feature low ESR values (at 100 kHz). Any capacitor with
further lower ESR than the given plot value must be evaluated in each and every case.
Figure 23. Maximum load variation response
Vo = 50 mV/div
Io = 50 mA/div
VS = 13.5 V
Io = 8 to 300 mA
Tc = 25 °C
Co = 220 nF
GAPGCFT00128
Doc ID 15542 Rev. 15
15/34
Application information
L5150CJ / L5150CS
3.2
Reset
The reset circuit monitors the output voltage Vo. If the output voltage becomes lower than
o_th then Res goes low with a delay time (trr). When the output voltage becomes higher
V
than Vo_th then Res goes high with a delay time trd. This delay is obtained by 32 periods of
oscillator. The oscillator period is given by:
Equation 1
Tosc = [(VRhth - VRlth) x Ctr] / Icr + [(VRhth - VRlth) x Ctr] / Idr
where:
I
cr = 20 µA is an internally generated charge current,
dr = 20 µA is an internally generated discharge current,
I
V
Rhth = 2.5 V (typ) and VRlth = 0.9 V (typ) are two voltage thresholds,
Ctr is an external capacitor put between Vcr pin and GND.
16/34
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
Application information
Reset pulse delay Trd is given by:
Equation 2
trd = 32 x Tosc
The Output Voltage Reset threshold can be adjusted via an external voltage divider R1 + R2
(R1 connected between Res_Adj and V0, R2 connected between Res_Adj and GND) according
to the following formula:
Equation 3
Vthre = [(R1 + R2) / R2] * VRes_adj
The Output Voltage Reset threshold can be decreased down to 3.5 V. If it is needed to
maintain it to its default value (8% below V0_ref typical), it is enough to connect the Res_Adj
pin directly to GND.
Figure 24. Reset time diagram
:
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Doc ID 15542 Rev. 15
17/34
Application information
L5150CJ / L5150CS
3.3
Early warning
This circuit compares the EWi input signal with the internal voltage reference (typically
2.5 V). The use of an external voltage divider makes the comparator very flexible in the
application. This function can be used to supervise the supply input voltage either before or
after the protection diode and to give additional information to the microprocessor such as
low voltage warnings.
Figure 25. Early warning time diagram
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18/34
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
Package and PCB thermal data
4
Package and PCB thermal data
4.1
PowerSSO-12 thermal data
Figure 26. PowerSSO-12 PC board(1)
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1. Layout condition of R and Z measurements (PCB: double layer, thermal vias,
th
th
FR4 area = 77 mm x 86 mm, PCB thickness = 1.6 mm, Cu thickness = 70 µm (front and back side),
thermal vias separation 1.2 mm, thermal via diameter 0.3 mm +/- 0.08 mm, Cu thickness on vias 25 µm,
footprint dimension 4.1 mm x 6.5 mm ).
Figure 27. Rthj-amb vs PCB copper area in open box free air condition
57+MDPE
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Doc ID 15542 Rev. 15
19/34
Package and PCB thermal data
L5150CJ / L5150CS
Figure 28. PowerSSO-12 thermal impedance junction ambient single pulse
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Equation 4: pulse calculation formula
= R ⋅ δ + Z (1 – δ)
THtp
Z
THδ
TH
where δ = tP/T
Figure 29. Thermal fitting model of Vreg in PowerSSO-12
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20/34
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
Table 8.
Package and PCB thermal data
PowerSSO-12 thermal parameter
Area (cm2)
R1 (°K/W)
R2 (°K/W)
R3 (°K/W)
R4 (°K/W)
R5 (°K/W)
R6 (°K/W)
C1 (W.s/°K)
C2 (W.s/°K)
C3 (W.s/°K)
C4 (W.s/°K)
C5 (W.s/°K)
C6 (W.s/°K)
Footprint
1.53
3.21
5.2
2
8
7
7
8
22
15
20
10
15
26
0.00004
0.0016
0.08
0.2
0.1
0.8
6
0.1
1
0.27
3
9
Doc ID 15542 Rev. 15
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Package and PCB thermal data
L5150CJ / L5150CS
4.2
SO-8 thermal data
Figure 30. SO-8 PC board(1)
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1. Layout condition of R and Z measurements (PCB: double layer, thermal vias,
th
th
FR4 area = 48 mm x 48 mm, PCB thickness = 2 mm, Cu thickness = 35 µm (front and back side),
Cu thickness on vias 25 µm, Footprint dimension 4.1 mm x 6.5 mm ).
Figure 31. Rthj-amb vs. PCB copper area in open box free air condition
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22/34
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
Package and PCB thermal data
Figure 32. SO-8 thermal impedance junction ambient single pulse
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Equation 5: pulse calculation formula
= R ⋅ δ + Z
Z
(1 – δ)
THδ
TH
THtp
where δ = tP/T
Figure 33. Thermal fitting model of Vreg in in SO-8
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Doc ID 15542 Rev. 15
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Package and PCB thermal data
L5150CJ / L5150CS
Table 9.
SO-8 thermal parameter
Area (cm2)
Footprint
2
R1 (°K/W)
R2 (°K/W)
R3 (°K/W)
R4 (°K/W)
R5 (°K/W)
R6 (°K/W)
C1 (W.s/°K)
C2 (W.s/°K)
C3 (W.s/°K)
C4 (W.s/°K)
C5 (W.s/°K)
C6 (W.s/°K)
1.53
3.21
5.4
32
34
52
36
0.00004
0.0016
0.04
0.05
0.15
1
2.5
24/34
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
Package and packing information
5
Package and packing information
®
5.1
ECOPACK
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
5.2
PowerSSO-12 mechanical data
Figure 34. PowerSSO-12 package dimensions
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Doc ID 15542 Rev. 15
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Package and packing information
L5150CJ / L5150CS
Table 10. PowerSSO-12 mechanical data
Millimeters
Typ.
Symbol
Min.
1.250
0.000
1.100
0.230
0.190
4.800
3.800
Max.
1.620
0.100
1.650
0.410
0.250
5.000
4.000
A
A1
A2
B
C
D
E
e
0.800
H
5.800
0.250
0.400
0°
6.200
0.500
1.270
8°
h
L
k
X
1.900
3.600
2.500
4.200
0.100
Y
ddd
26/34
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
Package and packing information
5.3
SO-8 package information
Figure 35. SO-8 package dimensions
Doc ID 15542 Rev. 15
27/34
Package and packing information
L5150CJ / L5150CS
Table 11.
SO-8 mechanical data
Millimeters
Typ.
Symbol
Min.
Max.
1.75
0.25
A
A1
A2
b
0.10
1.25
0.28
0.17
4.80
5.80
3.80
0.48
0.23
5.00
6.20
4.00
c
D(1)
E
4.90
6.00
3.90
1.27
E1(2)
e
h
0.25
0.40
0.50
1.27
L
L1
k
1.04
0°
8°
ccc
0.10
1. Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs
shall not exceed 0.15 mm in total (both side).
2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25 mm per side.
28/34
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
Package and packing information
5.4
PowerSSO-12 packing information
Figure 36. PowerSSO-12 tube shipment (no suffix)
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Doc ID 15542 Rev. 15
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Package and packing information
L5150CJ / L5150CS
5.5
SO-8 packing information
Figure 38. SO-8 tube shipment (no suffix)
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30/34
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
Revision history
6
Revision history
Table 12. Document revision history
Date
Revision
Changes
09-Aug-2007
1
Initial release.
Updated Table 5.: General:
– changed Vo_ref, Vline, Vload test conditions
– added notes to Ilim and Vdp parameters
– added Ioth_H, Ioth_L, oth
Updated Table 6.: Reset:
– added Vres_adj parameter
I
parameters.
06-Mar-2008
2
– changed VRlth values (min./ typ./ max.) from 17/20/23 to 20/23/26
(% Vo_ref).
Modified Section 3.2: Reset.
Updated Table 5.: General :
– changed Ilim values (Min./Typ./Max.) from 0.7/1/1.30 A to
280/470/660 mA
09-May-2008
3
– Vo_ref parameter : updated Io test condition
Old -> Io = 0.1 mA to I0 mA
New -> Io = 0.1 mA to 8 mA.
Updated Table 5.: General :
– Vload parameter : updated Io test condition
Old -> Io = 5 mA to I50 mA
New -> Io = 8 mA to 150 mA.
13-Oct-2008
23-Oct-2008
4
5
Added S0-8 package option.
Doc ID 15542 Rev. 15
31/34
Revision history
L5150CJ / L5150CS
Table 12. Document revision history (continued)
Date
Revision
Changes
Updated corporate template from V2 to V3
Updated Figure 2: Configuration diagram (top view)
Table 2: Pins description
– Added new row
Table 3: Absolute maximum ratings
– VEn: deleted row
Table 4: Thermal data
– Rthj-amb: changed value
– Added new row
– Updated TableFootnote
Table 5: General
– Vload: changed max value for Vs = 8 V to 18 V, added new row
– Iqn_1: changed Test conditions (added Tj = 25 °C), added new row
Table 6: Reset
– VRlth: changed min/typ/max value
– VRes_adjl: replaced with VRlth, changed Parameter
Table 7: Early warning
– Updated symbols
Added Figure 3: Output voltage vs. Tj
Added Figure 4: Output voltage vs. VS
Added Figure 5: Drop voltage vs. output current
Added Figure 6: Current consumption vs. output current
16-Apr-2009
6
Added Figure 7: Current consumption vs. output current (at light load
condition)
Added Figure 8: Current consumption vs. input voltage (Io = 0.1 mA)
Added Figure 9: Current consumption vs. input voltage (Io = 75 mA)
Added Figure 10: Current limitation vs. Tj
Added Figure 11: Current limitation vs. input voltage
Added Figure 12: Short-circuit current vs. Tj
Added Figure 13: Short-circuit current vs. input voltage
Added Figure 14: VRhth vs. Tj
Added Figure 15: VRlth vs. Tj
Added Figure 16: VEWi_thh vs. Tj
Added Figure 17: VEWi_thl vs. Tj
Added Figure 18: Icr vs. Tj
Added Figure 19: Idr vs. Tj
Added Figure 20: PSRR
Section 3.1: Voltage regulator
– Updated text
– Added Figure 21: Application schematic
– Added Figure 23: Maximum load variation response
Section 3.2: Reset
–
VRlth: changed value from 1.15 V to 0.9 V in Equation 1
Added Section 4: Package and PCB thermal data
Changed Section 5.1: ECOPACK®
32/34
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
Revision history
Table 12. Document revision history (continued)
Date
Revision
Changes
Changed document title
Table 5: General
– Ioth_H, Ioth_L: added test condition
Updated Figure 4: Output voltage vs. VS
Section 3.3: Early warning
09-Jun-2009
7
– changed internal voltage reference typical value
from 1.23 V to 2.5 V
Updated Figure 28: PowerSSO-12 thermal impedance junction
ambient single pulse
Updated Figure 32: SO-8 thermal impedance junction ambient single
pulse
Updated features list.
Updated Table 2: Pins description.
Updated Section 3.1: Voltage regulator.
Corrected Equation 3 on Section 3.2: Reset.
04-Dec-2009
8
Updated Table 5: General:
26-Mar-2010
12-Apr-2010
9
– Iqn_1, Iqn_150: removed test condition En = high.
Table 4: Thermal data:
10
– Rthj-amb: updated PowerSSO-12 value
Table 4: Thermal data:
14-Mar-2011
11
– Rthj-amb: updated PowerSSO-12 value
– Rthj-lead: updated SO-8 value
30-Jan-2012
07-Feb-2012
12
13
Updated Figure 22: Stability region on page 15.
Modified Figure 22: Stability region on page 15.
Table 6: Reset:
17-Apr-2012
19-Sep-2013
14
15
– Trd: updated maximum value
Updated disclaimer.
Doc ID 15542 Rev. 15
33/34
L5150CJ / L5150CS
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