L4995RK [STMICROELECTRONICS]
5V, 500mA low drop voltage regulator; 5V ， 500毫安低压降稳压器
| 型号： | L4995RK |
| 厂家： | 
ST |
| 描述： | 5V, 500mA low drop voltage regulator |
| 文件： | 总35页 (文件大小：1062K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L4995
5V, 500mA low drop voltage regulator
Datasheet − production data
Features
Max DC supply voltage
Max output voltage tolerance
Max dropout voltage
Output current
VS
ΔV0
Vdp
I0
40V
+/-2%
500mV
500mA
3µA(1)
PowerSSO-12
PowerSSO-24
Description
Quiescent current
Iqn
L4995 is a family of monolithic integrated 5 V
voltage regulators with a low drop voltage at
currents of up to 500 mA, available in both 12 and
24 pin packages.
1. Typical value with regulator disabled
■ Operating DC supply voltage range 5.6V to
31V
The output voltage regulating element consists of
a p-channel MOS and regulation is performed
regardless of input voltage transients of up to 40V.
■ Low dropout voltage
■ Low quiescent current consumption
■ Reset circuit sensing of output voltage down to
The high precision of the output voltage is
obtained using a pre-trimmed reference voltage.
The L4995 family is protected against short circuit
and overtemperature protection switches off the
devices in the case of extremely high power
dissipation. The L4995 integrates the watchdog,
enable and externally programmable reset
circuits. The L4995A features the externally
programmable reset and enable. Finally the
L4995R features the externally programmable
reset.
1 V
■ Programmable reset pulse delay with external
capacitor
■ Programmable watchdog(a) timer with external
capacitor
■ Thermal shutdown and short circuit protection
■ Wide temperature range (Tj = -40 °C to 150 °C)
■ Enable(a) input for enabling/disabling the
voltage regulator
The combination of such features makes this
device particularly flexible and suitable to supply
microprocessor systems in automotive
applications.
a. Watchdog and Enable facilities are available
according to Device summary table.
Table 1.
Device summary
Package
Order codes
Tape and reel
Tube
PowerSSO-12 (exposed pad)
PowerSSO-24 (exposed pad)
P/N
L4995J - L4995AJ - L4995RJ
L4995K - L4995AK - L4995RK
L4995JTR - L4995AJTR - L4995RJTR
L4995KTR - L4995AKTR - L4995RKTR
Watchdog
Reset
Enable
L4995J - L4995K
X
-
X
X
X
X
X
-
L4995AJ - L4995AK
L4995RJ - L4995RK
-
October 2012
Doc ID 13103 Rev 13
1/35
This is information on a product in full production.
www.st.com
1
Contents
L4995
Contents
1
2
Block diagrams and pins descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
2.3
2.4
2.5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Test circuit and waveforms plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5.1
Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1
3.2
3.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4
5
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1
4.2
PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
®
5.1
5.2
5.3
5.4
ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PowerSSO-12 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PowerSSO-24 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2/35
Doc ID 13103 Rev 13
L4995
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pins descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PowerSSO-12 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PowerSSO-24 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Doc ID 13103 Rev 13
3/35
List of figures
L4995
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram of L4995 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block diagram of L4995A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block diagram of L4995R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pins configurations (L4995) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Output voltage vs Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output voltage vs VS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Drop voltage vs output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Current consumption vs output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Current consumption vs input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. Current limitation vs Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. Current limitation vs input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Short circuit current vs input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 13. Output voltage vs enable voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
V
V
V
V
V
V
En_high vs Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
EN_LOW vs Tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Rhth vs Tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Rlth vs Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
whth vs Tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
wlth vs Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 20. Icr and Icwc vs Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 21.
Figure 22.
I
T
dr and Icwd vs Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
wop vs Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 23. PSRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 24. Load regulation test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 25. Maximum load variation response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 26. L4995 application schematic(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 27. Stability region(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 28. Behavior of output current versus regulated voltage Vo . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 29. Reset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 30. Watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 31. PowerSSO-12 PC board(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 32. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 20
Figure 33. PowerSSO-12 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 21
Figure 34. Thermal fitting model of Vreg in PowerSSO-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 35. PowerSSO-24 PC board(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 36. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 23
Figure 37. PowerSSO-24 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 24
Figure 38. Thermal fitting model of Vreg in PowerSSO-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 39. PowerSSO-12 package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 40. PowerSSO-24 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 41. PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 42. PowerSSO-12 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 43. PowerSS0-24 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 44. PowerSSO-24 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4/35
Doc ID 13103 Rev 13
L4995
Block diagrams and pins descriptions
1
Block diagrams and pins descriptions
Figure 1.
Block diagram of L4995
9R
9V
)S
)O
9RV
6
6WDUWꢀXS
3
ꢁꢄꢅꢆ9
)
%N
9ROWDJH
5HIHUHQFH
(Q
6O
ꢃ
ꢁꢂꢂP9
B
6%N
9FZ
)CW
6CW
5HV
:L
ZDWFKGRJ
6WI
6
2ES
/RZꢀ9ROWDJH
5HVHW
9FU
'.$
6CR
("1(.4ꢀꢀꢀꢁꢂ
Figure 2.
Block diagram of L4995A
9R
9V
)S
)O
9RV
6
6WDUWꢀXS
3
ꢁꢄꢅꢆ9
)
%N
9ROWDJH
5HI HU HQ FH
(Q
6O
ꢃ
B
ꢁꢂꢂP9
6%N
5HV
6
2ES
/RZꢀ9ROWDJH
5HVHW
9FU
'.$
6CR
'!0'-3ꢀꢀꢀꢁꢂ
Doc ID 13103 Rev 13
5/35
Block diagrams and pins descriptions
L4995
Figure 3.
Block diagram of L4995R
9R
9V
)S
)O
9RV
6
6WDUWꢀXS
3
ꢁꢄꢅꢆ9
9ROWDJH
5HIHUHQFH
6O
ꢃ
B
ꢁꢂꢂP9
6%N
5HV
6
2ES
/RZꢀ9ROWDJH
5HVHW
9FU
'.$
6CR
'!0'-3ꢀꢀꢀꢁꢃ
Table 2.
Pins descriptions
PowerSSO-12 PowerSSO-24
Pin
Function
name
pin #
pin #
Enable input (L4995 and L4996A only, otherwise not
connected).
En
1
13, 14, 15
If high regulator, watchdog and reset are operating. If
low regulator, watchdog and reset are shutdown.
Connect to Vs if not used.
NC
2, 4, 8
3
3, 5, 6, 9, 11 Not connected.
GND
16, 17, 18
TAB, 1, 12
Ground reference.
Substrate of the chip: connect the pins or the TAB to
GND.
-
TAB
5
Reset output.
Res
19, 20, 21
22, 23, 24
It is pulled down when output voltage goes below Vo_th
or frequency at Wi is too low. Leave floating if not used.
Reset timing adjust.
Vcr
6
7
A capacitor between Vcr pin and GND. Sets the reset
delay time (trd). Leave floating if Reset is not used.
Watchdog timer adjust (L4995 only, otherwise not
connected).
Vcw
2
A capacitor between Vcw pin and GND. Sets the time
response of the watchdog monitor.
6/35
Doc ID 13103 Rev 13
L4995
Block diagrams and pins descriptions
Table 2.
Pins descriptions (continued)
PowerSSO-12 PowerSSO-24
Pin
Function
name
pin #
pin #
Watchdog input (L4995 only, otherwise not connected).
Wi
Vos
Vo
9
4
7
8
If the frequency at this input pin is too low, the Reset
output is activated.
10
11
Regulator voltage output sensing.
5 voltage regulator output.
Block to ground with a capacitor >100nF (needed for
regulator stability).
Supply voltage.
VS
12
10
Block to ground directly at VS pin with a ceramic
capacitor (e.g. 200nF).
Figure 4.
Pins configurations (L4995)
SUBSTRATE
4!" ꢄ SUBSTRATE
SUBSTRATE
4!" ꢄ SUBSTRATE
'!0'-3ꢀꢀꢀꢁꢅ
Doc ID 13103 Rev 13
7/35
Electrical specifications
L4995
2
Electrical specifications
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 3.
Symbol
Absolute maximum ratings
Parameter
Value
- 0.3 to 40
Unit
VVsdc
IVsdc
DC supply voltage
V
Input current
Internally limited
- 0.3 to 6
(1)
VVo
DC output voltage
V
IVo
VWi
Vod
Iod
DC output current
Internally limited
-0.3 to VVo + 0.3
-0.3 to VVo + 0.3
Internally limited
- 0.3 to VVo + 0.3
- 0.3 to VVo + 0.3
- 0.3 to VVsdc +0.3
- 40 to 150
Watchdog input voltage
Res output voltage
V
V
Res output current
Vcr
Vcr voltage
V
V
Vcw
VEn
Tj
Watchdog delay voltage
Enable input
V
Junction temperature
ESD voltage level (HBM-MIL STD 883C)
ESD voltage level (CDM AEC-Q100-011)
C
VESD
VESD
2
kV
V
750
1. Using the typical application schematic with Cout= 10 µF and Iout=0 A, when the regulator is switched-on,
an overshoot exceeding 6 V could occur.This behavior does not impact the reliability of the regulator.
8/35
Doc ID 13103 Rev 13
L4995
Electrical specifications
2.2
Thermal data
For details, please refer to Section 4.1: PowerSSO-12 thermal data and Section 4.2:
PowerSSO-24 thermal data.
mm
Table 4.
Symbol
Thermal data(1)
Parameter
Value
Unit
Thermal resistance Junction to Case:
PowerSSO-12
Rthj-case
5
4
°K/W
°K/W
PowerSSO-24
Thermal resistance Junction to Ambient:
PowerSSO-12
Rthj-amb
52
38
°K/W
°K/W
PowerSSO-24
1. The values quoted are for PCB 77mm x 86mm x 1.6mm, FR4, double layer; Copper thickness 0.070mm
Copper area 3cm2 Thermal Vias, Thermal vias separation 1.2 mm, Thermal via diameter 0.3 mm +/- 0.08
mm, Cu thickness on vias 0.025 mm.
2.3
Electrical characteristics
Values specified in this section are for Vs = 5.6V to 31V, Tj = -40 °C to +150 °C unless
otherwise stated.
Table 5.
Pin
General
Symbol
Parameter
Test condition
Min. Typ. Max.
4.9 5.00 5.1
550 800 1050
600 900 1250
25
Unit
V
VS = 5.6 to 31V
Io = 0 to 500mA
Vo
Vo_ref
Ishort
Output voltage
Vo
Short circuit current
Output current limitation
Line regulation voltage
Load regulation voltage
Drop voltage
VS = 13.5V (1)
mA
mA
mV
mV
mV
dB
Vo
Ilim
VS = 13.5V (1)
(2)
VS = 5.6 to 31V
Io = 0 to 500mA
VS, Vo
Vo
Vline
Vload
Io = 0 to 500mA
Io = 400mA
25
(3)
VS, Vo
VS, Vo
VS, Vo
VS, Vo
VS, Vo
Vdp
270 500
SVR
Iqs
Ripple rejection
fr = 100 Hz (4)
55
Current consumption with VS = 13.5V,
regulator disabled
3
10
µA
En = low
Current consumption
with regulator enabled
VS = 13.5V,
Io < 1mA,
Iqn_1
Iqn_50
90
160
µA
Current consumption
with regulator enabled
VS = 13.5V,
Io = 50mA,
290 400
µA
Doc ID 13103 Rev 13
9/35
Electrical specifications
Table 5.
L4995
General (continued)
Symbol Parameter
Pin
Test condition
Min. Typ. Max.
Unit
µA
Current consumption
with regulator enabled
VS = 13.5V,
Io = 150mA,
VS, Vo
VS, Vo
VS, Vo
Iqn_150
Iqn_250
Iqn_500
Tw
740 1000
Current consumption
with regulator enabled
VS= 13.5V,
Io= 250mA,
1
1.4
2.7
190
mA
mA
°C
Current consumption
with regulator enabled
VS= 13.5V,
Io= 500mA,
2.1
Thermal protection
temperature
150
Thermal protection
temperature hysteresis
Tw_hy
10
°C
1. See Figure 28.
2. Measured output current when the output voltage has dropped 100mV from its nominal value obtained at
Vs=13.5V and I = 250mA.
o
3. Vs-V measured when the output voltage has dropped 100mV from its nominal value obtained at Vs=13.5V
o
and I = 250mA.
o
4. Guaranteed by design.
Table 6.
Pin
Reset
Symbol
Parameter
Test condition
Min. Typ. Max.
Unit
V
R
ext = 5kΩ to Vo,
Vo > 1V
Res
Res
Res
Res
Vcr
Vres_l
IRes_lkg
RRes
Vo_th
VRlth
VRhth
Icr
Reset output low voltage
0.4
1
Reset output high leakage
current
VRes = 5V
µA
kΩ
Pull up internal resistance
(versus Vo)
10
20
40
VS = 5.6 to 31V
Io = 1 to 500mA
Vo out of regulation
threshold
below
Vo_ref
6%
8% 10%
Reset delay circuit low
threshold
VS = 13.5V
VS =13.5V
VS = 13.5V
VS = 13.5V
10% 13% 16% Vo_ref
44% 47% 50% Vo_ref
Reset delay circuit high
threshold
Vcr
Vcr
Charge current
8
8
15
15
30
30
µA
µA
µs
Vcr
Idr
Discharge current
Reset reaction time(1)
Reset delay time
Res
Res
T
Vo = Vo_th -100mV 100 250 700
VS = 13.5V,
rr
T
12
33
73
ms
rd
Ctr = 47nF
1. When V becomes lower than 4V, the reset reaction time decreases down to 2µs assuring a faster reset
o
condition in this particular case.
10/35
Doc ID 13103 Rev 13
L4995
Electrical specifications
Table 7.
Pin
Watchdog
Symbol
Parameter
Input high voltage
Input low voltage
Input hysteresis
Test condition
VS = 13.5V
Min. Typ. Max.
Unit
V
Wi
Wi
Vih
Vil
3.5
1.5
500
VS = 13.5V
V
Wi
Vih
VS = 13.5V
mV
µA
VS = 13.5V
Vwi = 3.5V
Wi
Iwi
Pull down current
Low threshold
6
10
Vcw
Vcw
Vcw
Vcw
Vcw
Res
Vwlth
Vwhth
Icwc
Icwd
Twop
twol
VS = 13.5V
10% 13% 16% Vo_ref
44% 47% 50% Vo_ref
High threshold
VS = 13.5V
VS = 13.5V,
Charge current
5
10
20
5
µA
µA
ms
ms
V
cw = 0.1V
VS = 13.5V,
cw = 2.5V
Discharge current
Watchdog period
Watchdog output low time
1.25 2.5
V
VS = 13.5V,
Ctw = 47nF
20
4
40
8
80
16
VS = 13.5V,
Ctw = 47nF
Table 8.
Pin
Enable
Symbol
Parameter
Test condition
Min. Typ. Max.
Unit
V
En
En
En
En
VEn_low En input low voltage
VEn_high En input high voltage
VEn_hyst En input hysteresis
1
3
V
830
mV
µA
IEn
Pull down current
VS = 13.5V
10
18
Doc ID 13103 Rev 13
11/35
Electrical specifications
L4995
2.4
Electrical characteristics curves
Figure 5.
Output voltage vs Tj
Figure 6. Output voltage vs VS
6O?REF ꢉ6ꢊ
ꢈꢀ
6O?REF ꢉ6ꢊ
ꢁꢋꢁ
ꢁꢋꢅ
ꢁꢋꢃ
ꢁꢋꢂ
ꢁꢋꢈ
ꢁ
ꢎ
ꢍ
6Sꢄ ꢈꢃꢏꢁ6
)ꢀ ꢄ ꢂꢁꢀM!
ꢇ
)ꢀ ꢄ ꢂꢁꢀ M!
4J ꢄ ꢂꢁ
#
ꢌ
ꢁ
ꢅ
ꢃ
ꢂ
ꢅꢋꢎ
ꢅꢋꢍ
ꢅꢋꢇ
ꢅꢋꢌ
ꢅꢋꢁ
ꢈ
ꢀ
ꢀ
ꢁ
ꢈꢀ
ꢈꢁ
6S ꢉ6 ꢊ
ꢂꢀ
ꢂꢁ
ꢃꢀ
ꢃꢁ
ꢆꢁꢀ
ꢆꢂꢁ
ꢀ
ꢂꢁ
ꢁꢀ
ꢇꢁ
ꢈꢀꢀ
ꢈꢂꢁ
ꢈꢁꢀ
4Jꢉ # ꢊ
'!0'-3ꢀꢀꢀꢁꢌ
'!0'-3ꢀꢀꢀꢁꢁ
Figure 7.
Drop voltage vs output current
Figure 8.
Current consumption vs output
current
6DP ꢉ6ꢊ
ꢀꢋꢁ
)QN ꢉ!ꢊ
ꢂꢁꢀꢀ
ꢂꢀꢀꢀ
ꢈꢁꢀꢀ
ꢈꢀꢀꢀ
ꢁꢀꢀ
6Sꢄ ꢈꢃꢏꢁ 6
ꢀꢋꢅꢁ
ꢀꢋꢅ
4Jꢄ ꢂꢁ
#
%Nꢄ (IGH
ꢀꢋꢃꢁ
ꢀꢋꢃ
4Jꢄ ꢈꢂꢁ
#
ꢀꢋꢂꢁ
ꢀꢋꢂ
4Jꢄ ꢂꢁ
#
ꢀꢋꢈꢁ
ꢀꢋꢈ
ꢀ
ꢀꢋꢀꢁ
ꢆꢈꢀꢀ
ꢀ
ꢈꢀꢀ
ꢂꢀꢀ
ꢃꢀꢀ
ꢅꢀꢀ
ꢁꢀꢀ
ꢌꢀꢀ
)O ꢉM!ꢊ
ꢀ
'!0'-3ꢀꢀꢀꢁꢍ
ꢆꢈꢀꢀ
ꢀ
ꢈꢀꢀ
ꢂꢀꢀ
ꢃꢀꢀ
ꢅꢀꢀ
ꢁꢀꢀ
ꢌꢀꢀ
)O ꢉM!ꢊ
'!0'-3ꢀꢀꢀꢁꢇ
Figure 9.
Current consumption vs input
voltage
Figure 10. Current limitation vs Tj
)QNꢉ! ꢊ
ꢈꢂꢀꢀ
)LIM ꢉM!ꢊ
ꢈꢂꢀꢀ
ꢈꢈꢀꢀ
ꢈꢀꢀꢀ
ꢎꢀꢀ
ꢍꢀꢀ
ꢇꢀꢀ
ꢌꢀꢀ
ꢁꢀꢀ
ꢅꢀꢀ
ꢃꢀꢀ
ꢂꢀꢀ
ꢈꢀꢀ
4J ꢄ ꢂꢁ
%N ꢄ (IGH
#
)Oꢄ ꢂꢁꢀM!
)Oꢄ ꢈꢁꢀM!
ꢈꢈꢀꢀ
ꢈꢀꢀꢀ
6Sꢄ ꢈꢃꢏꢁ6
ꢎꢀꢀ
ꢍꢀꢀ
ꢇꢀꢀ
ꢌꢀꢀ
ꢁꢀꢀ
)O ꢄꢁꢀM!
)O ꢐ ꢈM!
ꢀ
ꢀ
ꢆꢁꢀ
ꢆꢂꢁ
ꢀ
ꢂꢁ
ꢁꢀ
ꢇꢁ
ꢈꢀꢀ
ꢈꢂꢁ
ꢈꢁꢀ
ꢁ
ꢈꢀ
ꢈꢁ
ꢂꢀ
ꢂꢁ
ꢃꢀ
ꢃꢁ
4Jꢉ # ꢊ
'!0'-3ꢀꢀꢀꢌꢀ
6S ꢉ6 ꢊ
'!0'-3ꢀꢀꢀꢁꢎ
12/35
Doc ID 13103 Rev 13
L4995
Electrical specifications
Figure 11. Current limitation vs input voltage Figure 12. Short circuit current vs input
voltage
e
)LIM ꢉM!ꢊ
)SHORT ꢉM! ꢊ
ꢈꢂꢀꢀ
ꢈꢀꢀꢀ
ꢈꢈꢁꢀ
ꢎꢁꢀ
ꢈꢈꢀꢀ
ꢈꢀꢁꢀ
ꢈꢀꢀꢀ
ꢎꢁꢀ
ꢎꢀꢀ
ꢍꢁꢀ
ꢍꢀꢀ
ꢇꢁꢀ
ꢇꢀꢀ
ꢌꢁꢀ
ꢌꢀꢀ
ꢁꢁꢀ
ꢁꢀꢀ
ꢎꢀꢀ
ꢍꢁꢀ
ꢍꢀꢀ
ꢇꢁꢀ
ꢇꢀꢀ
ꢌꢁꢀ
ꢌꢀꢀ
ꢁꢁꢀ
ꢁꢀꢀ
4J ꢄ ꢂꢁ
#
4J ꢄ ꢂꢁ
#
4J ꢄ ꢈꢁꢀ
#
4J ꢄ ꢈꢂꢁ
#
ꢀ
ꢁ
ꢈꢀ
ꢈꢁ
ꢂꢀ
ꢂꢁ
ꢃꢀ
ꢃꢁ
ꢀ
ꢁ
ꢈꢀ
ꢈꢁ
ꢂꢀ
ꢂꢁ
ꢃꢀ
ꢃꢁ
6S ꢉ6 ꢊ
'!0'-3ꢀꢀꢀꢌꢈ
6S ꢉ6 ꢊ
'!0'-3ꢀꢀꢀꢌꢂ
Figure 13. Output voltage vs enable voltage
Figure 14. VEn_high vs Tj
6EN?HIGH ꢉ6ꢊ
ꢃ
ꢇꢁꢀ
ꢆꢁꢀ
ꢅꢁꢀ
ꢄꢁꢀ
ꢃꢁꢀ
ꢂꢁꢀ
ꢀꢁꢀ
ꢂꢋꢎ
ꢂꢋꢍ
ꢂꢋꢇ
ꢂꢋꢌ
ꢂꢋꢁ
ꢂꢋꢅ
ꢂꢋꢃ
ꢂꢋꢂ
ꢂꢋꢈ
ꢂ
6Sꢄ ꢁꢏꢌ6 TO ꢃꢈ6
ꢀꢁꢀ
ꢀꢁꢈ
ꢂꢁꢅ
ꢂꢁꢉ
ꢃꢁꢀ
ꢁꢄ
ꢃꢁꢇ
ꢃꢁꢊ
ꢆꢁꢀ
ꢆꢁꢀ
ꢆꢂꢁ
ꢀ
ꢂꢁ
ꢁꢀ
ꢇꢁ
ꢈꢀꢀ
ꢈꢂꢁ
ꢈꢁꢀ
6EN ꢉ ꢊ
4Jꢉ # ꢊ
'!0'-3ꢀꢀꢀꢌꢃ
'!0'-3ꢀꢀꢀꢌꢅ
Figure 15. VEN_LOW vs Tj
Figure 16. VRhth vs Tj
6RHTH ꢉꢑ 6O?REF ꢊ
ꢍꢀ
6EN?LOW ꢉ6ꢊ
ꢂ
6Sꢄ ꢁꢏꢌ6 TO ꢃꢈ6
ꢇꢀ
ꢌꢀ
ꢁꢀ
ꢅꢀ
ꢃꢀ
ꢂꢀ
ꢈꢋꢎ
ꢈꢋꢍ
6Sꢄ ꢁꢏꢌ6 TO ꢃꢈ6
ꢈꢋꢇ
ꢈꢋꢌ
ꢈꢋꢁ
ꢈꢋꢅ
ꢆꢁꢀ
ꢆꢂꢁ
ꢀ
ꢂꢁ
ꢁꢀ
ꢇꢁ
ꢈꢀꢀ
ꢈꢂꢁ
ꢈꢁꢀ
ꢆꢁꢀ
ꢆꢂꢁ
ꢀ
ꢂꢁ
ꢁꢀ
ꢇꢁ
ꢈꢀꢀ
ꢈꢂꢁ
ꢈꢁꢀ
4Jꢉ # ꢊ
4Jꢉ # ꢊ
'!0'-3ꢀꢀꢀꢌꢁ
'!0'-3ꢀꢀꢀꢌꢌ
Doc ID 13103 Rev 13
13/35
Electrical specifications
Figure 17. VRlth vs Tj
L4995
Figure 18. Vwhth vs Tj
6RLTH ꢉꢑ 6O?REFꢊ
ꢁꢀ
6WHTH ꢉꢑ 6O?REF ꢊ
ꢍꢀ
6Sꢄ ꢁꢏꢌ6 TO ꢃꢈ6
ꢇꢀ
ꢌꢀ
ꢁꢀ
ꢅꢀ
ꢃꢀ
ꢂꢀ
6Sꢄ ꢁꢏꢌ6 TO ꢃꢈ6
ꢅꢀ
ꢃꢀ
ꢂꢀ
ꢈꢀ
ꢀ
ꢆꢁꢀ
ꢆꢂꢁ
ꢀ
ꢂꢁ
ꢁꢀ
ꢇꢁ
ꢈꢀꢀ
ꢈꢂꢁ
ꢈꢁꢀ
ꢆꢁꢀ
ꢆꢂꢁ
ꢀ
ꢂꢁ
ꢁꢀ
ꢇꢁ
ꢈꢀꢀ
ꢈꢂꢁ
ꢈꢁꢀ
4Jꢉ # ꢊ
4Jꢉ # ꢊ
'!0'-3ꢀꢀꢀꢌꢇ
'!0'-3ꢀꢀꢀꢌꢍ
Figure 19. Vwlth vs Tj
Figure 20. Icr and Icwc vs Tj
6WLTH ꢉꢑ 6O?REFꢊ
ꢁꢀ
)CR ꢒ )CWC ꢉ!ꢊ
ꢂꢀ
6Sꢄ ꢁꢏꢌ6 TO ꢃꢈ6
6CWꢄ ꢀꢏꢈ6
ꢈꢍ
6Sꢄ ꢁꢏꢌ6 TO ꢃꢈ6
ꢅꢀ
ꢃꢀ
ꢂꢀ
ꢈꢀ
ꢀ
ꢈꢌ
)CR
ꢈꢅ
ꢈꢂ
)CWC
ꢈꢀ
ꢍ
ꢌ
ꢆꢁꢀ
ꢆꢂꢁ
ꢀ
ꢂꢁ
ꢁꢀ
ꢇꢁ
ꢈꢀꢀ
ꢈꢂꢁ
ꢈꢁꢀ
ꢆꢁꢀ
ꢆꢂꢁ
ꢀ
ꢂꢁ
ꢁꢀ
ꢇꢁ
ꢈꢀꢀ
ꢈꢂꢁ
ꢈꢁꢀ
4Jꢉ # ꢊ
4Jꢉ # ꢊ
'!0'-3ꢀꢀꢀꢇꢀ
'!0'-3ꢀꢀꢀꢌꢎ
Figure 21. Idr and Icwd vs Tj
Figure 22. Twop vs Tj
)DR ꢒ )CWD ꢉ!ꢊ
ꢂꢀ
4WOP ꢉMSꢊ
ꢍꢀ
ꢈꢍ
6Sꢄ ꢁꢏꢌ6 TO ꢃꢈ6
6CW ꢄ ꢂꢏꢁ6
ꢇꢀ
ꢌꢀ
ꢁꢀ
ꢅꢀ
ꢃꢀ
ꢂꢀ
ꢈꢌ
ꢈꢅ
ꢈꢂ
ꢈꢀ
ꢍ
)DR
6Sꢄ ꢁꢏꢌ6 TO ꢃꢈ6
#TWꢄ ꢅꢇN&
ꢌ
ꢅ
)CWD
ꢂ
ꢀ
ꢆꢁꢀ
ꢆꢂꢁ
ꢀ
ꢂꢁ
ꢁꢀ
4Jꢉ # ꢊ
ꢇꢁ
ꢈꢀꢀ
ꢈꢂꢁ
ꢈꢁꢀ
ꢆꢁꢀ
ꢆꢂꢁ
ꢀ
ꢂꢁ
ꢁꢀ
ꢇꢁ
ꢈꢀꢀ
ꢈꢂꢁ
ꢈꢁꢀ
4Jꢉ # ꢊ
'!0'-3ꢀꢀꢀꢇꢂ
'!0'-3ꢀꢀꢀꢇꢈ
14/35
Doc ID 13103 Rev 13
L4995
Electrical specifications
Figure 23. PSRR
C0= 44.77 µF
PSRR [dB]
80,00
70,00
60,00
50,00
40,00
30,00
20,00
10,00
0,00
0,10
1,00
10,00
100,00
1000,00 10000,00
FREQUENCY [KHz]
GAPGMS00073
2.5
Test circuit and waveforms plot
2.5.1
Load regulation
Figure 24. Load regulation test circuit
ꢁꢂ
'!0'-3ꢀꢀꢀꢇꢅ
Doc ID 13103 Rev 13
15/35
Electrical specifications
L4995
Figure 25. Maximum load variation response
V0 [1V / div]
I
0 [
200mA / div]
0,00E+00
5,00E-05
1,00E-04
1,50E-04
2,00E-04
2,50E-04
3,00E-04
3,50E-04
4,00E-04
Time [s]
GAPGMS00081
16/35
Doc ID 13103 Rev 13
L4995
Application information
3
Application information
Figure 26. L4995 application schematic(1)
6O
6S
6I
#Oꢈ
#Oꢂ
6O
S
3TART UP
ꢈꢏꢂꢁ6
GND
%N
6OLTAGE
2EFERENCE
ꢓ
?
ꢈꢀꢀM6
6CW
#TW
7I
2ES
WATCHDOG
,OW 6OLTAGE
2ESET
6CR
#TR
'!0'-3ꢀꢀꢀꢇꢁ
1. The input capacitor Cs > 200nF is necessary for the smoothing of line disturbances. The output capacitor
C01 > 100nF is necessary for the stability of the regulation loop. In order to dampen output voltage
oscillations during high load current surges, it is recommended an additional electrolytic capacitor C02 >
10µF to be placed at the output pin.
Figure 27. Stability region(1)
100
Unstable region
10
1
Stability region
ESR min
ESR max
0.1
0.01
Undefined region
0.001
0.5
5
10 15 20 25 30 35 40 45 50
Co (uF)
1. The curve which describes the minimum ESR is derived from characterization data on the regulator with
connected ceramic capacitors which feature low ESR values (at 100 kHz). Any capacitor with further lower
ESR than the given plot value must be evaluated in each and every case.
Doc ID 13103 Rev 13
17/35
Application information
L4995
3.1
Voltage regulator
Voltage regulator uses a p-channel transistor as a regulating element. With this structure,
very low dropout voltage at current up to 500mA is obtained. The output voltage is regulated
up to transient input supply voltage of 40V. No functional interruption due to over-voltage
pulses is generated. A short circuit protection to GND is provided.
The voltage regulator is active when En is high.
Figure 28. Behavior of output current versus regulated voltage Vo
Vo
Vo_ref
Ishort Ilim
Iout
3.2
Reset
The reset circuit supervises the output voltage Vo. The Vo_th reset threshold is defined with
the in-ternal reference voltage and a resistor output divider. If the output voltage becomes
lower than Vo_th then Res goes low with a reaction time trr. The reset low signal is
guaranteed for an output voltage Vo greater than 1V.
When the output voltage becomes higher than Vo_th then Res goes high with a delay trd.
This delay is obtained by an internal oscillator.
The oscillator period is given by:
Equation 1
Tosc = [(VRhth-VRlth) x Ctr] / Icr + [(VRhth-VRlth) x Ctr] / Idr
where:
Icr:is an internally generated charge current
Idr:is an internally generated discharge current
VRhth, VRlth:are two voltages defined with the output voltage and a resistor output
divider
Ctr:is an external capacitance.
trd is given by:
Equation 2
trd = (VRhth x Ctr)/Icr + 3 x Tosc
Doc ID 13103 Rev 13
18/35
L4995
Application information
Reset is active when En is high.
Figure 29. Reset timing diagram
Wi
Vout_th
< trr
Vo
Tosc
Vrhth
Vrlth
trr
Vcr
trd
Res
GAPGMS00077
3.3
Watchdog
A connected microcontroller is monitored by the watchdog input Wi. If pulses are missing,
the Reset output pin is set to low. The pulse sequence time can be set within a wide range
with the external capacitor, Ctw. The watchdog circuit discharges the capacitor Ctw, with the
constant current Icwd. If the lower threshold Vwlth is reached, a watchdog reset is generated.
To prevent this the microcontroller must generate a positive edge during the discharge of the
capacitor before the voltage has reached the threshold Vwlth. In order to calculate the
minimum time t, during which the micro-controller must output the positive edge, the
following equation can be used:
Equation 3
(Vwhth-Vwlth) x Ctw = Icwd x t
Every Wi positive edge switches the current source from discharging to charging. The same
happens when the lower threshold is reached. When the voltage reaches the upper
threshold, Vwhth, the current switches from charging to discharging. The result is a saw-tooth
voltage at the watchdog timer capacitor Ctw.
Figure 30. Watchdog timing diagram
:
L
7ZRS
9ZKWK
9FZ
9ZOWK
7ZRO
5HV
'!0'-3ꢀꢀꢀꢇꢌ
Doc ID 13103 Rev 13
19/35
Package and PCB thermal data
L4995
4
Package and PCB thermal data
4.1
PowerSSO-12 thermal data
Figure 31. PowerSSO-12 PC board(1)
("1($'5ꢀꢀꢃꢄꢃ
1. Layout condition of R and Z measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x
th
th
86mm,PCB thickness=1.6mm, Cu thickness=70μm (front and back side) Thermal vias separation 1.2 mm,
Thermal via diameter 0.3 mm +/- 0.08 mm, Cu thickness on vias 0.025 mm, Footprint dimension 4.1 mm x
6.5 mm).
Figure 32. Rthj-amb vs PCB copper area in open box free air condition
RTHj__aamb(°C/ W)
70
65
60
55
50
45
40
0
2
4
6
8
10
PCB Cu heatsink areaa (cm^ 2)
GAPGMS00082
20/35
Doc ID 13103 Rev 13
L4995
Package and PCB thermal data
Figure 33. PowerSSO-12 thermal impedance junction ambient single pulse
ZTH (°C/ W)
100
Footprint
2
2 cm
2
8 cm
10
1
0,1
0,0001
0,001
0,01
0,1
Time (s)
1
10
100
1000
Equation 4: pulse calculation formula
= R ⋅ δ + Z (1 – δ)
Z
THδ
TH
THtp
where δ = tP/T
Figure 34. Thermal fitting model of Vreg in PowerSSO-12
'!0'-3ꢀꢀꢀꢇꢍ
Doc ID 13103 Rev 13
21/35
Package and PCB thermal data
L4995
Table 9.
PowerSSO-12 thermal parameter
Area/island (cm2)
Footprint
0.45
1.79
7
2
8
R1 (°C/W)
R2 (°C/W)
R3 (°C/W)
R4 (°C/W)
10
10
15
20
9
R5 (°C/W)
22
10
15
R6 (°C/W)
26
C1 (W.s/°C)
C2 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
0.001
0.0022
0.05
0.2
0.1
0.8
6
0.1
1
0.27
3
9
22/35
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L4995
Package and PCB thermal data
4.2
PowerSSO-24 thermal data
Figure 35. PowerSSO-24 PC board(1)
GAPGCFT00418
1. Layout condition of R and Z measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x
th
th
86mm,PCB thickness=1.6mm, Cu thickness=70μm (front and back side) Thermal vias separation 1.2 mm,
Thermal via diameter 0.3 mm +/- 0.08 mm, Cu thickness on vias 0.025 mm, Footprint dimension 4.1 mm x
6.5 mm).
Figure 36. Rthj-amb vs PCB copper area in open box free air condition
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Doc ID 13103 Rev 13
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Package and PCB thermal data
L4995
Figure 37. PowerSSO-24 thermal impedance junction ambient single pulse
ZTH (°C/ W)
100
Footprint
2
2 cm
2
8 cm
10
1
0,1
0,0001
0,001
0,01
0,1
Time (s)
1
10
100
1000
Equation 5: pulse calculation formula
= R ⋅ δ + Z (1 – δ)
Z
THδ
TH
THtp
where δ = tP/T
Figure 38. Thermal fitting model of Vreg in PowerSSO-24
'!0'-3ꢀꢀꢀꢍꢀ
24/35
Doc ID 13103 Rev 13
L4995
Package and PCB thermal data
Table 10. PowerSSO-24 thermal parameter
Area/island (cm2)
Footprint
2
8
R1 (°C/W)
R2 (°C/W)
R3 (°C/W)
R4 (°C/W)
R5 (°C/W)
R6 (°C/W)
C1 (W.s/°C)
C2 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
0.45
1.79
6
7.7
9
9
8
28
17
10
0.001
0.0022
0.025
0.75
1
4
5
9
2.2
17
Doc ID 13103 Rev 13
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Package and packing information
L4995
5
Package and packing information
®
5.1
ECOPACK
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 39. PowerSSO-12 package dimensions
26/35
Doc ID 13103 Rev 13
L4995
Package and packing information
Table 11.
PowerSSO-12 mechanical data
Millimeters
Typ.
Symbol
Min.
1.250
0.000
1.100
0.230
0.190
4.800
3.800
Max.
1.620
0.100
1.650
0.410
0.250
5.000
4.000
A
A1
A2
B
C
D
E
e
0.800
H
5.800
0.250
0.400
0º
6.200
0.500
1.270
8º
h
L
k
X
2.200
2.900
2.800
3.500
0.100
Y
ddd
Doc ID 13103 Rev 13
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Package and packing information
L4995
5.2
PowerSSO-24 mechanical data
Figure 40. PowerSSO-24 package dimensions
("1($'5ꢀꢀꢅꢆꢆ
28/35
Doc ID 13103 Rev 13
L4995
Package and packing information
Table 12. PowerSSO-24 mechanical data(1)(2)
Millimeters
Typ.
Symbol
Min.
Max.
2.45
2.35
0.10
0.51
0.32
10.50
7.60
A
A2
a1
b
2.15
0
0.33
0.23
10.10
7.40
c
D(3)
E(3)
e
0.8
8.8
2.3
e3
F
G
G1
H
0.1
0.06
10.5
0.4
10.1
h
k
0°
8°
L
0.55
0.85
O
Q
S
1.2
0.8
2.9
3.65
1
T
U
N
10º
4.7
X
4.1
6.5
4.9(4)
7.1
5.5(4)
Y
1. No intrusion allowed inwards the leads.
2. Flash or bleeds on exposed die pad shall not exceed 0.4 mm per side
3. “D and E” do not include mold Flash or protusions.
Mold Flash or protusions shall not exceed 0.15 mm.
4. Variations for small window leadframe option.
Doc ID 13103 Rev 13
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Package and packing information
L4995
5.3
PowerSSO-12 packing information
Figure 41. PowerSSO-12 tube shipment (no suffix)
B
Base q.ty
100
2000
532
C
Bulk q.ty
Tube length ( 0.5)
A
1.85
6.75
0.6
A
B
C ( 0.1)
All dimensions are in mm.
Figure 42. PowerSSO-12 tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base q.ty
Bulk q.ty
A (max)
B (min)
C ( 0.2)
F
2500
2500
330
1.5
13
20.2
12.4
60
G (+ 2 / -0)
N (min)
T (max)
18.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
W
12
4
Tape hole spacing
Component spacing
Hole diameter
P0 ( 0.1)
P
8
D ( 0.05)
D1 (min)
F ( 0.1)
K (max)
P1 ( 0.1)
1.5
1.5
5.5
4.5
2
Hole diameter
Hole position
Compartment depth
Hole spacing
All dimensions are in mm.
End
Start
Top
No components
500mm min
Components
No components
500mm min
cover
tape
Empty components pockets
saled with cover tape.
User direction of feed
30/35
Doc ID 13103 Rev 13
L4995
Package and packing information
5.4
PowerSSO-24 packing information
Figure 43. PowerSS0-24 tube shipment (no suffix)
C
B
A
GAPGCFT00002
Figure 44. PowerSSO-24 tape and reel shipment (suffix “TR”)
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Doc ID 13103 Rev 13
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Revision history
L4995
6
Revision history
Table 13. Document revision history
Date
Revision
Changes
26-May-2006
1
Initial release.
L4995A and L4995R versions added:
Features section updated and table added.
Table 1 updated.
Table 5: General, Watchdog Iwi entry updated.
Figure 2: Block diagram of L4995A and Figure 3: Block diagram of
L4995R added.
Table 2: Pins descriptions updated.
05-Jan-2007
2
Table 4: Thermal data updated.
List of tables and List of figures added.
Packaging information provided in new format.
Table 11: PowerSSO-12 mechanical data X and Y values updated.
Some sections reformatted for clarity.
New disclaimer added.
Updated Table 2: Pins descriptions.
18-May-2007
3
Updated Figure 4: Pins configurations (L4995).
Table 1: Device summary changed title.
09-Jul-2007
09-Aug-2007
4
5
Updated Table 2: Pins descriptions.
Updated Table 2: Pins descriptions.
Updated Table 12: PowerSSO-24 mechanical data.
32/35
Doc ID 13103 Rev 13
L4995
Revision history
Table 13. Document revision history (continued)
Date
Revision
Changes
Updated Section 2.2: Thermal data:
– corrected note changing single layer with double layer.
Updated Table 5: General:
– changed Ishort typ. value from 750 to 800 mA
– added Ishort max. value
– changed Ilim typ. value from 820 to 900 mA
– added Ilim max. value
– added Ilim note
– added Vdp note
– changed Iqn_1 typ. value from 110 to 90 µA
– added Iqn_1 max. value
– added Iqn_50 max. value
– added Iqn_150 max. value
– changed Iqn_250 typ. value from 1.2 to 1 mA
– added Iqn_250 max. value
– changed Iqn_500 typ. value from 2.4 to 2.1 mA
– added Iqn_500 max. value
07-Dec-2007
6
Updated Table 6: Reset:
– changed VRlth parameter definition from “Reset timing low” to
“Reset delay circuit low threshold”
– changed VRhth parameter definition from “Reset timing high” to
“Reset delay circuit high threshold”
– added Trd min. and max. values
Updated Table 7: Watchdog:
– added Iwi max value
Updated Table 8: Enable:
– changed Pull down current symbol from REn to En
I
– changed IEn typ. value from 2.5 to 10 µA
– added IEn max. value
Added Section 2.4: Electrical characteristics curves.
Added Section 2.5: Test circuit and waveforms plot.
Added Section 4: Package and PCB thermal data
Updated PowerSSO-24 information:
03-Oct-2008
19-Mar-2009
19-May-2009
7
8
9
– changed Figure 40: PowerSSO-24 package dimensions
– changed Table 12: PowerSSO-24 mechanical data.
Updated Table 4: Thermal data
Updated Table 2: Pins descriptions.
Updated Figure 4: Pins configurations (L4995)
– Changed GND to substrate
Doc ID 13103 Rev 13
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Revision history
L4995
Table 13. Document revision history (continued)
Date
Revision
Changes
Table 12: PowerSSO-24 mechanical data:
– Deleted A (min) value
– Changed A (max) value from 2.50 to 2.45
– Changed A2 (max) value from 2.40 to 2.35
– Updated K row
24-Jun-2009
10
– Changed L (min) value from 0.6 to 0.55
– Changed L (max) value from 1 to 0.85
12-Jul-2010
09-Mar-2012
11
12
Added Figure 27: Stability region(1)
.
Added footnote in Table 3: Absolute maximum ratings.
Table 6: Reset:
17-Oct-2012
13
– T : updated min, typ and max values
rd
34/35
Doc ID 13103 Rev 13
L4995
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
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UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT
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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2012 STMicroelectronics - All rights reserved
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