E-STE12PS [STMICROELECTRONICS]
12 channel integrated PSE line manager; 12通道集成PSE线经理
| 型号： | E-STE12PS |
| 厂家： | 
ST |
| 描述： | 12 channel integrated PSE line manager |
| 文件： | 总44页 (文件大小：794K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STE12PS
12 channel integrated PSE line manager
Preliminary Data
Features
■ PSE power control device
■ Supports up to 12 independent, 4(a)or 6(b) 30W
“boosted” ports
■ Wide operating range: up to 90V
■ IEEE 802.3af compliant
■ Open circuit detection: AC and DC methods
■ Advanced power management algorithm
PBGA23x23
■ Current sensing with as low as 500mΩ,
external, series resistors
■ No need for external FETs
■ In-rush current control
The STE12PS is fully progmmable, supporting
the detection and powering of IEEE802.3af as
well as legacy PDs. The flexibility of the STE12PS
allows the user to select a suitable system
configuration: up to 12 ports as well as 4(a) or 6(b)
“booste” channels. If needed, the STE12PS can
ao efficiently manage cases or applications
where a limited amount of power is available to
the ports (smart-power capability) by means of
integrated, power MOSFET devices. All
■ Short-circuit protection
■ Adaptable signature detection capability
■ On-chip 3.3V SMPS controller
■ Low-noise, 12-bit ADC
■ Standard I2C interface
■ Parallel monitor interface
operations are controlled via the I2C bus also
notifying externally some ports status condition
via dedicated pins.
Description
STE12PS is designed to supply power over
multiple Ethernet channels in der to avoid
different, individual power supply units for
applications such as Web cams, IP Phones,
Bluetooth accespoints and WLAN access
points.
Ethernet port isolation can be easily maintained
thanks to an integrated 3.3V SMPS power source
and by means of optocouplers.
The STE12PS has five address selection inputs
to choose up to 32 possible different addresses.
The eqpment that provides the power to the
twisted pair cabling is referred to as Power
Surcing Equipment (PSE).
Power can be provided to the PD using either
spare lines of the Ethernet cable or using the data
wires, as specified by IEEE 802.3af.
The PSE’s main functions are: looking for links to
a Powered Device (PD), classifying a PD,
supplying power to the link, monitoring power on
the link, and removing power from the link.
a. In AUTO mode
b. In MANUAL mode
August 2007
Rev 3
1/44
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
www.st.com
44
Contents
STE12PS
Contents
1
2
3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1
3.2
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Detection and classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2.1
3.2.2
3.2.3
Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Detection and classification FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3
Power ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.1
3.3.2
3.3.3
Under load (disconnection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Short circuit, overload and overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . 15
Thermal monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4
3.5
3.6
3.7
3.8
Internal 3.3V/10V generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Logic interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6MHz clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Smart-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power boost mode - 30W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.8.1
3.8.2
Four channels in Auto mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Six channels in Manual mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.9
Measurement and parameter codings . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4
5
I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
I2C slave protocol overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Error cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
I2C device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Register addressing: write command format . . . . . . . . . . . . . . . . . . . . . . 28
Register addressing: read command format . . . . . . . . . . . . . . . . . . . . . . 29
Parallel monitoring interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2/44
STE12PS
Contents
Electrical specifications and timings . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Ball coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Package information - mechanical data . . . . . . . . . . . . . . . . . . . . . . . . 41
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6
7
8
9
10
3/44
Block diagram
STE12PS
1
Block diagram
Figure 1.
STE12PS functional block diagram
Analog front end
Line detection
classification
monitoring
Programmable
detection/
interface
classification
I2C
12-bit
ADC
AC
Smart power
& port priority
management
disconnect
generator &
detector
~
50Hz
Power-on control
inrush current limiting
12 x power
switches
Programmable
timer settings
Digital
controller
3.3V
SMPS
controller
Tri-level
temperature
protection
Internal
clock
generator
Monitoring
output
interface
Figure 2.
Typical application diagram
Low Cost
PMOS
+48V
R1
L1
3.3V
To Other
Devices
R2
D3
C2
C1
R3
D1 x 12
D4
SMPS_VL
VL
RLIM VDRIVE
SMPS_GND
V3_3
Px
GNDs
D2 x 12
FSRPx
I2C_ADDRx
SCLIN
SDAIN
SDAOUT
INTN
SSRPx
STE12PS
Rsense
x 12
I2C
BUS
To Opto
Couplers
HQGND
Rmon
RMONS
CLKgenx
ACSx
SPx
RMONF
C4
C5
C3 x12
4/44
STE12PS
Pin description
2
Pin description
Table 1.
Analog pins description
Pin name
I/O
Function
Anti-aliasing filter capacitor to be connected between the analog input and
ground to improve ADC noise performance. C = 180pF.
IDET_HVLV
IMON_HVLV
Vbat_mon
Vbatref
O
Anti-aliasing filter capacitor to be connected between the analog input and
ground. C = 180pF.
O
O
O
O
Anti-aliasing filter capacitor to be connected between the analog input and
ground. C = 100nF.
Anti-aliasing filter capacitor to be connected between the analog input and
ground. C = 100nF.
Anti-aliasing filter capacitor to be connected between the analog input and
ground. C = 180pF.
I_REF
CDETSLOW
RSENSE
O
O
Detection rise/fall time capacitor (up to 25nF). Tr/f can be set from 1ns to 4ms.
SMPS precision, external, current limiting reference resistor: 100mΩ
External p-channel MOSFET gate driving voltage for SMPS. It provides a
square wave with VL as upper limit and (VL-10V) as lower limit voltage.
VDRIVE
O
SFTSTR
FB
O
Switched Mode Power Supply (SMPS) soft start capacitor, 200nF.
SMPS feedback pin, Cfb = 2.2nF
IO
Power DMOS device drain, if DMOS is turned-on, channel “n” where n = 1,…12
is activated.
Pn
O
ACSn
SPn
O
I
It provides a 50Hz AC disconnection signal for port “n”, n = 1, … 12.
Detection classification and AC disconnection sensing port “n”, n = 1, … 12.
Line current to the monitoring resistor for channel “n”, n = 1,… 12. Allowed
values are 0.523, 1.05, 1.58 and 2.1ohms (see also SENSPROG preset pins).
Sensing pin.
SSRPn
I
Source terminal for power DMOS connected to the sense resistor for channel
“n”, n = 1,… 12, a “forcing” pin.
FSRPn
RMONF
RMONS
O
O
O
Mirror monitoring resistance (500 × Rsense) pin to let internal ADC evaluate line
currents. Forcing pin.
Mirror monitoring resistance (500 × Rsense) pin to let internal ADC evaluate line
currents. A “sensing” pin.
RREF
I
I
Reference bias resistor: 18.7kΩ
CLK_GEN1
CLK_GEN2
MCLK
Crystal oscillator pin1 for high performance clock generation.
Crystal oscillator pin2 for high performance clock generation.
Master clock output for multi device configuration.
Low profile clock input pin or clock input pin in multi-device configuration.
50Hz sinusoidal input
I
O
I
CLK_GEN3
ACin
I
ACout
O
50Hz sinusoidal output, internally generated
5/44
Pin description
STE12PS
Table 2.
Digital pins description
Pin name
I/O
Function
Reset
RESETN
I
Reset pin. Active LOW
Status flag interface
Channel identification “n”, where n = 1,… 12. Indicates the channel whose
status flags (POK, …) are currently notified externally. CH_SEL is incremented
every 60 * MCLK clock cycles. The status flag notification is enabled via the
configuration register Global_cfg2, STATUS_FLAG_EN bit.
CH_SELn
POK
O
O
Power OK flag. This flag indicates condition of the currently powered channel:
‘1’→power ON and NO faults are present
‘0’→power OFF or (power ON and faults present)
Overload Alarm Flag for the currently powered channel. Current overload
condition (Icut is over threshold):
OVLD
O
‘1’→channel overload condition detected
‘0’→NO overload
Short circuit Alarm Flag for the currently powered channel. Current limiting
condition:
OVCUR
O
O
‘1’→Overcurrent or detection failed condition detected
‘0’→ANY Short Circuit condition detected
AC/DC Disconnection Alarm Flag for the currently powered channel:
‘1’→AC/DC disconnection detected
‘0’→ANY disconnection detected
AC_DC_DISCON
DET_CLASS
Detection/Classification flag.
O
O
‘1’→Detection or Classification procedure is running
‘0’→Detection/Classification procedure is not running.
Por_N
‘1’ →VL, 10V and 3.3V supply Power ON succeeded
Thermal monitoring
Thermal monitoring (x = 0,1).
These bits encode the internal temperature’s threshold measured in the
following way:
“00” →Temperature under 110°C
T_MONITORx
O
“01” →Temperature between the 110°C to 130°C
“11” →Temperature between the 130°C to 150°C
“10” →Temperature is above 150°C
6/44
STE12PS
Table 2.
Pin description
Digital pins description (continued)
Pin name
I/O
Function
Configuration signals
A or B alternative configuration mode select.
‘0’→Alternative B (Midspan-PSE)
A_BN_SEL
I
‘1’→Alternative A (Endpoint-PSE)
12- or 4-boost channel select. x = 0,1.
‘00’ →12 channels configuration
‘01’ →NA
‘10’ →NA
‘11’ → 4-boost channel configuration
CH_NUMx
I
I
AUTO Start Mode enable.
‘0’→Auto Start Mode disabled: all the ports are disabled after Reset, Neither
detection nor power on is performed (MODE[1:0] register selected to Power
Down at the reset event)
AUTO_START
‘1’→Auto Start Mode enabled: all the ports are automatically enabled,
detection, classification and power are performed (MODE[1:0] register selected
to AUTO after the reset event)
SMPS (Switch Mode Power Supply) mode selector bit (supplier / User). When
Not connected the device works as DC-DC converter controller.
S/UPIN
I
I
Preset pins for sensing resistor programmability (x=0,1). The programmed
value must match the mounted Rsense resistors.
‘00’ →Rsense = 0.5Ω
‘01’ →Rsense = 1Ω
‘10’ →Rsense = 1.5Ω
‘11’ →Rsense = 2Ω
SENSEPROGx
Power ON controller signals
POWER_ENx
I2C Signals
I2C_ADDRx
SCLIN
I
Reserved. (x = 0, …11).
I
I
This defines the device address for the I2C interface. x = 0, … 4.
Serial clock input pin for the I2C interface.
Serial data input pin for the I2C interface. When “jumpered” with the SDAOUT
pin, this connection becomes the standard bi-directional serial data line (SDA).
SDAIN
I
Serial data output pin for the I2C interface. When jumpered with the SDAIN pin,
this connection becomes the standard bi-directional serial data line (SDA).
SDAOUT
O
O
INTN
I2C Open drain output that goes low when interrupt event is notified
Test mode signals
Test Mode Enable (x = 0,1).
‘00’ →Functional mode
‘01’ →Reserved
‘10’ →Reserved
‘11’ →Reserved
TEST_MODEx
SCAN_EN
I
I
Reserved. Preset to ‘0’.
7/44
Pin description
STE12PS
Table 3.
Power and ground pins description
Pin name
I/O
Function
GND, AGND
SMPSGND
SMPS_VL
V3_3,Vdd,Vdde
V10, Vdd10
HQGND
I
Analog grounds
I
SMPS power ground
+48V battery voltage for SMPS
3.3V supply
I
I
I/O
10V supply to power-up the output DMOS and minimize its ON resistance
Dedicated ground for Kelvin line current sense resistor (a high quality ground)
Digital grounds
I
I
I
DGND, gnd, gnde
VL
+48V battery voltage.
8/44
STE12PS
Functional description
3
Functional description
The STE12PS architecture provides a complete PSE interface and smart digital controller to
efficiently manage the functions in a PoE system. All operations can be controlled through
R/W registers via a standard I2C bus interface.
The STE12PS is designed to control power delivery of up to 12 separate lines. This is
performed by controlling 12 integrated, power MOS transistors connected to the low side of
the line - monitoring the line voltage and sensing line current by means of external, series
sensing resistors (one per port). Turning on a port means to switch the relative MOS
transistor thus controlling the inrush current in order to rise the port voltage up to 48V
(typical battery voltage) after a valid PD signature has been detected. The flexibility of the
STE12PS allows the user to select a suitable system configuration: 12 "standard", 4 or 6
"boosted" 30W channels, by means of pins CH_NUMn. Also, one can select the type of
architecture (Endpoint PSE/ Alternative A or Midspan PSE/Alternative B) for all channels via
pin A_BN_SEL.
Some typical applications for the STE12PS include:
●
●
●
●
Ethernet switches/routers
Midspan power supplies
IP-PBX
WLAN access points
3.1
Operating modes
The digital controller can operate in one of five possible modes for all the channels,
selectable through the Global Configuration registers: Stand-by, Auto, Semi Auto, Manual or
Power Down.
When the reset condition is removed, the controller defaults to Power Down mode if the
AUTO_START pin is tied low; if AUTO_START is tied HIGH the mode is configured in AUTO.
The mode can be changed only during a limited amount of time (100ms), after the reset is
released, accessing the Global Configuration registers before the detection procedure is
started, or placing the device in STAND-BY mode via the I2C interface.
The characteristics of the Five possible operating modes are described below:
●
STAND-BY: the controller allows only the read write operations suitable for changing
programmability. To enable this mode set the reset bit 1 of the REG0x05.
●
AUTO: the controller autonomously performs detection, classification and Power ON
command without the need of host commands. A subset of status flags stored in the
channels monitor registers is reported externally through the Status Flag Notifies pins
allowing operation without the presence of the host controller.
●
●
SEMIAUTO: after a triggering command the controller autonomously performs
detection and classification waiting a dedicated command from host processor for the
power on. Based on the detection and classification results reported in the Channels
Status registers, the host controller can decide to power on the selected channel. The
disconnection of a channel is automatic as in the AUTO mode, unless disabled.
MANUAL: any action is performed manually. The host controller has the responsibility
to force any state transition in the FSM. Then based on the measures performed
automatically by the ADC on several parameters, the host controller can decide to
9/44
Functional description
STE12PS
classify the channel and afterwards to issue the power on command. The STE12PS
controller can also automatically disconnect a channel in fault condition (if not enabled,
the STE12PS will notify automatically only a short circuit condition or an AC
disconnection event. Overload or DC disconnection is responsibility of the host
controller.) The host controller can also power on a channel skipping detection and/or
classification procedures.
●
POWER DOWN: the controller is put in power down state. No actions are performed
until the power down mode is removed.
For all operating modes, except power-down and stand-by, the power ON/OFF condition of
each channel can also be managed, directly, by the host processor or controller via a
dedicated command.
Moreover, the power removal procedure is performed automatically (also in MANUAL mode)
when a fault event has been detected (AC/DC disconnection, overload or overcurrent); this
behavior can be changed configuring appropriately some dedicated enable/disable bits of
channels event registers.
With Priority Management in AUTO mode and Smart-power management enabled, it is also
possible to set different priorities for different channels. The STE12PS will probe channels
starting from those with the highest priority. In case of a shortage of available power, it is
also possible to disable powering of newly detected, lower priority ports until the highest
detected ones are served.
3.2
Detection and classification
3.2.1
Detection
The STE12PS looks for, in turn on the free available ports (according to the priority list if
enabled), for a valid PD signature (25kΩslope characteristic) by driving two different voltage
levels at the port (4V and 8V), and calculating the slope resistance/ conductance by
monitoring the current difference. The equivalent circuit for the IEEE802.3af detection phase
is shown in Figure 3 below.
Figure 3.
IEEE802.3af detection circuit
Zsource
P+
D1(one per port) is external.
D2
D2 (one per port) external is required only if
the AC_Disconnection function is used,
otherwise it is internally emulated.
+
V
D1
_
P-
PC00103
As detection is performed by multiplexing a common voltage generator. If more than one
port is connected to several PDs, an extra delay in the detection start will be introduced. See
Table 12: Electrical characteristics, parameter Tdetd.
10/44
STE12PS
Functional description
By default, the STE12PS will recognize a valid signature with the following characteristics:
–
an inverse slope of the port current vs. voltage (I-V) characteristic measuring
between 19 and 26.5kΩ (Rdl and Rdh),
–
a port capacitance of less than 4µF.
If required, the STE12PS can also perform a custom, resistive detection search – modifying
the acceptance window. This can be easily performed by changing the Rdh and Rdl limits or
by changing Gdl and Gdh via the logic interface.
In Midspan applications, where power is applied via spare wires, when the PSE fails to
detect a PD, the port remains in high-impedance (Hi-Z) for at least two seconds. If the
signature resistance is greater than 500kΩ, then the two second wait is avoided.
Transition rates of the port voltage between the two probing levels can be adjusted with
capacitance Cdetslow.
Table 4.
Class
PD power classification
Maximum power level at
Usage
Power level at PD input
Iclass
PSE output (Pall)
0
1
2
3
4
0
Default
Optional
Optional
Optional
Optional
Default
15.4W (programmable)
4W (programmable)
7W (programmable)
15.4W (programmable)
-
0.44 to 12.95W
0.44 to 3.84W
3.84 to 6.49W
6.49 to 12.95W
Reserved
Iclass < Ithcl0
Ithcl0 < Iclass < Ithcl1
Ithcl1< Iclass < Ithcl2
Ithcl2 < Iclass < Ithcl3
Ithcl3 < Iclass < Ithcl4
Ithcl4 < Iclass
15.4W (programmable)
0.44 to 12.95W
3.2.2
Classification
Once a valid signature is detected, the port is probed for classification in order to perform
smart-power management (if enabled).
Port probing is performed by forcing a DC voltage in the range of 16V to 18V (one DC
generator multiplexed between the channels) and monitoring current Iclass. The
measurement is repeated and stored in the Channel Monitor Classification registers to
ensure a coherent classification. The PD power class is defined as shown in Table 4 above.
The detected class is then stored in the Channel Status registers.
Note:
The power absorbed in a link is calculated considering the actual value of the battery
voltage in order to arrive at a true power measurement result.
11/44
Functional description
STE12PS
3.2.3
Detection and classification FSM
This FSM manages all operations related to the detection and classification procedures.
For these two procedures, the following assumptions are made:
1. A channel is detected ONLY if:
a) the channel has not yet been detected, and Channel Detection has been enabled,
and
b) the Backoff Detection timer and Subsequent Attempt timer are NOT running (after
a corresponding fault detection or failed signature).
2. A channel is classified ONLY if:
a) Channel Classification is enabled, and
b) the previous related detection procedure has reported an Rgood/Ggood value
(Auto and SemiAuto modes).
Three general macro operations can be performed:
●
STARTUP: the following operations are related to the startup procedure:
–
–
RESET: reset and initialize all digital aspects of the STE12PS,
WAIT_POWER_UP: wait 100ms for completion of the power-up procedure. During
this period, the I2C bus is active - allowing the host to initialize registers while the
detection procedure is waiting to start.
–
DETECTION START: all setting-up needed to start operations is performed in this
state. The first battery voltage sample is latched in a dedicated register.
●
DETECTION: the following operations are related to the detection procedure for the
channel selected:
–
Low voltage detection command (4V) is issued via registers; detection timer is
started to execute the command for a duration of ½Tdet ms.
–
–
–
Wait for 5ms to acquire a stable measurement.
Sampled sensing current values are acquired via A/D converter.
The samples previously acquired are averaged and the resulting value, reported
into the Channels Monitor register, is compared against programmed min/max
values. If the sensing current is higher than maximum allowed value, the detection
procedure is considered as having FAILED: backoff timer is started (Alternative B)
and an alarm flag raised according to the Channel Status registers.
–
–
If the sensing current results lower than the minimum allowed value the detection
procedure is continued: the alarm flag is raised in the Channel Status registers.
The described operations are repeated for the High-Voltage detection command
(8V).
–
–
Signature Resistance is calculated:
If 2µsec < Gmeas < Glow or Ghigh < Gmeas, then backoff timer is started
(Alternative B) and detection result failure is reported in the Channel Status
registers.
–
Else, Glow < Gmeas < Ghigh and the result of a successful detection is reported
in the Channel Status registers.
12/44
STE12PS
Functional description
●
CLASSIFICATION: The following operations are related to the classification procedure
for the corresponding channel
–
–
If classification is not enabled, the default Class 0 is assigned.
High Voltage detection command (17V) is issued via registers; detection timer is
started to execute the command for 15ms duration.
–
–
–
Wait for 5ms to acquire a stable measurement
Sampled sensing current values are acquired via A/D converter.
Average the previously acquired samples and report the resulting value in a
dedicated register. The power class is identified and the result is reported in the
Channel Status registers.
–
Channel is ready to be powered: if the smart-power algorithm is enabled (via the
MISCELLANEOUS registers) the channel is powered only if the required power is
within the remaining power budget; the channel can be powered regardless of the
power-check availability via registers.
If the power availability check has a positive result (or it hasn’t been performed), the channel
is powered. Otherwise, it is rejected, and the alarm flag raised in the Channel Events
register. The channel number is registered into a scheduler FIFO so that power will again be
available when the channel is ready to be switched-on.
Figure 4.
Detection and classification equivalent architecture
+48V
VL
Detection/classification
D1
x12
+
+
-
+
-
-
-
+4V
SPx
Px
+8V
+
+17V
D2 x12
Digital
controller
12-bit A/D
converter
180pF
IDET_HVLV
STE12PS
13/44
Functional description
STE12PS
3.3
Power ON
After the classification phase the port will be powered.
Once activated, the power-on sequencer manages the channel’s activation requests
received through the signature detection circuitry. For the incoming channel, activation
requests are stored in the power-on sequencer and then serviced, one at a time, only when
the previously activated channel leaves the current limiting condition that normally occurs
during power on due to the capacitive part of the load. (see also smart-power mode and
special issues)
A port is turned-on by ramping-up the voltage and increasing the current limit to its upper
limit. After a programmable time (Tinrush), if the port has reached full voltage and is out of
current limitation, it is marked as powered. The related port power bit and the power class
bits are set according to the class in the logic interface bit stream.
The active ports are continuously monitored in order to detect a fault condition such as
Short Circuit, Disconnection or Excess Power (overload).
3.3.1
Under load (disconnection)
Detection of a disconnection, if enabled (default condition), can be performed via a DC and/or AC
method - default is DC ⊕ AC (logical OR):
●
DC method
If this method is selected via the logic interface and if the port current drops under
7.5mA for more than 10ms, then the STE12PS will detect a DC disconnection. If this
condition persist for Tmpdo (Table 12), then power is removed and the port is marked
as free, enabling a new detection.
●
AC method
If this method is selected via the logic interface, the STE12PS probes the channels via
coupling capacitors and detects when the AC load impedance, Zac, exceeds the
maximum, 100kΩ limit for a time longer than 20ms. In this case, the PSE will detect an
AC disconnection. If this condition persist for a time Tmpdo (Table 12), power is
removed and the port is marked as free, enabling a new detection.
Disconnection modes are as following: Disabled, DC method only, AC method only, both AC
and DC (combined in OR ⊕ logic or in AND ⊗ logic).
14/44
STE12PS
Figure 5.
Functional description
Power ON and monitoring
+48V
VL
D1
x12
x12
Power DMOS
Px
FSRPx
SSRPx
HQGND
x12
D2 x12
Power EN
werOnctrl
r
u
s
h
c
u
rr
e
n
t
Short Flag
l
i
i
t
in
g
12-bit A/D
converter
Rsense x12
(0.5, 1, 1.5, 2 ȍ)
+
-
Rmon
(§500xRsense)
Digital
controller
RMONS
RMONF
AC disconnect
300nF
ACSx
SPx
detector
50Hz
~
5Vpp
STE12PS
AC_Discon flag
3.3.2
Short circuit, overload and overcurrent
A short circuit is defined when port current reaches 425mA, typ. Moreover, if port voltage
drops below 25V, then maximum loop current is decreased, linearly, to limit power
dissipation. A short condition is considered as a fault after a period of 65ms, typ. (see
Table 12: Electrical characteristics, parameter Tshort).
When the above conditions are met, the port is disconnected, and the fault bit set HIGH in
the Channel Event registers.
Overload or excess power is defined when port power consumption reaches 15.4W for
longer than 65ms, typ. (see Table 12: Electrical characteristics, parameter Tovld).
If smart-power management is active, then the overload power limit is set instead -
according to the power class.
When the above conditions are met, the port is disconnected, and the fault bit is set HIGH.
15/44
Functional description
Monitor overload FSM
STE12PS
This FSM manages all operations related to monitoring an overload event.
All operations described below are related to channels currently powered.
●
STARTUP: the following operations are related to a startup procedure:
START: channel to be monitored is selected.
–
●
POWER MEASUREMENT: the following operations are related to a power
measurement procedure
–
–
–
–
SAMPLE Imeas: the current measurement is sampled and the next powered
channel is prepared for the next monitor procedure.
MEASURE Power: the power is measured and its value is compared against the
required Power class.
START MONITOR OVERLOAD: if the measured power exceeds the required
power class the Tovld timer and the averaging process are started.
COUNTER RESET: Tovld timer is reset if the measured power doesn’t exceed the
required
●
POWER REMOVAL: the following operations are related to a power removal
procedure:
–
COUNTER CHECK: all Tovld timers are checked, and those that have expired are
identified.
–
POWER REMOVAL: all the channels whose timers have expired and whose
average power exceeds the maximum are switched OFF through the
POWER_EN(n) pins.
–
ALARM SET: for all the channels whose timers have expired, a corresponding
alarm flag is raised in the Channel Event registers, and the related Ted timer is
started.
16/44
STE12PS
Functional description
Monitor overcurrent FSM
This particular FSM manages all operations related to procedures that are able to monitor
an overcurrent event.
All operations described below are related to channels currently powered.
●
●
●
STARTUP:
–
START: the channel to be monitored is selected.
VOLTAGE BATTERY:
–
SAMPLE Vbat: every 12 channels cycle the Vbat measurement is executed.
OVERCURRENT CHECK: the following operations are related to an overcurrent check
–
Imeas CHECK: if Imeas>Ilim the I_LIM_FLAG is raised and the next powered
channel is prepared for the next monitor procedure.
–
–
START MONITOR: the Tlim counter is started if I_LIM_FLAG is found asserted.
COUNTER RESET: if I_LIM_FLAG is found de-asserted Tlim counter is reset
taking into account that glitches of duration less than 10ms are filtered.
●
POWER REMOVAL: the following operations are related to a power removal operation:
–
COUNTER CHECK: all the Tlim timers are checked and those expired are
identified.
–
–
POWER REMOVAL: all the channels whose timer is expired are switched OFF.
ALARM SET: for all the channels whose timers are expired a corresponding alarm
flag is raised in the FAULT_EVENT_CHn register and the related Ted timer is
started.
3.3.3
Thermal monitoring
The procedures performed by the digital controller are impacted by the thermal monitoring
data indicating the measured temperature.
Its behavior is based on a three-level control system:
1. When the chip's internal temperature reaches 110°C, only the channels already
powered will be serviced. Possible new ones, will be rejected, redetected and
eventually processed when the internal temperature cools down to 100°C. This
behavior can be disabled setting the proper bit register.
2. A second temperature threshold is set at 130°C. When this value is reached, the
channels that are in current limiting or inrush condition are immediately switched OFF,
and their reactivation, subject to positive redetection, will only be possible when the
chip's internal temperature has cooled down to 100°C. This behavior can be disabled
by setting the proper bit register.
3. The third temperature threshold is set at 150°C. When this temperature is reached, all
activated channels will be immediately switched OFF, and their reactivation, subject to
positive redetection, will only be possible when the chip's internal temperature has
decreased to 100°C. This behavior cannot be disabled.
17/44
Functional description
STE12PS
3.4
Internal 3.3V/10V generator
The STE12PS can be configured either as 3.3V and 10V generator or load by means of the
S/U control input. In this manner, the need for extra, low-voltage batteries is avoided, greatly
simplifying the system design. If S/U is left open, the device will operate as an SMPS
controller. With the SMPS configured at 3.3V, the device can be used to power up a “1Amp”
load with high efficiency voltage conversion.
Figure 6 on page 19 shows a typical DC-DC, buck converter configuration for the 3.3V
supply. The 10V supply is generated by means of an internal, linear regulator. The 3.3V
supply can source up to 1A.
In Figure 7, use of a small transformer for the 10V supply can save up to 0.3W for each
powered device. Both the 3.3V and 10V supplies can power others devices.
Figure 8 depicts a typical application with an external supply.
3.5
Logic interface
The STE12PS can operate autonomously - notifying, externally, ports status via dedicated
pins (Parallel Monitor Interface) - or it can be controlled as a slave device via the I2C
interface by a host processor. In the latter case, the host can perform system configurations,
monitor status conditions and assert alarm flags making it possible to drive, manually,
different operations for detection, classification and monitoring.
18/44
STE12PS
Figure 6.
Functional description
Simple SMPS
+48V
To other
devices
Ext low cost
PMOS
V3.3
V10
RLIM
VL SMPS
VDRIVE
Internal linear
regulator
FB
E/A
PMOS
driver
Current
limiting
PWM & ramp
generator
Soft
start
RREF1
Bandgap &
Clock
gen
SFTSTR
reference
STE12PS
S/Upin
19/44
Functional description
STE12PS
Figure 7.
Advanced SMPS
+48V
To other
devices
.
V3.3
V10
VDRIVE
VL SMPS RLIM
FB
E/A
PMOS
driver
Current
limiting
PWM & ramp
generator
Soft
Start
RREF1
Bandgap &
reference
Clock
gen
SFTSTR
S/Upin
STE12PS
20/44
STE12PS
Functional description
Figure 8.
With external power supplies
+48V
+3.3V
+10V
Optional
RLIM
VL
VDRIVE
V3.3
V10
FB
E/A
PMOS
driver
VL SMPS
Current
limiting
PWM & ramp
generator
Soft
start
RREF1
Bandgap &
reference
Clock
gen.
SFTSTR
S/Upin
STE12PS
3.6
3.7
6MHz clock generator
Figure 10 on page 23, and Figure 11 and Figure 12 on page 24 show the three possible
clock generation configurations:
a) with a 6MHz crystal for a high precision clock,
b) with an external RC for low-cost applications,
c) with an external clock.
Smart-power mode
When this mode is enabled, the whole system is set to manage and deliver a limited amount
of power to the channel. In Auto Mode, it is actually possible to set a maximum power
budget for the device. When a PD is connected to a port, the STE12PS verifies the class
and decides to power the line only if there’s enough power available. It is also possible to set
different priorities for the different channels. The device probes channels starting with those
of highest priority. In case of shortage of available power, it is possible to disable the
powering of newly detected ports of lower priority until the ones with a higher detected
priority are serviced. If a channel exceeds its power class, that channel can be powered-
down, and its power made available again. A 12-bit ADC is used to provide high-quality
voltage and current measurements during the various phases of port detection,
21/44
Functional description
STE12PS
classification and powering. These measurements can be loaded into dedicated registers
via the I2C bus and are intended to be averaged over time in order to maximize PSSR and
noise rejection as well as minimize 50 to 60Hz interference.
3.8
Power boost mode - 30W
3.8.1
Four channels in Auto mode
When this mode is activated, the device will run the classification extending the IEEE
classes with an extra PD_Class boost as detailed in Table 4. If class boost is detected, an
equivalent double port (parallel of two channels) is switched-on allowing up to 30W of power
to be supplied. All the other IEEE classes behave as a standard port (powering on one
channel only). Table 5 below describes channel parallelism:
Table 5.
Power boost mode: master/slave channel parallelism
Master Channel (MC)
Slave Channel (SC)
1
2
3
4
5
6
7
8
Channels in boost mode behave as master or slave according to the above table.
Detection and classification are performed only on the master ports. If a class 0 to 4 PD is
detected, only MC is powered. Otherwise, if Boost Class is detected, both MC and the
related SC are powered. Once powered, any fault condition (short circuit, over current, over
power, PD disconnection) occurring either for MC or SC forces the reaction of both
channels. All status and measurement information are stored in registers pertaining to the
MC. Detection procedure is the same as the standard one while the classification phase is
performed with 3 classification impulses (total classification time 70ms).
3.8.2
Six channels in Manual mode
To activate this mode the device should be set with CH_NUMx ="00" and the Manual mode
must be selected. Under these conditions the output channels can be shorted together as
illustrated in Figure 9 and according to the following table.
Table 6.
Power boost mode: master/slave channel parallelism
Master Channel (MC)
Slave Channel (SC)
1
2
5
6
3
7
4
8
9
12
11
10
22/44
STE12PS
Functional description
All the functions that manage the six "boost" channels must be implemented by an external
microcontroller.
Figure 9.
Power boost mode
+48V
D1
x12
VL
Det/Class
X4
Power
DMOS
X8
MC
Power EN
Power-on ctrl,
Inrush current
limiting
D2
x4
Short Flag
SC
12-bit A/D
converter
SSRPMC
SSRPSC
Rsense
+
-
Digital
HQGND
Rmon
controller
(§500xRsense)
RMONS
RMONF
300nF
ACSMC
SPMC
AC disconnect detector
~
STE12PS
AC_Discon flag
Figure 10. Crystal oscillator
STE12PS
MCLKout
CLKgen3
CLKgen2
CLKgen1
16pF
16pF
6MHz Crystal
23/44
Functional description
Figure 11. Low cost RC oscillator
STE12PS
STE12PS
MCLKout
CLKgen3
820 ohm
CLKgen2
CLKgen1
210pF
Figure 12. With external oscillator
STE12PS
MCLKout
CLKgen3
CLKgen2
CLKgen1
External 6MHz
24/44
STE12PS
Functional description
3.9
Measurement and parameter codings
Table 7 below lists codifications for the various parameters such as detection conductance
or resistances, classification or monitoring currents, port voltages, port powers and power
budgets.
Table 7.
Measurement and parameter codings
Parameter
Description
Range
Step
Units
Number of steps
Idet
Detection current
0 to 1023
0 to 256
8 to 48.96
0 to 70
1
µA
µS
1024
1024
4096
1024
Gdet, Gdl, Gdh
Rdet, Rdl, Rdh(1)
Iclass
Detection conductances
Detection residences
Current classification
0.250
0.01
KΩ
mA
0.065064
Channel current during
powering
Imon
0 to 1024
0.0312662
mA
32768
Vport
Battery voltage
0 to 70
0.27451
35.149
V
256
Pmeas
Channel power usage
0 to 35000
mW
1024
1. Rdet, Rdl and Rdh are the alternative to Gdet, Gdl and Gdh which are the default. If Rdet measures more than 500kohms,
the “open-circuit” flag is raised, that is set HIGH.
25/44
I2C interface
STE12PS
4
I2C interface
The STE12PS has an I2C interface to allow the access to the internal device registers. The
external controller can be fully isolated from the Ethernet port thanks to an integrated 3.3V
SMPS power source and using optocouplers on I2C bus.(Figure 13).
Figure 13. Isolated ethernet power system using optocouplers for I2C interface
Controller GND
SDA bus
SCL bus
INT bus
OPC 1
OPC 2
SDAIN
SDAOUT
DGND
Controller VDD
SCLIN
INTn
OPC 3
STE12PS
OPC 4
Digital ground
3.3V
26/44
STE12PS
I2C slave protocol overview
5
I2C slave protocol overview
The interface is capable of recognizing its own address (7 bit).
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte following the
start condition contains the device address.
A 9th clock pulse follows the 8 clock cycles of a byte transfer during which the receiver must
pull LOW the SDA line to acknowledge the transfer.
The speed of the I2C interface is fixed at Fast I2C, that is, 100 to 400kHz.
5.1
Functional description
As soon as a start condition is detected, the address is received from the SDA line and sent
to a shift register; then it is compared with the internal address that is composed by the five
pins for the five LSB and by a hardwired value equal to “01” for the other two bits.
In case of address mismatch the interface ignores it and waits for another Start condition.
If address is matched the interface generates an acknowledge pulse.
Following the address reception, POE digital controller receives bytes from the SDA line into
the data register via an internal shift register or sends bytes from the data register to the
SDA line through the internal shift register. After each byte reception an acknowledge pulse
is generated by the controller.
A Stop condition generated by the host processor, after the last data byte is transferred,
closes the communication.
5.2
5.3
5.4
Error cases
An error state is generated when Stop or Start conditions are detected during a byte
transfer. If it is a Stop then the interface discards the data, releases the lines and waits for
another Start condition. If it is a Start then the interface discards the data and waits for the
next slave address on the bus.
Interrupts
Irq register bits indicate which signals can generate an interrupt. The register is read only
and to clear the interrupt bits the corresponding source event has to be cleared. The logic
OR condition of the interrupt bits causes the INTN pin assertion. The INTN assertion can be
masked via the interrupt mask register Irq_mask.
2
I C device address
²
The device is required to have an I C address of: 01xxxxxb(A6 down to A0).
Pins I2C_ADDR[4:0] can be used to set the lower I2C address bits.
27/44
I2C slave protocol overview
STE12PS
5.5
Register addressing: write command format
I2C write command format is shown in Figure 14.
Figure 14. Write command
S
Device address
Register address (K)
6
5
4
3
2
1
0 W
.
7
6
5
4
3
2
1
0
Write data
Write data (K + 1)
7
6
5
4
3
2
1
0
.
7
6
5
4
3
2
1
0
Write data (K + N)
7
6
5
4
3
2
1
0
The formatting bits shown in Figure 14 are defined as follows:
●
●
●
●
●
S - I2C start condition
P - I2C stop condition
ACK – acknowledge
NACK - not acknowledge
R/W - read/write
The device address is the value specified in I2C device address. The register address is an
eight-bit value that is written into an internal Index Register. Each time a byte of data is
written to, or read from the POE controller, the Index Register increments by one.
If the initial value written to the Index Register is K, then the byte immediately following the
Register Address byte is written to the register with an address of K. The next byte is written
to the register with the address of K+1, and so on.
An I2C write command can contain from 0 to 255 write data bytes. Write commands to an
unknown register location are ignored by the interface.
As shown in Figure 14, bits are ordered with the most significant bit first.
28/44
STE12PS
I2C slave protocol overview
5.6
Register addressing: read command format
The general format of the read command is shown in Figure 15.
First part of the general read command consists of writing an address to the Index Register
of the POE controller. If the Index Register already contains the address of the register to be
read, as the result of a previous read or write command, then it is not necessary to write that
address to the Index Register again.
After each byte is read from the POE controller, the Index Register is required to increment
by one.
A read command can contain from 0 to 255 bytes.
Figure 15. Read command
S
Device address
Register address (K)
6
5
4
3
2
1
0 W
.
7
6
5
4
3
2
1
0
S
Device address
Read data (K)
6
5
4
3
2
1
0 R
.
7
7
6
5
4
3
2
1
0
0
Read data (K + 1)
Read data (K + 2)
7
6
5
4
3
2
1
0
6
5
4
3
2
1
P
Read data (K + N)
7
6
5
4
3
2
1
0
29/44
I2C slave protocol overview
STE12PS
5.7
Parallel monitoring interface
In order to monitor the status of the different ports without the I2C register addressing, a
simple, output status interface has been implemented.
This digital interface is comprised of 9 output pins: CH_SEL[3:0], POK, OVLD, OVCUR,
AC_DC_DISCON and DET_CLASS.
Bits CH_SEL[3:0] indicate the channel status flags (POK,..., DET_CLASS) that are currently
notified, externally. CH_SEL is incremented every 60MCLK clock cycles.
POK stands for Power OK. When HIGH, it indicates that the channel is currently powered-on
in normal condition.
OVLD stands for OverLoad and indicates a faulty condition due to abnormal power
dissipation (more than Pclass) of a powered channel.
OVCUR stands for OverCurrent, and it highlights a channel whose current has reached the
power-on current limit of 425mA (typ. value).
Bit AC_DC_DISCON goes HIGH when a powered channel fails in providing a correct MPS
(maintain power signature). This typically happens when a PD is disconnected from the line.
DET_CLASS indicates a situation where a channel is not yet powered and whose
“signature” is currently being probed.
Status flag notification is enabled by bit STATUS_FLAG_EN of the configuration register
Global_cfg2. By default this bit is HIGH, that is, enabled.
This information is particularly useful in simple applications without a microprocessor or for
testing purposes. Another use is to easily build-up an LED graphical interface showing
runtime status of the various channels.
30/44
STE12PS
Electrical specifications and timings
6
Electrical specifications and timings
Table 8.
Absolute maximum ratings
Symbol
VL, SMPSVL
Parameter
Value
Units
Battery voltage
90
3.6
12
V
V
Vcc3,Vdd,Vdde
V10,Vdd10
Tj
3.3V power supply
10V power supply
V
Maximum junction temperature
150
°C
Table 9.
Operating range
Symbol
Parameter
Value
Units
Topt
Operating temperature range
Battery voltage
-20 to +85
44 to 57
-0.3
°C
V
VL, SMPSVL
GNDs
Ground separation
V
Vcc3, Vdd, Vdde
V10, Vdd10
3.3V when externally supplied
10V when externally supplied
10V current sink (when externally supplied)
3 to 3.6
9 to 11
6.7 typ.
V
V
IV10, IVdd10
mA
Battery current sink
IVl
0.4 typ.
mA
(when 10V is externally supplied)
Battery current sink
IVl
7.4 typ.
20 typ.
mA
mA
(when 10V is self generated)
Iv3.3
3.3V current sink (AUTO mode)
Table 10. Thermal data
Symbol
Parameter
Value
Units
Thermal resistance junction-to-ambient (natural
convection)
Rth j-amb
25
°C/W
Table 11. ESD
Symbol
Parameter
Value
Units
All pins but pins Px_1-2 & Px_3
All pins but pins FSRPx_1-2 & Px_3 (x = 1 to 12)
Pins Px_1-2 & Px_3
-2 to +2
kV
HBM
(Human Body Model)
-250 to +250
V
Pins FSRPx_1-2 & Px_3 (x = 1 to 12)
31/44
Electrical specifications and timings
STE12PS
Table 11. ESD (continued)
Symbol
Parameter
Value
Units
Corner pins
-750 to +750
V
All pins but pins Px_1-2 & Px_3
All pins but pins FSRPx_1-2 & Px_3 (x = 1 to 12)
Pins Px_1-2 & Px_3
-500 to +500
-250 to +250
-200 to +200
-50 to +50
V
V
V
V
CDM
(Charge Device Model)
Pins FSRPx_1-2 & Px_3 (x = 1 to 12)
All pins but pins Px_1-2 & Px_3
All pins but pins FSRPx_1-2 & Px_3 (x = 1 to 12)
Pins Px_1-2 & Px_3
MM
(Machine Model)
Pins FSRPx_1-2 & Px_3 (x = 1 to 12)
Table 12. Electrical characteristics
Symbol
Parameter
Min.
Typ.
Max.
Units
Notes
Detection
Vdl
Detection voltage LOW level
Detection voltage HIGH level
3.7
7.4
4
8
4.3
8.6
V
V
Between port terminals
Between port terminals
Vdh
Transient time between Vdl and
Vdh
Adjustable with external
capacitor Cdetslow
Tds
Gdl
300
25
µs
Conductance signature, lower
limit
50
82
24
µmhos Software programmable)
(Software programmable)
Conductance signature, upper
limit
Gdh
Rdl
41
12
20
µmhos Software programmable
Software programmable,
(Software programmable)
Resistance signature, lower limit
(Software programmable)
kΩ
to be used as an
alternative to Gdh
Software programmable,
to be used as an
alternative to Gdl
Resistance signature, upper limit
(Software programmable)
Rdh
40
kΩ
Idlim
Tdet
Current limit during detection
Detection time
1.1
mA
ms
12-port configuration,
one channel at a time
50
Detection delay time
Maximum delay for 12-
port configuration
Tdetd
852
ms
(from PD insertion to end of
detection phase)
Back off time in case of
failed PD detection,
avoided if Rdet > 500kΩ
or Gdet < 2µmhos
Tdbo
Ted
Back-off time (midspan mode)
Error delay time
2
sec.
ms
750
32/44
STE12PS
Electrical specifications and timings
Table 12. Electrical characteristics (continued)
Symbol
Parameter
Min.
Typ.
Max.
Units
Notes
Classification
Vcl
Classification probing voltage
15.9
55
17
18.1
70
V
Between port terminals
Icllim
Current limit during classification
mA
One channel at a time,
classification
measurement has to be
considered as sampled
and integrated over this
time interval.
Tcl
Classification time
15
ms
Ithcl0
Ithcl1
Class0-1 current threshold
Class1-2 current threshold
Class2-3 current threshold
Class3-4 current threshold
Class4-0 current threshold
5.5
6.5
14.5
23
7.5
mA
mA
mA
mA
mA
13.5
21.8
31.5
45.5
15.5
24.2
34.5
47.5
Ithcl2
Ithcl3
33
Ithcl4
46.5
Powering
See also classification
paragraph
Pall
Maximum power per channel
15.4
W
(doubled in case of Boost
configuration)
Iinrush
Imin
Output current startup mode
Power off current
400
5
450
10
mA
mA
Inrush current soft start
Disconnect for t >
TPMDO (DC
disconnection method)
AC disconnection sinusoidal
generator
Frequency spread related
to clock stability
Acfre
Vacd
Zac
50
2.5
100
Hz
Vpp
kΩ
AC generator open line voltage
AC impedance needed to
maintain power
The STE12PS will not
remove power if the PD
maintenance signal is
absent for less than
300ms duration. If an
absence of power
maintenance signal has
been detected, the
STE12PS shall remove
power within 400ms
max(1)
PD power maintenance request
drop out time limit
Tmpdo
300
400
400
ms
(Software programmable)
After time duration of
Tovld the STE12PS will
disconnect the power
from the port.
Icut
Over load current
Pall/Vport
mA
33/44
Electrical specifications and timings
STE12PS
Table 12. Electrical characteristics (continued)
Symbol
Parameter
Min.
Typ.
Max.
Units
Notes
In fault condition for
Over load time limit
Tovld
50
65
75
ms
Tovld, the STE12PS will
(Software programmable)
disconnect the port. (1)
In fault condition for
Short-circuit/inrush time limit
(Software programmable)
Tshort
50
65
75
ms
Tshort, the STE12PS will
disconnect the port.(1)
Max. value of port current
during short circuit
condition. Power will be
disconnected from the
port within Tshort
Output load current under short -
circuit condition
Ilim
400
450
mA
Expired Tinrush if the
channel is still in limiting
condition it is considered
in fault
Tinrush Rise time of Vport time limit
75
ms
Toff
Turn off time
100
1
ms
From VPort to 2.8V DC
Internal MOSFET resistance in
ON mode
Ron
ohms
VsLR
3V range in generator mode
3
2
3.3
8.7
3.6
V
V
V10 int
10V range internally generated
Digital
Fclk
VIH
VIL
IIH
Clock frequency
6
MHz
V
Input HIGH level voltage
Input LOW level voltage
Input High current
@ VDD = 3.3V
@ VDD = 3.3V
0.8
V
30
10
µA
µA
IIL
Input LOW current
1. See also timer programmability
34/44
STE12PS
Ball coordinates
7
Ball coordinates
Figure 16. Balls top view layout (as viewed through package)
35/44
Ball coordinates
STE12PS
Table 13. Pad coordinates
Column
Row
Pin name
Column
Row
Pin name
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
A
AA
AB
B
C
D
E
F
CH_SEL0
P9_3
SP9
2
3
3
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
P
M
N
R
T
NC
FSRp5_3
ACS1
CH_SEL2
vdd10
SMPSGND
S/U
NC
NC
U
V
NC
NC
NC
W
Y
NC
G
H
J
RSENSE
Vdrive
SMPSVL
VL
NC
AA
AB
A
NC
NC
K
L
OVLD
NC
B
AC_DC_DISCON
V3_3
M
N
P
R
T
P5_1-2
P5_3
SP5
C
D
E
ACin
RREF
NC
F
FB
P1_1-2
P1_3
SP1
G
H
J
SenseProgPin0
SenseProgPin1
ACS5
U
V
W
Y
A
B
C
D
E
F
NC
K
SSRp5
FSRp5_1-2
SSRp1
FSRp1_1-2
FSRp1_3
ACS9
P9_1-2
CH_SEL1
CH_SEL3
V10
L
P
R
T
SFTstr
NC
U
V
SSRp9
FSRp9_1-2
FSRp9_3
NC
NC
W
Y
G
H
J
NC
NC
AA
AB
A
NC
P6_1-2
SCL
K
L
NC
NC
B
DET_CLASS
POK
M
N
NC
C
D
NC
ACout
36/44
STE12PS
Ball coordinates
Pin name
Table 13. Pad coordinates (continued)
Column
Row
Pin name
Column
Row
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
7
AA
AB
E
NC
P6_3
9
9
B
C
TEST_MODE0
AUTO_START
I2C_ADDR2
I2C_ADDR4
CLK_GEN2
GND
gnd
7
B
F
gnd
7
C
G
H
DGND
DGND
GND
7
D
7
W
Y
J
7
ACS2
K
GND
7
AA
AB
A
NC
L
GND
7
P2_1-2
CH_NUM1
TEST_MODE1
A_BN_SEL
MCLKout
SSRp2
FSRp2_1-2
NC
M
N
GND
8
GND
8
B
P
GND
8
C
R
GND
8
D
T
GND
8
W
Y
U
GND
8
V
GND
8
AA
AB
A
W
Y
GND
8
P2_3
ACS6
INTN
9
CH_NUM0
CLK_GEN3
GND
A
9
D
AA
AB
B
NC
9
P
SP6
9
W
J
GND
I2C_ADDR0
OVCUR
gnd
9
gnd
C
9
K
GND
D
9
L
GND
W
Y
SSRp6
FSRp6_1-2
SDAIN
NC
9
M
N
GND
9
GND
A
9
Y
FSRp2_3
VDDA
AA
AB
B
10
10
9
D
NC
J
gnd
I2C_ADDR1
I2C_ADDR3
CLK_GEN1
GND
AA
AB
A
NC
C
9
SP2
D
10
10
10
10
AGND
W
Y
B
AGND
FSRp6_3
SDAOUT
C
SCAN_EN
GND
A
K
37/44
Ball coordinates
Table 13. Pad coordinates (continued)
STE12PS
Column
Row
Pin name
Column
Row
Pin name
10
10
10
10
10
10
10
10
11
11
11
11
11
11
11
11
11
11
11
11
11
11
12
12
12
12
12
12
12
12
12
12
12
12
12
AA
AB
L
NC
NC
13
13
12
13
13
13
13
13
13
14
14
13
13
13
13
13
13
14
14
14
14
14
14
15
14
14
14
14
14
14
15
15
15
15
15
K
L
GND
GND
GND
AB
A
P10_3
Vbatref
Vbatmon
AGND
GND
M
N
P
GND
GND
B
GND
C
W
Y
GND
D
ACS10
IDET_HVLV
NC
J
GND
A
M
K
GND
AA
AB
B
GND
P10_1-2
AGND
AGND
gnd
L
GND
N
GND
C
D
J
P
GND
W
Y
GND
gnd
FSRp10_3
NC
K
GND
AA
AB
A
L
GND
SP10
AGND
AGND
AGND
gnde
M
N
P
GND
GND
B
GND
C
W
Y
GND
D
SSRp10
I_REF
NC
J
gnd
A
M
Y
GND
AA
B
FSRp11_3
GND
IMON_HVLV
AGND
gnd
N
C
D
J
P
GND
W
Y
GND
gnd
FSRp11_1-2
NC
K
GND
AA
AB
A
L
GND
NC
M
N
P
GND
RESETN
vdde
GND
B
GND
C
vdde
W
Y
GND
D
gnde
FSRp10_1-2
W
GND
38/44
STE12PS
Ball coordinates
Pin name
Table 13. Pad coordinates (continued)
Column
Row
Pin name
Column
Row
15
15
16
16
16
16
16
16
16
16
17
17
17
17
17
17
17
17
18
18
18
18
18
18
18
18
19
19
19
19
19
19
19
19
19
AA
AB
A
NC
SP11
PORn
NC
19
19
19
19
19
19
19
19
19
19
19
20
20
19
19
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
K
L
SSRp4
GND
M
V
GND
AA
AB
B
GND
P11_3
vdde
gnde
vdd
W
N
P
SSRp3
GND
C
GND
D
R
T
GND
W
Y
GND
SSRp11
vdde
NC
GND
U
Y
GND
A
FSRp3_1-2
POWER_EN9
CdetSlow
NC
AA
AB
B
D
E
P11_1-2
gnde
vdd
AA
AB
A
C
SP3
D
vdd
POWER_EN0
POWER_EN3
POWER_EN6
RMONF
ACS12
W
Y
GND
ACS11
gnde
NC
B
C
F
A
AA
AB
B
M
N
G
H
J
NC
SSRp12
FSRp8_1-2
FSRp8_3
ACS4
vdd
C
gnd
D
gnd
W
Y
GND
FSRp3_3
vdd
K
FSRp4_1-2
FSRp4_3
FSRp12_1-2
FSRp12_3
ACS7
L
A
P
B
gnd
R
T
C
gnd
D
gnd
U
V
SSRp7
E
gnd
FSRp7_1-2
FSRp7_3
ACS3
F
RMONS
HQgnd
ACS8
SSRp8
W
Y
G
H
AA
AB
NC
J
P3_3
39/44
Ball coordinates
Table 13. Pad coordinates (continued)
STE12PS
Column
Row
Pin name
Column
Row
Pin name
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
22
22
22
22
22
22
22
22
22
22
22
22
22
22
A
AB
B
C
D
E
F
POWER_EN1
22
22
22
22
22
22
22
22
R
T
P12_3
SP12
NC
P3_1-2
POWER_EN4
U
POWER_EN7
V
P7_1-2
P7_3
SP7
POWER_EN10
W
Y
NC
NC
AA
AB
NC
G
H
J
NC
NC
NC
NC
K
L
NC
NC
M
N
P
R
T
NC
NC
NC
NC
NC
U
V
W
Y
A
B
C
D
E
F
NC
NC
NC
NC
POWER_EN2
POWER_EN5
POWER_EN8
POWER_EN11
NC
P8_1-2
P8_3
G
H
J
SP8
NC
K
L
P4_1-2
P4_3
M
N
P
SP4
NC
P12_1-2
40/44
STE12PS
Package information - mechanical data
8
Package information - mechanical data
In order to meet environmental requirements, ST Microelectronics offers these devices in
ECOPACK® packages. These packages have a lead-free second level interconnect. The
category of second level interconnect is marked on the package on the inner box label, in
compliance with JEDEC standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST Microelectronics
trademark. ECOPACK specifications are available at: www.st.com.
Package code: TN
JEDEC/EIAJ reference number: JEDEC standard No. 95-1, section 14 (ball grid array
package design guide)
Table 14. Package dimensions
Databook (mm)
Drawing (mm)
Typ.
Ref.
Min.
Typ.
Max.
Min.
Max.
A
1.720
1.620
0.350
1.720
0.400
1.320
0.500
23.000
1.820
0.450
A1
A2
b
0.270
1.320
0.500
0.450
0.550
0.450
0.550
23.100
21.000
23.100
21.000
1.050
D
22.800
23.000
21.000
23.000
21.000
1.000
23.200
22.900
D1
E
22.800
23.200
22.900
23.000
E1
e
0.950
0.875
1.050
1.125
0.200
0.950
0.875
1.000
1.000
f
1.000
1.125
ddd
0.200
Note:
1
Maximum mounted height, dimension A, is 1.77mm based on a 0.35mm ball pad diameter.
Solder paste is 0.15mm thick and 0.35mm in diameter.
2
3
PBGA stands for Plastic Ball Grid Array.
The terminal A1 corner must be on the top surface by using a corner chamfer, ink,
metallized markings or some other feature of the package body or internal heatslug.
4
5
A distinguishing feature is allowed on the bottom surface of the package to identify terminal
the A1 corner.
Exact shape of each corner is optional.
41/44
Package information - mechanical data
STE12PS
Figure 17. PBGA23x23 package mechanical drawing
42/44
STE12PS
Ordering information
9
Ordering information
Table 15. Order codes
Part number
Temperature range
-40°C to +85 °C
Package
E-STE12PS(1)
PBGA (23mm x 23mm x 1.82mm)
1. E-: ECOPACK®
10
Revision history
Table 16. Document revision history
Date
Revision
Changes
10-Nov-2006
1
Initial release
Updated the number of 30W boosted ports to be four or six instead
of four previously (cover page and Section 3.8).
13-Dec-2006
17-Aug-2007
2
3
Added Table 11: ESD in Chapter 6.
43/44
STE12PS
Please Read Carefully:
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right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
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WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
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GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
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44/44
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