74LVX373MTC [STMICROELECTRONICS]
Low Voltage Octal Transparent Latch with TRI-STATE Outputs; 低电压八路透明锁存器与三态输出
| 型号： | 74LVX373MTC |
| 厂家： | 
ST |
| 描述： | Low Voltage Octal Transparent Latch with TRI-STATE Outputs |
| 文件： | 总13页 (文件大小：304K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVX373
LOW VOLTAGE CMOS OCTAL D-TYPE LATCH
(3-STATE NON INV.) WITH 5V TOLERANT INPUTS
■
HIGH SPEED:
=5.8ns (TYP.) at V = 3.3V
t
PD
CC
■
■
■
5V TOLERANT INPUTS
POWER-DOWN PROTECTION ON INPUTS
INPUT VOLTAGE LEVEL:
V
= 0.8V, V = 2V at V =3V
IL
IH CC
SOP
TSSOP
■
■
■
■
■
■
■
LOW POWER DISSIPATION:
= 4 µA (MAX.) at T =25°C
I
CC
A
LOW NOISE:
= 0.3V (TYP.) at V =3.3V
Table 1: Order Codes
PACKAGE
V
OLP
CC
SYMMETRICAL OUTPUT IMPEDANCE:
|I | = I = 4 mA (MIN) at V =3V
T & R
OH
OL
CC
SOP
74LVX373MTR
74LVX373TTR
BALANCED PROPAGATION DELAYS:
TSSOP
t
t
PLH
PHL
OPERATING VOLTAGE RANGE:
(OPR) = 2V to 3.6V (1.2V Data Retention)
V
When the LE is taken low, the Q outputs will be
latched precisely at the logic level of D input data.
While the (OE) input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V. It
combines high speed performance with the true
CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
CC
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVX373 is a low voltage CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
This 8 bit D-Type latch is controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input precisely.
2
Figure 1: Pin Connection And IEC Logic Symbols
Rev. 4
1/13
August 2004
74LVX373
Figure 2: Input Equivalent Circuit
Table 2: Pin Description
PIN N°
SYMBOL
NAME AND FUNCTION
1
OE
3 State Output Enable
Input (Active LOW)
3, 4, 7, 8, 13,
14, 17, 18
D0 to D7
Q0 to Q7
Data Inputs
2, 5, 6, 9, 12,
15, 16,19
3-State Outputs
11
10
20
LE
Latch Enable Input
Ground (0V)
GND
V
Positive Supply Voltage
CC
Table 3: Truth Table
OE
INPUTS
LE
OUTPUT
Q
D
H
L
L
L
X
L
X
X
L
Z
NO CHANGE*
H
H
L
H
H
X : Don’t Care
Z : High Impedance
* : Q Outputs are Latched at the time when the LE INPUT is taken low logic level
Figure 3: Logic Diagram
This logic diagram has not be used to estimate propagation delays
2/13
74LVX373
Table 4: Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
V
Supply Voltage
-0.5 to +7.0
-0.5 to +7.0
V
V
CC
V
DC Input Voltage
I
V
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
-0.5 to V + 0.5
V
O
CC
I
- 20
± 20
mA
mA
mA
mA
°C
°C
IK
I
OK
I
± 25
O
I
or I
DC V or Ground Current
± 50
CC
GND
CC
T
Storage Temperature
-65 to +150
300
stg
T
Lead Temperature (10 sec)
L
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 5: Recommended Operating Conditions
Symbol
Parameter
Value
Unit
V
Supply Voltage (note 1)
Input Voltage
2 to 3.6
0 to 5.5
V
V
CC
V
I
V
Output Voltage
0 to V
V
O
CC
T
Operating Temperature
-55 to 125
0 to 100
°C
ns/V
op
Input Rise and Fall Time (note 2) (V = 3V)
dt/dv
CC
1) Truth Table guaranteed: 1.2V to 3.6V
2) V from 0.8V to 2.0V
IN
Table 6: DC Specifications
Test Condition
Value
T = 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
V
High Level Input
Voltage
2.0
3.0
3.6
2.0
3.0
3.6
2.0
1.5
2.0
2.4
1.5
2.0
2.4
1.5
2.0
2.4
IH
V
V
V
Low Level Input
Voltage
0.5
0.8
0.8
0.5
0.8
0.8
0.5
0.8
0.8
IL
V
High Level Output
Voltage
I =-50 µA
1.9
2.9
2.0
3.0
1.9
2.9
1.9
2.9
2.4
OH
O
I =-50 µA
3.0
3.0
2.0
3.0
3.0
V
O
I =-4 mA
2.58
2.48
O
V
Low Level Output
Voltage
I =50 µA
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
OL
OZ
O
I =50 µA
V
O
I =4 mA
0.36
0.44
0.55
O
I
High Impedance
Output Leakage
Current
V = V or V
IL
I
IH
3.6
±0.25
± 2.5
± 5
µA
V
= V or GND
CC
O
I
Input Leakage Current
V = 5V or GND
3.6
3.6
± 0.1
± 1
± 1
µA
µA
I
I
I
Quiescent Supply
Current
CC
V = V or GND
4
40
40
I
CC
3/13
74LVX373
Table 7: Dynamic Switching Characteristics
Test Condition
Value
T = 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
V
Dynamic Low
0.3
0.8
OLP
Voltage Quiet
Output (note 1, 2)
3.3
V
-0.8
2.0
-0.3
OLV
Dynamic High
Voltage Input
(note 1, 3)
V
C = 50 pF
L
3.3
3.3
V
IHD
Dynamic Low
Voltage Input
(note 1, 3)
V
0.8
ILD
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V ), 0V to threshold
ILD
(V ), f=1MHz.
IHD
Table 8: AC Electrical Characteristics (Input t = t = 3ns)
r
f
Test Condition
Value
T = 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
C
L
CC
(V) (pF)
Min. Typ. Max. Min. Max. Min. Max.
t
t
Propagation Delay
Time
LE to Q
2.7
2.7
15
50
15
7.5
14.5
1.0
1.0
1.0
17.5
21.0
12.0
1.0
1.0
1.0
18.5
22.0
13.0
PLH
PHL
10.0 18.0
ns
ns
ns
(*)
6.8
9.3
7.7
10.3
13.8
15.0
3.3
3.3
(*)
50
15
50
15
1.0
1.0
1.0
1.0
15.5
18.5
22.0
11.5
1.0
1.0
1.0
1.0
16.5
19.5
23.0
12.5
t
t
Propagation Delay
Time
D to Q
2.7
2.7
PLH
PHL
10.2 18.5
(*)
5.8
8.5
7.7
9.7
3.3
3.3
(*)
50
15
50
15
13.2
15.0
1.0
1.0
1.0
1.0
15.0
18.5
22.0
11.5
1.0
1.0
1.0
1.0
16.0
19.5
23.0
12.5
t
t
Output Enable
Time
2.7
2.7
PZL
10.2 18.5
PZH
(*)
6.0
8.5
9.8
8.2
9.7
13.2
18.0
12.8
6.5
3.3
3.3
(*)
50
50
50
50
50
50
50
50
50
50
1.0
1.0
1.0
15.0
21.0
14.5
7.5
1.0
1.0
1.0
16.0
22.0
15.5
7.5
2.7
t
t
Output Disable
Time
PLZ
PHZ
ns
ns
ns
ns
(*)
3.3
3.3
3.3
3.3
2.7
LE pulse Width,
HIGH
t
W
(*)
5.0
5.0
5.0
2.7
6.0
6.0
6.0
Setup Time D to LE
HIGH or LOW
t
S
(*)
4.0
4.0
4.0
2.7
1.0
1.0
1.0
Hold Time D to LE
HIGH or LOW
t
h
(*)
1.0
1.0
1.0
Output to Output
Skew Time (note
1,2)
2.7
0.5
0.5
1.0
1.5
1.5
t
t
OSLH
ns
(*)
50
1.0
1.5
1.5
OSHL
3.3
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
4/13
74LVX373
Table 9: Capacitive Characteristics
Test Condition
Value
-40 to 85°C -55 to 125°C Unit
Min. Typ. Max. Min. Max. Min. Max.
T = 25°C
Symbol
Parameter
A
V
CC
(V)
C
Input Capacitance
3.3
3.3
5
10
10
pF
pF
IN
C
Output
Capacitance
OUT
10
C
Power Dissipation
Capacitance
(note 1)
PD
f
= 10MHz
3.3
40
pF
IN
1) C is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
PD
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
= C x V x f + I /8 (per circuit)
CC(opr)
PD CC IN CC
Figure 4: Test Circuit
TEST
SWITCH
t
t
t
, t
Open
PLH PHL
, t
V
CC
PZL PLZ
, t
GND
PZH PHZ
C
R
R
=15/50pF or equivalent (includes jig and probe capacitance)
= R1 = 1KΩ or equivalent
L
L
T
= Z
of pulse generator (typically 50Ω)
OUT
5/13
74LVX373
Figure 5: Waveform - LE To Qn Propagation Delays, LE Minimum Pulse Width, Dn To LE Setup
And Hold Times (f=1MHz; 50% duty cycle)
Figure 6: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle)
6/13
74LVX373
Figure 7: Waveform - Propagation Delay Time (f=1MHz; 50% duty cycle)
7/13
74LVX373
SO-20 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
MIN.
MAX.
A
A1
B
2.35
2.65
0.093
0.104
0.1
0.33
0.23
12.60
7.4
0.30
0.51
0.32
13.00
7.6
0.004
0.013
0.009
0.496
0.291
0.012
0.020
0.013
0.512
0.299
C
D
E
e
1.27
0.050
H
10.00
0.25
0.4
10.65
0.75
1.27
8°
0.394
0.010
0.016
0°
0.419
0.030
0.050
8°
h
L
k
0°
ddd
0.100
0.004
0016022D
8/13
74LVX373
TSSOP20 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
1.2
MIN.
MAX.
0.047
0.006
0.041
0.012
0.0079
0.260
0.260
0.176
A
A1
A2
b
0.05
0.8
0.15
1.05
0.30
0.20
6.6
0.002
0.031
0.007
0.004
0.252
0.244
0.169
0.004
0.039
1
0.19
0.09
6.4
c
D
6.5
6.4
0.256
0.252
E
6.2
6.6
E1
e
4.3
4.4
4.48
0.173
0.65 BSC
0.0256 BSC
K
0˚
8˚
0˚
8˚
L
0.45
0.60
0.75
0.018
0.024
0.030
A2
A
K
L
b
e
A1
E
c
D
E1
PIN 1 IDENTIFICATION
1
0087225C
9/13
74LVX373
Tape & Reel SO-20 MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
MAX.
330
MIN.
MAX.
12.992
0.519
A
C
12.8
20.2
60
13.2
0.504
0.795
2.362
D
N
T
30.4
11
1.197
0.433
0.528
0.130
0.161
0.476
Ao
Bo
Ko
Po
P
10.8
13.2
3.1
0.425
0.520
0.122
0.153
0.468
13.4
3.3
3.9
4.1
11.9
12.1
10/13
74LVX373
Tape & Reel TSSOP20 MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
MAX.
330
MIN.
MAX.
12.992
0.519
A
C
12.8
20.2
60
13.2
0.504
0.795
2.362
D
N
T
22.4
7
0.882
0.276
0.280
0.075
0.161
0.476
Ao
Bo
Ko
Po
P
6.8
6.9
0.268
0.272
0.067
0.153
0.468
7.1
1.9
4.1
12.1
1.7
3.9
11.9
11/13
74LVX373
Table 10: Revision History
Date
Revision
Description of Changes
Ordering Codes Revision - pag. 1.
27-Aug-2004
4
12/13
74LVX373
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
All other names are the property of their respective owners
© 2004 STMicroelectronics - All Rights Reserved
STMicroelectronics group of companies
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www.st.com
13/13
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