74LVQ174TTR [STMICROELECTRONICS]
HEX D-TYPE FLIP FLOP WITH CLEAR; HEX D型触发器与Clear FLOP
| 型号： | 74LVQ174TTR |
| 厂家： | 
ST |
| 描述： | HEX D-TYPE FLIP FLOP WITH CLEAR |
| 文件： | 总13页 (文件大小：302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVQ174
HEX D-TYPE FLIP FLOP WITH CLEAR
■
HIGH SPEED:
= 150 MHz (TYP.) at V = 3.3 V
f
MAX
CC
■
■
COMPATIBLE WITH TTL OUTPUTS
LOW POWER DISSIPATION:
I
= 4 µA (MAX.) at T =25°C
CC
A
■
■
■
LOW NOISE:
= 0.3V (TYP.) at V = 3.3V
75Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
SOP
TSSOP
V
OLP
CC
Table 1: Order Codes
PACKAGE
|I | = I = 12mA (MIN) at V = 3.0 V
T & R
OH
OL
CC
■
■
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
SOP
74LVQ174MTR
74LVQ174TTR
TSSOP
t
t
PHL
PLH
■
■
■
OPERATING VOLTAGE RANGE:
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 174
technology. It is ideal for low power and low noise
3.3V applications.
Information signals applied to D inputs are
transferred to the Q outputs on the positive going
edge of the CLK pulse.
V
CC
IMPROVED LATCH-UP IMMUNITY
When the CLR input is held low, the Q outputs are
held low independently of the other inputs.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The 74LVQ174 is a low voltage CMOS HEX
D-TYPE FLIP FLOP WITH CLEAR NON
INVERTING fabricated with sub-micron silicon
2
gate and double-layer metal wiring C MOS
Figure 1: Pin Connection And IEC Logic Symbols
Rev. 5
1/13
July 2004
74LVQ174
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description
PIN N°
SYMBOL
NAME AND FUNCTION
1
CLR
Asynchronous Master
Reset (Active LOW)
2, 5, 7, 10,
12, 15
Q0 to Q5 Flip-Flop Outputs
3, 4, 6, 11,
13, 14
D0 to D5 Data Inputs
9
CLK
Clock Input (Positive Edge
Triggered)
8
GND
Ground (0V)
16
V
Positive Supply Voltage
CC
Table 3: Truth Table
INPUTS
OUTPUT
FUNCTION
CLR
L
D
X
L
CLK
Q
L
X
CLEAR
H
L
H
H
H
X
H
Q
NO CHANGE
n
X : Don’t Care
Figure 3: Logic Diagram
This logic diagram has not to be used to estimate propagation delays
2/13
74LVQ174
Table 4: Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
V
Supply Voltage
-0.5 to +7
V
V
CC
V
DC Input Voltage
-0.5 to V + 0.5
I
CC
V
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
-0.5 to V + 0.5
V
O
CC
I
± 20
± 20
mA
mA
mA
mA
°C
°C
IK
I
OK
I
± 50
O
I
or I
DC V or Ground Current
± 300
CC
GND
CC
T
Storage Temperature
-65 to +150
300
stg
T
Lead Temperature (10 sec)
L
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 5: Recommended Operating Conditions
Symbol
Parameter
Value
Unit
V
Supply Voltage (note 1)
Input Voltage
2 to 3.6
V
V
CC
V
0 to V
I
CC
V
Output Voltage
0 to V
V
O
CC
T
Operating Temperature
-55 to 125
0 to 10
°C
ns/V
op
Input Rise and Fall Time V = 3.0V (note 2)
dt/dv
CC
1) Truth Table guaranteed: 1.2V to 3.6V
2) V from 0.8V to 2V
IN
Table 6: DC Specifications
Test Condition
Value
T = 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
V
High Level Input
Voltage
IH
2.0
2.0
2.0
V
V
3.0 to
3.6
V
Low Level Input
Voltage
IL
0.8
0.8
0.8
V
High Level Output
Voltage
I =-50 µA
2.9
2.99
2.9
2.48
2.2
2.9
2.48
2.2
OH
O
I =-12 mA
3.0
3.0
2.58
V
V
O
I =-24 mA
O
V
Low Level Output
Voltage
I =50 µA
0.002 0.1
0.1
0.1
OL
O
I =12 mA
0
0.36
0.44
0.55
0.44
0.55
O
I =24 mA
O
I
Input Leakage
Current
I
V = V or GND
3.6
3.6
± 0.1
± 1
± 1
µA
µA
I
CC
I
Quiescent Supply
Current
CC
V = V or GND
4
40
40
I
CC
I
V
= 0.8 V max
= 2 V min
36
25
mA
mA
OLD
OLD
Dynamic Output
Current (note 1, 2)
3.6
I
V
OHD
-25
-25
OHD
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75Ω
3/13
74LVQ174
Table 7: Dynamic Switching Characteristics
Test Condition
Value
T = 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
V
Dynamic Low
0.3
0.8
OLP
Voltage Quiet
Output (note 1, 2)
3.3
3.3
V
V
V
-0.8
2
-0.3
OLV
V
Dynamic High
Voltage Input
(note 1, 3)
IHD
C = 50 pF
L
V
Dynamic Low
Voltage Input
(note 1, 3)
3.3
0.8
V
ILD
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V ), 0V to threshold
ILD
(V ), f=1MHz.
IHD
Table 8: AC Electrical Characteristics (C = 50 pF, R = 500 Ω, Input t = t = 3ns)
L
L
r
f
Test Condition
Value
T = 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
t
t
Propagation Delay
Time CK to Q
2.7
6.7
5.5
8.3
7.0
1.0
1.0
1.0
11.0
8.0
12.5
9.5
14.5
11.0
18.0
13.0
PLH PHL
ns
ns
ns
(*)
3.3
2.7
t
Propagation Delay
Time CLR to Q
13.5
10.0
15.5
11.5
PHL
(*)
3.3
2.7
t
CLR Pulse Width,
LOW
4.0
3.0
4.0
4.0
3.0
4.0
5.0
4.0
5.0
W(L)
(*)
3.3
2.7
t
CLOCK Pulse
Width, HIGH or
LOW
W
ns
(*)
3.3
3.0
1.0
3.0
4.0
t
Setup Time D to
CK, HIGH or LOW
2.7
4.0
3.0
3.0
2.0
3.0
2.0
60
-0.5
-0.4
0.5
4.0
3.0
3.0
2.0
3.0
2.0
50
4.0
3.0
3.0
2.0
3.0
2.0
50
sL
ns
ns
(*)
t
sH
3.3
2.7
t
Hold Time D to CK,
HIGH or LOW
hL
(*)
t
hH
0.4
3.3
2.7
t
Recovery Time
CLR to CK
-0.3
-0.3
150
150
0.5
REM
ns
(*)
3.3
2.7
f
Maximum Clock
Frequency
MAX
MHz
(*)
90
70
70
3.3
2.7
t
t
Output To Output
Skew Time
(note1, 2)
1.0
1.0
1.0
1.0
1.0
1.0
OSLH
OSHL
ns
(*)
0.5
3.3
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
= |t
- t
|, t
= |t
- t
|)
OSLH
PLHm PLHn OSHL
PHLm PHLn
4/13
74LVQ174
Table 9: Capacitive Characteristics
Test Condition
Value
-40 to 85°C -55 to 125°C Unit
T = 25°C
Symbol
Parameter
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
C
Input Capacitance
3.3
4
pF
pF
IN
C
Power Dissipation
Capacitance
(note 1)
PD
f
= 10MHz
3.3
23
IN
1) C is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
PD
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
flop)
= C x V x f + I /6 (per flip
CC(opr)
PD CC IN CC
Figure 4: Test Circuit
C
R
R
= 50pF or equivalent (includes jig and probe capacitance)
L
L
T
= R = 500Ω or equivalent
1
OUT
= Z
of pulse generator (typically 50Ω)
5/13
74LVQ174
Figure 5: Waveform - Propagation Delays, Setup And Hold Times, Clock Pulse Width (f=1MHz;
50% duty cycle)
Figure 6: Waveform - Propagation Delays (f=1MHz; 50% duty cycle)
6/13
74LVQ174
Figure 7: Waveform - Recovery Time, Clear Pulse Width (f=1MHz; 50% duty cycle)
7/13
74LVQ174
SO-16 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
1.75
0.25
1.64
0.46
0.25
MIN.
MAX.
0.068
0.010
0.063
0.018
0.010
A
a1
a2
b
0.1
0.004
0.35
0.19
0.013
0.007
b1
C
0.5
0.019
c1
D
45° (typ.)
9.8
5.8
10
0.385
0.228
0.393
0.244
E
6.2
e
1.27
8.89
0.050
0.350
e3
F
3.8
4.6
0.5
4.0
5.3
0.149
0.181
0.019
0.157
0.208
0.050
0.024
G
L
1.27
0.62
M
S
8° (max.)
0016020D
8/13
74LVQ174
TSSOP16 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
1.2
MIN.
MAX.
0.047
0.006
0.041
0.012
0.0079
0.201
0.260
0.176
A
A1
A2
b
0.05
0.8
0.15
1.05
0.30
0.20
5.1
0.002
0.031
0.007
0.004
0.193
0.244
0.169
0.004
0.039
1
0.19
0.09
4.9
c
D
5
6.4
0.197
0.252
E
6.2
6.6
E1
e
4.3
4.4
4.48
0.173
0.65 BSC
0.0256 BSC
K
0˚
8˚
0˚
8˚
L
0.45
0.60
0.75
0.018
0.024
0.030
A2
A
K
L
b
e
A1
c
E
D
E1
PIN 1 IDENTIFICATION
1
0080338D
9/13
74LVQ174
Tape & Reel SO-16 MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
MAX.
330
MIN.
MAX.
12.992
0.519
A
C
12.8
20.2
60
13.2
0.504
0.795
2.362
D
N
T
22.4
6.65
10.5
2.3
0.882
0.262
0.414
0.090
0.161
0.319
Ao
Bo
Ko
Po
P
6.45
10.3
2.1
0.254
0.406
0.082
0.153
0.311
3.9
4.1
7.9
8.1
10/13
74LVQ174
Tape & Reel TSSOP16 MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
MAX.
330
MIN.
MAX.
12.992
0.519
A
C
12.8
20.2
60
13.2
0.504
0.795
2.362
D
N
T
22.4
6.9
5.5
1.8
4.1
8.1
0.882
0.272
0.217
0.071
0.161
0.319
Ao
Bo
Ko
Po
P
6.7
5.3
1.6
3.9
7.9
0.264
0.209
0.063
0.153
0.311
11/13
74LVQ174
Table 10: Revision History
Date
Revision
Description of Changes
Ordering Codes Revision - pag. 1.
29-Jul-2004
5
12/13
74LVQ174
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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All other names are the property of their respective owners
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