74LVQ02 [STMICROELECTRONICS]

QUAD 2-INPUT NOR GATE; 四路2输入NOR门
74LVQ02
型号: 74LVQ02
厂家: ST    ST
描述:

QUAD 2-INPUT NOR GATE
四路2输入NOR门

输入元件
文件: 总8页 (文件大小:59K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
74LVQ02  
QUAD 2-INPUT NOR GATE  
HIGH SPEED:tPD =5 ns (TYP.) atVCC =3.3V  
COMPATIBLEWITH TTL OUTPUTS  
LOW POWER DISSIPATION:  
I
CC =2 µA (MAX.) at TA =25 oC  
LOWNOISE:  
VOLP =0.3 V (TYP.)at VCC = 3.3V  
M
T
(Micro Package)  
(TSSOPPackage)  
75 TRANSMISSIONLINEDRIVING  
ORDER CODES :  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
74LVQ02M  
74LVQ02T  
|IOH| = IOL = 12 mA (MIN)  
technology.It is ideal for low power and low noise  
3.3V applications.  
The internal circuit is composed of 3 stages  
including buffer output, which enables high noise  
immunity and stable output.  
It has better speed performance at 3.3V than 5V  
LS-TTL family combined with the true CMOS low  
power consumption.  
PCI BUSLEVELSGUARANTEED AT 24mA  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
OPERATING VOLTAGERANGE:  
VCC (OPR)= 2V to 3.6V(1.2VDataRetention)  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES02  
IMPROVED LATCH-UP IMMUNITY  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The LVQ02 is a low voltage CMOS QUAD  
2-INPUT NOR GATE fabricated with sub-micron  
silicon gate and double-layermetal wiring C2MOS  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/8  
February 1999  
74LVQ02  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
PIN DESCRIPTION  
PIN No  
2, 5, 8, 11  
3, 6, 9, 12  
1, 4, 10, 13  
7
SYMBOL NAME AND FUNCTION  
1A to 4A Data Inputs  
1B to 4B Data Inputs  
1Y to 4Y Data Outputs  
GND  
VCC  
Ground (0V)  
14  
Positive Supply Voltage  
TRUTH TABLE  
A
L
B
Y
H
L
L
L
L
H
L
L
H
H
H
ABSOLUTE MAXIMUM RATINGS  
Symbol  
VCC  
VI  
Parameter  
Value  
Unit  
V
Supply Voltage  
-0.5 to +7  
DC Input Voltage  
DC Output Voltage  
DC Input Diode Current  
-0.5 to VCC + 0.5  
-0.5 to VCC + 0.5  
± 20  
V
VO  
V
IIK  
mA  
mA  
mA  
mA  
oC  
IOK  
DC Output Diode Current  
DC Output Current  
20  
±
IO  
± 50  
± 200  
ICC or IGND DC VCC or Ground Current  
Tstg  
TL  
Storage Temperature  
-65 to +150  
300  
Lead Temperature (10 sec)  
oC  
AbsoluteMaximum Ratingsarethose values beyond whichdamage tothe device may occur. Functional operation under these condition isnot implied.  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
VCC  
VI  
Parameter  
Supply Voltage (note 1)  
Value  
2 to 3.6  
0 to VCC  
0 to VCC  
-40 to +85  
0 to 10  
Unit  
V
Input Voltage  
V
VO  
Output Voltage  
V
oC  
Top  
Operating Temperature:  
Input Rise and Fall Time (VCC = 3V) (note 2)  
dt/dv  
ns/V  
1) Truth Table guaranteed: 1.2V to 3.6V  
2)VIN from0.8Vto2V  
2/8  
74LVQ02  
DC SPECIFICATIONS  
Symbol  
Parameter  
Test Conditions  
Value  
TA = 25 oC  
Min. Typ. Max. Min. Max.  
Unit  
VCC  
(V)  
-40 to 85 oC  
VIH  
VIL  
High Level Input Voltage  
Low Level Input Voltage  
2.0  
2.0  
V
V
3.0 to  
3.6  
0.8  
0.8  
VOH  
High Level Output  
Voltage  
3.0  
IO=-50 µA  
2.9  
2.99  
2.9  
2.48  
2.2  
VI(*)  
VIL  
=
=
V
IO=-12 mA 2.58  
IO=-24 mA  
IO=50 µA  
VOL  
Low Level Output  
Voltage  
3.0  
VI(*)  
0.002 0.1  
0.36  
0.1  
V
IH or  
VIL  
V
IO=12 mA  
0
0.44  
0.55  
IO=24 mA  
II  
Input Leakage Current  
VI = VCC or GND  
VI = VCC or GND  
0.1  
±
2
1
A
µ
3.6  
3.6  
±
ICC  
Quiescent Supply  
Current  
20  
µA  
IOLD  
IOHD  
Dynamic Output Current  
(note 1, 2)  
3.6  
VOLD = 0.8 V max  
VOHD = 2 V min  
36  
mA  
mA  
-25  
1) Maximum test duration 2ms, one output loaded attime  
2)Incident wave switchingis guaranteed ontransmission lines withimpedances aslowas50 .  
(*) All outputs loaded.  
DYNAMIC SWITCHING CHARACTERISTICS  
Symbol  
Parameter  
Test Conditions  
Value  
TA = 25 oC  
Min. Typ. Max. Min. Max.  
Unit  
VCC  
(V)  
-40 to 85 oC  
VOLP Dynamic Low Voltage  
3.3  
0.3  
0.8  
Quiet Output (note 1, 2)  
VOLV  
-0.8  
-0.3  
VIHD  
VILD  
Dynamic High Voltage  
Input (note 1, 3)  
3.3  
3.3  
2
CL = 50 pF  
V
Dynamic Low Voltage  
Input (note 1, 3)  
0.8  
1)Worstcase package.  
2)Max number ofoutputs defined as (n). Datainputs aredriven 0Vto3.3V, (n -1)outputs switching andone outputatGND.  
3)Max number ofdatainputs (n)switching.(n-1)switching 0Vto3.3V. Inputsunder testswitching: 3.3Vtothreshold (VILD),0V tothreshold (VIHD).,f=1MHz.  
3/8  
74LVQ02  
AC ELECTRICAL CHARACTERISTICS  
(CL = 50 pF, RL = 500 , Input tr = t =3 ns)  
f
Symbol  
Parameter  
Test Condition  
Value  
TA = 25 oC  
Min. Typ. Max. Min. Max.  
Unit  
VCC  
(V)  
-40 to 85 oC  
tPLH  
tPHL  
Propagation Delay Time  
2.7  
3.3(*)  
2.7  
3.3(*)  
6.0  
5.0  
0.5  
0.5  
10.5  
7.5  
1.5  
1.5  
12.0  
8.0  
1.5  
1.5  
ns  
ns  
tOSLH Output to Output Skew  
tOSHL  
Time (note 1, 2)  
1) Skewis defined astheabsolute value ofthe difference between theactual propagation delay for any twooutputs of thesame device switching inthe  
same direction, either HIGHor LOW (tOSLH = |tPLHm -tPLHn|,tOSHL =|tPHLm -tpHLn|)  
2) Parameter guaranteed bydesign  
(*) Voltagerangeis3.3V ± 0.3V  
CAPACITIVE CHARACTERISTICS  
Symbol  
Parameter  
Test Conditions  
Value  
TA = 25 oC  
Unit  
VCC  
-40 to 85 oC  
(V)  
Min. Typ. Max. Min. Max.  
CIN  
Input Capacitance  
4
3.3  
3.3  
pF  
pF  
CPD  
Power Dissipation  
fIN = 10 MHz  
40  
Capacitance (note 1)  
1)CPD isdefined as thevalue ofthe IC’sinternal equivalent capacitance whichiscalculated fromthe operating current consumption without load. (Referto  
TestCircuit).Average operting current can beobtained bythe followingequation. ICC(opr)= CPD VCC fIN + ICC/4(pergate)  
4/8  
74LVQ02  
TEST CIRCUIT  
CL = 50 pF or equivalent (includes jigand probe capacitance)  
R =R =500 orequivalent  
L
1
RT = ZOUT ofpulse generator (typically50)  
WAVEFORM: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)  
5/8  
74LVQ02  
SO-14 MECHANICAL DATA  
mm  
inch  
TYP.  
DIM.  
MIN.  
TYP.  
MAX.  
1.75  
0.2  
MIN.  
MAX.  
0.068  
0.007  
0.064  
0.018  
0.010  
A
a1  
a2  
b
0.1  
0.003  
1.65  
0.46  
0.25  
0.35  
0.19  
0.013  
0.007  
b1  
C
0.5  
0.019  
c1  
D
45 (typ.)  
8.55  
5.8  
8.75  
6.2  
0.336  
0.228  
0.344  
0.244  
E
e
1.27  
7.62  
0.050  
0.300  
e3  
F
3.8  
4.6  
0.5  
4.0  
5.3  
0.149  
0.181  
0.019  
0.157  
0.208  
0.050  
0.026  
G
L
1.27  
0.68  
M
S
8 (max.)  
P013G  
6/8  
74LVQ02  
TSSOP14 MECHANICAL DATA  
mm  
inch  
TYP.  
DIM.  
MIN.  
TYP.  
MAX.  
1.1  
MIN.  
MAX.  
0.433  
0.006  
0.374  
0.0118  
0.0079  
0.201  
0.256  
0.176  
A
A1  
A2  
b
0.05  
0.85  
0.19  
0.09  
4.9  
0.10  
0.9  
0.15  
0.95  
0.30  
0.20  
5.1  
0.002  
0.335  
0.0075  
0.0035  
0.193  
0.246  
0.169  
0.004  
0.354  
c
D
5
6.4  
0.197  
0.252  
E
6.25  
4.3  
6.5  
E1  
e
4.4  
4.48  
0.173  
0.65 BSC  
4o  
0.0256 BSC  
4o  
K
0o  
8o  
0o  
8o  
L
0.50  
0.60  
0.70  
0.020  
0.024  
0.028  
A2  
A
K
L
b
e
A1  
c
E
D
E1  
PIN 1 IDENTIFICATION  
1
7/8  
74LVQ02  
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences  
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is  
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are  
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products  
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.  
The ST logo is a trademark of STMicroelectronics  
1999 STMicroelectronics – Printed in Italy – All Rights Reserved  
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.
8/8  

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