74LCX574TTR [STMICROELECTRONICS]
OCTAL D-TYPE FLIP FLOP NON-INVERTING (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS; 八路D型触发器非反相（ 3 -STATE ） ，容许5V输入和输出
| 型号： | 74LCX574TTR |
| 厂家： | 
ST |
| 描述： | OCTAL D-TYPE FLIP FLOP NON-INVERTING (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS |
| 文件： | 总13页 (文件大小：268K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LCX574
OCTAL D-TYPE FLIP FLOP NON-INVERTING (3-STATE)
WITH 5V TOLERANT INPUTS AND OUTPUTS
■
■
5V TOLERANT INPUTS AND OUTPUTS
HIGH SPEED:
f
= 150 MHz (MIN.) at V = 3V
MAX
CC
■
■
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
SOP
TSSOP
|I | = I = 24mA (MIN) at V = 3V
OH
OL
CC
■
■
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
Table 1: Order Codes
PACKAGE
t
t
PLH
PHL
■
OPERATING VOLTAGE RANGE:
(OPR) = 2.0V to 3.6V (1.5V Data
T & R
V
CC
SOP
74LCX574MTR
74LCX574TTR
Retention)
TSSOP
■
■
■
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 574
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
outputs will be set to the logic state that were
setup at the D inputs.
While the (OE) input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
MM > 200V
The Output control does not affect the internal
operation of flip flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The 74LCX574 is a low voltage CMOS OCTAL
D-TYPE FLIP FLOP with 3 STATE OUTPUT
NON-INVERTING fabricated with sub-micron
2
silicon gate and double-layer metal wiring C MOS
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to 5V
signal environment for both inputs and outputs.
These 8 bit D-Type flip-flops are controlled by a
clock input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
Figure 1: Pin Connection And IEC Logic Symbols
Rev. 5
1/13
September 2004
74LCX574
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description
Table 3: Truth Table
INPUT
PIN N°
SYMBOL
NAME AND FUNCTION
OUTPUT
1
OE
3-State Output Enable
Input (Active LOW)
OE
H
CK
D
X
X
Q
X
Z
2, 3, 4, 5, 6,
7, 8, 9
D0 to D7 Data Inputs
L
NO CHANGE
12, 13, 14,
15, 16, 17,
18, 19
Q0 to Q7 3-State Outputs
L
L
L
L
H
H
11
CK
Clock Input (LOW-to-HIGH
Edge Triggered)
X : Don’t Care
Z : High Impedance
10
20
GND
Ground (0V)
V
Positive Supply Voltage
CC
Figure 3: Logic Diagram
This logic diagram has not be used to estimate propagation delays
2/13
74LCX574
Table 4: Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
V
Supply Voltage
-0.5 to +7.0
-0.5 to +7.0
-0.5 to +7.0
V
V
CC
V
DC Input Voltage
I
V
DC Output Voltage (OFF State)
DC Output Voltage (High or Low State) (note 1)
DC Input Diode Current
V
O
V
-0.5 to V + 0.5
V
O
CC
I
- 50
- 50
mA
mA
mA
mA
mA
°C
°C
IK
I
DC Output Diode Current (note 2)
DC Output Current
OK
I
± 50
O
I
DC Supply Current per Supply Pin
DC Ground Current per Supply Pin
Storage Temperature
± 100
± 100
-65 to +150
300
CC
I
GND
T
stg
T
Lead Temperature (10 sec)
L
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) I absolute maximum rating must be observed
O
2) V < GND
O
Table 5: Recommended Operating Conditions
Symbol
Parameter
Value
Unit
V
Supply Voltage (note 1)
Input Voltage
2.0 to 3.6
0 to 5.5
0 to 5.5
V
V
CC
V
I
V
Output Voltage (OFF State)
V
O
V
Output Voltage (High or Low State)
0 to V
V
O
CC
I
I
, I
High or Low Level Output Current (V = 3.0 to 3.6V)
± 24
± 12
mA
mA
°C
ns/V
OH OL
CC
, I
High or Low Level Output Current (V = 2.7V)
OH OL
CC
T
Operating Temperature
-55 to 125
0 to 10
op
dt/dv
Input Rise and Fall Time (note 2)
1) Truth Table guaranteed: 1.5V to 3.6V
2) V from 0.8V to 2V at V = 3.0V
IN
CC
3/13
74LCX574
Table 6: DC Specifications
Test Condition
Value
Symbol
Parameter
-40 to 85 °C
Min. Max.
-55 to 125 °C
Unit
V
(V)
CC
Min.
Max.
V
High Level Input
Voltage
IH
2.0
2.0
V
V
2.7 to 3.6
V
Low Level Input
Voltage
IL
0.8
0.8
V
High Level Output
Voltage
I =-100 µA
V
-0.2
V
-0.2
2.7 to 3.6
2.7
OH
O
CC
CC
I =-12 mA
2.2
2.4
2.2
2.2
O
V
V
I =-18 mA
2.4
2.2
O
3.0
I =-24 mA
O
V
Low Level Output
Voltage
I =100 µA
2.7 to 3.6
2.7
0.2
0.4
0.2
0.4
OL
O
I =12 mA
O
I =16 mA
0.4
0.4
O
3.0
I =24 mA
0.55
0.55
O
I
Input Leakage
Current
I
V = 0 to 5.5V
2.7 to 3.6
0
± 5
± 5
µA
µA
I
I
Power Off Leakage
Current
off
V or V = 5.5V
10
10
I
O
I
High Impedance
Output Leakage
Current
OZ
V = V or V
I
IH
IL
2.7 to 3.6
± 5
± 5
µA
V
= 0 to V
O
CC
I
Quiescent Supply
Current
V = V or GND
I CC
10
10
CC
2.7 to 3.6
2.7 to 3.6
µA
µA
V or V = 3.6 to 5.5V
± 10
500
± 10
500
I
O
∆I
I
incr. per Input
V
= V - 0.6V
CC
CC
IH
CC
Table 7: Dynamic Switching Characteristics
Test Condition
Value
T = 25 °C
Symbol
Parameter
Unit
A
V
CC
(V)
Min.
Typ.
Max.
V
Dynamic Low Level Quiet
Output (note 1)
0.8
C = 50pF
OLP
L
3.3
V
V
= 0V, V = 3.3V
V
-0.8
IL
IH
OLV
1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.
4/13
74LCX574
Table 8: AC Electrical Characteristics
Test Condition
Value
-55 to 125 °C
Symbol
Parameter
-40 to 85 °C
Unit
V
C
R
t = t
CC
L
L
s
r
(V)
(pF)
(Ω)
(ns)
Min.
Max.
Min.
Max.
t
t
Propagation Delay
Time
2.7
3.0 to 3.6
2.7
1.5
1.5
1.5
9.5
8.5
9.5
1.5
1.5
1.5
9.5
8.5
9.5
PLH PHL
50
500
2.5
ns
ns
t
t
Output Enable Time
to HIGH and LOW
level
PZL PZH
50
50
50
500
500
500
2.5
2.5
2.5
3.0 to 3.6
2.7
1.5
1.5
1.5
2.5
2.5
1.5
1.5
8.5
8.5
7.5
1.5
1.5
1.5
2.5
2.5
1.5
1.5
8.5
8.5
7.5
t
t
Output Disable Time
from HIGH to LOW
level
PLZ PHZ
ns
ns
3.0 to 3.6
2.7
t
Set-Up Time, HIGH
or LOW level
(Dn to CK)
S
3.0 to 3.6
2.7
t
Hold Time, HIGH or
LOW level
(Dn to CK)
h
50
50
500
500
2.5
2.5
ns
ns
3.0 to 3.6
t
CK Pulse Width,
HIGH or LOW
2.7
3.3
3.3
3.3
3.3
W
3.0 to 3.6
f
Clock Pulse
Frequency
MAX
3.0 to 3.6
3.0 to 3.6
50
50
500
500
2.5
2.5
165
150
MHz
ns
t
Output To Output
Skew Time (note1,
2)
1.0
1.0
OSLH
OSHL
t
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
2) Parameter guaranteed by design
= | t
- t
|, t
= | t
- t
|)
OSLH
PLHm PLHn OSHL
PHLm PHLn
Table 9: Capacitive Characteristics
Test Condition
Value
T = 25 °C
Symbol
Parameter
Unit
A
V
CC
(V)
Min.
Typ.
Max.
C
Input Capacitance
V
V
= 0 to V
3.3
3.3
3.3
6
pF
pF
IN
IN
CC
CC
C
Output Capacitance
= 0 to V
12
25
OUT
IN
C
Power Dissipation Capacitance
(note 1)
f
= 10MHz
= 0 or V
CC
PD
IN
IN
pF
V
1) C is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
PD
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
flip-flop)
= C x V x f + I /8 (per
CC(opr)
PD CC IN CC
5/13
74LCX574
Figure 4: Test Circuit
TEST
SWITCH
t
t
t
, t
Open
6V
PLH PHL
, t
PZL PLZ
, t
GND
PZH PHZ
C
L
R
L
R
T
= 50 pF or equivalent (includes jig and probe capacitance)
= R1 = 500Ω or equivalent
= Z
of pulse generator (typically 50Ω)
OUT
Figure 5: Waveform - Propagation Delays, Setup And Hold Times, Maximum CK Frequency
(f=1MHz; 50% duty cycle)
6/13
74LCX574
Figure 6: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle)
Figure 7: Waveform - Pulse Width (f=1MHz; 50% duty cycle)
7/13
74LCX574
SO-20 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
MIN.
MAX.
A
A1
B
2.35
2.65
0.093
0.104
0.1
0.33
0.23
12.60
7.4
0.30
0.51
0.32
13.00
7.6
0.004
0.013
0.009
0.496
0.291
0.012
0.020
0.013
0.512
0.299
C
D
E
e
1.27
0.050
H
10.00
0.25
0.4
10.65
0.75
1.27
8°
0.394
0.010
0.016
0°
0.419
0.030
0.050
8°
h
L
k
0°
ddd
0.100
0.004
0016022D
8/13
74LCX574
TSSOP20 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
1.2
MIN.
MAX.
0.047
0.006
0.041
0.012
0.0079
0.260
0.260
0.176
A
A1
A2
b
0.05
0.8
0.15
1.05
0.30
0.20
6.6
0.002
0.031
0.007
0.004
0.252
0.244
0.169
0.004
0.039
1
0.19
0.09
6.4
c
D
6.5
6.4
0.256
0.252
E
6.2
6.6
E1
e
4.3
4.4
4.48
0.173
0.65 BSC
0.0256 BSC
K
0˚
8˚
0˚
8˚
L
0.45
0.60
0.75
0.018
0.024
0.030
A2
A
K
L
b
e
A1
E
c
D
E1
PIN 1 IDENTIFICATION
1
0087225C
9/13
74LCX574
Tape & Reel SO-20 MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
MAX.
330
MIN.
MAX.
12.992
0.519
A
C
12.8
20.2
60
13.2
0.504
0.795
2.362
D
N
T
30.4
11
1.197
0.433
0.528
0.130
0.161
0.476
Ao
Bo
Ko
Po
P
10.8
13.2
3.1
0.425
0.520
0.122
0.153
0.468
13.4
3.3
3.9
4.1
11.9
12.1
10/13
74LCX574
Tape & Reel TSSOP20 MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
MAX.
330
MIN.
MAX.
12.992
0.519
A
C
12.8
20.2
60
13.2
0.504
0.795
2.362
D
N
T
22.4
7
0.882
0.276
0.280
0.075
0.161
0.476
Ao
Bo
Ko
Po
P
6.8
6.9
0.268
0.272
0.067
0.153
0.468
7.1
1.9
4.1
12.1
1.7
3.9
11.9
11/13
74LCX574
Table 10: Revision History
Date
Revision
Description of Changes
Ordering Codes Revision - pag. 1.
15-Sep-2004
5
12/13
74LCX574
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
All other names are the property of their respective owners
© 2004 STMicroelectronics - All Rights Reserved
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13/13
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