54HC08_V02 [SS]
High Speed CMOS Logic;
| 型号： | 54HC08_V02 |
| 厂家： | 
Silicon Supplies |
| 描述： | High Speed CMOS Logic |
| 文件： | 总5页 (文件大小：456K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Speed CMOS Logic – 54HC08
Rev 1.0
07/02/19
Quad 2-Input AND Gate in bare die form
Description
Features:
The 54HC08 quad 2-input AND gate is fabricated on a
.35µm CMOS process combining high speed LSTTL
performance with CMOS low power. The device
consists of four independent 2-input AND gates with
standard push-pull outputs and performs the Boolean
function Y = A ● B or Y = A + B. Device inputs are
compatible with standard CMOS outputs; with pull-up
resistors, they are compatible with LSTTL outputs. All
inputs are protected against ESD and excess voltage
transients. The die size is significantly smaller than
industry peers due to its re-design and production using
a more advanced CMOS process.
Output Drive Capability: 10 LSTTL Loads
Low Input Current: 1µA
Outputs directly interface CMOS, NMOS and TTL
Operating Voltage Range: 2V to 6V
Function compatible with 54LS08
High Noise Immunity CMOS process
Full Military Temperature Range.
Ordering Information
Die Dimensions in µm (mils)
The following part suffixes apply:
610 (24)
No suffix - MIL-STD-883 /2010B Visual Inspection
“H” - MIL-STD-883 /2010B Visual Inspection
+ MIL-PRF-38534 Class H LAT
“K” - MIL-STD-883 /2010A Visual Inspection (Space)
+ MIL-PRF-38534 Class K LAT
LAT = Lot Acceptance Test.
For further information on LAT process flows see below.
www.siliconsupplies.com\quality\bare-die-lot-qualification
Supply Formats:
Mechanical Specification
Default – Die in Waffle Pack (400 per tray capacity)
610 x 610
Die Size (Unsawn)
µm
mils
24 x 24
Sawn Wafer on Tape – On request
85 x 85
Minimum Bond Pad Size
3.35 x 3.35
µm
mils
Unsawn Wafer – On request
350 (±20)
Die Thickness
µm
mils
Die Thickness <> 350µm(14 Mils) – On request
Assembled into Ceramic Package – On request
13.78 (±0.79)
Top Metal Composition
Back Metal Composition
Al 1%Si 1.1µm
N/A – Bare Si
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High Speed CMOS Logic – 54HC08
d
Rev 1.0
07/02/19
Pad Layout and Functions
COORDINATES (µm)
PAD
FUNCTION
5
4
3
2
1
X
Y
1
2
1A
1B
230
230
95
95
6
230
230
230
230
140
45
3
1Y
7
8
4
2A
0
5
2B
-220
-230
-230
-230
-230
-95
0
0,0
14
6
2Y
7
GND
3Y
8
-52
9
3A
-230
-230
-230
-230
-230
-45
9
10
11
12
13
10
11
12
13
14
3B
4Y
4A
95
610µm (24 mils)
4B
230
230
VCC
CONNECT CHIP BACK TO VCC OR FLOAT
Logic Diagram
Function Table
INPUTS
OUTPUT
A
B
L
Y
L
L
L
H
L
L
H
H
L
H
H
H = High level (steady state)
L = Low level (steady state)
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High Speed CMOS Logic – 54HC08
Rev 1.0
Absolute Maximum Ratings1
07/02/19
PARAMETER
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current
SYMBOL
VCC
VALUE
-0.5 to +7.0
-0.5 to VCC +0.5
-0.5 to VCC +0.5
±20
UNIT
V
VIN
V
VOUT
IIN
IOUT
ICC
V
mA
mA
mA
mW
°C
DC Output Current, per pad
±25
DC Supply Current, VCC or GND, per pad
Power Dissipation in Still Air2
±50
PD
750
Storage Temperature Range
TSTG
-65 to 150
1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may
reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method.
Recommended Operating Conditions3 (Voltages referenced to GND)
PARAMETER
SYMBOL
MIN
MAX
UNITS
Supply Voltage
VCC
2
6
V
V
DC Input or Output Voltage
VIN ,VOUT
TJ
0
VCC
Operating Temperature Range
-55
0
+125
1000
°C
VCC = 2V
tr, tf
Input Rise or Fall Times
VCC = 4.5V
VCC = 6.0V
ns
0
0
500
400
3. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken
to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be
constrained to the range GND ≤ (VIN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
DC Electrical Characteristics (Voltages Referenced to GND)
LIMITS
PARAMETER
SYMBOL
VCC
CONDITIONS
UNITS
25°C
1.5
85°C
1.5
FULL RANGE4
2.0V
3.0V
4.5V
6.0V
2.0V
3.0V
4.5V
6.0V
1.5
2.1
VOUT = 0.1V or
VCC -0.1V
│IOUT│≤ 20µA
2.1
2.1
Minimum High-Level
Input Voltage
VIH
V
3.15
4.2
3.15
4.2
3.15
4.2
0.5
0.5
0.5
VOUT = 0.1V or
VCC -0.1V
│IOUT│≤ 20µA
0.9
0.9
0.9
Maximum Low-Level
Input Voltage
VIL
V
1.35
1.8
1.35
1.8
1.35
1.8
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High Speed CMOS Logic – 54HC08
Rev 1.0
07/02/19
DC Electrical Characteristics Continued (Voltages Referenced to GND)
LIMITS
85°C
PARAMETER
SYMBOL
VCC
CONDITIONS
UNITS
25°C
1.9
FULL RANGE4
2.0V
4.5V
6.0V
1.9
4.4
5.9
1.9
4.4
5.9
VIN = VIH or VIL
│IOUT│≤ 20µA
V
4.4
5.9
VIN = VIH or VIL
│IOUT│≤ 2.4mA
Minimum High-Level
Output Voltage
3.0V
4.5V
6.0V
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
VOH
VIN = VIH or VIL
│IOUT│≤ 4.0mA
V
V
V
VIN = VIH or VIL
│IOUT│≤ 5.2mA
2.0V
4.5V
6.0V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
VIN = VIL or VIL
│IOUT│≤ 20µA
VIN = VIL or VIL
│IOUT│≤ 2.4mA
Maximum Low-Level
Output Voltage
3.0V
4.5V
6.0V
6.0V
0.26
0.26
0.26
±0.1
0.33
0.33
0.33
±1.0
0.40
0.40
0.40
±1.0
VOL
VIN = VIL or VIL
│IOUT│≤ 4.0mA
VIN = VIL or VIL
│IOUT│≤ 5.2mA
Maximum Input
Leakage Current
IIN
VIN = VCC or GND
µA
µA
Maximum Quiescent
Supply Leakage
Current
VIN = VCC or GND
IOUT = 0µA
ICC
6.0V
1
10
40
4. -55˚C ≤ TJ ≤ +125˚C
AC Electrical Characteristics5
LIMITS
PARAMETER
SYMBOL
VCC
CONDITIONS
UNITS
25°C
75
85°C
95
FULL RANGE4
2.0V
3.0V
4.5V
6.0V
2.0V
3.0V
4.5V
6.0V
110
55
Maximum Propagation
Delay, Input A or B to
Output Y
CL = 50pF,
Input
tr = tf = 6ns
30
40
tPLH, tPHL
ns
15
19
22
(Figure 1,2)
13
16
19
75
95
110
36
Maximum Output Rise
and Fall Time,
Any Output
CL = 50pF,
Input
tr = tf = 6ns
27
32
tTLH, tTHL
ns
15
19
22
(Figure 1,2)
13
16
19
5. Not production tested in die form, characterized by chip design and tested in package.
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High Speed CMOS Logic – 54HC08
Rev 1.0
AC Electrical Characteristics Continued5
24/11/17
LIMITS
85°C
PARAMETER
SYMBOL
VCC
CONDITIONS
UNITS
pF
25°C
FULL RANGE4
Maximum Input
Capacitance
CIN
-
-
-
10
10
10
TYPICAL
Power Dissipation
TJ = 25°C,
VCC =5.0V
CPD
pF
Capacitance Per Gate6
20
6. Used to determine the no-load dynamic power consumption: PD = CPD VCC2f + ICC VCC
.
Switching Waveform
Test Circuit
TEST POINT
OUTPUT
DUT
CL*
* Includes all probe and jig capacitance
Figure 1 – Propagation Delay & Output Transition Time
Figure 2
DISCLAIMER: The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to
any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Silicon Supplies Ltd
hereby disclaims any and all warranties and liabilities of any kind.
LIFE SUPPORT POLICY: Silicon Supplies Ltd components may be used in life support devices or systems only with the express written
approval of Silicon Supplies Ltd, if a failure of such components can reasonably be expected to cause the failure of that life support device or system or
to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to
support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
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