SST39WF800B-70-4C-B3KE [SST]
8 Mbit (x16) Multi-Purpose Flash; 8兆位（ X16 ）多用途闪存
| 型号： | SST39WF800B-70-4C-B3KE |
| 厂家： | 
SILICON STORAGE TECHNOLOGY, INC |
| 描述： | 8 Mbit (x16) Multi-Purpose Flash |
| 文件： | 总26页 (文件大小：862K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
Data Sheet
FEATURES:
•
•
Organized as 512K x16
Single Voltage Read and Write Operations
– 1.65-1.95V
•
Fast Erase and Word-Program
– Sector-Erase Time: 36 ms (typical)
– Block-Erase Time: 36 ms (typical)
– Chip-Erase Time: 140 ms (typical)
– Word-Program Time: 28 µs (typical)
Automatic Write Timing
– Internal VPP Generation
End-of-Write Detection
– Toggle Bit
– Data# Polling
CMOS I/O Compatibility
JEDEC Standard
– Flash EEPROM Pinouts and command sets
•
•
Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
•
•
Low Power Consumption (typical values at 5 MHz)
– Active Current: 5 mA (typical)
– Standby Current: 5 µA (typical)
•
•
•
•
Sector-Erase Capability
– Uniform 2 KWord sectors
Block-Erase Capability
– Uniform 32 KWord blocks
Fast Read Access Time
– 70 ns
•
•
•
Packages Available
– 48-ball TFBGA (6mm x 8mm)
– 48-ball WFBGA (5mm x 6mm) Micro-Package
– 48-ball XFLGA (5mm x 6mm) Micro-Package
Latched Address and Data
•
All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST39WF800B is a 512K x16 CMOS Multi-Purpose
Flash (MPF) manufactured with SST proprietary, high-per-
formance CMOS SuperFlash technology. The split-gate
cell design and thick-oxide tunneling injector attain better
reliability and manufacturability compared to alternate
approaches. The SST39WF800B writes (Program or
Erase) with a 1.65-1.95V power supply. This device con-
forms to JEDEC standard pin assignments for x16 memo-
ries.
during Erase and Program than alternative flash technolo-
gies. When programming a flash device, the total energy
consumed is a function of the applied voltage, current, and
time of application. For any given voltage range, Super-
Flash technology uses less current to program and has a
shorter erase time; therefore, the total energy consumed
during any Erase or Program operation is less than alterna-
tive flash technologies. These devices also improve flexibil-
ity while lowering the cost for program, data, and
configuration storage applications.
The SST39WF800B features high-performance Word-Pro-
gramming which provides a typical Word-Program time of
28 µsec. It uses Toggle Bit or Data# Polling to detect the
completion of the Program or Erase operation. On-chip
hardware and software data protection schemes protects
against inadvertent writes. Designed, manufactured, and
SuperFlash technology provides fixed Erase and Program
times independent of the number of Erase/Program cycles
that have occurred. Consequently, the system software or
hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
tested for
a wide spectrum of applications, the
SST39WF800B is offered with a guaranteed typical endur-
ance of 100,000 cycles. Data retention is rated at greater
than 100 years.
To meet surface mount requirements, the SST39WF800B
is offered in a 48-ball TFBGA package and a 48-ball Micro-
Package. See Figure 3 and Figure 2 for pin assignments.
The SST39WF800B is suited for applications that require
convenient and economical updating of program, configu-
ration, or data memory. It significantly improves perfor-
mance and reliability of all system applications while
lowering power consumption. It inherently uses less energy
©2007 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
S71344-00-000
1
2/07
These specifications are subject to change without notice.
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
Data Sheet
Device Operation
Sector-/Block-Erase Operation
Commands, which are used to initiate the memory opera-
tion functions of the device, are written to the device using
standard microprocessor write sequences. A command is
written by asserting WE# low while keeping CE# low. The
address bus is latched on the falling edge of WE# or CE#,
whichever occurs last. The data bus is latched on the rising
edge of WE# or CE#, whichever occurs first.
The SST39WF800B offers both Sector-Erase and Block-
Erase modes which allow the system to erase the device
on a sector-by-sector, or block-by-block, basis.
The sector architecture is based on uniform sector size of 2
KWord. Initiate the Sector-Erase operation by executing a
six-byte command sequence with Sector-Erase command
(30H) and sector address (SA) in the last bus cycle.
The Block-Erase mode is based on uniform block size of
32 KWord. Initiate the Block-Erase operation by executing
a six-byte command sequence with Block-Erase command
(50H) and block address (BA) in the last bus cycle.
Read
The Read operation of the SST39WF800B is controlled by
CE# and OE#; both have to be low for the system to obtain
data from the outputs.
The sector or block address is latched on the falling edge of
the sixth WE# pulse, while the command (30H or 50H) is
latched on the rising edge of the sixth WE# pulse. The
internal Erase operation begins after the sixth WE# pulse.
CE# is used for device selection. When CE# is high, the
chip is deselected and only standby power is consumed.
OE# is the output control and is used to gate data from the
output pins. The data bus is in high impedance state when
either CE# or OE# is high. See Figure 4.
The End-of-Erase operation can be determined using
either Data# Polling or Toggle Bit methods. See Figures 9
and 10 for timing waveforms. Any commands issued during
the Sector- or Block-Erase operation are ignored.
Word-Program Operation
The SST39WF800B is programmed on a word-by-word
basis. The sector where the word exists must be fully
erased before programming.
Chip-Erase Operation
The SST39WF800B provides a Chip-Erase operation,
which allows the user to erase the entire memory array to
the ‘1’ state. This is useful when the entire device must be
quickly erased.
Programming is accomplished in three steps:
1. Load the three-byte sequence for Software Data
Protection.
Initiate the Chip-Erase operation by executing a six-byte
command sequence with Chip-Erase command (10H) at
address 5555H in the last byte sequence.
2. Load word address and word data. During the
Word-Program operation, the addresses are
latched on the falling edge of either CE# or WE#,
whichever occurs last. The data is latched on the
rising edge of either CE# or WE#, whichever
occurs first.
The Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase
operation, the only valid read is Toggle Bit or Data# Polling.
See Table 4 for the command sequence, Figure 8 for the
timing diagram, and Figure 19 for the flowchart. Any com-
mands issued during the Chip-Erase operation are
ignored.
3. Initiate the internal Program operation after the
rising edge of the fourth WE# or CE#, whichever
occurs first. Once initiated, the Program operation
will be completed within 40 µs. See Figures 5 and
6 for WE# and CE# controlled Program operation
timing diagrams and Figure 16 for flowcharts.
During the Program operation, the only valid reads are
Data# Polling and Toggle Bit. During the internal Program
operation, the host is free to perform additional tasks. Any
commands issued during the internal Program operation
are ignored.
©2007 Silicon Storage Technology, Inc.
S71344-00-000
2/07
2
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
Data Sheet
The Toggle Bit is valid after the rising edge of fourth WE#
(or CE#) pulse for Program operation. For Sector-, Block-
or Chip-Erase, the Toggle Bit is valid after the rising edge of
sixth WE# (or CE#) pulse. See Figure 0-1 for Toggle Bit
timing diagram and Figure 17 for a flowchart.
Write Operation Status Detection
To optimize the system write cycle time, the
SST39WF800B provides two software means to detect the
completion of a Program or Erase write cycle. The software
detection includes two status bits—Data# Polling (DQ7)
and Toggle Bit (DQ6). The End-of-Write detection mode is
enabled after the rising edge of WE#, which initiates the
internal Program or Erase operation.
Data Protection
The SST39WF800B provides both hardware and software
features to protect nonvolatile data from inadvertent writes.
The completion of the nonvolatile Write is asynchronous
with the system; therefore, either a Data# Polling or Toggle
Bit read may occur simultaneously with the completion of
the Write cycle. If this occurs, the system may get an erro-
neous result, i.e., valid data may appear to conflict with
either DQ7 or DQ6. To prevent spurious rejection in the
event of an erroneous result, the software routine must
include a loop to read the accessed location an additional
two (2) times. If both Reads are valid, then the device has
completed the Write cycle, otherwise the rejection is valid.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.0V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Data# Polling (DQ7)
Software Data Protection (SDP)
When the SST39WF800B is in the internal Program oper-
ation, any attempt to read DQ7 will produce the comple-
ment of the true data. Once the Program operation is
complete, DQ7 will produce true data.
The SST39WF800B provides the JEDEC approved Soft-
ware Data Protection scheme for all data alteration opera-
tions, i.e., Program and Erase. Any Program operation
requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. This group of devices are shipped with
the Software Data Protection permanently enabled. See
Table 4 for the specific software command codes. During
SDP command sequence, invalid commands will abort the
device to Read mode within TRC. The contents of DQ15-
DQ8 can be VIL or VIH, but no other value, during any SDP
command sequence.
Although DQ7 may have valid data immediately following
the completion of an internal Write operation, the remain-
ing data outputs may still be invalid. Valid data on the
entire data bus will appear in subsequent successive
Read cycles after an interval of 1 µs. During an internal
Erase operation, any attempt to read DQ7 will produce a
‘0’. Once the internal Erase operation is complete, DQ7 will
produce a ‘1’.
The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block-, or Chip-Erase, the Data# Polling is valid after the
rising edge of sixth WE# (or CE#) pulse. See Figure 7 for
Data# Polling timing diagram and Figure 17 for a flowchart.
Common Flash Memory Interface (CFI)
The SST39WF800A contains the CFI information that
describes the characteristics of the device, and supports
both the original SST CFI Query mode implementation for
compatibility with existing SST devices, as well as the gen-
eral CFI Query mode.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating ‘1’s
and ‘0’s, i.e., toggling between ‘1’ and ‘0’.
When the Program or Erase operation is complete, the
DQ6 bit will stop toggling and the device is ready for the
next operation.
To enter the SST CFI Query mode, the system must write
the three-byte sequence, same as the Product ID Entry
command, with 98H (CFI Query command) to address
5555H in the last byte sequence.
©2007 Silicon Storage Technology, Inc.
S71344-00-000
2/07
3
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
Data Sheet
To enter the general CFI Query mode, the system must
write a one-byte sequence using the Entry command with
98H to address 55H.
Product Identification Mode Exit/
CFI Mode Exit
To return to the standard Read mode, exit the Software
Product Identification mode. Issue the Software ID Exit
command sequence which returns the device to the Read
mode.
Once the device enters the CFI Query mode, the system
can read CFI data at the addresses given in Tables 5
through 7. The system must write the CFI Exit command to
return to Read mode from the CFI Query mode.
The Software ID Exit command may also be used to reset
the device to the Read mode after any inadvertent transient
condition that causes the device to behave abnormally,
e.g., not read correctly.
Product Identification
The Product Identification mode identifies the device as the
SST39WF800B and manufacturer as SST. This mode is
accessed by software operations. Use Software Product
Identification operation to identify the part (i.e., using the
device ID) when using multiple manufacturers in the same
socket. For details, see Table 4 for software operation,
Figure 11 for the Software ID Entry and Read timing
diagram, and Figure 18 for the Software ID Entry
command sequence flowchart.
The Software ID Exit/CFI Exit command is ignored during
an internal Program or Erase operation. See Table 4 for
software command codes, Figure 13 for timing waveform,
and Figure 18 for a flowchart.
TABLE 1: Product Identification Table
Address
Data
Manufacturer’s ID
Device ID
0000H
00BFH
SST39WF800B
0001H
273EH
T1.0 1344
©2007 Silicon Storage Technology, Inc.
S71344-00-000
2/07
4
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
Data Sheet
SuperFlash
Memory
X-Decoder
Memory Address
Address Buffer & Latches
Y-Decoder
CE#
OE#
WE#
I/O Buffers and Data Latches
Control Logic
DQ - DQ
15
0
1344 B1.0
FIGURE 1: Functional Block Diagram
TOP VIEW (balls facing down)
SST39WF800B
6
A2
A1
A0
A4
A3
A6
A7
A17 NC
NC
NC WE# NC
NC A10 A13 A14
A8 A12 A15
A9
A11
5
4
3
2
1
A5 A18
CE# DQ8 DQ10
OE# DQ9 NC
DQ0 DQ1 DQ2 DQ3
DQ4 DQ11 A16
V
SS
NC DQ5 DQ6 DQ7
V
DD
DQ12 DQ13 DQ14 DQ15 V
SS
A B C D E F G H J K L
1344 48-wfbga M2Q P02.0
FIGURE 2: Pin Assignments for 48-Ball WFBGA and 48-Ball XFLGA
©2007 Silicon Storage Technology, Inc.
S71344-00-000
2/07
5
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
Data Sheet
TOP VIEW (balls facing down)
SST39WF800B
6
5
4
3
2
1
A12 A14 A15 A16 NC
A8 A10 A11 DQ7 DQ14
A13
A9
DQ15
V
SS
DQ13 DQ6
NC
NC
NC DQ5 DQ12
V
WE#
NC
DQ4
DD
NC A18 NC DQ2 DQ10
DQ11 DQ3
A5 DQ0 DQ8
DQ9 DQ1
A17 A6
A7
A4
A2
A1
A0
CE#
A3
OE#
V
SS
A
B
C
D
E
F
G
H
1344 48-tfbga P01.0
FIGURE 3: Pin Assignments for 48-ball TFBGA
TABLE 2: Pin Description
Symbol
Pin Name
Functions
AMS1-A0
Address Inputs
To provide memory addresses. During Sector-Erase AMS-A11 address lines will select the
sector. During Block-Erase AMS-A15 address lines will select the block.
DQ15-DQ0
Data Input/output
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
CE#
OE#
WE#
VDD
VSS
NC
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide power supply voltage:
1.65-1.95V for SST39WF800B
No Connection
Unconnected pins.
T2.0 1344
1. AMS = Most significant address
AMS = A18 for SST39WF800B
TABLE 3: Operation Modes Selection
Mode
Read
CE#
VIL
OE#
VIL
WE#
VIH
VIL
DQ
DOUT
DIN
X1
Address
AIN
Program
Erase
VIL
VIH
VIH
AIN
VIL
VIL
Sector or Block address,
XXH for Chip-Erase
Standby
VIH
X
X
VIL
X
X
X
High Z
X
X
X
Write Inhibit
High Z/ DOUT
High Z/ DOUT
X
VIH
Product Identification
Software Mode
VIL
VIL
VIH
See Table 4
T3.0 1344
1. X can be VIL or VIH, but no other value.
©2007 Silicon Storage Technology, Inc.
S71344-00-000
2/07
6
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
Data Sheet
TABLE 4: Software Command Sequence
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2
5555H AAH 2AAAH 55H 5555H A0H Data
WA3
Word-Program
Sector-Erase
Block-Erase
Chip-Erase
4
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H
SAX
BAX
30H
50H
4
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Software ID Entry5,6 5555H AAH 2AAAH 55H 5555H 90H
SST CFI Query
Entry5
5555H AAH 2AAAH 55H 5555H 98H
General CFI Query
Mode
Software ID Exit7/
CFI Exit
55H
98H
F0H
XXH
Software ID Exit7/
CFI Exit
5555H AAH 2AAAH 55H 5555H F0H
T4.0 1344
1. Address format A14-A0 (Hex), Addresses AMS-A15 can be VIL or VIH, but no other value, for the Command sequence.
A
A
MS = Most significant address
MS = A18 for SST39WF800B
2. DQ15-DQ8 can be VIL or VIH, but no other value, for the Command sequence
3. WA = Program word address
4. SAX for Sector-Erase; uses AMS-A11 address lines
BAX for Block-Erase; uses AMS-A15 address lines
5. The device does not remain in Software Product ID mode if powered down.
6. With AMS-A1 = 0; SST Manufacturer’s ID = 00BFH, is read with A0 = 0,
SST39WF800B Device ID = 273EH, is read with A0 = 1.
7. Both Software ID Exit operations are equivalent
TABLE 5: CFI Query Identification String1 for SST39WF800B
Address
10H
11H
12H
13H
14H
15H
16H
17H
Data
Data
0051H
0052H
0059H
0001H
0007H
0000H
0000H
0000H
0000H
0000H
0000H
Query Unique ASCII string “QRY”
Primary OEM command set
Address for Primary Extended Table
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
18H
19H
1AH
T5.0 1344
1. Refer to CFI publication 100 for more details.
©2007 Silicon Storage Technology, Inc.
S71344-00-000
2/07
7
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
Data Sheet
TABLE 6: System Interface Information for SST39WF800B
Address
Data
Data
1BH
0016H
VDD Min (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1CH
0020H
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
0000H
0000H
0005H
0000H
0005H
0007H
0001H
0000H
0001H
0001H
V
PP min (00H = no VPP pin)
VPP max (00H = no VPP pin)
Typical time out for Word-Program 2N µs (25 = 32 µs)
Typical time out for min size buffer program 2N µs (00H = not supported)
Typical time out for individual Sector/Block-Erase 2N ms (25 = 32 ms)
Typical time out for Chip-Erase 2N ms (27 = 128 ms)
Maximum time out for Word-Program 2N times typical (21 x 25 = 64 µs)
Maximum time out for buffer program 2N times typical
Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 25 = 64 ms)
Maximum time out for Chip-Erase 2N times typical (21 x 27 = 256 ms)
T6.0 1344
T7.0 1344
2/07
TABLE 7: Device Geometry Information for SST39WF800B
Address
27H
28H
Data
Data
0014H
0001H
0000H
0000H
0000H
0002H
00FFH
0000H
0010H
0000H
000FH
0000H
0000H
0001H
Device size = 2N Byte (14H = 20; 220 = 1 MByte)
Flash Device Interface description; 0001H = x16-only asynchronous interface
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
Maximum number of byte in multi-byte write = 2N (00H = not supported)
Number of Erase Sector/Block sizes supported by device
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
y = 255 + 1 = 256 sectors (00FFH = 255)
z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)
Block Information (y + 1 = Number of blocks; z x 256B = block size)
y = 15 + 1 = 16 blocks (000FH = 15)
z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
©2007 Silicon Storage Technology, Inc.
S71344-00-000
8
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
Data Sheet
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 11V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.
Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest information.
2. Outputs shorted for no more than one second. No more than one output shorted at a time.
Operating Range
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Industrial
1.65-1.95V
1.65-1.95V
-40°C to +85°C
AC Conditions of Test
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 14 and 15
©2007 Silicon Storage Technology, Inc.
S71344-00-000
2/07
9
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
Data Sheet
TABLE 8: DC Operating Characteristics, VDD = 1.65-1.95V1
Limits
Symbol
Parameter
Min
Max
Units
Test Conditions
IDD
Power Supply Current
Address input=VILT/VIHT, at f=5 MHz,
VDD=VDD Max
Read
15
20
mA
mA
µA
µA
µA
CE#=VIL, OE#=WE#=VIH, all I/Os open
CE#=WE#=VIL, OE#=VIH
CE#=VDD, VDD=VDD Max
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
Program and Erase
Standby VDD Current2
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
ISB
ILI
40
1
ILO
VIL
VIH
VOL
VOH
1
0.2VDD
0.8VDD
V
V
V
VDD=VDD Max
0.1
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
VDD-0.1
T8.0 1344
1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C
(room temperature), and VDD = 1.8V. Not 100% tested.
2. 40 µA is the maximum ISB for all SST39WF800B commercial grade devices. 40 µA is the maximum ISB for all 39WF800A industrial
grade devices. For all SST39WF800B commercial and industrial devices, ISB typical is under 5 µA.
TABLE 9: Recommended System Power-up Timings
Symbol
Parameter
Minimum
100
Units
µs
1
TPU-READ
Power-up to Read Operation
Power-up to Program/Erase Operation
1
TPU-WRITE
100
µs
T9.0 1344
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: Capacitance (TA = 25°C, f=1 MHz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
1
CI/O
I/O Pin Capacitance
Input Capacitance
12 pF
6 pF
1
CIN
VIN = 0V
T10.0 1344
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11: Reliability Characteristics
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Cycles
Years
mA
Test Method
1,2
NEND
10,000
100
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard 78
1
TDR
1
ILTH
100 + IDD
T11.0 1344
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a
higher minimum specification.
©2007 Silicon Storage Technology, Inc.
S71344-00-000
2/07
10
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
Data Sheet
AC CHARACTERISTICS
TABLE 12: Read Cycle Timing Parameters
70 ns
Symbol
TRC
Parameter
Min
Max
Units
ns
Read Cycle Time
70
TCE
Chip Enable Access Time
Address Access Time
70
70
35
ns
TAA
ns
TOE
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
ns
1
TCLZ
0
0
ns
1
TOLZ
ns
1
TCHZ
40
40
ns
1
TOHZ
ns
1
TOH
0
ns
T12.0 1344
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 13: Program/Erase Cycle Timing Parameters
Symbol
TBP
Parameter
Min
Max
Units
µs
Word-Program Time
Address Setup Time
Address Hold Time
WE# and CE# Setup Time
WE# and CE# Hold Time
OE# High Setup Time
OE# High Hold Time
CE# Pulse Width
40
TAS
0
50
0
ns
TAH
ns
TCS
ns
TCH
0
ns
TOES
TOEH
TCP
0
ns
10
50
50
30
30
50
0
ns
ns
TWP
WE# Pulse Width
ns
1
TWPH
WE# Pulse Width High
CE# Pulse Width High
Data Setup Time
ns
1
TCPH
ns
TDS
ns
1
TDH
Data Hold Time
ns
1
TIDA
Software ID Access and Exit Time
Sector-Erase
150
50
ns
TSE
ms
ms
ms
TBE
Block-Erase
50
TSCE
Chip-Erase
200
T13.0 1344
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2007 Silicon Storage Technology, Inc.
S71344-00-000
2/07
11
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
Data Sheet
T
T
AA
RC
ADDRESS A
MS-0
T
CE
CE#
T
OE
OE#
WE#
T
OHZ
T
OLZ
V
IH
T
T
T
CHZ
OH
CLZ
HIGH-Z
HIGH-Z
DQ
15-0
DATA VALID
DATA VALID
1344 F03.0
Note: AMS = Most significant address
MS = A18 for SST39WF800B
A
FIGURE 4: Read Cycle Timing Diagram
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
MS-0
T
AH
T
DH
T
WP
WE#
OE#
T
T
WPH
DS
T
AS
T
CH
CE#
T
CS
DQ
15-0
XXAA
SW0
XX55
SW1
XXA0
SW2
DATA
WORD
(ADDR/DATA)
1344 F04.0
Note: AMS = Most significant address
MS = A18 for SST39WF800B
X can be VIL or VIH, but no other value.
A
FIGURE 5: WE# Controlled Program Cycle Timing Diagram
©2007 Silicon Storage Technology, Inc.
S71344-00-000
2/07
12
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
Data Sheet
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
MS-0
T
AH
T
DH
T
CP
CE#
OE#
WE#
T
T
DS
CPH
T
AS
T
CH
T
CS
DQ
15-0
XXAA
SW0
XX55
SW1
XXA0
SW2
DATA
WORD
(ADDR/DATA)
1344 F05.0
Note: AMS = Most significant address
MS = A18 for SST39WF800B
X can be VIL or VIH, but no other value.
A
FIGURE 6: CE# Controlled Program Cycle Timing Diagram
ADDRESS A
MS-0
T
CE
CE#
OE#
WE#
T
T
OEH
OES
T
OE
DQ
7
DATA
DATA#
DATA#
DATA
1344 F06.0
Note: AMS = Most significant address
MS = A18 for SST39WF800B
A
FIGURE 7: Data# Polling Timing Diagram
©2007 Silicon Storage Technology, Inc.
S71344-00-000
2/07
13
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
Data Sheet
ADDRESS A
MS-0
T
CE
CE#
OE#
WE#
T
T
OES
OEH
T
OE
DQ
6
TWO READ CYCLES
WITH SAME OUTPUTS
1344 F07.0
Note: AMS = Most significant address
MS = A18 for SST39WF800B
A
FIGURE
0-1: Toggle Bit Timing Diagram
T
SIX-BYTE CODE FOR CHIP-ERASE
SCE
5555
2AAA
5555
5555
2AAA
5555
ADDRESS A
MS-0
CE#
OE#
WE#
T
WP
DQ
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX10
SW5
1344 F08.0
Note: This device also supports CE# controlled Chip-Erase operation The WE# and CE# signals are interchange-
able as long as minimum timings are met. (See Table 13)
A
A
MS = Most significant address
MS = A18 for SST39WF800B
X can be VIL or VIH, but no other value.
FIGURE 8: WE# Controlled Chip-Erase Timing Diagram
©2007 Silicon Storage Technology, Inc.
S71344-00-000
2/07
14
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
Data Sheet
T
SIX-BYTE CODE FOR BLOCK-ERASE
BE
5555
2AAA
5555
5555
2AAA
BA
X
ADDRESS A
MS-0
CE#
OE#
WE#
T
WP
DQ
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX50
SW5
1344 F09.0
Note: This device also supports CE# controlled Block-Erase operation The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 13)
A
A
MS = Most significant address
MS = A18 for SST39WF800B
X can be VIL or VIH, but no other value.
FIGURE 9: WE# Controlled Block-Erase Timing Diagram
T
SE
SIX-BYTE CODE FOR SECTOR-ERASE
5555
2AAA
5555
5555
2AAA
SA
X
ADDRESS A
MS-0
CE#
OE#
WE#
T
WP
DQ
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX30
SW5
1344 F10.0
Note: This device also supports CE# controlled Sector-Erase operation The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 13)
AMS = Most significant address
A
MS = A18 for SST39WF800B
X can be VIL or VIH, but no other value.
FIGURE 10: WE# Controlled Sector-Erase Timing Diagram
©2007 Silicon Storage Technology, Inc.
S71344-00-000
2/07
15
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID ENTRY
ADDRESS A
5555
2AAA
5555
0000
0001
14-0
CE#
OE#
WE#
T
T
IDA
WP
T
T
AA
WPH
DQ
15-0
XXAA
SW0
XX55
SW1
XX90
SW2
00BF
Device ID
1344 F11.0
Note: Device ID = 273FH for SST39WF800B
X can be VIL or VIH, but no other value.
FIGURE 11: Software ID Entry and Read
THREE-BYTE SEQUENCE FOR
SST CFI QUERY ENTRY
ADDRESS A
5555
2AAA
5555
14-0
CE#
OE#
WE#
T
T
WP
IDA
T
T
AA
WPH
DQ
15-0
XXAA
SW0
XX55
SW1
XX98
SW2
1344 F12.0
Note: X can be VIL or VIH, but no other value.
FIGURE 12: SST CFI Query Entry and Read
©2007 Silicon Storage Technology, Inc.
S71344-00-000
2/07
16
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
5555
2AAA
5555
ADDRESS A
DQ
14-0
XXAA
XX55
XXF0
15-0
T
IDA
CE#
OE#
T
T
WP WHP
WE#
SW0
SW1
SW2
1344 F13.0
Note: X can be VIL or VIH, but no other value.
FIGURE 13: Software ID Exit/CFI Exit
©2007 Silicon Storage Technology, Inc.
S71344-00-000
2/07
17
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
Data Sheet
V
IHT
V
V
INPUT
REFERENCE POINTS
OUTPUT
OT
IT
V
ILT
1344 F14.0
AC test inputs are driven at VIHT (VDD) for a logic ‘1’ and VILT (VSS) for a logic ‘0’. Measurement reference points for inputs
and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times are (10% ↔ 90%) <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
V
V
IHT - VINPUT HIGH Test
ILT - VINPUT LOW Test
FIGURE 14: AC Input/Output Reference Waveforms
V
DD
TO TESTER
25KΩ
TO DUT
C
L
25KΩ
1344 F15.0
FIGURE 15: A Test Load Example
©2007 Silicon Storage Technology, Inc.
S71344-00-000
2/07
18
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
Data Sheet
Start
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XXA0H
Address: 5555H
Load Word
Address/Word
Data
Wait for end of
Program (T
Data# Polling
,
BP
bit, or Toggle bit
operation)
Program
Completed
Note:
X can be V or V , but no other value.
IL IH
1344 F16.0
FIGURE 16: Word-Program Algorithm
©2007 Silicon Storage Technology, Inc.
S71344-00-000
2/07
19
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
Data Sheet
Toggle Bit
Data# Polling
Internal Timer
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Read DQ
7
Read word
Wait T
,
BP
T
T
SCE, SE
or T
BE
Read same
word
Is DQ =
7
No
true data?
Program/Erase
Completed
Yes
No
Does DQ
match?
Program/Erase
Completed
6
Yes
Program/Erase
Completed
1344 F17.0
FIGURE 17: Wait Options
©2007 Silicon Storage Technology, Inc.
S71344-00-000
2/07
20
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
Data Sheet
CFI Query Entry
Command Sequence
Software ID Entry
Command Sequence
Software ID Exit/CFI Exit
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXF0H
Address: XXH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Wait T
IDA
Load data: XX98H
Address: 5555H
Load data: XX90H
Address: 5555H
Load data: XXF0H
Address: 5555H
Return to normal
operation
Wait T
Wait T
Wait T
IDA
IDA
IDA
Return to normal
operation
Read CFI data
Read Software ID
Note:
X can be V or V , but no other value.
IL IH
1344 F18.0
FIGURE 18: Software ID/CFI Command Flowcharts
©2007 Silicon Storage Technology, Inc.
S71344-00-000
2/07
21
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
Data Sheet
Chip-Erase
Sector-Erase
Block-Erase
Command Sequence
Command Sequence
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX10H
Address: 5555H
Load data: XX30H
Load data: XX50H
Address: SA
Address: BA
X
X
Wait T
Wait T
Wait T
BE
SCE
SE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
Note:
X can be V or V , but no other value.
IL IH
1344 F19.0
FIGURE 19: Erase Command Sequence
©2007 Silicon Storage Technology, Inc.
S71344-00-000
2/07
22
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
Data Sheet
PRODUCT ORDERING INFORMATION
SST 39 WF 800B
-
70
-
4C
-
B3K
E
XX XX XXXX
-
XX
-
XX - XXX
X
Environmental Attribute
E1 = non-Pb
Package Modifier
K = 48 balls
Q = 48 balls (66 possible positions)
Package Type
B3 = TFBGA (0.8mm pitch, 6mm x 8mm)
M2 = WFBGA (0.5mm pitch, 5mm x 6mm)
C2 = XFLGA (0.5mm pitch, 5mm x 6mm)
MB = WFBGA (0.5mm pitch, 5mm x 6mm)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
Device Density
800 = 8 Mbit
Voltage
W = 1.65-1.95V
Product Series
39 = Multi-Purpose Flash
1. Environmental suffix “E” denotes non-Pb solder.
SST non-Pb solder devices are “RoHS Compliant”.
Valid combinations for SST39WF800B
SST39WF800B-70-4C-B3KE
SST39WF800B-70-4I-B3KE
SST39WF800B-70-4C-M2QE
SST39WF800B-70-4I-M2QE
SST39WF800B-70-4C-C2QE
SST39WF800B-70-4I-C2QE
SST39WF800B-70-4C-MBQE
SST39WF800B-70-4I-MBQE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2007 Silicon Storage Technology, Inc.
S71344-00-000
2/07
23
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
Data Sheet
PACKAGING DIAGRAMS
TOP VIEW
BOTTOM VIEW
5.60
8.00 0.20
0.45 0.05
0.80
(48X)
6
5
4
3
2
1
6
5
4
3
2
1
4.00
0.80
6.00 0.20
A
B C D E F G H
H
G F E D C B A
A1 CORNER
A1 CORNER
1.10 0.10
SIDE VIEW
0.12
SEATING PLANE
1mm
0.35 0.05
Note:
1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm ( 0.05 mm)
48-tfbga-B3K-6x8-450mic-4
FIGURE 20: 48-Ball Thin-Profile, Fine-Pitch Ball Grid Array (TFBGA) 6mm x 8mm
SST Package Code: B3K
TOP VIEW
BOTTOM VIEW
6.00 0.08
5.00
0.50
0.29 0.05
(48X)
6
5
4
3
2
1
6
5
4
3
2
1
5.00 0.08
2.50
0.50
A B C D E F G H J K L
L K J H G F E D C B A
A1 CORNER
A1 INDICATOR4
0.52 max.
0.473 nom.
DETAIL
SIDE VIEW
0.08
SEATING PLANE
0.04 + 0.025/ - 0.015
1mm
Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-222,
this specific package is not registered.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.08 mm
4. No bump is present in position A1; a gold-colored indicator is present.
48-xflga-C2Q-5x6-29mic-NR
FIGURE 21: 48-Ball Extremely Thin-Profile, Fine-Pitch Land Grid Array (XFLGA) 5mm x 6mm
SST Package Code: C2Q
©2007 Silicon Storage Technology, Inc.
S71344-00-000
2/07
24
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
Data Sheet
TOP VIEW
BOTTOM VIEW
6.00 0.08
5.00
0.50
0.32 0.05
(48X)
6
5
4
3
2
1
6
5
4
3
2
1
5.00 0.08
2.50
0.50
A B C D E F G H J K L
L K J H G F E D C B A
A1 CORNER
A1 INDICATOR4
0.63 0.10
DETAIL
SIDE VIEW
0.08
SEATING PLANE
0.20 0.06
1mm
Note:
1. Although many dimensions are similar to those of JEDEC Publication 95, MO-225, this specific package is not registered.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.08 mm
4. No ball is present in position A1; a gold-colored indicator is present.
5. Ball opening size is 0.29 mm ( 0.05 mm)
48-wfbga-M2Q-5x6-32mic-0
FIGURE 22: 48-Ball Very-Very-Thin-Profile, Fine-Pitch Ball Grid Array (WFBGA) 5mm x 6mm
SST Package Code: M2Q
TOP VIEW
BOTTOM VIEW
6.00 0.08
5.00
0.50
0.32 0.05
(48X)
6
5
4
3
2
1
6
5
4
3
2
1
5.00 0.08
2.50
0.50
A B C D E F G H J K L
L K J H G F E D C B A
A1 CORNER
A1 INDICATOR
0.73 max.
0.636 nom.
DETAIL
SIDE VIEW
0.08
SEATING PLANE
0.20 0.06
1mm
Note:
1. Although many dimensions are similar to those of JEDEC Publication 95, MO-225,
this specific package is not registered.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.08 mm
4. Ball opening size is 0.29 mm ( 0.05 mm)
48-wfbga-MBQ-5x6-32mic-0
FIGURE 23: 48-ball Very-very-thin-profile, Fine-pitch Ball Grid Array (WFBGA) 5mm x 6mm
SST Package Code MBQ
©2007 Silicon Storage Technology, Inc.
S71344-00-000
2/07
25
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
Data Sheet
TABLE 14: Revision History
Number
Description
Date
00
Feb 2007
•
Initial release of data sheet
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2007 Silicon Storage Technology, Inc.
S71344-00-000
2/07
26
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