SS13L [SSC]
Schottky Barrier Rectifiers; 肖特基势垒整流器器型号: | SS13L |
厂家: | SILICON STANDARD CORP. |
描述: | Schottky Barrier Rectifiers |
文件: | 总3页 (文件大小:230K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SS12L thru SS115L
Schottky Barrier Rectifiers
PRODUCT SUMMARY
1.0 Amp. Surface Mount
FEATURES
Sub SMA
For surface mounted application
Low-Profile Package
Ideal for automated pick & place
Low power loss, high efficiency ꢀ
High current capability, low VF ꢀ
High surge current capability
Plastic material used carriers Underwriters
Laboratory Classification 94V-0 ꢀ
Epitaxial construction
High temperature soldering: 260 oC / 10 seconds at
terminals
MECHANICAL DATA
Dimensions in inches and (millimeters)
Cases: Sub SMA plastic case ꢀ
Terminal : Pure tin plated, lead free. ꢀ
Polarity: Color band denotes cathode end
Packaging: 12mm tape per EIA STD RS-481
Weight approx. 15mg
Pb-free; RoHS-compliant
08/22/2007 Rev.1.00
www.SiliconStandard.com
1
SS12L thru SS115L
MAXIMUM RATINGS AND ELECTRICAL CHARACTERISTICS
Rating at 25 oC ambient temperature unless otherwise specified.
Single phase, half wave, 60 Hz, resistive or inductive load.
For capacitive load, de-rate current by 20%
Symbol SS SS
SS SS
SS
SS SS
SS
Units
Type Number
12L 13L 14L 15L 16L 19L 110L 115L
Maximum Recurrent Peak
Reverse Voltage
20
14
20
30
21
30
40
28
40
50
35
50
60
42
60
90 100 150
63 70 105
90 100 150
V
V
V
VRRM
VRMS
VDC
Maximum RMS Voltage
Maximum DC Blocking Voltage
Marking Code (Note 2)
12LYM 13LYM 14LYM 15LYM 16LYM 19LYM 10LYM A5LYM
Maximum Average Forward Rectified
Current
1.0
A
A
I(AV)
Peak Forward Surge Current, 8.3 ms
Single Half Sine-wave Superimposed on
Rated Load (JEDEC method )
Maximum Instantaneous Forward Voltage
30
IFSM
(Note 1)
@ 0.5A
@ 1.0A
0.385 0.43 0.51
0.45 0.50 0.55
0.58
0.70
V
0.65
0.80
0.75
0.90
VF
Maximum DC Reverse Current
o
@ TA =25 C at Rated DC Blocking
o
0.4
0.05
0.5
mA
mA
IR
Voltage @ TA=100 C
8.0
6.0
Maximum Thermal Resistance (Note 3)
R
100
45
o
θJA
C/
W
R
θJL
o
Operating Temperature Range
Storage Temperature Range
TJ
-55 to +150
-55 to + 150
C
o
TSTG
C
Notes:
1. Pulse Test with PW=300 usec, 1% Duty Cycle.
2. 12LYM: 1-1A, 2-20V, L-Low Profile, Y-Year Code, M-Month Code.
3. Measured on P.C.Board with 0.2” x 0.2” (5.0mm x 5.0mm) Copper Pad Areas.
08/22/2007 Rev.1.00
www.SiliconStandard.com
2
SS12L thru SS115L
RATINGS AND CHARACTERISTIC CURVES
FIG.2- MAXIMUM NON-REPETITIVE FORWARD
SURGE CURRENT
FIG.1- MAXIMUM FORWARD CURRENT DERATING
CURVE
100
50
1.2
1.0
0.8
0.6
0.4
0.2
0
20
10
5
8.3ms Single
Half Sine Wave
Tj=Tj max
2
1
0
20
40
60
80
100
120
140
160
1
2
5
10
20
50
100
LEAD TEMPERATURE. (oC)
NUMBER OF CYCLES AT 60Hz
FIG.4- TYPICAL REVERSE CHARACTERISTICS
FIG.3- TYPICAL FORWARD CHARACTERISTICS
100
50
10,000
1,000
100
10
SS15L-SS16L
SS13L-SS14L
20
10
5
SS12L
2
1
SS115L
0.5
0.2
0.1
SS19L-SS110L
1
0.05
0.02
0.01
0.1
0
20
40
60
80
100
120
140
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
PERCENT OF RATED PEAK REVERSE VOLTAGE. (%)
FORWARD VOLTAGE. (V)
FIG.6- TYPICAL TRANSIENT THERMAL
CHARACTERISTICS
FIG.5- TYPICAL JUNCTION CAPACITANCE
100
50
100
Tj=25OC
f=1.0MHz
Vsig=50mVp-p
20
10
10
5
1
2
1
0.1
0.1
1.0
10
100
1000
0.01
0.1
1
10
100
T, PULSE DURATION. (sec)
REVERSE VOLTAGE. (V)
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
08/22/2007 Rev.1.00
www.SiliconStandard.com
3
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