SL2309ZI-1 [SPECTRALINEAR]
Low Jitter and Skew 10 to 140MHz Zero Delay Buffer (ZDB); 低抖动和偏斜10到140MHz的零延迟缓冲器（ ZDB ）
| 型号： | SL2309ZI-1 |
| 厂家： | 
SPECTRALINEAR INC |
| 描述： | Low Jitter and Skew 10 to 140MHz Zero Delay Buffer (ZDB) |
| 文件： | 总12页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SL2309
Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer (ZDB)
Key Features
Description
x
x
x
10 to 140 MHz operating frequency range
Low output clock skew: 50ps-typ
Low output clock jitter:
The SL2309 is a low skew, low jitter and low power Zero
Delay Buffer (ZDB) designed to produce up to nine (9)
clock outputs from one (1) reference input clock, for high
speed clock distribution applications.
50 ps-typ cycle-to-cycle jitter
The product has an on-chip PLL which locks to the input
clock at CLKIN and receives its feedback internally from
the CLKOUT pin.
x
x
x
Low part-to-part output skew: 150 ps-typ
3.3 V power supply range
Low power dissipation:
The SL2309 has two (2) clock driver banks each with four
(4) clock outputs. These outputs are controlled by two (2)
select input pins S1 and S2. When only four (4) outputs
are needed, four (4) bank-B output clock buffers can be tri-
stated to reduce power dissipation and jitter. The select
inputs can also be used to tri-state both banks A and B or
drive them directly from the input bypassing the PLL and
making the product behave like a Non-Zero Delay Buffer
(NZDB).
28 mA-max at 66 MHz
44 mA –max at 140 MHz
x
x
x
x
x
x
One input drives 9 outputs organized as 4+4+1
Select mode to bypass PLL or tri-state outputs
SpreadThru™ PLL that allows use of SSCG
Standard and High-Drive options
Available in 16-pin SOIC and TSSOP packages
Available in Commercial and Industrial grades
The high-drive (-1H) version operates up to 140MHz and
low drive (-1) version operates up to 100MHz at 3.3V.
Applications
x
x
x
x
x
x
Printers and MFPs
Benefits
Digital Copiers
x
x
Up to nine (9) distribution of input clock
PCs and Work Stations
DTV
Standard and High-Dirive levels to control impedance
level, frequency range and EMI
Routers, Switchers and Servers
Digital Embeded Systems
x
x
Low power dissipation, jitter and skew
Low cost
Block Diagram
Low Power and
Low Jitter
PLL
MUX
CLKOUT
CLKIN
CLKA1
CLKA2
CLKA3
CLKA4
S2
S1
Input Selection
Decoding Logic
CLKB1
CLKB2
CLKB3
CLKB4
2
2
VDD
GND
Rev 1.1, May 29, 2007
Page 1 of 12
2200 Laurelwood Road, Santa Clara, CA 95054 Tel: (408) 855-0555 Fax: (408) 855-0550 www.SpectraLinear.com
SL2309
Pin Configuration
16-Pin SOIC and TSSOP
Pin Description
Pin
Number
Pin Name
Pin Type
Pin Description
1
CLKIN
Input
Reference Frequency Clock Input. Weak pull-down (250kȍ).
2
3
CLKA1
CLKA2
VDD
Output
Output
Power
Power
Output
Output
Input
Buffered Clock Output, Bank A. Weak pull-down (250kȍ).
Buffered Clock Output, Bank A. Weak pull-down (250kȍ).
3.3V Power Supply.
4
5
GND
Power Ground.
6
CLKB1
CLKB2
S2
Buffered Clock Output, Bank B. Weak pull-down (250kȍ).
Buffered Clock Output, Bank B. Weak pull-down (250kȍ).
Select Input, select pin S2. Weak pull-up (250kȍ).
Select Input, select pin S1. Weak pull-up (250kȍ).
Buffered Clock Output, Bank B. Weak pull-down (250kȍ).
Buffered Clock Output, Bank B. Weak pull-down (250kȍ).
Power Ground.
7
8
9
S1
Input
10
11
12
13
14
15
16
CLKB3
CLKB4
GND
Output
Output
Power
Power
Output
Output
Output
VDD
3.3V Power Supply.
CLKA3
CLKA4
CLKOUT
Buffered Clock Output, Bank A. Weak pull-down (250kȍ).
Buffered Clock Output, Bank A. Weak pull-down (250kȍ).
Buffered Clock Output, PLL Internal Feedback Output. Weak pull-down (250kȍ).
Rev 1.1, May 29, 2007
Page 2 of 12
SL2309
General Description
Select Input Control
The SL2309 is a low skew, low jitter Zero Delay Buffer with
very low operating current.
The SL2309 provides two (2) input select control pins
called S1 (Pin-9) and S2 (Pin-8). This feature enables
users to select various states of output clock banks-A and
bank-B, output source and PLL shutdown features as
shown in the Table 2.
The product includes an on-chip high performance PLL
that locks into the input reference clock and produces nine
(9) output clock drivers tracking the input reference clock
for systems requiring clock distribution.
The S1 (Pin-9) and S2 (Pin-8) inputs include 250 kȍ weak
pull-up resistors to VDD.
in addition to CLKOUT that is used for internal PLL
feedback, there are two (2) banks with four (4) outputs in
each bank, bringing the number of total available output
clocks to nine (9).
PLL Bypass Mode
If the S1 and S2 pins are logic Low(0) and High(1)
respectively, the on-chip PLL is shutdown and bypassed,
and all the nine output clocks bank A, bank B and
CLKOUT clocks are driven by directly from the reference
input clock. In this operation mode SL2309 works like a
non-ZDB fanout buffer. In this operation mode the input
power-down detection circuit is disabled and outputs
follow the input clock from DC to rated frequencies based
on drive levels and load specifications.
Input and Output Frequency Range
The input and output frequency range is the same. But, it
depends on the drive and CL levels as given in the below
Table 1.
Drive
CL(pF)
Min(MHz)
Max(MHz)
HIGH
15
10
140
High and Low-Drive Product Options
HIGH
LOW
LOW
30
15
30
10
10
10
100
100
66
The SL2309 is offered with High Drive “-1H” and Standard
Drive “-1” options. These drive options enable the users
to control load levels, frequency range and EMI. Refer to
the switching electrical tables for the details.
Table 1. Input/Output Frequency Range
Skew and Zero Delay
If the input clock is DC (GND to VDD) or floating, this is
detected by an input frequency detection circuitry and all
nine (9) clock outputs are forced to Hi-Z. The PLL is
shutdown to save power. In this shutdown state, the
product draws less than 12ȝA-max supply current.
All outputs should drive the similar load to achieve the
output-to-output skew and input-to-output specifications
given in the switching electrical tables. However, Zero
Delay between input and outputs can be adjusted by
changing the loading at CLKOUT relative to the banks A
and B clocks since CLKOUT is the feedback to the PLL.
In PLL by-pass mode (S2=1 and S1=0), the detection
circuit is disabled and input frequency range is 10 to
100MHz for standard (-1) drive and 10 to 140MHz for high
(-1H) drive.
Power Supply Range (VDD)
The SL2309 is designed to operate at VDD=3.3V (+/-
10%). An internal on-chip voltage regulator is used to
provide PLL constant power supply of 1.8V, leading to a
consistent and stable PLL electrical performance in terms
of skew, jitter and power dissipation.
SpreadThru™ Feature
If a Spread Spectrum Clock (SSC) were to be used as an
input clock, the SL2309 is designed to pass the
modulated Spread Spectrum Clock (SSC) signal from its
reference input to the output clocks. The same spread
characteristics at the input are passed through the PLL
and drivers without any degradation in spread percent
(%), spread profile and modulation frequency
Refer to SL23EP09 for 3.3V to 2.5V and SL23EPL09 for
1.8V power supply operations.
Rev 1.1, May 29, 2007
Page 3 of 12
SL2309
S2
S1
Clock A1-A4
Clock B1-4
CLKOUT
Output Source
PLL Status
0
0
Tri-state
Tri-state
Driven
PLL
On
On
Off
On
0
1
1
1
0
1
Driven
Driven
Driven
Tri-state
Driven
Driven
Driven
Driven
Driven
PLL
Reference
PLL
Table 2. Select Input Decoding
1500
1000
500
0
-30
-25
-15
-10
-5
0
5
10
15
20
25
30
-20
-500
-1000
-1500
Output Load Difference: FBK Load – CLKA or CLKB Load (pF)
Figure 1. CLKIN Input to CLK A and B Delay
(In terms of load difference between CLKOUT and CLK A and B)
Rev 1.1, May 29, 2007
Page 4 of 12
SL2309
Absolute Maximum Ratings
Description
Condition
Min
Max
Unit
Supply voltage, VDD
– 0.5
4.6
V
All Inputs and Outputs
– 0.5
0
VDD+0.5
85
V
Ambient Operating Temperature
Ambient Operating Temperature
Storage Temperature
In operation, C-Grade
In operation, I-Grade
°C
°C
°C
°C
°C
V
– 40
– 65
–
85
No power is applied
150
125
260
–
Junction Temperature
In operation, power is applied
Soldering Temperature
–
ESD Rating (Human Body Model)
MIL-STD-883, Method 3015
2000
Operating Conditions: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades
Symbol
Description
Condition
Min
3.0
0
Max
3.6
85
Unit
V
VDD
3.3V Supply Voltage
3.3V+/-10%
TA
Operating Temperature(Ambient) Commercial
Industrial
°C
°C
– 40
85
CLOAD
Load Capacitance
10 to 140 MHz, -1H high drive
All active PLL modes
–
–
–
–
15
30
15
30
pF
pF
10 to 100 MHz, -1H high drive
All active PLL modes
10 to 100MHz, -1 standard drive
All active PLL modes
pF
pF
10 to 66MHz, -1 standard drive
All active PLL modes
CIN
tpu
Input Capacitance
Power-up Time
S1, S2 and CLKIN pins
–
7
pF
Power-up time for all VDDs to reach
minimum VDD voltage (VDD=3.0V).
0.05
100
ms
CLBW
ZOUT
Closed-loop bandwidth
Output Impedance
3.3V, (typical)
1.2
MHz
3.3V, (typical), -1H high drive
3.3V, (typical), -1 standard drive
22
32
Rev 1.1, May 29, 2007
Page 5 of 12
SL2309
DC Electrical Specifications: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades
Symbol
VDD
VIL
Description
Condition
Min
3.0
–
Max
Unit
V
Supply Voltage
3.6
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
CLKIN, S2 and S1 Pins
0.8
V
VIH
CLKIN, S2 and S1 pins
2.0
–
VDD+0.3
V
µA
µA
V
IIL
CLKIN, S2 and S1 Pins, 0 < VIN < 0.8V
CLKIN, S2 and S1 Pins, VIN = VDD
IOL = 8 mA (standard drive)
IOL = 12 mA (high drive)
25
50
0.4
0.4
–
IIH
–
–
Output LOW Voltage
(All outputs)
VOL
VOH
–
V
IOH = –8 mA (standard drive)
IOH = –12 mA (high drive)
2.4
2.4
V
Output HIGH Voltage
(All outputs)
–
V
Power Down Supply Current
CLKIN=0 to VDD or floating (input
will be pulled-down by 250k
weak pull-down on-chip resistor)
C-Grade
I-Grade
–
–
12
µA
IDDPD
25
20
µA
All Outputs CL=0, 33MHz CLKIN
S2=S1=1 (High)
IDD1
IDD2
IDD3
IDD4
RPU/D
Power Supply Current
Power Supply Current
Power Supply Current
Power Supply Current
Pull-up and Pull-down Resistors
–
mA
All Outputs CL=0, 66MHz CLKIN
S2=S1=1 (High)
–
28
36
mA
mA
mA
k
All Outputs CL=0, 100MHz CLKIN
S2=S1=1 (High)
–
All Outputs CL=0, 140MHz CLKIN
S2=S1=1 (High)
–
44
Pins-1/2/3/6/7/8/9/10/11/14/15/16
250k-typ
175
325
Rev 1.1, May 29, 2007
Page 6 of 12
SL2309
Switching Specifications: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades
Symbol
Description
Condition
Min
Typ
Max
Unit
FMAX1
Maximum Frequency [1]
(Input=Output )
High drive (-1H). All outputs CL=15pF
High drive (-1H), All outputs CL=30pF
Standard drive, (-1), All outputs CL=15pf
10
10
10
10
0
–
–
140
100
100
66
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%
All Active PLL Modes
–
Standard drive, (-1), All outputs CL=30pf
High drive (-1H). All outputs CL=15pF
–
FMAX2
Maximum Frequency [1]
(Input=Output )
–
140
100
100
66
High drive (-1H), All outputs CL=30pF
Standard drive, (-1), All outputs CL=15pf
0
–
PLL Bypass Mode
(S2=1 and S1=0)
0
–
Standard drive, (-1), All outputs CL=30pf
Measured at 1.4V, Fout=66MHz, CL=15pF
Measured at 1.4V, Fout=66MHz, CL=15pF
High drive (-1H), CL=15pF
0
–
Input Duty Cycle
INDC
30
40
–
50
50
–
70
OUTDC
Output Duty Cycle[2]
60
%
tr/f
Rise, Fall Time (3.3V) [2]
(Measured at: 0.8 to 2.0V)
1.5
1.8
2.2
2.5
ns
High drive (-1H), CL=30pF
–
–
ns
Standard drive (-1), CL=15pF
–
–
ns
Standard drive (-1), CL=30pF
–
–
ns
t1
t2
t3
Output-to-Output Skew[2]
(Measured at VDD/2)
Device-to-Device Skew[2]
All outputs CL=0 or equally loaded, -1 or
-1H drives
–
–
50
150
5
120
400
8.7
ps
ps
ns
ps
ms
All outputs CL=0 or equally loaded, -1 or
-1H drives
(Measured at VDD/2)
Delay Time, CLKIN Rising
Edge to CLKOUT Rising
Edge[2]
PLL Bypass mode
1.5
–150
–
Only when S2=1 and S1=0
PLL enabled
(Measured at VDD/2)
–
150
1.0
All active PLL modes
tPLOCK PLL Lock Time[2]
Time from 90% of VDD to valid clocks on
all the output clocks
–
CCJ
Cycle-to-cycle Jitter [2]
Fin=Fout=66 MHz, <CL=15pF, -1H drive
Fin=Fout=66 MHz, <CL=15pF, -1 drive
Fin=Fout=66 MHz, <CL=30pF, -1H drive
Fin=Fout=66 MHz, <CL=30pF, -1 drive
–
–
–
–
50
60
65
75
100
120
130
150
ps
ps
ps
ps
Notes:
1. For the given maximum loading conditions. See CL in Operating Conditions Table.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Rev 1.1, May 29, 2007
Page 7 of 12
SL2309
External Components & Design Considerations
Typical Application Schematic
Comments and Recommendations
Decoupling Capacitor: A decoupling capacitor of 0.1ȝF must be used between VDD and VSS pins. Place the capacitor s
on the component side of the PCB as close to the VDD pins as possible. The PCB trace to the VDD pin and to the GND
via should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD pin.
Series Termination Resistor: A series termination resistor is recommended if the distance between the output clocks and
the load is over 1 ½ inch. The nominal impedance of the clock outputs is given on the page 4. Place the series termination
resistors as close to the clock outputs as possible.
Zero Delay and Skew Control: All outputs and CLKIN pins should be loaded with the same load to achieve “Zero Delay”
between the CLKIN and the outputs. The CLKOUT pin is connected to CLKIN internally on-chip for feedback to PLL, and
sees an additional 2 pF load with respect to Bank A and B clocks. For applications requiring zero input/output delay, the
load at the all output pins including the CLKOUT pin must be the same. If any delay adjustment is required, the
capacitance at the CLKOUT pin could be increased or decreased to increase or decrease the delay between Bank A and
B clocks and CLKIN.
For minimum pin-to-pin skew, the external load at all the Bank A and B clocks must be the same.
Rev 1.1, May 29, 2007
Page 8 of 12
SL2309
Switching Waveforms
Figure 2. Output to Output Skew
Figure 3. Input-to-Output Skew
Figure 4. Part-to-Part Skew
Rev 1.1, May 29, 2007
Page 9 of 12
SL2309
Package Drawing and Dimensions
16-Lead TSSOP (4.4mm)
9
16
6.250(0.246)
6.500(0.256)
4.300(0.169)
4.500(0.177)
Dimensions are in milimeters(inches).
Top line: (MIN) and Bottom line: (Max)
Pin-1 ID
1
8
2.900(0.114)
3.100(0.122)
1.100(0.043) MAX
0.650(0.025)
BSC
0.090(0.003)
0.200(0.008)
0.050(0.002)
0.150(0.006)
0.850(0.033)
0.950(0.037)
Gauge
Plane
0.076(0.003)
Seating Plane
0.500(0.020)
0.700(0.027)
0.190(0.007)
0.300(0.012)
0 to 8°
0.650(0.025)
BSC
Thermal Characteristics
Parameter
Symbol
Condition
Min
Typ
80
Max
Unit
°C/W
°C/W
°C/W
ș JA
Still air
-
-
-
-
-
-
Thermal Resistance
Junction to Ambient
ș JA
1m/s air flow
3m/s air flow
70
ș JA
68
Thermal Resistance
Junction to Case
ș JC
Independent of air flow
-
36
-
°C/W
Rev 1.1, May 29, 2007
Page 10 of 12
SL2309
Package Drawing and Dimensions (Cont.)
16-Lead SOIC (150 Mil)
16
9
Dimensions are in milimeters(inches).
Top line: (MIN) and Bottom line: (Max)
0.150(3.810)
0.157(3.987
Pin-1 ID
0.230(5.842)
0.244(6.197)
1
8
0.189(4.800)
0.196(4.978)
0.010(0.2540)
0.016(0.406)
X 45°
0.0075(0.190)
0.0098(0.249)
0.061(1.549)
0.068(1.727)
0.004(0.102)
Seating plane
0.050(1.270)
BSC
0.016(0.406)
0.035(0.889)
0° to 8°
0.004(0.102)
0.0098(0.249)
0.0138(0.350)
0.0192(0.487)
Thermal Characteristics
Parameter
Symbol
Condition
Min
Typ
120
115
105
Max
Unit
°C/W
°C/W
°C/W
ș JA
Still air
-
-
-
-
-
-
Thermal Resistance
Junction to Ambient
ș JA
ș JA
1m/s air flow
3m/s air flow
Thermal Resistance
Junction to Case
ș JC
Independent of air flow
-
60
-
°C/W
Rev 1.1, May 29, 2007
Page 11 of 12
SL2309
Ordering Information[3]
Ordering Number
Marking
Shipping Package
Package
Temperature
SL2309ZC-1
SL2309ZC-1T
SL2309ZC-1H
SL2309ZC-1HT
SL2309ZI-1
SL2309ZC-1
SL2309ZC-1
SL2309ZC-1H
SL2309ZC-1H
SL2309ZI-1
Tube
Tape and Reel
Tube
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin SOIC
16-pin SOIC
16-pin SOIC
16-pin SOIC
16-pin SOIC
16-pin SOIC
16-pin SOIC
16-pin SOIC
0 to 70°C
0 to 70°C
0 to 70°C
Tape and Reel
Tube
0 to 70°C
-40 to 85°C
-40 to 85°C
-40 to 85°C
-40 to 85°C
0 to 70°C
SL2309ZI-1T
SL2309ZI-1H
SL2309ZI-1HT
SL2309SC-1
SL2309SC-1T
SL2309SC-1H
SL2309SC-1HT
SL2309SI-1
SL2309ZI-1
Tape and Reel
Tube
SL2309ZI-1H
SL2309ZI-1H
SL2309SC-1
SL2309SC-1
SL2309SC-1H
SL2309SC-1H
SL2309SI-1
Tape and Reel
Tube
Tape and Reel
Tube
0 to 70°C
0 to 70°C
Tape and Reel
Tube
0 to 70°C
-40 to 85°C
-40 to 85°C
-40 to 85°C
-40 to 85°C
SL2309SI-1T
SL2309SI-1H
SL2309SI-1HT
SL2309SI-1
Tape and Reel
Tube
SL2309SI-1H
SL2309SI-1H
Tape and Reel
Notes:
3. The SL2309 products are RoHS compliant.
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any
circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for
use in normal commercial applications and is not warranted not is it intended for use in life support, critical medical instruments, or any other
application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to
additional processing by Spectra Linear Inc., and an expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the
right to change any circuitry or specification without notice.
Rev 1.1, May 29, 2007
Page 12 of 12
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