S71WS512NC0BAWA33 [SPANSION]
Stacked Multi-Chip Product (MCP); 堆叠式多芯片产品（ MCP ）
| 型号： | S71WS512NC0BAWA33 |
| 厂家： | 
SPANSION |
| 描述： | Stacked Multi-Chip Product (MCP) |
| 文件： | 总188页 (文件大小：3789K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S71WS-Nx0 Based MCPs
Stacked Multi-Chip Product (MCP)
128/256/512 Megabit (32M/16M x 16 bit) CMOS
1.8 Volt-only Simultaneous Read/Write,
Burst-mode Flash Memory with
pSRAM Type 4
ADVANCE
INFORMATION
Data Sheet
Notice to Readers: This document states the current technical specifications
regarding the Spansion product(s) described herein. Each product described
herein may be designated as Advance Information, Preliminary, or Full
Production. See Notice On Data Sheet Designations for definitions.
Publication Number S71WS-N_01 Revision A Amendment 4 Issue Date September 15, 2005
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not
design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
A d v a n c e I n f o r m a t i o n
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise
readers of product information or intended specifications throughout the product life cycle, includ-
ing development, qualification, initial production, and full production. In all cases, however,
readers are encouraged to verify that they have the latest information before finalizing their de-
sign. The following descriptions of Spansion data sheet designations are presented here to
highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one or more spe-
cific products, but has not committed any design to production. Information presented in a
document with this designation is likely to change, and in some cases, development on the prod-
uct may discontinue. Spansion LLC therefore places the following conditions upon Advance
Information content:
“This document contains information on one or more products under development at Spansion LLC. The
information is intended to help you evaluate this product. Do not design in this product without con-
tacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the product
life cycle, including product qualification, initial production, and the subsequent phases in the
manufacturing process that occur before full production is achieved. Changes to the technical
specifications presented in a Preliminary document should be expected while keeping these as-
pects of production under consideration. Spansion places the following conditions upon
Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. The Preliminary status of this document indicates that product qualification has been completed,
and that initial production has begun. Due to the phases of the manufacturing process that require
maintaining efficiency and quality, this document may be revised by subsequent versions or modifica-
tions due to changes in technical specifications.”
Combination
Some data sheets will contain a combination of products with different designations (Advance In-
formation, Preliminary, or Full Production). This type of document will distinguish these products
and their designations wherever necessary, typically on the first page, the ordering information
page, and pages with the DC Characteristics table and the AC Erase and Program table (in the
table notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal
changes may include those affecting the number of ordering part numbers available, such as the
addition or deletion of a speed option, temperature range, package type, or VIO range. Changes
may also include those needed to clarify a description or to correct a typographical error or incor-
rect specification. Spansion LLC applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. Spansion LLC deems the products to have been in sufficient production volume such that sub-
sequent versions of this document are not expected to change. However, typographical or specification
corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local AMD or Fujitsu
sales office.
ii
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
S71WS-Nx0 Based MCPs
Stacked Multi-Chip Product (MCP)
128/256/512 Megabit (32M/16M x 16 bit) CMOS
1.8 Volt-only Simultaneous Read/Write,
Burst-mode Flash Memory with
pSRAM Type 4
ADVANCE
INFORMATION
General Description
The S71WS-N Series is a product line of stacked Multi-Chip Product (MCP) packages and consists
of the following items:
One or more flash memory die
pSRAM Type 4—Compatible pSRAM
The products covered by this document are listed in the table below. For details about their spec-
ifications, please refer to the individual constituent datasheet for further details.
Flash Density
pSRAM Density
64 Mb 32 Mb
Device
512 Mb
256 Mb
128 Mb
64 Mb
128 Mb
16 Mb
S71WS512ND0
S71WS256ND0
S71WS256NC0
S71WS128NC0
Distinctive Characteristics
MCP Features
Power supply voltage of 1.7 V to 1.95 V
Burst Speed: 54 MHz, 66 MHz
Package
— 8 x 11.6 mm, 9 x 12 mm
Operating Temperature
— Wireless, –25° C to +85° C
Publication Number S71WS-N_01 Revision A Amendment 4 Issue Date September 15, 2005
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not
design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
A d v a n c e I n f o r m a t i o n
Contents
S71WS-Nx0 Based MCPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Input/Output Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Connection Diagrams/Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 Special Handling Instructions for FBGA Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5.2 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2
3
4
5
5.2.1
1.8 V RAM Type 4 – Based Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
5.2.2 Look-Ahead Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
5.3 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
5.3.1
TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 11.6 x 8.0 x 1.2 mm. . . . . . . . . . . . . . . . . . . . . . . . .17
5.3.2 TSD084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 x 1.2 mm . . . . . . . . . . . . . . . . . . . . . . . .18
5.3.3 FEA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 x 1.4 mm . . . . . . . . . . . . . . . . . . . . . . . .19
S29WS-N MirrorBitTM Flash Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
6
7
8
9
Input/Output Descriptions & Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Product Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
10 Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.1 Device Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.2 Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.3 Synchronous (Burst) Read Mode & Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.3.4 Continuous Burst Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.3.5 8-, 16-, 32-Word Linear Burst Read with Wrap Around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.3.6 8-, 16-, 32-Word Linear Burst without Wrap Around. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.3.7 Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10.4 Autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.5 Program/Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.5.1 Single Word Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.5.2 Write Buffer Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.5.3 Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10.5.4 Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.5.5 Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.5.6 Program Suspend/Program Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.5.7 Accelerated Program/Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
10.5.8 Unlock Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.5.9 Write Operation Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.6 Simultaneous Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.7 Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.8 Handshaking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.9 Hardware Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.10 Software Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11 Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.1 Lock Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
11.2 Persistent Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
11.3 Dynamic Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.4 Persistent Protection Bit Lock Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
11.5 Password Protection Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
11.6 Hardware Data Protection Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
11.6.1 WP# Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
A d v a n c e I n f o r m a t i o n
11.6.2 ACC Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
11.6.3 Low VCC Write Inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
11.6.4 Write Pulse “Glitch Protection” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
11.6.5 Power-Up Write Inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
12 Power Conservation Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
12.1 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12.2 Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12.3 Hardware RESET# Input Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12.4 Output Disable (OE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
13 Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
13.1 Factory Secured SiliconSector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
13.2 Customer Secured Silicon Sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13.3 Secured Silicon Sector Entry/Exit Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
14 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
14.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
14.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
14.3 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
14.4 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
14.5 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
14.6
VCC Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
14.7 DC Characteristics (CMOS Compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
14.8 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
14.8.1 CLK Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
14.8.2 Synchronous/Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
14.8.3 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
14.8.4 AC Characteristics—Asynchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
14.8.5 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
14.8.6 Erase/Program Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
14.8.7 Erase and Programming Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
14.8.8 BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
15 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
15.1 Common Flash Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
16 Commonly Used Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
1.8V pSRAM Type 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
17 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
18 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
19 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
20 Power Up and Standby Mode Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
20.1 Power Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
20.2 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
21 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
22 Mode Register Setting Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
22.1 Mode Register Set (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
22.2 Mode Register Setting Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
23 Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
23.1 Asynchronous 4 Page Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
23.2 Asynchronous Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
23.3 Asynchronous Write Operation in Synchronous Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
24 Synchronous Burst Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
24.1 Synchronous Burst Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
24.2 Synchronous Burst Write Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
25 Synchronous Burst Operation Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
25.1 Clock (CLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
25.2 Latency Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
25.3 Burst Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
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25.4 Burst Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
25.5 Wait Control (WAIT#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
25.6 Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
26 Low Power Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
26.7 Partial Array Refresh (PAR) mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
26.8 Driver Strength Optimization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
26.1 Internal TCSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
27 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
28 DC Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
29 Capacitance (Ta = 25°C, f = 1 MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
30 DC and Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
30.1 Common . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
31 AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
31.1 Test Conditions (Test Load and Test Input/Output Reference) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
31.2 Asynchronous AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
31.3 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
31.3.1 Asynchronous Read Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
31.3.2 Asynchronous Write Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
31.3.3 Asynchronous Write Timing Waveform in Synchronous Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
31.3.4 Asynchronous Write Timing Waveform in Synchronous Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
32 AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
32.1 Test Conditions (Test Load and Test Input/Output Reference) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
32.2 Synchronous AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
32.3 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
32.3.1 Synchronous Burst Operation Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
32.3.2 Synchronous Burst Read Timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
32.3.3 Synchronous Burst Read Stop Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
32.3.4 Synchronous Burst Write Stop Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
32.3.5 Synchronous Burst Read Suspend Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
33 Transition Timing Waveform Between Read And Write . . . . . . . . . . . . . . . . . . . . . . . . . . 139
1.8V pSRAM Type 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
34 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
35 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
36 Power Up and Standby Mode Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
36.1 Power Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
36.2 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
37 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
38 Mode Register Setting Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
38.1 Mode Register Set (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
38.2 MRS Pin Control Type Mode Register Setting Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
39 Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
39.1 Asynchronous 4 Page Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
39.2 Asynchronous Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
39.3 Asynchronous Write Operation in Synchronous Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
40 Synchronous Burst Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
40.1 Synchronous Burst Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
40.2 Synchronous Burst Write Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
41 Synchronous Burst Operation Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
41.1 Clock (CLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
41.2 Latency Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
41.3 Burst Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
41.4 Burst Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
41.5 Wait Control (WAIT#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
41.6 Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
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42 Low Power Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
42.1 Internal TCSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
42.2 Driver Strength Optimization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
42.3 Partial Array Refresh (PAR) mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
43 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
44 DC Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
45 Capacitance (Ta = 25°C, f = 1 MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
46 DC and Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
46.1 Common . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
47 AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
47.1 Test Conditions (Test Load and Test Input/Output Reference) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
47.2 Asynchronous AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
47.3 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
47.3.1 Asynchronous Read Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
47.3.2 Asynchronous Write Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
47.3.1 Asynchronous Write Timing Waveform in Synchronous Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
48 AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
48.1 Test Conditions (Test Load and Test Input/Output Reference) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
48.2 Synchronous AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
48.3 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
48.3.1 Synchronous Burst Operation Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
48.3.2 Synchronous Burst Read Timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
48.3.3 Synchronous Burst Read Stop Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
48.3.4 Synchronous Burst Write Stop Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
48.3.5 Synchronous Burst Read Suspend Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
49 Transition Timing Waveform Between Read And Write . . . . . . . . . . . . . . . . . . . . . . . . . . 180
50 Revisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
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Tables
Table 3.1
Table 6.1
Table 9.1
Table 9.2
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
S29WS256N Sector & Memory Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
S29WS128N Sector & Memory Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10.1 Device Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 10.2 Address Latency (S29WS256N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 10.3 Address Latency (S29WS128N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 10.4 Address/Boundary Crossing Latency (S29WS256N @ 80MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 10.5 Address/Boundary Crossing Latency (S29WS256N @ 66 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 10.6 Address/Boundary Crossing Latency (S29WS256N @ 54MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 10.7 Address/Boundary Crossing Latency (S29WS128N). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 10.8 Burst Address Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 10.9 Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 10.10 Autoselect Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 10.11 Autoselect Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 10.12 Autoselect Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 10.13 Software Functions and Sample Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 10.14 Software Functions and Sample Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 10.15 Software Functions and Sample Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 10.16 Software Functions and Sample Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 10.17 Software Functions and Sample Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 10.18 Software Functions and Sample Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 10.19 Software Functions and Sample Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 10.20 Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 10.21 Reset LLD Function = lld_ResetCmd). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 11.1 Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 11.2 Advanced Sector Protection Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 13.1
Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 13.2 Secured Silicon Sector Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 13.3 Secured Silicon Sector Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 13.4 Secured Silicon Sector Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 14.1 Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 14.2 Synchronous Wait State Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 15.1
Memory Array Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 15.2 Sector Protection Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 15.3 CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 15.4 System Interface String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 15.5 Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 15.6 Primary Vendor-Specific Extended Query. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 21.1 Asynchronous 4 Page Read & Asynchronous Write Mode (A15/A14=0/0). . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 21.2 Synchronous Burst Read & Asynchronous Write Mode (A15/A14=0/1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 21.3 Synchronous Burst Read & Synchronous Burst Write Mode(A15/A14 = 1/0). . . . . . . . . . . . . . . . . . . . . . . . 106
Table 22.1 Mode Register Setting According to Field of Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 22.2 Mode Register Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 22.3 MRS AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 25.1 Latency Count Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 25.2 Number of CLocks for 1st Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 25.3 Burst Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 26.1 PAR Mode Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 31.1 Asynchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 31.2 Asynchronous Page Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 31.3 Asynchronous Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 31.4 Asynchronous Write AC Characteristics (UB# & LB# Controlled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6
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A d v a n c e I n f o r m a t i o n
Table 31.5 Asynchronous Write in Synchronous Mode AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 31.6 Asynchronous Write in Synchronous Mode AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 31.7 Asynchronous Write in Synchronous Mode AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 31.8 Asynchronous Write in Synchronous Mode AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 31.9 Asynchronous Write in Synchronous Mode AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 32.1 Burst Operation AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 32.2 Burst Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 32.3 Burst Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 32.4 Burst Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 32.5 Burst Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 32.6 Burst Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 32.7 Burst Read Stop AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 32.8 Burst Write Stop AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 32.9 Burst Read Suspend AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 33.1 Burst Read to Asynchronous Write (Address Latch Type) AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 139
Table 33.2 Burst Read to Asynchronous Write (Low ADV# Type) AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 33.3 Asynchronous Write (Address Latch Type) to Burst Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 141
Table 33.4 Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 33.5 Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 33.6 Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 37.1 Asynchronous 4 Page Read & Asynchronous Write Mode (A15/A14=0/0). . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 37.2 Synchronous Burst Read & Asynchronous Write Mode (A15/A14=0/1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 37.3 Synchronous Burst Read & Synchronous Burst Write Mode(A15/A14 = 1/0). . . . . . . . . . . . . . . . . . . . . . . . 149
Table 38.1 Mode Register Setting According to Field of Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 38.2 Mode Register Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 38.3 MRS AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 41.1 Latency Count Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 41.2 Number of CLocks for 1st Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 41.3 Burst Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 42.1 PAR Mode Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 47.1 Asynchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 47.2 Asynchronous Page Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 47.3 Asynchronous Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 47.4 Asynchronous Write AC Characteristics (UB# & LB# Controlled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 47.5 Asynchronous Write in Synchronous Mode AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 47.6 Asynchronous Write in Synchronous Mode AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 47.7 Asynchronous Write in Synchronous Mode AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 47.8 Asynchronous Write in Synchronous Mode AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 48.1 Burst Operation AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 48.2 Burst Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 48.3 Burst Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 48.4 Burst Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 48.5 Burst Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 48.6 Burst Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 48.7 Burst Read Stop AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 48.8 Burst Write Stop AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 48.9 Burst Read Suspend AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 49.1 Burst Read to Asynchronous Write (Address Latch Type) AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 180
Table 49.2 Burst Read to Asynchronous Write (Low ADV# Type) AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 49.3 Asynchronous Write (Address Latch Type) to Burst Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 182
Table 49.4 Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 49.5 Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 49.6 Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 185
September 15, 2005 S71WS-N_01_A4
S71WS-Nx0 Based MCPs
7
A d v a n c e I n f o r m a t i o n
Figures
Figure 7.1
S29WS-N Block Diagram....................................................................................................................22
Synchronous/Asynchronous State Diagram...........................................................................................27
Synchronous Read ............................................................................................................................29
Single Word Program.........................................................................................................................35
Write Buffer Programming Operation ...................................................................................................39
Sector Erase Operation ......................................................................................................................41
Write Operation Status Flowchart ........................................................................................................48
Advanced Sector Protection/Unprotection .............................................................................................55
PPB Program/Erase Algorithm.............................................................................................................58
Lock Register Program Algorithm.........................................................................................................61
Maximum Negative Overshoot Waveform .............................................................................................68
Maximum Positive Overshoot Waveform...............................................................................................68
Test Setup .......................................................................................................................................69
Input Waveforms and Measurement Levels...........................................................................................70
VCC Power-up Diagram ......................................................................................................................70
CLK Characterization .........................................................................................................................72
CLK Synchronous Burst Mode Read......................................................................................................74
8-word Linear Burst with Wrap Around.................................................................................................75
8-word Linear Burst without Wrap Around ............................................................................................75
Figure 10.1
Figure 10.2
Figure 10.3
Figure 10.4
Figure 10.5
Figure 10.6
Figure 11.1
Figure 11.2
Figure 11.3
Figure 14.1
Figure 14.2
Figure 14.3
Figure 14.4
Figure 14.5
Figure 14.6
Figure 14.7
Figure 14.8
Figure 14.9
Figure 14.10 Linear Burst with RDY Set One Cycle Before Data..................................................................................76
Figure 14.11 Asynchronous Mode Read...................................................................................................................77
Figure 14.12 Reset Timings...................................................................................................................................78
Figure 14.13 Chip/Sector Erase Operation Timings...................................................................................................80
Figure 14.14 Program Operation Timing Using AVD#................................................................................................81
Figure 14.15 Program Operation Timing Using CLK in Relationship to AVD#.................................................................82
Figure 14.16 Accelerated Unlock Bypass Programming Timing ...................................................................................83
Figure 14.17 Data# Polling Timings (During Embedded Algorithm).............................................................................83
Figure 14.18 Toggle Bit Timings (During Embedded Algorithm)..................................................................................84
Figure 14.19 Synchronous Data Polling Timings/Toggle Bit Timings ............................................................................84
Figure 14.20 DQ2 vs. DQ6....................................................................................................................................85
Figure 14.21 Latency with Boundary Crossing when Frequency > 66 MHz....................................................................85
Figure 14.22 Latency with Boundary Crossing into Program/Erase Bank......................................................................86
Figure 14.23 Example of Wait States Insertion ........................................................................................................87
Figure 14.24 Back-to-Back Read/Write Cycle Timings ...............................................................................................88
Figure 20.1
Figure 20.2
Power Up Timing.............................................................................................................................104
Standby Mode State Machines ..........................................................................................................104
Figure 22.1
Figure 22.2
Pin MRS Timing Waveform (OE# = VIH) .............................................................................................108
Software MRS Timing Waveform .......................................................................................................109
Figure 23.1
Figure 23.2
Figure 24.1
Figure 24.2
Figure 25.1
Figure 25.2
Figure 26.1
Figure 31.1
Figure 31.2
Figure 31.3
Figure 31.4
Figure 31.5
Figure 31.6
Figure 31.7
Figure 31.8
Figure 31.9
Asynchronous 4-Page Read ..............................................................................................................110
Asynchronous Write.........................................................................................................................110
Synchronous Burst Read ..................................................................................................................111
Synchronous Burst Write..................................................................................................................111
Latency Configuration (Read)............................................................................................................112
WAIT# and Read/Write Latency Control .............................................................................................113
PAR Mode Execution and Exit............................................................................................................115
PAR Mode Execution and Exit............................................................................................................117
Timing Waveform Of Asynchronous Read Cycle ...................................................................................119
Timing Waveform Of Page Read Cycle................................................................................................120
Timing Waveform Of Write Cycle.......................................................................................................121
Timing Waveform of Write Cycle(2) ...................................................................................................122
Timing Waveform Of Write Cycle (Address Latch Type) ........................................................................123
Timing Waveform Of Write Cycle (Low ADV# Type) .............................................................................124
Timing Waveform Of Write Cycle (Low ADV# Type) .............................................................................125
Timing Waveform Of Write Cycle (Low ADV# Type) .............................................................................126
8
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
A d v a n c e I n f o r m a t i o n
Figure 31.10 Timing Waveform Of Multiple Write Cycle (Low ADV# Type)..................................................................127
Figure 32.1
Figure 32.2
Figure 32.3
Figure 32.4
Figure 32.5
Figure 32.6
Figure 32.7
Figure 32.8
Figure 32.9
AC Output Load Circuit.....................................................................................................................128
Timing Waveform Of Basic Burst Operation.........................................................................................130
Timing Waveform of Burst Read Cycle (1) ..........................................................................................131
Timing Waveform of Burst Read Cycle (2) ..........................................................................................132
Timing Waveform of Burst Read Cycle (3) ..........................................................................................133
Timing Waveform of Burst Write Cycle (1)..........................................................................................134
Timing Waveform of Burst Write Cycle (2)..........................................................................................135
Timing Waveform of Burst Read Stop by CS# .....................................................................................136
Timing Waveform of Burst Write Stop by CS#.....................................................................................137
Figure 32.10 Timing Waveform of Burst Read Suspend Cycle (1)..............................................................................138
Figure 33.1
Figure 33.2
Figure 33.3
Figure 33.4
Figure 33.5
Figure 33.6
Figure 36.1
Figure 36.2
Figure 38.1
Figure 39.1
Figure 39.2
Synchronous Burst Read to Asynchronous Write (Address Latch Type) ...................................................139
Synchronous Burst Read to Asynchronous Write (Low ADV# Type) ........................................................140
Asynchronous Write (Address Latch Type) to Synchronous Burst Read Timing .........................................141
Asynchronous Write (Low ADV# Type) to Synchronous Burst Read Timing..............................................142
Synchronous Burst Read to Synchronous Burst Write Timing.................................................................143
Synchronous Burst Write to Synchronous Burst Read Timing.................................................................144
Power Up Timing.............................................................................................................................147
Standby Mode State Machines ..........................................................................................................147
Mode Register Setting Timing (OE# = VIH) .........................................................................................151
Asynchronous 4-Page Read ..............................................................................................................152
Asynchronous Write.........................................................................................................................152
Figure 40.1
Figure 40.2
Figure 41.1
Figure 41.2
Figure 42.1
Figure 47.1
Figure 47.2
Figure 47.3
Figure 47.4
Figure 47.5
Figure 47.6
Figure 47.7
Figure 47.8
Figure 47.9
Figure 48.1
Figure 48.2
Figure 48.3
Figure 48.4
Figure 48.5
Figure 48.6
Figure 48.7
Figure 48.8
Figure 48.9
Synchronous Burst Read ..................................................................................................................153
Synchronous Burst Write..................................................................................................................153
Latency Configuration (Read)............................................................................................................154
WAIT# and Read/Write Latency Control .............................................................................................155
PAR Mode Execution and Exit............................................................................................................157
PAR Mode Execution and Exit............................................................................................................159
Timing Waveform Of Asynchronous Read Cycle ...................................................................................161
Timing Waveform Of Page Read Cycle................................................................................................162
Timing Waveform Of Write Cycle.......................................................................................................163
Timing Waveform of Write Cycle(2) ...................................................................................................164
Timing Waveform Of Write Cycle (Address Latch Type) ........................................................................165
Timing Waveform Of Write Cycle (Low ADV# Type) .............................................................................166
Timing Waveform Of Write Cycle (Low ADV# Type) .............................................................................167
Timing Waveform Of Multiple Write Cycle (Low ADV# Type)..................................................................168
AC Output Load Circuit.....................................................................................................................169
Timing Waveform Of Basic Burst Operation.........................................................................................171
Timing Waveform of Burst Read Cycle (1) ..........................................................................................172
Timing Waveform of Burst Read Cycle (2) ..........................................................................................173
Timing Waveform of Burst Read Cycle (3) ..........................................................................................174
Timing Waveform of Burst Write Cycle (1)..........................................................................................175
Timing Waveform of Burst Write Cycle (2)..........................................................................................176
Timing Waveform of Burst Read Stop by CS# .....................................................................................177
Timing Waveform of Burst Write Stop by CS#.....................................................................................178
Figure 48.10 Timing Waveform of Burst Read Suspend Cycle (1)..............................................................................179
Figure 49.1
Figure 49.2
Figure 49.3
Figure 49.4
Figure 49.5
Figure 49.6
Synchronous Burst Read to Asynchronous Write (Address Latch Type) ...................................................180
Synchronous Burst Read to Asynchronous Write (Low ADV# Type) ........................................................181
Asynchronous Write (Address Latch Type) to Synchronous Burst Read Timing .........................................182
Asynchronous Write (Low ADV# Type) to Synchronous Burst Read Timing..............................................183
Synchronous Burst Read to Synchronous Burst Write Timing.................................................................184
Synchronous Burst Write to Synchronous Burst Read Timing.................................................................185
September 15, 2005 S71WS-N_01_A4
S71WS-Nx0 Based MCPs
9
A d v a n c e I n f o r m a t i o n
1 Product Selector Guide
DYB
Power-Up
State
pSRAM
Density Speed
(Mb)
Flash
pSRAM
Speed
(MHz)
Model
Numbers
pSRAM
Supplier
Package
(mm)
Device
Flash
(MHz)
(See Note)
A3
A7
A2
A6
Y3
Y7
Y2
Y6
E3
E7
E2
E6
A3
A7
A2
A6
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
54
54
66
54
66
54
66
54
66
S71WS256NC0
64
11.6x8.0x1.2
9x12x1.2
66
54
66
54
66
54
66
WS256N
S71WS256ND0
S71WS512ND0
S71WS128NC0
128
128
64
1.8V RAM Type 4
WS512N
WS128N
9x12x1.4
11.6x8.0x1.2
Note: 0 (Protected), 1 (Unprotected [Default State])
10
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
A d v a n c e I n f o r m a t i o n
2 Ordering Information
The ordering part number is formed by a valid combination of the following:
S71WS 256
N
C
0
BA
W
A
3
0
Packing Type
0
2
3
=
=
=
Tray
7” Tape and Reel
13” Tape and Reel
RAM Supplier, DYB Power Up, Speed Combinations
3
7
2
6
=
=
=
=
RAM Type 4, 0, 54 MHz
RAM Type 4, 1, 54 MHz
RAM Type 4, 0, 66 MHz
RAM Type 4, 1, 66 MHz
Package Modifier
A
E
Y
=
=
=
1.2 mm, 8 x 11.6, 84-ball FBGA
1.2 mm, 9 x 12, 84-ball FBGA
1.4 mm, 9 x 12, 84-ball FBGA
Temperature Range
Wireless (-25°C to +85°C)
W
=
Package Type
BA
=
Very Thin Fine-Pitch BGA
Lead (Pb)-free Compliant Package
Very Thin Fine-Pitch BGA
Lead (Pb)-free Package
BF
=
Chip Contents—2
No content
pSRAM Density
C = 64 Mb
D = 128 Mb
Process Technology
N
=
110nm MirrorBit™ Technology
Flash Density
512
256
=
=
512Mb (2x256Mb)
256Mb
Device Family
S71WS= Multi-Chip Product
1.8 Volt-only Simultaneous Read/Write Burst Mode
Flash Memory + xRAM
Valid Combinations
S71WS128N
S71WS256N
C
A
E
2, 6, 3, 7
3, 7
D
C
0
BA, BF
W
A
Y
E
2, 6, 3, 7
2, 6
S71WS512N
D
2, 6, 3, 7
Package Marking Note:
The package marking omits the leading S from the ordering part number.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult
your local sales office to confirm availability of specific valid combinations and to check on newly
released combinations.
September 15, 2005 S71WS-N_01_A4
S71WS-Nx0 Based MCPs
11
A d v a n c e I n f o r m a t i o n
3 Input/Output Descriptions
Table 3.1 identifies the input and output package connections provided on the device.
Table 3.1 Input/Output Descriptions
Symbol
A23-A0
Description
Address inputs
DQ15-DQ0
OE#
Data input/output
Output Enable input. Asynchronous relative to CLK for the Burst mode.
WE#
Write Enable input.
V
Ground
SS
NC
No Connect; not connected internally
RDY
Ready output. Indicates the status of the Burst read. The WAIT# pin of the pSRAM is tied to RDY.
Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK increment
CLK
the internal address counter. Should be at V or V while in asynchronous mode
IL
IH
Address Valid input. Indicates to device that the valid address is present on the address inputs.
Low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be
latched.
AVD#
High = device ignores address inputs
F-RST#
F-WP#
Hardware reset input. Low = device resets and returns to reading array data
Hardware write protect input. At V , disables program and erase functions in the four outermost
IL
sectors. Should be at V for all other conditions.
IH
Accelerated input. At V , accelerates programming; automatically places device in unlock bypass
HH
F-ACC
mode. At V , disables all program and erase functions. Should be at V for all other conditions.
IL
IH
R-CE1#
F1-CE#
Chip-enable input for pSRAM.
Chip-enable input for Flash 1. Asynchronous relative to CLK for Burst Mode.
Chip-enable input for Flash 2. Asynchronous relative to CLK for Burst Mode. This applies to the 512Mb
MCP only.
F2-CE#
R-MRS
F-VCC
R-VCC
R-UB#
R-LB#
DNU
Mode register select for Type 4.
Flash 1.8 Volt-only single power supply.
pSRAM Power Supply.
Upper Byte Control (pSRAM).
Lower Byte Control (pSRAM)
Do Not Use
12
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
A d v a n c e I n f o r m a t i o n
4 MCP Block Diagram
F-VCC
Flash-only Address
Shared Address
V
V
ID
CC
DQ15 to DQ0
CLK
WP#
22
16
DQ15 to DQ0
CLK
WP#
ACC
F1-CE#
OE#
ACC
CE#
OE#
(Note 1)
Flash 1
(Note 3)
Flash 2
WE#
F-RST#
AVD#
WE#
RESET#
AVD#
RDY
RDY
VSS
F2-CE#
R-VCC
22
VCCQ
VCC
16
(Note 1)
I/O15 to I/O0
CLK
R-CE1#
CE#
WE#
pSRAM
WAIT#
OE#
UB#
LB#
CE2
R-UB#
R-LB#
R-CE2
V
SSQ
AVD#
Notes:
1. For 1 Flash + pSRAM, F1-CE# = CE#. For 2 Flash + pSRAM, CE# = F1-CE# and F2-CE# is the chip-enable pin for the
second Flash.
2. Only needed for S71WS512N.
3. For the 128M pSRAM devices, there are 23 shared addresses.
September 15, 2005 S71WS-N_01_A4
S71WS-Nx0 Based MCPs
13
A d v a n c e I n f o r m a t i o n
5 Connection Diagrams/Physical Dimensions
This section contains the I/O designations and package specifications for the S71WS-N.
5.1
Special Handling Instructions for FBGA Packages
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning meth-
ods. The package and/or data integrity may be compromised if the package body is exposed to
temperatures above 150° C for prolonged periods of time.
14
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
A d v a n c e I n f o r m a t i o n
5.2 Connection Diagrams
5.2.1
1.8 V RAM Type 4 – Based Pinout
84-ball Fine-Pitch Ball Grid Array
Type 4-based Pinout (Top View, Balls Facing Down)
A10
A1
DNU
DNU
B2
B3
RFU
C3
A7
D3
A6
E3
B4
CLK
C4
B5
F2-CE#
C5
B6
RFU
C6
B7
RFU
C7
B8
RFU
C8
B9
RFU
C9
AVD#
C2
F-WP#
D2
Legend
RFU
D9
R-LB#
D4
F-ACC
D5
WE#
D6
A8
A11
D8
D7
Shared
A3
R-UB# F-RST#
RFU
E6
A19
E7
A12
E8
A15
E9
E2
E4
A18
F4
E5
RDY
F5
Flash XIP only
A2
F2
A1
G2
A0
A5
F3
A20
F6
A9
A13
F8
A21
F9
F7
RAM only
A4
A17
G4
A10
G7
A14
G8
A22
G9
RFU
G5
A23
G6
G3
1st Flash
Only
VSS
DQ1
RFU
RFU
DQ6
RFU
A16
H2
H3
H4
H5
H6
H7
H8
H9
F1-CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
R-MRS
2nd Flash
Only
J9
J2
J3
J4
DQ10
K4
J5
J6
J7
J8
R-CE1#
DQ0
F-VCC
R-VCC
DQ12
DQ7
VSS
K2
K8
K3
K5
K7
K6
RFU
L6
K9
RFU
L9
Reserved for
Future Use
DQ14
DQ8
DQ2
DQ5
DQ11
RFU
L3
L4
L5
L7
L8
L2
RFU
RFU
RFU
F-VCC
RFU
RFU
RFU
RFU
M10
DNU
M1
DNU
Notes:
1. In MCPs based on a single S29WS256N (S71WS256N), ball B5 is RFU. In MCPs based on two S29WS256N (S71WS512),
ball B5 is or F2-CE#.
2. Addresses are shared between Flash and RAM depending on the density of the pSRAM.
MCP
Flash-only Addresses
Shared Addresses
A21-A0
S71WS128NC0
S71WS256NC0
S71WS512ND0
A22
A23-A22
A23
A21-A0
A22-A0
September 15, 2005 S71WS-N_01_A4
S71WS-Nx0 Based MCPs
15
A d v a n c e I n f o r m a t i o n
5.2.2
Look-Ahead Connection Diagram
A2
RFU
B2
A10
RFU
B10
RFU
A9
RFU
B9
A1
RFU
B1
Legend:
X
RFU
(Reserved for
Future Use)
RFU
RFU
C2
RFU
C9
C8
C3
VSS
D3
A7
C4
CLK
D4
C5
F2-CE#
D5
C6
F-VCC
D6
C7
X
AVD#
D2
F-CLK# R-OE# F2-OE#
Code Flash Only
D7
A8
D8
A11
E8
D9
F3-CE#
E9
WP#
E2
R-LB#
D4
ACC
WE#
E6
X
E3
E7
C7
MirrorBit Data
Only
A3
A6
R-UB# F-RST# R1-CE2
F4 F5 F6
A18 RDY/WAIT# A20
A19
A12
A15
F2
F3
F7
F8
F9
X
A2
A5
A9
A13
A21
Flash/Data
Shared
G2
A1
G3
A4
G4
A17
H4
G5
G6
A23
H6
G7
A10
H7
G8
A14
H8
G9
A22
H9
R2-CE1
X
H2
H3
H5
Flash/xRAM
Shared
A0
VSS
DQ1
R2-VCC R2-CE2
DQ6
A24
A16
J9
J3
J4
J5
J6
J7
J8
J2
X
F1-CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15 R-CRE or
R-MRS
pSRAM Only
K2
R1-CE1#
L2
K3
DQ0
L3
K4
DQ10
L4
E6
R1-VCC
L6
K7
K8
DQ7
L8
K9
K5
F-VCC
L5
DQ12
VSS
X
L7
DQ5
M7
L9
WP#
M9
xRAM Shared
R-VCC
M2
DQ8
M3
DQ2
M4
DQ11
M5
A25
DQ14
M8
M6
A27
A26
VSS
F-VCC
F4-CE# R-VCCQ F-VCCQ R-CLK#
N2
N1
N10
F-DQS1
P10
N9
RFU
P9
RFU
P2
F-DQS0
P1
RFU
RFU
RFU
RFU
Notes:
Ball
3.0 V V
1.8 V V
CC
CC
1. In a 3.0V system, the GL device used as Data has to have WP tied to V
2. F1 and F2 denote XIP/Flash, F3 and F4 denote Data/Companion Flash
D2
D5
F5
NC
F-WP#
ACC
CC
WP#/ACC
RY/BY
F-RDY/R-WAIT#
16
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
A d v a n c e I n f o r m a t i o n
5.3
Physical Dimensions
5.3.1
TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 11.6 x 8.0 x 1.2 mm
A
D1
D
eD
0.15
(2X)
C
10
9
8
SE
7
7
6
E
B
E1
5
4
3
2
1
eE
J
H
G
F
E
D
C
B
A
M
L K
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
C
C
A2
A
0.08
C
A1
SIDE VIEW
6
84X
b
0.15
0.08
M
C
C
A
B
M
NOTES:
PACKAGE
JEDEC
TLA 084
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
11.60 mm x 8.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
1.20
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.17
0.81
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.97
BODY THICKNESS
BODY SIZE
D
11.60 BSC.
8.00 BSC.
8.80 BSC.
7.20 BSC.
12
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
E1
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
84
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Ø b
eE
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SD / SE
SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9
B1,B10,C1,C10,D1,D10,
E1,E10,F1,F10,G1,G10,
H1,H10,J1,J10,K1,K10,L1,L10,
M2,M3,M4,M5,M6,M7,M8,M9
DEPOPULATED SOLDER BALLS
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3372-2 \ 16-038.22a
September 15, 2005 S71WS-N_01_A4
S71WS-Nx0 Based MCPs
17
A d v a n c e I n f o r m a t i o n
5.3.2
TSD084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 x 1.2 mm
A
D1
D
eD
0.15
(2X)
C
10
9
8
SE
7
7
6
E
B
E1
5
4
3
2
1
eE
J
H
G
F
E
D
C
B
A
M
L K
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
0.08
C
C
A2
A
C
A1
SIDE VIEW
6
84X
b
0.15
0.08
M
C
C
A
B
M
NOTES:
PACKAGE
JEDEC
TSD 084
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
12.00 mm x 9.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
---
1.20
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.17
0.81
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.94
BODY THICKNESS
BODY SIZE
D
12.00 BSC.
9.00 BSC.
8.80 BSC.
7.20 BSC.
12
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
84
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
φb
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eE
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
A2,A3,A4,A5,A6,7,A8,A9
B1,B10,C1,C10,D1,D10
E1,E10,F1,F10,G1,G10
H1,H10,J1,J10,K1,K10,L1,L10
M2,M3,M4,M5,M6,M7,M8,M9
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3426\ 16-038.22
18
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
A d v a n c e I n f o r m a t i o n
5.3.3
FEA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 x 1.4 mm
A
D1
D
eD
0.15
(2X)
C
10
9
8
SE
7
7
6
E
B
E1
5
4
3
2
1
eE
J
H
G
F
E
D
C
B
A
M
L K
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
C
C
A2
A
0.08
C
A1
SIDE VIEW
6
84X
0.15
b
M
C
C
A B
0.08
M
NOTES:
PACKAGE
JEDEC
FEA 084
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
12.00 mm x 9.00 mm
PACKAGE
NOTE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
1.40
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.10
1.11
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
1.26
BODY THICKNESS
BODY SIZE
D
12.00 BSC.
9.00 BSC.
8.80 BSC.
7.20 BSC.
12
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
E1
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
84
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Ø b
eE
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SD / SE
SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9
B1,B10,C1,C10,D1,D10
E1,E10,F1,F10,G1,G10
H1,H10,J1,J10,K1,K10,L1,L10
M2,M3,M4,M5,M6,M7,M8,M9
DEPOPULATED SOLDER BALLS
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3423 \ 16-038.21a
BSC is an ANSI standard for Basic Space Centering
September 15, 2005 S71WS-N_01_A4
S71WS-Nx0 Based MCPs
19
S29WS-N MirrorBitTM Flash Family
S29WS256N, S29WS128N
256/128 Megabit (16/8 M x 16 bit) CMOS 1.8 Volt-only
Simultaneous Read/Write, Burst-mode Flash Memory
ADVANCE
INFORMATION
General Description
The Spansion S29WS256/128 are MirrorbitTM Flash products fabricated on 110-nm process technology.
These burst mode Flash devices are capable of performing simultaneous read and write operations with
zero latency on two separate banks using separate data and address pins. These products can operate up
to 80 MHz and use a single VCC of 1.7 V to 1.95 V that makes them ideal for today’s demanding wireless
applications requiring higher density, better performance and lowered power consumption.
Distinctive Characteristics
Single 1.8 V read/program/erase (1.70–1.95 V)
110 nm MirrorBit™ Technology
Command set compatible with JEDEC (42.4)
standard
Hardware (WP#) protection of top and bottom
sectors
Simultaneous Read/Write operation with zero
latency
32-word Write Buffer
Dual boot sector configuration (top and bottom)
Low VCC write inhibit
Sixteen-bank architecture consisting of 16/8
Mwords for WS256N/128N, respectively
Persistent and Password methods of Advanced
Sector Protection
Four 16 Kword sectors at both top and bottom of
memory array
Write operation status bits indicate program and
erase operation completion
254/126 64 Kword sectors (WS256N/128N)
Programmable linear (8/16/32) with or without
wrap around and continuous burst read modes
Suspend and Resume commands for Program and
Erase operations
Secured Silicon Sector region consisting of 128
words each for factory and customer
Unlock Bypass program command to reduce
programming time
20-year data retention (typical)
Synchronous or Asynchronous program operation,
independent of burst control register settings
Cycling Endurance: 100,000 cycles per sector
(typical)
ACC input pin to reduce factory programming time
Support for Common Flash Interface (CFI)
RDY output indicates data available to system
Performance Characteristics
Read Access Times
Current Consumption (typical values)
Speed Option (MHz)
Max. Synch. Latency, ns (t
80
80
66
80
54
80
Continuous Burst Read @ 80 MHz
38 mA
50 mA
19 mA
19 mA
20 µA
)
Simultaneous Operation (asynchronous)
Program (asynchronous)
IACC
Max. Synch. Burst Access, ns (t
)
9
11.2
80
13.5
80
BACC
Max. Asynch. Access Time, ns (t
)
80
Erase (asynchronous)
ACC
Max CE# Access Time, ns (t
)
80
80
80
Standby Mode (asynchronous)
CE
Max OE# Access Time, ns (t
)
13.5
13.5
13.5
OE
Typical Program & Erase Times
Single Word Programming
Effective Write Buffer Programming (V ) Per Word
40 µs
9.4 µs
6 µs
CC
Effective Write Buffer Programming (V
Sector Erase (16 Kword Sector)
Sector Erase (64 Kword Sector)
) Per Word
ACC
150 ms
600 ms
Publication Number S71WS-N_01 Revision A Amendment 4 Issue Date September 15, 2005
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not
design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
A d v a n c e I n f o r m a t i o n
6 Input/Output Descriptions & Logic Symbol
Table 6.1 identifies the input and output package connections provided on the device.
Table 6.1 Input/Output Descriptions
Symbol
A23–A0
DQ15–DQ0
CE#
Type
Input
Description
Address lines for WS256N (A22-A0 for WS128).
Data input/output.
I/O
Input
Chip Enable. Asynchronous relative to CLK.
Output Enable. Asynchronous relative to CLK.
Write Enable.
OE#
Input
WE#
Input
V
Supply
I/O
Device Power Supply.
CC
SS
V
Ground.
NC
No Connect
Output
Not connected internally.
RDY
Ready. Indicates when valid burst data is ready to be read.
Clock Input. In burst mode, after the initial word is output, subsequent active edges of CLK
CLK
Input
increment the internal address counter. Should be at V or V while in asynchronous
IL IH
mode.
Address Valid. Indicates to device that the valid address is present on the address inputs.
When low during asynchronous mode, indicates valid address; when low during burst
mode, causes starting address to be latched at the next active clock edge.
AVD#
Input
When high, device ignores address inputs.
RESET#
WP#
Input
Input
Hardware Reset. Low = device resets and returns to reading array data.
Write Protect. At V , disables program and erase functions in the four outermost sectors.
IL
Should be at V for all other conditions.
IH
Acceleration Input. At V , accelerates programming; automatically places device in
HH
ACC
RFU
Input
unlock bypass mode. At V , disables all program and erase functions. Should be at V for
I
L
I
H
all other conditions.
Reserved
Reserved for future use (see MCP look-ahead pinout for use with MCP).
September 15, 2005 S71WS-N_01_A4
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A d v a n c e I n f o r m a t i o n
7 Block Diagram
DQ15–DQ0
V
V
CC
SS
RDY
Buffer
RDY
Input/Output
Buffers
Erase Voltage
Generator
WE#
RESET#
WP#
State
Control
ACC
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
CE#
OE#
Y-Decoder
Y-Gating
VCC
Detector
Timer
Cell Matrix
X-Decoder
Burst
State
Control
Burst
Address
Counter
AVD#
CLK
Amax–A0*
*
WS256N: A23-A0
WS128N: A22-A0
Figure 7.1 S29WS-N Block Diagram
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A d v a n c e I n f o r m a t i o n
8 Additional Resources
Visit www.amd.com and www.fujitsu.com to obtain the following related documents:
Application Notes
Using the Operation Status Bits in AMD Devices
Understanding Burst Mode Flash Memory Devices
Simultaneous Read/Write vs. Erase Suspend/Resume
MirrorBit™ Flash Memory Write Buffer Programming and Page Buffer Read
Design-In Scalable Wireless Solutions with Spansion Products
Common Flash Interface Version 1.4 Vendor Specific Extensions
Specification Bulletins
Contact your local sales office for details.
Drivers and Software Support
Spansion low-level drivers
Enhanced Flash drivers
Flash file system
CAD Modeling Support
VHDL and Verilog
IBIS
ORCAD
Technical Support
Contact your local sales office or contact Spansion LLC directly for additional technical support:
Email
US and Canada: HW.support@amd.com
Asia Pacific: asia.support@amd.com
Europe, Middle East, and Africa
Japan: http://edevice.fujitsu.com/jp/support/tech/#b7
Frequently Asked Questions (FAQ)
http://ask.amd.com/
http://edevice.fujitsu.com/jp/support/tech/#b7
Phone
US: (408) 749-5703
Japan (03) 5322-3324
Spansion LLC Locations
915 DeGuigne Drive, P.O. Box 3453
Sunnyvale, CA 94088-3453, USA
Telephone: 408-962-2500 or
1-866-SPANSION
Spansion Japan Limited
4-33-4 Nishi Shinjuku, Shinjuku-ku
Tokyo, 160-0023
Telephone: +81-3-5302-2200
Facsimile: +81-3-5302-2674
http://www.spansion.com
September 15, 2005 S71WS-N_01_A4
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A d v a n c e I n f o r m a t i o n
9 Product Overview
The S29WS-N family consists of 256, 128 Mbit, 1.8 volts-only, simultaneous read/write burst
mode Flash device optimized for today’s wireless designs that demand a large storage array, rich
functionality, and low power consumption.
These devices are organized in 16 or 8 Mwords of 16 bits each and are capable of continuous,
synchronous (burst) read or linear read (8-, 16-, or 32-word aligned group) with or without wrap
around. These products also offer single word programming or a 32-word buffer for programming
with program/erase and suspend functionality. Additional features include:
Advanced Sector Protection methods for protecting sectors as required
256 words of Secured Silicon area for storing customer and factory secured information. The
Secured Silicon Sector is One Time Programmable.
9.1
Memory Map
The S29WS256/128N Mbit devices consist of 16 banks organized as shown in Table 9.1–Table 9.2.
Table 9.1 S29WS256N Sector & Memory Address Map
Bank
Size
Sector
Count
Sector Size
(KB)
Sector/
Sector Range
Bank
Address Range
Notes
SA000
000000h–003FFFh
SA001
004000h–007FFFh
Contains four smaller sectors at
bottom of addressable memory.
4
32
2 MB
0
SA002
008000h–00BFFFh
SA003
00C000h–00FFFFh
15
16
16
16
16
16
16
16
16
16
16
16
16
16
16
15
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
SA004 to SA018
SA019 to SA034
SA035 to SA050
SA051 to SA066
SA067 to SA082
SA083 to SA098
SA099 to SA114
SA115 to SA130
SA131 to SA146
SA147 to SA162
SA163 to SA178
SA179 to SA194
SA195 to SA210
SA211 to SA226
SA227 to SA242
SA243 to SA257
SA258
010000h–01FFFFh to 0F0000h–0FFFFFh
100000h–10FFFFh to 1F0000h–1FFFFFh
200000h–20FFFFh to 2F0000h–2FFFFFh
300000h–30FFFFh to 3F0000h–3FFFFFh
400000h–40FFFFh to 4F0000h–4FFFFFh
500000h–50FFFFh to 5F0000h–5FFFFFh
600000h–60FFFFh to 6F0000h–6FFFFFh
700000h–70FFFFh to 7F0000h–7FFFFFh
800000h–80FFFFh to 8F0000h–8FFFFFh
900000h–90FFFFh to 9F0000h–9FFFFFh
A00000h–A0FFFFh to AF0000h–AFFFFFh
B00000h–B0FFFFh to BF0000h–BFFFFFh
C00000h–C0FFFFh to CF0000h–CFFFFFh
D00000h–D0FFFFh to DF0000h–DFFFFFh
E00000h–E0FFFFh to EF0000h–EFFFFFh
F00000h–F0FFFFh to FE0000h–FEFFFFh
FF0000h–FF3FFFh
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
1
2
3
4
5
6
All 128 KB sectors.
Pattern for sector address range
is xx0000h–xxFFFFh.
(see note)
7
8
9
10
11
12
13
14
2 MB
15
SA259
FF4000h–FF7FFFh
Contains four smaller sectors at
top of addressable memory.
4
32
SA260
FF8000h–FFBFFFh
SA261
FFC000h–FFFFFFh
Note: This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their
address ranges that are not explicitly listed (such as SA005–SA017) have sector starting and ending addresses that form the same
pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h–xxFFFFh.
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A d v a n c e I n f o r m a t i o n
Table 9.2 S29WS128N Sector & Memory Address Map
Sector
Count
Sector Size
(KB)
Sector/
Sector Range
Bank Size
Bank
Address Range
Notes
32
32
SA000
000000h–003FFFh
SA001
004000h–007FFFh
Contains four smaller sectors at
bottom of addressable memory.
4
1 MB
32
0
SA002
008000h–00BFFFh
32
SA003
00C000h–00FFFFh
7
8
8
8
8
8
8
8
8
8
8
8
8
8
8
7
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
32
SA004 to SA010
SA011 to SA018
SA019 to SA026
SA027 to SA034
SA035 to SA042
SA043 to SA050
SA051 to SA058
SA059 to SA066
SA067 to SA074
SA075 to SA082
SA083 to SA090
SA091 to SA098
SA099 to SA106
SA107 to SA114
SA115 to SA122
SA123 to SA129
SA130
010000h–01FFFFh to 070000h–07FFFFh
080000h–08FFFFh to 0F0000h–0FFFFFh
100000h–10FFFFh to 170000h–17FFFFh
180000h–18FFFFh to 1F0000h–1FFFFFh
200000h–20FFFFh to 270000h–27FFFFh
280000h–28FFFFh to 2F0000h–2FFFFFh
300000h–30FFFFh to 370000h–37FFFFh
380000h–38FFFFh to 3F0000h–3FFFFFh
400000h–40FFFFh to 470000h–47FFFFh
480000h–48FFFFh to 4F0000h–4FFFFFh
500000h–50FFFFh to 570000h–57FFFFh
580000h–58FFFFh to 5F0000h–5FFFFFh
600000h–60FFFFh to 670000h–67FFFFh
680000h–68FFFFh to 6F0000h–6FFFFFh
700000h–70FFFFh to 770000h–77FFFFh
780000h–78FFFFh to 7E0000h–7EFFFFh
7F0000h–7F3FFFh
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1
2
3
4
5
6
All 128 KB sectors.
Pattern for sector address range
is xx0000h–xxFFFFh.
(see note)
7
8
9
10
11
12
13
14
1 MB
32
15
SA131
7F4000h–7F7FFFh
Contains four smaller sectors at
top of addressable memory.
4
32
SA132
7F8000h–7FBFFFh
32
SA133
7FC000h–7FFFFFh
Note: This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their
address ranges that are not explicitly listed (such as SA005–SA009) have sector starting and ending addresses that form the same
pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h–xxFFFFh.
September 15, 2005 S71WS-N_01_A4
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A d v a n c e I n f o r m a t i o n
10 Device Operations
This section describes the read, program, erase, simultaneous read/write operations, handshak-
ing, and reset features of the Flash devices.
Operations are initiated by writing specific commands or a sequence with specific address and
data patterns into the command registers (see Tables 15.1 and 15.2). The command register itself
does not occupy any addressable memory location; rather, it is composed of latches that store
the commands, along with the address and data information needed to execute the command.
The contents of the register serve as input to the internal state machine and the state machine
outputs dictate the function of the device. Writing incorrect address and data values or writing
them in an improper sequence may place the device in an unknown state, in which case the sys-
tem must write the reset command to return the device to the reading array data mode.
10.1 Device Operation Table
The device must be setup appropriately for each operation. Table 10.1 describes the required
state of each control pin for any particular operation.
Table 10.1 Device Operations
Operation
CE#
L
OE#
L
WE#
Addresses
Addr In
Addr In
Addr In
Addr In
X
DQ15–0
Data Out
Data Out
I/O
RESET#
CLK
X
AVD#
Asynchronous Read - Addresses Latched
Asynchronous Read - Addresses Steady State
Asynchronous Write
H
H
L
H
H
H
H
H
L
L
L
X
L
L
L
H
X
Synchronous Write
L
H
L
I/O
Standby (CE#)
H
X
X
X
X
HIGH Z
HIGH Z
X
X
X
X
Hardware Reset
X
X
Burst Read Operations (Synchronous)
Load Starting Burst Address
L
L
X
L
H
H
Addr In
X
X
H
H
Advance Burst to next address with appropriate
Data presented on the Data Bus
Burst
Data Out
H
Terminate current Burst read cycle
H
X
X
X
H
H
X
X
HIGH Z
HIGH Z
H
L
X
X
Terminate current Burst read cycle via RESET#
X
Terminate current Burst read cycle and start new
Burst read cycle
L
X
H
Addr In
I/O
H
Legend: L = Logic 0, H = Logic 1, X = Don’t Care, I/O = Input/Output.
10.2 Asynchronous Read
All memories require access time to output array data. In an asynchronous read operation, data
is read from one memory location at a time. Addresses are presented to the device in random
order, and the propagation delay through the device causes the data on its outputs to arrive asyn-
chronously with the address on its inputs.
The device defaults to reading array data asynchronously after device power-up or hardware re-
set. To read data from the memory array, the system must first assert a valid address on Amax
–
A0, while driving AVD# and CE# to VIL. WE# must remain at VIH. The rising edge of AVD# latches
the address. The OE# signal must be driven to VIL, once AVD# has been driven to VIH. Data is
output on A/DQ15-A/DQ0 pins after the access time (tOE) has elapsed from the falling edge of
OE#.
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A d v a n c e I n f o r m a t i o n
10.3 Synchronous (Burst) Read Mode & Configuration Register
When a series of adjacent addresses needs to be read from the device (in order from lowest to
highest address), the synchronous (or burst read) mode can be used to significantly reduce the
overall time needed for the device to output array data. After an initial access time required for
the data from the first address location, subsequent data is output synchronized to a clock input
provided by the system.
The device offers both continuous and linear methods of burst read operation, which are dis-
cussed in subsections 10.3.4 and 10.3.5, and 10.3.6.
Since the device defaults to asynchronous read mode after power-up or a hardware reset, the
configuration register must be set to enable the burst read mode. Other Configuration Register
settings include the number of wait states to insert before the initial word (tIACC) of each burst
access, the burst mode in which to operate, and when RDY indicates data is ready to be read.
Prior to entering the burst mode, the system should first determine the configuration register set-
tings (and read the current register settings if desired via the Read Configuration Register
command sequence), and then write the configuration register command sequence. See Section
10.3.7, Configuration Register, and Table 15.1, Memory Array Commands for further details.
Power-up/
Hardware Reset
Asynchronous Read
Mode Only
Set Burst Mode
Configuration Register
Command for
Set Burst Mode
Configuration Register
Command for
Synchronous Mode
(CR15 = 0)
Asynchronous Mode
(CR15 = 1)
Synchronous Read
Mode Only
Figure 10.1 Synchronous/Asynchronous State Diagram
The device outputs the initial word subject to the following operational conditions:
tIACC specification: the time from the rising edge of the first clock cycle after addresses are
latched to valid data on the device outputs.
configuration register setting CR13–CR11: the total number of clock cycles (wait states)
that occur before valid data appears on the device outputs. The effect is that tIACC is
lengthened.
The device outputs subsequent words tBACC after the active edge of each successive clock cycle,
which also increments the internal address counter. The device outputs burst data at this rate sub-
ject to the following operational conditions:
September 15, 2005 S71WS-N_01_A4
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A d v a n c e I n f o r m a t i o n
starting address: whether the address is divisible by four (where A[1:0] is 00). A divisible-
by-four address incurs the least number of additional wait states that occur after the initial
word. The number of additional wait states required increases for burst operations in which
the starting address is one, two, or three locations above the divisible-by-four address (i.e.,
where A[1:0] is 01, 10, or 11).
boundary crossing: There is a boundary at every 128 words due to the internal architecture
of the device. One additional wait state must be inserted when crossing this boundary if the
memory bus is operating at a high clock frequency. Please refer to the tables below.
clock frequency: the speed at which the device is expected to burst data. Higher speeds
require additional wait states after the initial word for proper operation.
In all cases, with or without latency, the RDY output indicates when the next data is available to
be read.
Tables 10.2-10.7 reflect wait states required for S29WS256/128N devices. Refer to the “Config-
uration Register” table (CR11 - CR14) and timing diagrams for more details.
Table 10.2 Address Latency (S29WS256N)
Word
Wait States
Cycle
0
1
2
3
x ws
D0
D1
D2
D3
D1
D2
D2
D3
D3
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
D8
D8
D8
D8
x ws
1 ws
1 ws
1 ws
D4
x ws
D3
1 ws
1 ws
D4
x ws
1 ws
D4
Table 10.3 Address Latency (S29WS128N)
Word
Wait States
5, 6, 7 ws
5, 6, 7 ws
5, 6, 7 ws
5, 6, 7 ws
Cycle
0
1
2
3
D0
D1
D2
D3
D1
D2
D2
D3
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
D8
D8
D8
D8
1 ws
1 ws
1 ws
D3
1 ws
1 ws
1 ws
Table 10.4 Address/Boundary Crossing Latency (S29WS256N @ 80MHz)
Word
Wait States
Cycle
1 ws
1 ws
1 ws
1 ws
0
1
2
3
7 ws
D0
D1
D2
D3
D1
D2
D2
D3
D3
1 ws
1 ws
1 ws
1 ws
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
7 ws
1 ws
1 ws
1 ws
7 ws
D3
1 ws
1 ws
7 ws
1 ws
Table 10.5 Address/Boundary Crossing Latency (S29WS256N @ 66 MHz)
Word
Wait States
Cycle
1 ws
1 ws
1 ws
1 ws
0
1
2
3
6 ws
D0
D1
D2
D3
D1
D2
D2
D3
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
6 ws
1 ws
1 ws
1 ws
6 ws
D3
1 ws
1 ws
6 ws
1 ws
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A d v a n c e I n f o r m a t i o n
Table 10.6 Address/Boundary Crossing Latency (S29WS256N @ 54MHz)
Word
Wait States
Cycle
0
1
2
3
5 ws
D0
D1
D2
D3
D1
D2
D2
D3
D3
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
D8
D8
D8
D8
5 ws
1 ws
1 ws
1 ws
D4
5 ws
D3
1 ws
1 ws
D4
5 ws
1 ws
D4
Table 10.7 Address/Boundary Crossing Latency (S29WS128N)
Word
Wait States
5, 6, 7 ws
5, 6, 7 ws
5, 6, 7 ws
5, 6, 7 ws
Cycle
1 ws
1 ws
1 ws
1 ws
0
1
2
3
D0
D1
D2
D3
D1
D2
D2
D3
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
1 ws
1 ws
1 ws
D3
1 ws
1 ws
1 ws
Note: Setup Configuration Register parameters
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Set Configuration Register
Command and Settings:
Address 555h, Data D0h
Address X00h, Data CR
Command Cycle
CR = Configuration Register Bits CR15-CR0
Load Initial Address
Address = RA
RA = Read Address
Read Initial Data
RD = DQ[15:0]
RD = Read Data
Wait X Clocks:
Refer to the Latency tables.
Additional Latency Due to Starting
Address, Clock Frequency, and
Boundary Crossing
Read Next Data
RD = DQ[15:0]
No
Delay X Clocks
Crossing
Boundary?
No
End of Data?
Yes
Yes
Completed
Figure 10.2 Synchronous Read
September 15, 2005 S71WS-N_01_A4
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A d v a n c e I n f o r m a t i o n
10.3.4 Continuous Burst Read Mode
In the continuous burst read mode, the device outputs sequential burst data from the starting
address given and then wrap around to address 000000h when it reaches the highest addressable
memory location. The burst read mode continues until the system drives CE# high, or RESET=
VIL. Continuous burst mode can also be aborted by asserting AVD# low and providing a new ad-
dress to the device.
If the address being read crosses a 128-word line boundary (as mentioned above) and the sub-
sequent word line is not being programmed or erased, additional latency cycles are required as
reflected by the configuration register table (Table 10.9).
If the address crosses a bank boundary while the subsequent bank is programming or erasing,
the device provides read status information and the clock is ignored. Upon completion of status
read or program or erase operation, the host can restart a burst read operation using a new ad-
dress and AVD# pulse.
10.3.5 8-, 16-, 32-Word Linear Burst Read with Wrap Around
In a linear burst read operation, a fixed number of words (8, 16, or 32 words) are read from con-
secutive addresses that are determined by the group within which the starting address falls. The
groups are sized according to the number of words read in a single burst sequence for a given
mode (see Table 10.8).
For example, if the starting address in the 8-word mode is 3Ch, the address range to be read
would be 38-3Fh, and the burst sequence would be 3C-3D-3E-3F-38-39-3A-3Bh. Thus, the device
outputs all words in that burst address group until all word are read, regardless of where the start-
ing address occurs in the address group, and then terminates the burst read.
In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on
the starting address provided to the device, then wrap back to the first address in the selected
address group.
Note that in this mode the address pointer does not cross the boundary that occurs every 128
words; thus, no additional wait states are inserted due to boundary crossing.
Table 10.8 Burst Address Groups
Mode
Group Size
8 words
Group Address Ranges
0-7h, 8-Fh, 10-17h,...
0-Fh, 10-1Fh, 20-2Fh,...
00-1Fh, 20-3Fh, 40-5Fh,...
8-word
16-word
32-word
16 words
32 words
10.3.6 8-, 16-, 32-Word Linear Burst without Wrap Around
If wrap around is not enabled for linear burst read operations, the 8-word, 16-word, or 32-word
burst executes up to the maximum memory address of the selected number of words. The burst
stops after 8, 16, or 32 addresses and does not wrap around to the first address of the selected
group.
For example, if the starting address in the 8- word mode is 3Ch, the address range to be read
would be 39-40h, and the burst sequence would be 3C-3D-3E-3F-40-41-42-43h if wrap around
is not enabled. The next address to be read requires a new address and AVD# pulse. Note that
in this burst read mode, the address pointer may cross the boundary that occurs every 128 words,
which will incur the additional boundary crossing wait state.
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10.3.7 Configuration Register
The configuration register sets various operational parameters associated with burst mode. Upon
power-up or hardware reset, the device defaults to the asynchronous read mode, and the config-
uration register settings are in their default state. The host system should determine the proper
settings for the entire configuration register, and then execute the Set Configuration Register
command sequence, before attempting burst operations. The configuration register is not reset
after deasserting CE#. The Configuration Register can also be read using a command sequence
(see Table 15.1). The following list describes the register settings.
Table 10.9 Configuration Register
CR Bit
Function
Settings (Binary)
Set Device Read
Mode
0 = Synchronous Read (Burst Mode) Enabled
1 = Asynchronous Read Mode (default) Enabled
CR15
1 = S29WS256N at 6 or 7 Wait State setting
0 = All others
CR14
Reserved
54 MHz
66 Mhz
80 MHz
S29WS128N
S29WS256N
S29WS128N
S29WS256N
S29WS128N
011 = Data valid on 5th active CLK edge after addresses
CR13
CR12
0
1
1
latched
100 = Data valid on 6th active CLK edge after addresses
latched
101 = Data valid on 7th active CLK edge after addresses
latched (default)
110 = Reserved
111 = Reserved
1
1
0
0
0
1
Programmable
Wait State
Inserts wait states before initial data is available. Setting
greater number of wait states before initial data reduces
latency after initial data.
CR11
S29WS256N
(Notes 1, 2)
0 = RDY signal active low
CR10
CR9
RDY Polarity
Reserved
1 = RDY signal active high (default)
1 = default
0 = RDY active one clock cycle before data
1 = RDY active with data (default)
When CR13-CR11 are set to 000, RDY is active with data
regardless of CR8 setting.
CR8
RDY
CR7
CR6
CR5
CR4
Reserved
Reserved
Reserved
Reserved
1 = default
1 = default
0 = default
0 = default
0 = No Wrap Around Burst
1 = Wrap Around Burst (default)
CR3
Burst Wrap Around
000 = Continuous (default)
010 = 8-Word Linear Burst
011 = 16-Word Linear Burst
100 = 32-Word Linear Burst
(All other bit settings are reserved)
CR2
CR1
CR0
Burst Length
Notes:
1. Refer to Tables 10.2 - 10.7 for wait states requirements.
2. Refer to Synchronous Burst Read timing diagrams
3. Configuration Register is in the default state upon power-up or hardware reset.
Reading the Configuration Table. The configuration register can be read with a four-cycle com-
mand sequence. See Table 15.1 for sequence details. Once the data has been read from the
configuration register, a software reset command is required to set the device into the correct
state.
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10.4 Autoselect
The Autoselect is used for manufacturer ID, Device identification, and sector protection informa-
tion. This mode is primarily intended for programming equipment to automatically match a device
with its corresponding programming algorithm. The Autoselect codes can also be accessed in-sys-
tem. When verifying sector protection, the sector address must appear on the appropriate highest
order address bits (see Table 10.10). The remaining address bits are don't care. The most signif-
icant four bits of the address during the third write cycle selects the bank from which the
Autoselect codes are read by the host. All other banks can be accessed normally for data read
without exiting the Autoselect mode.
To access the Autoselect codes, the host system must issue the Autoselect command.
The Autoselect command sequence may be written to an address within a bank that is either
in the read or erase-suspend-read mode.
The Autoselect command may not be written while the device is actively programming or
erasing. Autoselect does not support simultaneous operations or burst mode.
The system must write the reset command to return to the read mode (or erase-suspend-
read mode if the bank was previously in Erase Suspend).
See Table 15.1 for command sequence details.
Table 10.10 Autoselect Addresses
Description
Manufacturer ID
Device ID, Word 1
Address
Read Data
(BA) + 00h 0001h
(BA) + 01h 227Eh
2230 (WS256N)
2231 (WS128N)
(BA) + 0Fh 2200
DQ15 - DQ8 = Reserved
Device ID, Word 2
Device ID, Word 3
(BA) + 0Eh
DQ7 (Factory Lock Bit): 1 = Locked, 0 = Not Locked
DQ6 (Customer Lock Bit): 1 = Locked, 0 = Not Locked
DQ5 (Handshake Bit): 1 = Reserved, 0 = Standard Handshake
DQ4, DQ3 (WP# Protection Boot Code): 00 = WP# Protects both Top Boot and
Bottom Boot Sectors. 01, 10, 11 = Reserved
Indicator Bits
(See Note)
(BA) + 03h
DQ2 = Reserved
DQ1 (DYB Power up State [Lock Register DQ4]): 1 = Unlocked (user option),
0 = Locked (default)
DQ0 (PPB Eraseability [Lock Register DQ3]): 1 = Erase allowed,
0 = Erase disabled
Sector Block Lock/
Unlock
(SA) + 02h 0001h = Locked, 0000h = Unlocked
Note: For WS128N and WS064, DQ1 and DQ0 are reserved.
Table 10.11 Autoselect Entry
(LLD Function = lld_AutoselectEntryCmd)
Cycle
Operation
Write
Byte Address
BAxAAAh
BAx555h
Word Address
BAx555h
Data
Unlock Cycle 1
Unlock Cycle 2
Autoselect Command
0x00AAh
0x0055h
0x0090h
Write
BAx2AAh
Write
BAxAAAh
BAx555h
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Table 10.12 Autoselect Exit
(LLD Function = lld_AutoselectExitCmd)
Cycle
Operation
Write
Byte Address
Word Address
base + XXXh
Data
Unlock Cycle 1
base + XXXh
0x00F0h
Notes:
1. Any offset within the device works.
2. BA = Bank Address. The bank address is required.
3. base = base address.
The following is a C source code example of using the autoselect function to read the manufac-
turer ID. Refer to the Spansion Low Level Driver User’s Guide (available on www.amd.com and
www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
/* Here is an example of Autoselect mode (getting manufacturer ID) */
/* Define UINT16 example: typedef unsigned short UINT16; */
UINT16 manuf_id;
/* Auto Select Entry */
*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */
/* multiple reads can be performed after entry */
manuf_id = *( (UINT16 *)bank_addr + 0x000 ); /* read manuf. id */
/* Autoselect exit */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* exit autoselect (write reset command) */
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10.5 Program/Erase Operations
These devices are capable of several modes of programming and or erase operations which are
described in detail in the following sections. However, prior to any programming and or erase op-
eration, devices must be setup appropriately as outlined in the configuration register (Table 10.8).
For any program and or erase operations, including writing command sequences, the system
must drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the device, and
drive WE# and CE# to VIL, and OE# to VIH when writing commands or programming data.
Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st
rising edge of WE# or CE#.
Note the following:
When the Embedded Program algorithm is complete, the device returns to the read mode.
The system can determine the status of the program operation by using DQ7 or DQ6. Refer
to the Write Operation Status section for information on these status bits.
A “0” cannot be programmed back to a “1.” Attempting to do so causes the device to set DQ5
= 1 (halting any further operation and requiring a reset command). A succeeding read shows
that the data is still “0.” Only erase operations can convert a “0” to a “1.”
Any commands written to the device during the Embedded Program Algorithm are ignored
except the Program Suspend command.
Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program oper-
ation is in progress.
A hardware reset immediately terminates the program operation and the program command
sequence should be reinitiated once the device has returned to the read mode, to ensure data
integrity.
Programming is allowed in any sequence and across sector boundaries for single word pro-
gramming operation.
10.5.1 Single Word Programming
Single word programming mode is the simplest method of programming. In this mode, four Flash
command write cycles are used to program an individual Flash address. The data for this pro-
gramming operation could be 8-, 16- or 32-bits wide. While this method is supported by all
Spansion devices, in general it is not recommended for devices that support Write Buffer Pro-
gramming. See Table 15.1 for the required bus cycles and Figure 10.3 for the flowchart.
When the Embedded Program algorithm is complete, the device then returns to the read mode
and addresses are no longer latched. The system can determine the status of the program oper-
ation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these
status bits.
During programming, any command (except the Suspend Program command) is ignored.
The Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program op-
eration is in progress.
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A hardware reset immediately terminates the program operation. The program command se-
quence should be reinitiated once the device has returned to the read mode, to ensure data
integrity.
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Program Command:
Address 555h, Data A0h
Setup Command
Program Address (PA),
Program Data (PD)
Program Data to Address:
PA, PD
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Polling Status
= Busy?
No
Yes
Polling Status
= Done?
Error condition
No
(Exceeded Timing Limits)
PASS. Device is in
read mode.
FAIL. Issue reset command
to return to read array mode.
Figure 10.3 Single Word Program
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Table 10.13 Software Functions and Sample Code
Cycle
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Word Address
Data
00AAh
Unlock Cycle 1
Unlock Cycle 2
Program Setup
Program
Write
0055h
Write
00A0h
Write
Data Word
Note: Base = Base Address.
The following is a C source code example of using the single word program function. Refer to
the Spansion Low Level Driver User’s Guide (available on www.amd.com and
www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
/* Example: Program Command
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x00A0;
/* write unlock cycle 1
/* write unlock cycle 2
/* write program setup command
/* write data to be programmed
*/
*/
*/
*/
*( (UINT16 *)pa )
= data;
/* Poll for program completion */
10.5.2 Write Buffer Programming
Write Buffer Programming allows the system to write a maximum of 32 words in one program-
ming operation. This results in a faster effective word programming time than the standard
“word” programming algorithms. The Write Buffer Programming command sequence is initiated
by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer
Load command written at the Sector Address in which programming occurs. At this point, the sys-
tem writes the number of “word locations minus 1” that are loaded into the page buffer at the
Sector Address in which programming occurs. This tells the device how many write buffer ad-
dresses are loaded with data and therefore when to expect the “Program Buffer to Flash” confirm
command. The number of locations to program cannot exceed the size of the write buffer or the
operation aborts. (Number loaded = the number of locations to program minus 1. For example,
if the system programs 6 address locations, then 05h should be written to the device.)
The system then writes the starting address/data combination. This starting address is the first
address/data pair to be programmed, and selects the “write-buffer-page” address. All subsequent
address/data pairs must fall within the elected-write-buffer-page.
The “write-buffer-page” is selected by using the addresses AMAX - A5.
The “write-buffer-page” addresses must be the same for all address/data pairs loaded into the
write buffer. (This means Write Buffer Programming cannot be performed across multiple “write-
buffer-pages.” This also means that Write Buffer Programming cannot be performed across mul-
tiple sectors. If the system attempts to load programming data outside of the selected “write-
buffer-page”, the operation ABORTs.)
After writing the Starting Address/Data pair, the system then writes the remaining address/data
pairs into the write buffer.
Note that if a Write Buffer address location is loaded multiple times, the “address/data pair”
counter is decremented for every data load operation. Also, the last data loaded at a location be-
fore the “Program Buffer to Flash” confirm command is programmed into the device. It is the
software's responsibility to comprehend ramifications of loading a write-buffer location more than
once. The counter decrements for each data load operation, NOT for each unique write-buffer-
address location. Once the specified number of write buffer locations have been loaded, the sys-
tem must then write the “Program Buffer to Flash” command at the Sector Address. Any other
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address/data write combinations abort the Write Buffer Programming operation. The device goes
“busy.” The Data Bar polling techniques should be used while monitoring the last address location
loaded into the write buffer. This eliminates the need to store an address in memory because the
system can load the last address location, issue the program confirm command at the last loaded
address location, and then data bar poll at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1
should be monitored to determine the device status during Write Buffer Programming.
The write-buffer “embedded” programming operation can be suspended using the standard sus-
pend/resume commands. Upon successful completion of the Write Buffer Programming operation,
the device returns to READ mode.
The Write Buffer Programming Sequence is ABORTED under any of the following conditions:
Load a value that is greater than the page buffer size during the “Number of Locations to Pro-
gram” step.
Write to an address in a sector different than the one specified during the Write-Buffer-Load
command.
Write an Address/Data pair to a different write-buffer-page than the one selected by the
“Starting Address” during the “write buffer data loading” stage of the operation.
Write data other than the “Confirm Command” after the specified number of “data load” cy-
cles.
The ABORT condition is indicated by DQ1 = 1, DQ7 = DATA# (for the “last address location
loaded”), DQ6 = TOGGLE, DQ5 = 0. This indicates that the Write Buffer Programming Operation
was ABORTED. A “Write-to-Buffer-Abort reset” command sequence is required when using the
write buffer Programming features in Unlock Bypass mode. Note that the Secured Silicon sector,
autoselect, and CFI functions are unavailable when a program operation is in progress.
Write buffer programming is allowed in any sequence of memory (or address) locations. These
flash devices are capable of handling multiple write buffer programming operations on the same
write buffer address range without intervening erases.
Use of the write buffer is strongly recommended for programming when multiple words are to be
programmed. Write buffer programming is approximately eight times faster than programming
one word at a time.
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Table 10.14 Software Functions and Sample Code
Cycle
Description
Unlock
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Word Address
Base + 555h
Base + 2AAh
Data
00AAh
1
2
3
4
Unlock
Write
0055h
Write Buffer Load Command
Write Word Count
Write
Program Address
Program Address
0025h
Write
Word Count (N–1)h
Number of words (N) loaded into the write buffer can be from 1 to 32 words.
5 to 36
Last
Load Buffer Word N
Write Buffer to Flash
Write
Write
Program Address, Word N
Sector Address
Word N
0029h
Notes:
1. Base = Base Address.
2. Last = Last cycle of write buffer program operation; depending on number of words written, the total
number of cycles may be from 6 to 37.
3. For maximum efficiency, it is recommended that the write buffer be loaded with
the highest number of words (N words) possible.
The following is a C source code example of using the write buffer program function. Refer to
the Spansion Low Level Driver User’s Guide (available on www.amd.com and
www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
/* Example: Write Buffer Programming Command
*/
/* NOTES: Write buffer programming limited to 16 words. */
/*
/*
/*
/*
All addresses to be written to the flash in
one operation must be within the same flash
page. A flash page begins at addresses
evenly divisible by 0x20.
*/
*/
*/
*/
UINT16 *src = source_of_data;
UINT16 *dst = destination_of_data;
/* address of source data
/* flash destination address
/* word count (minus 1)
/* write unlock cycle 1
/* write unlock cycle 2
*/
*/
*/
*/
*/
UINT16 wc
= words_to_program -1;
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)sector_address )
*( (UINT16 *)sector_address )
= 0x0025;
= wc;
/* write write buffer load command */
/* write word count (minus 1) */
loop:
*dst = *src; /* ALL dst MUST BE SAME PAGE */ /* write source data to destination */
dst++;
src++;
/* increment destination pointer
/* increment source pointer
*/
*/
if (wc == 0) goto confirm
wc--;
goto loop;
/* done when word count equals zero */
/* decrement word count
/* do it again
*/
*/
confirm:
*( (UINT16 *)sector_address )
/* poll for completion */
= 0x0029;
/* write confirm command
*/
/* Example: Write Buffer Abort Reset */
*( (UINT16 *)addr + 0x555 ) = 0x00AA;
*( (UINT16 *)addr + 0x2AA ) = 0x0055;
*( (UINT16 *)addr + 0x555 ) = 0x00F0;
/* write unlock cycle 1
/* write unlock cycle 2
/* write buffer abort reset
*/
*/
*/
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Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Issue
Write Buffer Load Command:
Address 555h, Data 25h
Load Word Count to Program
Program Data to Address:
SA = wc
wc = number of words – 1
Yes
Confirm command:
wc = 0?
No
SA = 0x29h
Wait 4 µs
(Recommended)
Write Next Word,
Decrement wc:
PA data , wc = wc – 1
No
Write Buffer
Abort Desired?
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Write to a Different
Sector Address to Cause
Write Buffer Abort
Yes
Polling Status
= Done?
No
Error?
Yes
No
Yes
Write Buffer
Abort?
No
RESET. Issue Write Buffer
Abort Reset Command
PASS. Device is in
read mode.
FAIL. Issue reset command
to return to read array mode.
Figure 10.4 Write Buffer Programming Operation
10.5.3 Sector Erase
The sector erase function erases one or more sectors in the memory array. (See Table 15.1,
Memory Array Commands; and Figure 10.5, Sector Erase Operation.) The device does not re-
quire the system to preprogram prior to erase. The Embedded Erase algorithm automatically
programs and verifies the entire memory for an all zero data pattern prior to electrical erase. After
a successful sector erase, all locations within the erased sector contain FFFFh. The system is not
required to provide any controls or timings during these operations.
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After the command sequence is written, a sector erase time-out of no less than tSEA occurs. Dur-
ing the time-out period, additional sector addresses and sector erase commands may be written.
Loading the sector erase buffer may be done in any sequence, and the number of sectors may be
from one sector to all sectors. The time between these additional cycles must be less than tSEA
.
Any sector erase address and command following the exceeded time-out (tSEA) may or may not
be accepted. Any command other than Sector Erase or Erase Suspend during the time-out period
resets that bank to the read mode. The system can monitor DQ3 to determine if the sector erase
timer has timed out (See the DQ3: Sector Erase Timeout State Indicator section.) The time-out
begins from the rising edge of the final WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading array data and ad-
dresses are no longer latched. Note that while the Embedded Erase operation is in progress, the
system can read data from the non-erasing banks. The system can determine the status of the
erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. Refer to Write Operation Status
for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other
commands are ignored. However, note that a hardware reset immediately terminates the erase
operation. If that occurs, the sector erase command sequence should be reinitiated once that
bank has returned to reading array data, to ensure data integrity.
Figure 10.5 illustrates the algorithm for the erase operation. Refer to the Erase and Programming
Performance section for parameters and timing diagrams.
Table 10.15 Software Functions and Sample Code
Cycle
Description
Unlock
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Base + AAAh
Base + 554h
Sector Address
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Base + 555h
Base + 2AAh
Sector Address
Data
1
2
3
4
5
6
00AAh
0055h
0080h
00AAh
0055h
0030h
Unlock
Write
Setup Command
Unlock
Write
Write
Unlock
Write
Sector Erase Command
Write
Unlimited additional sectors may be selected for erase; command(s) must be written within tSEA
.
The following is a C source code example of using the sector erase function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Sector Erase Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0080;
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
/* write unlock cycle 1
/* write unlock cycle 2
/* write setup command
/* write additional unlock cycle 1 */
/* write additional unlock cycle 2 */
*/
*/
*/
*( (UINT16 *)sector_address )
= 0x0030;
/* write sector erase command
*/
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Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Sector Erase Cycles:
Address 555h, Data 80h
Address 555h, Data AAh
Address 2AAh, Data 55h
Sector Address, Data 30h
Command Cycle 1
Command Cycle 2
Command Cycle 3
Specify first sector for erasure
Select
Additional
Sectors?
No
Yes
Write Additional
Sector Addresses
• Each additional cycle must be written within tSEA timeout
• Timeout resets after each additional cycle is written
• The host system may monitor DQ3 or wait tSEA to ensure
acceptance of erase commands
Yes
Last Sector
Selected?
No
• No limit on number of sectors
Poll DQ3.
DQ3 = 1?
• Commands other than Erase Suspend or selecting
additional sectors for erasure during timeout reset device
to reading array data
No
Yes
Wait 4 µs
(Recommended)
Perform Write Operation
Status Algorithm
Status may be obtained by reading DQ7, DQ6 and/or DQ2.
(see Figure 10.6)
Yes
Done?
No
No
Error condition (Exceeded Timing Limits)
DQ5 = 1?
Yes
PASS. Device returns
to reading array.
FAIL. Write reset command
to return to reading array.
Notes:
1. See Table 15.1 for erase command sequence.
2. See the section on DQ3 for information on the sector erase timeout.
Figure 10.5 Sector Erase Operation
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10.5.4 Chip Erase Command Sequence
Chip erase is a six-bus cycle operation as indicated by Table 15.1. These commands invoke the
Embedded Erase algorithm, which does not require the system to preprogram prior to erase. The
Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all
zero data pattern prior to electrical erase. After a successful chip erase, all locations of the chip
contain FFFFh. The system is not required to provide any controls or timings during these oper-
ations. The “Command Definition” section in the appendix shows the address and data
requirements for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read mode and ad-
dresses are no longer latched. The system can determine the status of the erase operation by
using DQ7 or DQ6/DQ2. Refer to “Write Operation Status” for information on these status bits.
Any commands written during the chip erase operation are ignored. However, note that a hard-
ware reset immediately terminates the erase operation. If that occurs, the chip erase command
sequence should be reinitiated once that bank has returned to reading array data, to ensure data
integrity.
Table 10.16 Software Functions and Sample Code
Cycle
Description
Unlock
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Base + 555h
Base + 2AAh
Base + 555h
Data
1
2
3
4
5
6
00AAh
0055h
0080h
00AAh
0055h
0010h
Unlock
Write
Setup Command
Unlock
Write
Write
Unlock
Write
Chip Erase Command
Write
The following is a C source code example of using the chip erase function. Refer to the Span-
sion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for
general information on Spansion Flash memory software development guidelines.
/* Example: Chip Erase Command */
/* Note: Cannot be suspended
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0080;
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x000 ) = 0x0010;
/* write unlock cycle 1
/* write unlock cycle 2
/* write setup command
/* write additional unlock cycle 1 */
/* write additional unlock cycle 2 */
*/
*/
*/
/* write chip erase command
*/
10.5.5 Erase Suspend/Erase Resume Commands
When the Erase Suspend command is written during the sector erase time-out, the device imme-
diately terminates the time-out period and suspends the erase operation. The Erase Suspend
command allows the system to interrupt a sector erase operation and then read data from, or
program data to, any sector not selected for erasure. The bank address is required when writing
this command. This command is valid only during the sector erase operation, including the min-
imum tSEA time-out period during the sector erase command sequence. The Erase Suspend
command is ignored if written during the chip erase operation.
When the Erase Suspend command is written after the tSEA time-out period has expired and dur-
ing the sector erase operation, the device requires a maximum of tESL (erase suspend latency) to
suspend the erase operation. Additionaly, when an Erase Suspend command is written during an
active erase operation, status information is unavailable during the transition from the sector
erase operation to the erase suspended state.
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After the erase operation has been suspended, the bank enters the erase-suspend-read mode.
The system can read data from or program data to any sector not selected for erasure. (The de-
vice “erase suspends” all sectors selected for erasure.) Reading at any address within erase-
suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6,
and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to
Table 10.20 for information on these status bits.
After an erase-suspended program operation is complete, the bank returns to the erase-suspend-
read mode. The system can determine the status of the program operation using the DQ7 or DQ6
status bits, just as in the standard program operation.
In the erase-suspend-read mode, the system can also issue the Autoselect command sequence.
Refer to the “Write Buffer Programming Operation” section and the “Autoselect Command Se-
quence” section for details.
To resume the sector erase operation, the system must write the Erase Resume command. The
bank address of the erase-suspended bank is required when writing this command. Further writes
of the Resume command are ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.
Table 10.17 Software Functions and Sample Code
Cycle
Operation
Byte Address
Word Address
Data
1
Write
Bank Address
Bank Address
00B0h
The following is a C source code example of using the erase suspend function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Erase suspend command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x00B0;
/* write suspend command
*/
Cycle
Operation
Byte Address
Word Address
Data
1
Write
Bank Address
Bank Address
0030h
The following is a C source code example of using the erase resume function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Erase resume command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x0030;
/* write resume command
*/
/* The flash needs adequate time in the resume state */
10.5.6 Program Suspend/Program Resume Commands
The Program Suspend command allows the system to interrupt an embedded programming op-
eration or a “Write to Buffer” programming operation so that data can read from any non-
suspended sector. When the Program Suspend command is written during a programming pro-
cess, the device halts the programming operation within tPSL (program suspend latency) and
updates the status bits. Addresses are “don't-cares” when writing the Program Suspend
command.
After the programming operation has been suspended, the system can read array data from any
non-suspended sector. The Program Suspend command may also be issued during a program-
ming operation while an erase is suspended. In this case, data may be read from any addresses
not in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector
area, then user must use the proper command sequences to enter and exit this region.
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The system may also write the Autoselect command sequence when the device is in Program Sus-
pend mode. The device allows reading Autoselect codes in the suspended sectors, since the codes
are not stored in the memory array. When the device exits the Autoselect mode, the device re-
verts to Program Suspend mode, and is ready for another valid operation. See “Autoselect
Command Sequence” for more information.
After the Program Resume command is written, the device reverts to programming. The system
can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in
the standard program operation. See “Write Operation Status” for more information.
The system must write the Program Resume command (address bits are “don't care”) to exit the
Program Suspend mode and continue the programming operation. Further writes of the Program
Resume command are ignored. Another Program Suspend command can be written after the de-
vice has resumed programming.
Table 10.18 Software Functions and Sample Code
Cycle
Operation
Byte Address
Word Address
Data
1
Write
Bank Address
Bank Address
00B0h
The following is a C source code example of using the program suspend function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Program suspend command */
*( (UINT16 *)base_addr + 0x000 ) = 0x00B0;
/* write suspend command
*/
Cycle
Operation
Byte Address
Word Address
Data
1
Write
Bank Address
Bank Address
0030h
The following is a C source code example of using the program resume function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Program resume command */
*( (UINT16 *)base_addr + 0x000 ) = 0x0030;
/* write resume command
*/
10.5.7 Accelerated Program/Chip Erase
Accelerated single word programming, write buffer programming, sector erase, and chip erase
operations are enabled through the ACC function. This method is faster than the standard chip
program and erase command sequences.
The accelerated chip program and erase functions must not be used more than 10 times
per sector. In addition, accelerated chip program and erase should be performed at room tem-
perature (25
°C
±
10 C).
°
If the system asserts VHH on this input, the device automatically enters the aforementioned Un-
lock Bypass mode and uses the higher voltage on the input to reduce the time required for
program and erase operations. The system can then use the Write Buffer Load command se-
quence provided by the Unlock Bypass mode. Note that if a “Write-to-Buffer-Abort Reset” is
required while in Unlock Bypass mode, the full 3-cycle RESET command sequence must be used
to reset the device. Removing VHH from the ACC input, upon completion of the embedded pro-
gram or erase operation, returns the device to normal operation.
Sectors must be unlocked prior to raising ACC to VHH
.
The ACC pin must not be at VHH for operations other than accelerated programming and ac-
celerated chip erase, or device damage may result.
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The ACC pin must not be left floating or unconnected; inconsistent behavior of the device may
result.
ACC locks all sector if set to VIL; ACC should be set to VIH for all other conditions.
10.5.8 Unlock Bypass
The device features an Unlock Bypass mode to facilitate faster word programming. Once the de-
vice enters the Unlock Bypass mode, only two write cycles are required to program data, instead
of the normal four cycles.
This mode dispenses with the initial two unlock cycles required in the standard program command
sequence, resulting in faster total programming time. The “Command Definition Summary” sec-
tion shows the requirements for the unlock bypass command sequences.
During the unlock bypass mode, only the Read, Unlock Bypass Program and Unlock Bypass Reset
commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock
bypass reset command sequence. The first cycle must contain the bank address and the data 90h.
The second cycle need only contain the data 00h. The bank then returns to the read mode.
The following are C source code examples of using the unlock bypass entry, program, and exit
functions. Refer to the Spansion Low Level Driver User’s Guide (available soon on www.amd.com
and www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
Table 10.19 Software Functions and Sample Code
Cycle
Description
Unlock
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Data
1
2
3
00AAh
0055h
0020h
Unlock
Write
Entry Command
Write
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/* Example: Unlock Bypass Entry Command
*/
*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)bank_addr + 0x555 ) = 0x0020;
/* write unlock cycle 1
/* write unlock cycle 2
/* write unlock bypass command
*/
*/
*/
/* At this point, programming only takes two write cycles.
/* Once you enter Unlock Bypass Mode, do a series of like
/* operations (programming or sector erase) and then exit
/* Unlock Bypass Mode before beginning a different type of
/* operations.
*/
*/
*/
*/
*/
Cycle
Description
Operation
Write
Byte Address
Base + xxxh
Word Address
Base +xxxh
Data
00A0h
1
2
Program Setup Command
Program Command
Write
Program Address
Program Address
Program Data
/* Example: Unlock Bypass Program Command */
/* Do while in Unlock Bypass Entry Mode! */
*( (UINT16 *)bank_addr + 0x555 ) = 0x00A0;
/* write program setup command
/* write data to be programmed
*/
*/
*( (UINT16 *)pa )
= data;
*/
/* Poll until done or error.
/* If done and more to program, */
/* do above two cycles again. */
Cycle
Description
Reset Cycle 1
Reset Cycle 2
Operation
Write
Byte Address
Word Address
Base +xxxh
Base +xxxh
Data
1
2
Base + xxxh
Base + xxxh
0090h
0000h
Write
/* Example: Unlock Bypass Exit Command */
*( (UINT16 *)base_addr + 0x000 ) = 0x0090;
*( (UINT16 *)base_addr + 0x000 ) = 0x0000;
10.5.9 Write Operation Status
The device provides several bits to determine the status of a program or erase operation. The
following subsections describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7.
DQ7: Data# Polling. The Data# Polling bit, DQ7, indicates to the host system whether an Em-
bedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase
Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command se-
quence. Note that the Data# Polling is valid only for the last word being programmed in the write-
buffer-page during Write Buffer Programming. Reading Data# Polling status on any word other
than the last word to be programmed in the write-buffer-page returns false status information.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the
datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend.
When the Embedded Program algorithm is complete, the device outputs the datum programmed
to DQ7. The system must provide the program address to read valid status information on DQ7.
If a program address falls within a protected sector, Data# polling on DQ7 is active for approxi-
mately tPSP, then that bank returns to the read mode.
During the Embedded Erase Algorithm, Data# polling produces a “0” on DQ7. When the Embed-
ded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling
produces a “1” on DQ7. The system must provide an address within any of the sectors selected
for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected,
Data# Polling on DQ7 is active for approximately tASP, then the bank returns to the read mode.
If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7
at an address within a protected sector, the status may not be valid.
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Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asyn-
chronously with DQ6-DQ0 while Output Enable (OE#) is asserted low. That is, the device may
change from providing status information to valid data on DQ7. Depending on when the system
samples the DQ7 output, it may read the status or valid data. Even if the device has completed
the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be
still invalid. Valid data on DQ7-D00 appears on successive read cycles.
See the following for more information: Table 10.20, Write Operation Status, shows the outputs
for Data# Polling on DQ7. Figure 10.6, Write Operation Status Flowchart, shows the Data# Polling
algorithm; and Figure 14.17, Data# Polling Timings (During Embedded Algorithm), shows the
Data# Polling timing diagram.
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START
Read 1
(Note 6)
YES
Erase
Operation
Complete
DQ7=valid
data?
NO
YES
YES
Read 2
Read 1
DQ5=1?
Read3=
valid data?
NO
NO
Read 3
Read 2
Read 3
Program
Operation
Failed
YES
Write Buffer
Programming?
YES
Programming
NO
Operation?
NO
Device BUSY,
Re-Poll
(Note 3)
(Note 5)
(Note 1)
YES
(Note 1)
(Note 2)
YES
YES
DQ6
toggling?
DQ6
DEVICE
ERROR
TIMEOUT
toggling?
NO
(Note 4)
NO
YES
Read3
DQ1=1?
NO
Device BUSY,
Re-Poll
DQ2
toggling?
NO
Read 2
Read 3
Device BUSY,
Re-Poll
Erase
Device in
Erase/Suspend
Mode
Operation
Complete
Read3
DQ1=1
YES
Write Buffer
AND DQ7 ≠
Valid Data?
Operation
Failed
NO
Notes:
1) DQ6 is toggling if Read2 DQ6 does not equal Read3 DQ6.
2) DQ2 is toggling if Read2 DQ2 does not equal Read3 DQ2.
3) May be due to an attempt to program a 0 to 1. Use the RESET
command to exit operation.
Device BUSY,
Re-Poll
4) Write buffer error if DQ1 of last read =1.
5) Invalid state, use RESET command to exit operation.
6) Valid data is the data that is intended to be programmed or all 1's for
an erase operation.
7) Data polling algorithm valid for all operations except advanced sector
protection.
Figure 10.6 Write Operation Status Flowchart
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DQ6: Toggle Bit I . Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algo-
rithm is in progress or complete, or whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of
the final WE# pulse in the command sequence (prior to the program or erase operation), and dur-
ing the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any ad-
dress cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6
toggles for approximately tASP [all sectors protected toggle time], then returns to reading array
data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or
is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm
is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops tog-
gling. However, the system must also use DQ2 to determine which sectors are erasing or erase-
suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector, DQ6 toggles for approximately tPAP after the
program command sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embed-
ded Program Algorithm is complete.
See the following for additional information: Figure 10.6, Write Operation Status Flowchart;
Figure 14.18, Toggle Bit Timings (During Embedded Algorithm), and Table 10.20.
Toggle Bit I on DQ6 requires either OE# or CE# to be de-asserted and reasserted to show the
change in state.
DQ2: Toggle Bit II. The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a par-
ticular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether
that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse
in the command sequence. DQ2 toggles when the system reads at addresses within those sectors
that have been selected for erasure. But DQ2 cannot distinguish whether the sector is actively
erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively eras-
ing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus,
both status bits are required for sector and mode information. Refer to Table 14.10 to compare
outputs for DQ2 and DQ6. See the following for additional information: Figure 10.6, the “DQ6:
Toggle Bit I” section, and Figures 14.17–14.20.
Reading Toggle Bits DQ6/DQ2. Whenever the system initially begins reading toggle bit status,
it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typ-
ically, the system would note and store the value of the toggle bit after the first read. After the
second read, the system would compare the new value of the toggle bit with the first. If the toggle
bit is not toggling, the device has completed the program or erases operation. The system can
read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read
cycles, the system determines that the toggle bit is still toggling, the system also should note
whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then deter-
mine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just
as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed
the program or erases operation. If it is still toggling, the device did not complete the operation
successfully, and the system must write the reset command to return to reading array data. The
remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5
has not gone high. The system may continue to monitor the toggle bit and DQ5 through succes-
sive read cycles, determining the status as described in the previous paragraph. Alternatively, it
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may choose to perform other system tasks. In this case, the system must start at the beginning
of the algorithm when it returns to determine the status of the operation. Refer to Figure 10.6 for
more details.
Note:
When verifying the status of a write operation (embedded program/erase) of a memory bank,
DQ6 and DQ2 toggle between high and low states in a series of consecutive and con-tiguous
status read cycles. In order for this toggling behavior to be properly observed, the consecu-
tive status bit reads must not be interleaved with read accesses to other memory banks. If it
is not possible to temporarily prevent reads to other memory banks, then it is recommended
to use the DQ7 status bit as the alternative method of determining the active or inactive sta-
tus of the write operation.
DQ5: Exceeded Timing Limits. DQ5 indicates whether the program or erase time has exceeded
a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that
the program or erase cycle was not successfully completed. The device may output a “1” on DQ5
if the system tries to program a “1” to a location that was previously programmed to “0.” Only an
erase operation can change a “0” back to a “1.” Under this condition, the device halts the opera-
tion, and when the timing limit has been exceeded, DQ5 produces a “1.”Under both these
conditions, the system must write the reset command to return to the read mode (or to the erase-
suspend-read mode if a bank was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timeout State Indicator. After writing a sector erase command sequence,
the system may read DQ3 to determine whether or not erasure has begun. (The sector erase
timer does not apply to the chip erase command.) If additional sectors are selected for erasure,
the entire time-out also applies after each additional sector erase command. When the time-out
period is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase
commands from the system can be assumed to be less than tSEA, the system need not monitor
DQ3. See Sector Erase Command Sequence for more details.
After the sector erase command is written, the system should read the status of DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and
then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands
(except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device
accepts additional sector erase commands. To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to and following each sub-sequent sector erase
command. If DQ3 is high on the second status check, the last command might not have been
accepted. Table 10.20 shows the status of DQ3 relative to the other status bits.
DQ1: Write to Buffer Abort. DQ1 indicates whether a Write to Buffer operation was aborted.
Under these conditions DQ1 produces a “1”. The system must issue the Write to Buffer Abort
Reset command sequence to return the device to reading array data. See Write Buffer Program-
ming Operation for more details.
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Table 10.20 Write Operation Status
INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
Program
Suspend
Mode
Reading within Program Suspended Sector
(Not
Allowed)
(Not
Allowed)
(Not
Allowed)
(Not
Allowed)
(Not
Allowed)
(Not
Allowed)
Reading within Non-Program Suspended
Sector
(Note 3)
Data
Data
Data
Data
Data
Data
BUSY State
DQ7#
DQ7#
DQ7#
Toggle
Toggle
Toggle
0
1
0
N/A
N/A
N/A
N/A
N/A
N/A
0
0
1
Write to
Buffer
(Note 5)
Exceeded Timing Limits
ABORT State
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the
section on DQ5 for more information.
2. DQ7 a valid address when reading status information. Refer to the appropriate subsection for further details.
3. Data are invalid for addresses in a Program Suspended sector.
4. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations.
5. The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7# during Write Buffer Programming
indicates the data-bar for DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location.
6. For any address changes after CE# assertion, re-assertion of CE# might be required after the addresses become stable for data polling
during the erase suspend operation using DQ2/DQ6.
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10.6 Simultaneous Read/Write
The simultaneous read/write feature allows the host system to read data from one bank of mem-
ory while programming or erasing another bank of memory. An erase operation may also be
suspended to read from or program another location within the same bank (except the sector
being erased). Figure 14.24, Back-to-Back Read/Write Cycle Timings, shows how read and write
cycles may be initiated for simultaneous operation with zero latency. Refer to the DC Character-
istics (CMOS Compatible) table for read-while-program and read-while-erase current
specification.
10.7 Writing Commands/Command Sequences
When the device is configured for Asynchronous read, only Asynchronous write operations are
allowed, and CLK is ignored. When in the Synchronous read mode configuration, the device is able
to perform both Asynchronous and Synchronous write operations. CLK and AVD# induced address
latches are supported in the Synchronous programming mode. During a synchronous write oper-
ation, to write a command or command sequence (which includes programming data to the
device and erasing sectors of memory), the system must drive AVD# and CE# to VIL, and OE#
to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH
when writing commands or data. During an asynchronous write operation, the system must drive
CE# and WE# to VIL and OE# to VIH when providing an address, command, and data. Addresses
are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of
WE# or CE#. An erase operation can erase one sector, multiple sectors, or the entire device.
Tables 9.1–9.2 indicate the address space that each sector occupies. The device address space is
divided into sixteen banks: Banks 1 through 14 contain only 64 Kword sectors, while Banks 0 and
15 contain both 16 Kword boot sectors in addition to 64 Kword sectors. A “bank address” is the
set of address bits required to uniquely select a bank. Similarly, a “sector address” is the address
bits required to uniquely select a sector. ICC2 in “DC Characteristics” represents the active current
specification for the write mode. “AC Characteristics-Synchronous” and “AC Characteristics-Asyn-
chronous” contain timing specification tables and timing diagrams for write operations.
10.8 Handshaking
The handshaking feature allows the host system to detect when data is ready to be read by simply
monitoring the RDY (Ready) pin, which is a dedicated output and controlled by CE#.
When the device is configured to operate in synchronous mode, and OE# is low (active), the initial
word of burst data becomes available after either the falling or rising edge of the RDY pin (de-
pending on the setting for bit 10 in the Configuration Register). It is recommended that the host
system set CR13–CR11 in the Configuration Register to the appropriate number of wait states to
ensure optimal burst mode operation (see Table 10.9, Configuration Register).
Bit 8 in the Configuration Register allows the host to specify whether RDY is active at the same
time that data is ready, or one cycle before data is ready.
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10.9 Hardware Reset
The RESET# input provides a hardware method of resetting the device to reading array data.
When RESET# is driven low for at least a period of tRP, the device immediately terminates any
operation in progress, tristates all outputs, resets the configuration register, and ignores all read/
write commands for the duration of the RESET# pulse. The device also resets the internal state
machine to reading array data.
To ensure data integrity the operation that was interrupted should be reinitiated once the device
is ready to accept another command sequence.
When RESET# is held at VSS, the device draws CMOS standby current (ICC4). If RESET# is held
at VIL, but not at VSS, the standby current is greater.
RESET# may be tied to the system reset circuitry which enables the system to read the boot-up
firmware from the Flash memory upon a system reset.
See Figures 14.5 and 14.12 for timing diagrams.
10.10 Software Reset
Software reset is part of the command set (see Table 15.1) that also returns the device to array
read mode and must be used for the following conditions:
1. to exit Autoselect mode
2. when DQ5 goes high during write status operation that indicates program or erase cycle was
not successfully completed
3. exit sector lock/unlock operation.
4. to return to erase-suspend-read mode if the device was previously in Erase Suspend mode.
5. after any aborted operations
Table 10.21 Reset LLD Function = lld_ResetCmd)
Cycle
Operation
Byte Address
Word Address
Data
Reset Command
Write
Base + xxxh
Base + xxxh
00F0h
Note: Base = Base Address.
The following is a C source code example of using the reset function. Refer to the Spansion
Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for general
information on Spansion Flash memory software development guidelines.
/* Example: Reset (software reset of Flash state machine) */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0;
The following are additional points to consider when using the reset command:
This command resets the banks to the read and address bits are ignored.
Reset commands are ignored once erasure has begun until the operation is complete.
Once programming begins, the device ignores reset commands until the operation is com-
plete
The reset command may be written between the cycles in a program command sequence be-
fore programming begins (prior to the third cycle). This resets the bank to which the system
was writing to the read mode.
If the program command sequence is written to a bank that is in the Erase Suspend mode,
writing the reset command returns that bank to the erase-suspend-read mode.
The reset command may be also written during an Autoselect command sequence.
If a bank has entered the Autoselect mode while in the Erase Suspend mode, writing the reset
command returns that bank to the erase-suspend-read mode.
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If DQ1 goes high during a Write Buffer Programming operation, the system must write the
"Write to Buffer Abort Reset" command sequence to RESET the device to reading array data.
The standard RESET command does not work during this condition.
To exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset com-
mand sequence [see the command table for details].
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11 Advanced Sector Protection/Unprotection
The Advanced Sector Protection/Unprotection feature disables or enables programming or erase
operations in any or all sectors and can be implemented through software and/or hardware meth-
ods, which are independent of each other. This section describes the various methods of
protecting data stored in the memory array. An overview of these methods in shown in Figure
11.1.
Hardware Methods
Software Methods
Lock Register
(One Time Programmable)
ACC = V
IL
All sectors locked)
Persistent Method
Password Method
(
(DQ1)
(DQ2)
WP# = V
IL
(All boot
sectors locked)
64-bit Password
(One Time Protect)
1. Bit is volatile, and defaults to “1” on
reset.
PPB Lock Bit1,2,3
2. Programming to “0” locks all PPBs to
their current state.
0 = PPBs Locked
1 = PPBs Unlocked
3. Once programmed to “0”, requires
hardware reset to unlock.
Persistent
Protection Bit
(PPB)4,5
Dynamic
Protection Bit
(DYB)6,7,8
Memory Array
Sector 0
Sector 1
Sector 2
PPB 0
PPB 1
PPB 2
DYB 0
DYB 1
DYB 2
Sector N-2
Sector N-1
PPB N-2
PPB N-1
PPB N
DYB N-2
DYB N-1
DYB N
Sector N3
3. N = Highest Address Sector.
4. 0 = Sector Protected,
1 = Sector Unprotected.
6. 0 = Sector Protected,
1 = Sector Unprotected.
5. PPBs programmed individually,
but cleared collectively
7. Protect effective only if PPB Lock Bit
is unlocked and corresponding PPB
is “1” (unprotected).
8. Volatile Bits: defaults to user choice
upon power-up (see ordering
options).
Figure 11.1 Advanced Sector Protection/Unprotection
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11.1 Lock Register
As shipped from the factory, all devices default to the persistent mode when power is applied, and
all sectors are unprotected, unless otherwise chosen through the DYB ordering option. The device
programmer or host system must then choose which sector protection method to use. Program-
ming (setting to “0”) any one of the following two one-time programmable, non-volatile bits locks
the part permanently in that mode:
Lock Register Persistent Protection Mode Lock Bit (DQ1)
Lock Register Password Protection Mode Lock Bit (DQ2)
Table 11.1 Lock Register
Device
DQ15-05
DQ4
DQ3
DQ2
DQ1
DQ0
Password
Protection
Mode Lock Bit
Persistent
Protection
Mode Lock Bit
Customer
SecSi Sector
Protection Bit
S29WS256N
1
1
1
DYB Lock Boot Bit
PPB One-Time
0 = sectors
power up
protected
Programmable Bit
Password
Protection
Mode Lock Bit
Persistent
Protection
Mode Lock Bit
0 = All PPB erase
command disabled
SecSi Sector
Protection Bit
S29WS128N Undefined
1 = sectors
power up
unprotected
1 = All PPB Erase
command enabled
For programming lock register bits refer to Table 15.2.
Notes
1. If the password mode is chosen, the password must be programmed before setting the cor-
responding lock register bit.
2. After the Lock Register Bits Command Set Entry command sequence is written, reads and
writes for Bank 0 are disabled, while reads from other banks are allowed until exiting this
mode.
3. If both lock bits are selected to be programmed (to zeros) at the same time, the operation
aborts.
4. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently
disabled, and no changes to the protection scheme are allowed. Similarly, if the Persistent
Mode Lock Bit is programmed, the Password Mode is permanently disabled.
After selecting a sector protection method, each sector can operate in any of the following three
states:
1. Constantly locked. The selected sectors are protected and can not be reprogrammed unless
PPB lock bit is cleared via a password, hardware reset, or power cycle.
2. Dynamically locked. The selected sectors are protected and can be altered via software
commands.
3. Unlocked. The sectors are unprotected and can be erased and/or programmed.
These states are controlled by the bit types described in Sections 11.2–.
11.2 Persistent Protection Bits
The Persistent Protection Bits are unique and nonvolatile for each sector and have the same en-
durances as the Flash memory. Preprogramming and verification prior to erasure are handled by
the device, and therefore do not require system monitoring.
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Notes
1. Each PPB is individually programmed and all are erased in parallel.
2. While programming PPB for a sector, array data can be read from any other bank, except
Bank 0 (used for Data# Polling) and the bank in which sector PPB is being programmed.
3. Entry command disables reads and writes for the bank selected.
4. Reads within that bank return the PPB status for that sector.
5. Reads from other banks are allowed while writes are not allowed.
6. All Reads must be performed using the Asynchronous mode.
7. The specific sector address (A23-A14 WS256N, A22-A14 WS128N) are written at the same
time as the program command.
8. If the PPB Lock Bit is set, the PPB Program or erase command does not execute and times-
out without programming or erasing the PPB.
9. There are no means for individually erasing a specific PPB and no specific sector address is
required for this operation.
10. Exit command must be issued after the execution which resets the device to read mode and
re-enables reads and writes for Bank 0
11. The programming state of the PPB for a given sector can be verified by writing a PPB
Status Read Command to the device as described by the flow chart shown in Figure 11.2.
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Enter PPB
Command Set.
Addr = BA
Program PPB Bit.
Addr = SA
Read Byte Twice
Addr = SA0
No
DQ6 =
Toggle?
Yes
No
DQ5 = 1?
Wait 500 µs
Yes
Read Byte Twice
Addr = SA0
No
Read Byte.
Addr = SA
DQ6 =
Toggle?
Yes
DQ0 =
No
'1' (Erase)
'0' (Pgm.)?
FAIL
Yes
Issue Reset
Command
PASS
Exit PPB
Command Set
Figure 11.2 PPB Program/Erase Algorithm
11.3 Dynamic Protection Bits
Dynamic Protection Bits are volatile and unique for each sector and can be individually modified.
DYBs only control the protection scheme for unprotected sectors that have their PPBs cleared
(erased to “1”). By issuing the DYB Set or Clear command sequences, the DYBs are set (pro-
grammed to “0”) or cleared (erased to “1”), thus placing each sector in the protected or
unprotected state respectively. This feature allows software to easily protect sectors against in-
advertent changes yet does not prevent the easy removal of protection when changes are
needed.
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Notes
1. The DYBs can be set (programmed to “0”) or cleared (erased to “1”) as often as needed.
When the parts are first shipped, the PPBs are cleared (erased to “1”) and upon power up or reset,
the DYBs can be set or cleared depending upon the ordering option chosen.
2. If the option to clear the DYBs after power up is chosen, (erased to “1”), then the sectors
may be modified depending upon the PPB state of that sector (see Table 11.2).
3. The sectors would be in the protected state If the option to set the DYBs after power up is
chosen (programmed to “0”).
4. It is possible to have sectors that are persistently locked with sectors that are left in the
dynamic state.
5. The DYB Set or Clear commands for the dynamic sectors signify protected or unprotected
state of the sectors respectively. However, if there is a need to change the status of the per-
sistently locked sectors, a few more steps are required. First, the PPB Lock Bit must be
cleared by either putting the device through a power-cycle, or hardware reset. The PPBs can
then be changed to reflect the desired settings. Setting the PPB Lock Bit once again locks
the PPBs, and the device operates normally again.
6. To achieve the best protection, it is recommended to execute the PPB Lock Bit Set command
early in the boot code and protect the boot code by holding WP# = VIL. Note that the PPB
and DYB bits have the same function when ACC = VHH as they do when ACC =VIH.
11.4 Persistent Protection Bit Lock Bit
The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set (programmed
to “0”), it locks all PPBs and when cleared (programmed to “1”), allows the PPBs to be changed.
There is only one PPB Lock Bit per device.
Notes
1. No software command sequence unlocks this bit unless the device is in the password pro-
tection mode; only a hardware reset or a power-up clears this bit.
2. The PPB Lock Bit must be set (programmed to “0”) only after all PPBs are configured to the
desired settings.
11.5 Password Protection Method
The Password Protection Method allows an even higher level of security than the Persistent Sector
Protection Mode by requiring a 64 bit password for unlocking the device PPB Lock Bit. In addition
to this password requirement, after power up and reset, the PPB Lock Bit is set “0” to maintain
the password mode of operation. Successful execution of the Password Unlock command by en-
tering the entire password clears the PPB Lock Bit, allowing for sector PPBs modifications.
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Notes
1. There is no special addressing order required for programming the password. Once the
Password is written and verified, the Password Mode Locking Bit must be set in order to pre-
vent access.
2. The Password Program Command is only capable of programming “0”s. Programming a “1”
after a cell is programmed as a “0” results in a time-out with the cell as a “0”.
3. The password is all “1”s when shipped from the factory.
4. All 64-bit password combinations are valid as a password.
5. There is no means to verify what the password is after it is set.
6. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the data
bus and further password programming.
7. The Password Mode Lock Bit is not erasable.
8. The lower two address bits (A1–A0) are valid during the Password Read, Password Program,
and Password Unlock.
9. The exact password must be entered in order for the unlocking function to occur.
10. The Password Unlock command cannot be issued any faster than 1 µs at a time to prevent
a hacker from running through all the 64-bit combinations in an attempt to correctly match
a password.
11. Approximately 1 µs is required for unlocking the device after the valid 64-bit password is
given to the device.
12. Password verification is only allowed during the password programming operation.
13. All further commands to the password region are disabled and all operations are ignored.
14. If the password is lost after setting the Password Mode Lock Bit, there is no way to clear the
PPB Lock Bit.
15. Entry command sequence must be issued prior to any of any operation and it disables reads
and writes for Bank 0. Reads and writes for other banks excluding Bank 0 are allowed.
16. If the user attempts to program or erase a protected sector, the device ignores the com-
mand and returns to read mode.
17. A program or erase command to a protected sector enables status polling and returns to
read mode without having modified the contents of the protected sector.
18. The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by writing
individual status read commands DYB Status, PPB Status, and PPB Lock Status to the
device.
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Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write
Enter Lock Register Command:
Address 555h, Data 40h
XXXh = Address don’t care
* Not on future devices
Program Lock Register Data
Address XXXh, Data A0h
Address 77h*, Data PD
Program Data (PD): See text for Lock Register
definitions
Caution: Lock register can only be progammed
once.
Wait 4 µs
(Recommended)
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Done?
No
No
DQ5 = 1?
Yes
Error condition (Exceeded Timing Limits)
PASS. Write Lock Register
Exit Command:
FAIL. Write rest command
to return to reading array.
Address XXXh, Data 90h
Address XXXh, Data 00h
Device returns to reading array.
Figure 11.3 Lock Register Program Algorithm
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Table 11.2 Advanced Sector Protection Software Examples
Unique Device PPB Lock Bit
0 = locked
Sector PPB
0 = protected
1 = unprotected
Sector DYB
0 = protected
1 = unprotected
1 = unlocked
Sector Protection Status
Protected through PPB
Protected through PPB
Unprotected
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
x
x
1
0
x
x
0
1
Protected through DYB
Protected through PPB
Protected through PPB
Protected through DYB
Unprotected
Figure 11.2 contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the
status of the sector. In summary, if the PPB Lock Bit is locked (set to “0”), no changes to the PPBs
are allowed. The PPB Lock Bit can only be unlocked (reset to “1”) through a hardware reset or
power cycle. See also Figure 11.1 for an overview of the Advanced Sector Protection feature.
11.6 Hardware Data Protection Methods
The device offers two main types of data protection at the sector level via hardware control:
When WP# is at VIL, the four outermost sectors are locked (device specific).
When ACC is at VIL, all sectors are locked.
There are additional methods by which intended or accidental erasure of any sectors can be pre-
vented via hardware means. The following subsections describes these methods:
11.6.1 WP# Method
The Write Protect feature provides a hardware method of protecting the four outermost sectors.
This function is provided by the WP# pin and overrides the previously discussed Sector Protec-
tion/Unprotection method.
If the system asserts VIL on the WP# pin, the device disables program and erase functions in the
“outermost” boot sectors. The outermost boot sectors are the sectors containing both the lower
and upper set of sectors in a dual-boot-configured device.
If the system asserts VIH on the WP# pin, the device reverts to whether the boot sectors were
last set to be protected or unprotected. That is, sector protection or unprotection for these sectors
depends on whether they were last protected or unprotected.
Note that the WP# pin must not be left floating or unconnected as inconsistent behavior of the
device may result.
The WP# pin must be held stable during a command sequence execution
11.6.2 ACC Method
This method is similar to above, except it protects all sectors. Once ACC input is set to VIL, all
program and erase functions are disabled and hence all sectors are protected.
11.6.3 Low V
Write Inhibit
CC
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during
VCC power-up and power-down.
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The command register and all internal program/erase circuits are disabled, and the device resets
to reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The system
must provide the proper signals to the control inputs to prevent unintentional writes when VCC is
greater than VLKO
.
11.6.4 Write Pulse “Glitch Protection”
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
11.6.5 Power-Up Write Inhibit
If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept com-
mands on the rising edge of WE#. The internal state machine is automatically reset to the read
mode on power-up.
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12 Power Conservation Modes
12.1 Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby
mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the
high impedance state, independent of the OE# input. The device enters the CMOS standby mode
when the CE# and RESET# inputs are both held at VCC ± 0.2 V. The device requires standard
access time (tCE) for read access, before it is ready to read data. If the device is deselected during
erasure or programming, the device draws active current until the operation is completed. ICC3 in
“DC Characteristics” represents the standby current specification
12.2 Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption while in asynchronous
mode. the device automatically enables this mode when addresses remain stable for tACC + 20
ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Stan-
dard address access timings provide new data when addresses are changed. While in sleep mode,
output data is latched and always available to the system. While in synchronous mode, the auto-
matic sleep mode is disabled. Note that a new burst operation is required to provide new data.
ICC6 in DC Characteristics (CMOS Compatible) represents the automatic sleep mode current
specification.
12.3 Hardware RESET# Input Operation
The RESET# input provides a hardware method of resetting the device to reading array data.
When RESET# is driven low for at least a period of tRP, the device immediately terminates any
operation in progress, tristates all outputs, resets the configuration register, and ignores all read/
write commands for the duration of the RESET# pulse. The device also resets the internal state
machine to reading array data. The operation that was interrupted should be reinitiated once the
device is ready to accept another command sequence to ensure data integrity.
When RESET# is held at VSS ± 0.2 V, the device draws CMOS standby current (ICC4). If RESET#
is held at VIL but not within VSS ± 0.2 V, the standby current is greater.
RESET# may be tied to the system reset circuitry and thus, a system reset would also reset the
Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
12.4 Output Disable (OE#)
When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the
high impedance state.
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13 Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector provides an extra Flash memory region that enables permanent part
identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 words
in length that consists of 128 words for factory data and 128 words for customer-secured areas.
All Secured Silicon reads outside of the 256-word address range returns invalid data. The Factory
Indicator Bit, DQ7, (at Autoselect address 03h) is used to indicate whether or not the Factory Se-
cured Silicon Sector is locked when shipped from the factory. The Customer Indicator Bit (DQ6)
is used to indicate whether or not the Customer Secured Silicon Sector is locked when shipped
from the factory.
Please note the following general conditions:
While Secured Silicon Sector access is enabled, simultaneous operations are allowed except
for Bank 0.
On power-up, or following a hardware reset, the device reverts to sending commands to the
normal address space.
Reads can be performed in the Asynchronous or Synchronous mode.
Burst mode reads within Secured Silicon Sector wrap from address FFh back to address 00h.
Reads outside of sector 0 return memory array data.
Continuous burst read past the maximum address is undefined.
Sector 0 is remapped from memory array to Secured Silicon Sector array.
Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon Sector Exit
command must be issued to exit Secured Silicon Sector Mode.
The Secured Silicon Sector is not accessible when the device is executing an Embedded Pro-
gram or Embedded Erase algorithm.
Table 13.1
Addresses
Sector
Customer
Factory
Sector Size
128 words
128 words
Address Range
000080h-0000FFh
000000h-00007Fh
13.1 Factory Secured SiliconSector
The Factory Secured Silicon Sector is always protected when shipped from the factory and has
the Factory Indicator Bit (DQ7) permanently set to a “1”. This prevents cloning of a factory locked
part and ensures the security of the ESN and customer code once the product is shipped to the
field.
These devices are available pre programmed with one of the following:
A random, 8 Word secure ESN only within the Factory Secured Silicon Sector
Customer code within the Customer Secured Silicon Sector through the SpansionTM program-
ming service.
Both a random, secure ESN and customer code through the Spansion programming service.
Customers may opt to have their code programmed through the Spansion programming services.
Spansion programs the customer's code, with or without the random ESN. The devices are then
shipped from the Spansion factory with the Factory Secured Silicon Sector and Customer Secured
Silicon Sector permanently locked. Contact your local representative for details on using Spansion
programming services.
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13.2 Customer Secured Silicon Sector
The Customer Secured Silicon Sector is typically shipped unprotected (DQ6 set to “0”), allowing
customers to utilize that sector in any manner they choose. If the security feature is not required,
the Customer Secured Silicon Sector can be treated as an additional Flash memory space.
Please note the following:
Once the Customer Secured Silicon Sector area is protected, the Customer Indicator Bit is
permanently set to “1.”
The Customer Secured Silicon Sector can be read any number of times, but can be pro-
grammed and locked only once. The Customer Secured Silicon Sector lock must be used with
caution as once locked, there is no procedure available for unlocking the Customer Secured
Silicon Sector area and none of the bits in the Customer Secured Silicon Sector memory space
can be modified in any way.
The accelerated programming (ACC) and unlock bypass functions are not available when pro-
gramming the Customer Secured Silicon Sector, but reading in Banks 1 through 15 is avail-
able.
Once the Customer Secured Silicon Sector is locked and verified, the system must write the
Exit Secured Silicon Sector Region command sequence which return the device to the mem-
ory array at sector 0.
13.3 Secured Silicon Sector Entry/Exit Command Sequences
The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured
Silicon Sector command sequence. The device continues to access the Secured Silicon Sector re-
gion until the system issues the four-cycle Exit Secured Silicon Sector command sequence.
See Command Definition Table [Secured Silicon Sector Command Table, Appendix
Table 15.1 for address and data requirements for both command sequences.
The Secured Silicon Sector Entry Command allows the following commands to be executed
Read customer and factory Secured Silicon areas
Program the customer Secured Silicon Sector
After the system has written the Enter Secured Silicon Sector command sequence, it may read
the Secured Silicon Sector by using the addresses normally occupied by sector SA0 within the
memory array. This mode of operation continues until the system issues the Exit Secured Silicon
Sector command sequence, or until power is removed from the device.
Software Functions and Sample Code
The following are C functions and source code examples of using the Secured Silicon Sector
Entry, Program, and exit commands. Refer to the Spansion Low Level Driver User’s Guide
(available soon on www.amd.com and www.fujitsu.com) for general information on Spansion
Flash memory software development guidelines.
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A d v a n c e I n f o r m a t i o n
Table 13.2 Secured Silicon Sector Entry
(LLD Function = lld_SecSiSectorEntryCmd)
Cycle
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Data
Unlock Cycle 1
Unlock Cycle 2
00AAh
0055h
0088h
Write
Entry Cycle
Write
Note: Base = Base Address.
/* Example: SecSi Sector Entry Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0088;
/* write unlock cycle 1
/* write unlock cycle 2
/* write Secsi Sector Entry Cmd
*/
*/
*/
Table 13.3 Secured Silicon Sector Program
(LLD Function = lld_ProgramCmd)
Cycle
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Word Address
Data
00AAh
Unlock Cycle 1
Unlock Cycle 2
Program Setup
Write
0055h
Write
00A0h
Program
Write
Data Word
Note: Base = Base Address.
/* Once in the SecSi Sector mode, you program */
/* words using the programming algorithm. */
Table 13.4 Secured Silicon Sector Exit
(LLD Function = lld_SecSiSectorExitCmd)
Cycle
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Data
Unlock Cycle 1
Unlock Cycle 2
00AAh
0055h
0090h
Write
Exit Cycle
Write
Note: Base = Base Address.
/* Example: SecSi Sector Exit Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0090;
*( (UINT16 *)base_addr + 0x000 ) = 0x0000;
/* write unlock cycle 1
/* write unlock cycle 2
/* write SecSi Sector Exit cycle 3 */
/* write SecSi Sector Exit cycle 4 */
*/
*/
September 15, 2005 S71WS-N_01_A4
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67
A d v a n c e I n f o r m a t i o n
14 Electrical Specifications
14.1 Absolute Maximum Ratings
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
Voltage with Respect to Ground:
All Inputs and I/Os except
as noted below (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +2.5 V
ACC (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +9.5 V
Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Notes:
1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or
I/Os may undershoot VSS to –2.0 V for periods of up to 20 ns. See Figure 14.1.
Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage transitions
outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 14.2.
2. Minimum DC input voltage on pin ACC is -0.5V. During voltage transitions, ACC may
overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 14.1. Maximum DC
voltage on pin ACC is +9.5 V, which may overshoot to 10.5 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short
circuit should not be greater than one second.
4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
data sheet is not implied. Exposure of the device to absolute maximum rating conditions
for extended periods may affect device reliability.
20 ns
20 ns
20 ns
VCC
+0.8 V
+2.0 V
VCC
+0.5 V
–0.5 V
–2.0 V
1.0 V
20 ns
20 ns
20 ns
Figure 14.1 Maximum Negative
Overshoot Waveform
Figure 14.2 Maximum Positive
Overshoot Waveform
Note:The content in this document is Advance information for the S29WS128N. Con-
tent in this document is Preliminary for the S29W256N.
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14.2 Operating Ranges
Wireless (W) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C
Supply Voltages
VCC Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+1.70 V to +1.95 V
Notes: Operating ranges define those limits between which the functionality of the device
is guaranteed.
14.3 Test Conditions
Device
Under
Test
C
L
Figure 14.3 Test Setup
Table 14.1 Test Specifications
Test Condition
All Speed Options
Unit
Output Load Capacitance, CL
(including jig capacitance)
30
pF
3.0 @ 54, 66 MHz
2.5 @ 80 MHz
Input Rise and Fall Times
Input Pulse Levels
ns
0.0–VCC
VCC/2
V
V
Input timing measurement
reference levels
Output timing measurement
reference levels
VCC/2
V
Note: The content in this document is Advance information for the S29WS128N. Con-
tent in this document is Preliminary for the S29W256N.
September 15, 2005 S71WS-N_01_A4
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69
A d v a n c e I n f o r m a t i o n
14.4 Key to Switching Waveforms
Waveform
Inputs
Outputs
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
Notes:
1. The content in this document is Advance information for the S29WS128N. Content in this document is Preliminary for the S29W256N.
14.5 Switching Waveforms
VCC
All Inputs and Outputs
VCC/2
VCC/2
Input
Measurement Level
Output
0.0 V
Figure 14.4 Input Waveforms and Measurement Levels
14.6 V
Power-up
CC
Parameter
Description
Test Setup
Speed
Unit
tVCS
VCC Setup Time
Min
1
ms
Notes:
1. The content in this document is Advance information for the S29WS128N. Content in this document is
Preliminary for the S29W256N.
2. S29WS128N: VCC ramp rate is > 1V/ 100 µs and for VCC ramp rate of < 1 V
/ 100 µs a hardware reset is required.
tVCS
VCC
RESET#
Figure 14.5
V
Power-up Diagram
CC
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14.7 DC Characteristics (CMOS Compatible)
Parameter
Description (Notes)
Input Load Current
Output Leakage Current (2)
Test Conditions (Notes 1, 8)
= V to V , V = V max
Min
Typ
Max
±1
±1
54
60
66
48
54
60
42
48
54
36
42
48
45
26
7
Unit
µA
I
V
V
LI
IN
SS
CC
CC
CC
I
= V to V , V = V max
µA
LO
OUT
SS
CC
CC
CC
54 MHz
27
28
30
28
30
32
29
32
34
32
35
38
34
17
4
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
CE# = V , OE# = V
,
IH
IL
WE# = V , burst length
66 MHz
80 MHz
54 MHz
66 MHz
80 MHz
54 MHz
66 MHz
80 MHz
54 MHz
66 MHz
80 MHz
10 MHz
5 MHz
IH
= 8
CE# = V , OE# = V
,
IH
IL
WE# = V , burst length
IH
= 16
I
V
Active burst Read Current
CC
CCB
CE# = V , OE# = V
,
IH
IL
WE# = V , burst length
IH
= 32
CE# = V , OE# = V
,
IH
IL
WE# = V , burst length
IH
= Continuous
V
Active Asynchronous
CE# = V , OE# = V
IL
,
,
CC
IH
IH
I
CC1
WE# = V
Read Current (3)
IH
1 MHz
V
1
5
ACC
CE# = V , OE# = V
IL
IH
I
I
V
V
Active Write Current (4)
Standby Current (5, 6)
CC2
CC3
CC
CC
ACC = V
V
24
1
52.5
5
mA
µA
CC
V
ACC
CE# = RESET# =
± 0.2 V
V
CC
V
20
70
70
250
µA
CC
I
I
I
V
V
Reset Current (6)
Active Current
RESET# = V CLK = V
IL
µA
CC4
CC5
CC6
CC
CC
IL,
CE# = V , OE# = V , ACC = V @
IH
IL
IH
50
60
mA
5 MHz
(Read While Write) (6)
V
Sleep Current (6)
CE# = V , OE# = V
IL
2
6
70
20
µA
mA
mA
V
CC
IH
V
CE# = V , OE# = V
IL
ACC
Accelerated Program Current
(7)
IH,
I
ACC
V
= 9.5 V
ACC
V
14
20
CC
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
V
V
= 1.8 V
= 1.8 V
–0.5
0.4
IL
CC
CC
OL
V
V
– 0.4
V
+ 0.4
V
IH
CC
CC
V
I
I
= 100 µA, V = V
= V
CC
0.1
V
OL
OH
CC
CC min
V
V
= –100 µA, V = V
= V
V
CC
V
OH
CC
CC min
CC
Voltage for Accelerated
Program
8.5
9.5
1.4
V
V
HH
V
Low V Lock-out Voltage
CC
LKO
Notes:
1. Maximum ICC specifications are tested with VCC = VCCmax.
2. CE# must be set high when measuring the RDY pin.
3. The ICC current listed is typically less than 3.5 mA/MHz, with OE# at VIH
4. ICC active while Embedded Erase or Embedded Program is in progress.
.
5. Device enters automatic sleep mode when addresses are stable for tACC + 20 ns. Typical sleep mode
current is equal to ICC3
.
6. VIH = VCC ± 0.2 V and VIL > –0.1 V.
7. Total current during accelerated programming is the sum of VACC and VCC currents.
8. VACC = VHH on ACC input.
9. The content in this document is Advance information for the S29WS128N. Content in this document is
Preliminary for the S29W256N.
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71
A d v a n c e I n f o r m a t i o n
14.8 AC Characteristics
14.8.1 CLK Characterization
Parameter
fCLK
Description
CLK Frequency
54 MHz
54
66 MHz
66
80 MHz
80
Unit
MHz
ns
Max
Min
tCLK
tCH
CLK Period
18.5
15.1
12.5
CLK High Time
CLK Low Time
CLK Rise Time
CLK Fall Time
Min
7.4
3
6.1
3
5.0
2.5
ns
ns
tCL
tCR
Max
tCF
Notes:
1. The content in this document is Advance information for the S29WS128N.
Content in this document is Preliminary for the S29W256N.
2. Not 100% tested.
t
CLK
t
t
CL
CH
CLK
t
t
CF
CR
Figure 14.6 CLK Characterization
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14.8.2 Synchronous/Burst Read
Parameter
JEDEC
Standard
Description
54 MHz
66 MHz
80
80 MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
tIACC
tBACC
tACS
tACH
tBDH
tCR
Latency
Max
Burst Access Time Valid Clock to Output Delay Max
13.5
5
11.2
9
Address Setup Time to CLK (Note 1)
Address Hold Time from CLK (Note 1)
Data Hold Time from Next Clock Cycle
Chip Enable to RDY Valid
Min
Min
Min
Max
Max
Max
Max
Min
Min
Max
Min
Min
Min
Min
4
6
3
7
4
13.5
13.5
11.2
9
tOE
Output Enable to Output Valid
Chip Enable to High Z (Note 2)
Output Enable to High Z (Note 2)
CE# Setup Time to CLK
11.2
tCEZ
tOEZ
tCES
tRDYS
tRACC
tCAS
tAVC
tAVD
fCLK
10
10
4
RDY Setup Time to CLK
5
4
3.5
9
Ready Access Time from CLK
CE# Setup Time to AVD#
AVD# Low to CLK
13.5
11.2
0
4
AVD# Pulse
8
1
1
1
Minimum clock frequency
Notes:
1. Addresses are latched on the first rising edge of CLK.
2. Not 100% tested.
3. The content in this document is Advance information for the S29WS128N. Content in this document is
Preliminary for the S29W256N.
Table 14.2 Synchronous Wait State Requirements
Max Frequency
Wait State Requirement
01 MHz < Freq. ≤ 14 MHz
14 MHz < Freq. ≤ 27 MHz
27 MHz < Freq. ≤ 40 MHz
40 MHz < Freq. ≤ 54 MHz
54 MHz < Freq. ≤ 67 MHz
67 MHz < Freq. ≤ 80 MHz
2
3
4
5
6
7
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A d v a n c e I n f o r m a t i o n
14.8.3 Timing Diagrams
5 cycles for initial access shown.
18.5 ns typ. (54 MHz)
tCEZ
tCES
CE#
1
2
3
4
5
6
7
CLK
tAVC
AVD#
tAVD
tACS
Addresses
Data (n)
Aa
tBACC
tACH
Hi-Z
tIACC
Da
Da + 1
Da + 2
Da + n
tOEZ
Da + 3
tBDH
OE#
tRACC
tOE
Hi-Z
Hi-Z
RDY (n)
tCR
tRDYS
Hi-Z
Hi-Z
Data (n + 1)
RDY (n + 1)
Da
Da + 1
Da + 2
Da + n
Da + 2
Hi-Z
Hi-Z
Hi-Z
Data (n + 2)
RDY (n + 2)
Da
Da + 1
Da + 1
Da + n
Da + 1
Hi-Z
Hi-Z
Hi-Z
Data (n + 3)
RDY (n + 3)
Da
Da
Da
Da + n
Da
Hi-Z
Notes:
1. Figure shows total number of wait states set to five cycles. The total number of
wait states can be programmed from two cycles to seven cycles.
2. If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”,
additional clock delay cycles are inserted, and are indicated by RDY.
3. The device is in synchronous mode.
Figure 14.7 CLK Synchronous Burst Mode Read
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A d v a n c e I n f o r m a t i o n
7 cycles for initial access shown.
tCES
CE#
CLK
1
2
3
4
5
6
7
tAVC
AVD#
tAVD
tACS
Ac
Addresses
Data
tBACC
tACH
tIACC
DC
DD
DE
DF
D8
DB
tBDH
OE#
RDY
tCR
tRACC
tRACC
tOE
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven
cycles.
2. If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”, additional clock delay cycles are inserted, and are indicated
by RDY.
3. The device is in synchronous mode with wrap around.
4. D8–DF in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure
is the 4th address in range (0-F).
Figure 14.8 8-word Linear Burst with Wrap Around
7
cycles for initial access shown.
tCES
CE#
CLK
1
2
3
4
5
6
7
tAVC
AVD#
tAVD
tACS
Ac
Addresses
Data
tBACC
tACH
tIACC
DC
DD
DE
DF
D8
DB
tBDH
OE#
RDY
tCR
tRACC
tOE
tRACC
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven
cycles. Clock is set for active rising edge.
2. If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”, additional clock delay cycles are inserted, and are indicated
by RDY.
3. The device is in asynchronous mode with out wrap around.
4. DC–D13 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure
is the 1st address in range (c-13).
Figure 14.9 8-word Linear Burst without Wrap Around
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A d v a n c e I n f o r m a t i o n
tCEZ
6 wait cycles for initial access shown.
tCES
CE#
CLK
1
5
6
7
tAVC
AVD#
tAVD
tACS
Aa
Addresses
Data
tBACC
tACH
Hi-Z
tIACC
Da
Da+1
Da+2
Da+3
Da + n
tBDH
tOEZ
tRACC
OE#
RDY
tCR
tOE
Hi-Z
Hi-Z
tRDYS
Notes:
1. Figure assumes 6 wait states for initial access and synchronous read.
2. The Set Configuration Register command sequence has been written with CR8=0; device outputs RDY one cycle before valid data.
Figure 14.10 Linear Burst with RDY Set One Cycle Before Data
14.8.4 AC Characteristics—Asynchronous Read
Parameter
80
MHz
JEDEC Standard
Description
Access Time from CE# Low
54 MHz
66 MHz
Unit
tCE
tACC
Max
Max
Min
Min
Min
Max
Min
Min
Max
Min
80
80
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Asynchronous Access Time
tAVDP
tAAVDS
tAAVDH
tOE
AVD# Low Time
Address Setup Time to Rising Edge of AVD#
Address Hold Time from Rising Edge of AVD#
Output Enable to Output Valid
4
7
6
13.5
0
Read
Output Enable Hold Time
Data# Polling
tOEH
10
10
0
tOEZ
tCAS
Output Enable to High Z (see Note)
CE# Setup Time to AVD#
Notes:
1. Not 100% tested.
2. The content in this document is Advance information for the S29WS128N.
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A d v a n c e I n f o r m a t i o n
CE#
OE#
tOE
tOEH
WE#
Data
tCE
tOEZ
Valid RD
tACC
RA
Addresses
AVD#
tAAVDH
tCAS
tAVDP
tAAVDS
Note: RA = Read Address, RD = Read Data.
Figure 14.11 Asynchronous Mode Read
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A d v a n c e I n f o r m a t i o n
14.8.5 Hardware Reset (RESET#)
Parameter
JEDEC
Std.
Description
All Speed Options
Unit
µs
tRP
tRH
RESET# Pulse Width
Reset High Time Before Read (See Note)
Min
Min
30
200
ns
Notes:
1. Not 100% tested.
2. The content in this document is Advance information for the S29WS128N. Content
in this document is Preliminary for the S29W256N.
CE#, OE#
tRH
RESET#
tRP
Figure 14.12 Reset Timings
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14.8.6 Erase/Program Timing
Parameter
JEDEC Standard
Description
54 MHz
66 MHz
80 MHz
Unit
ns
t
t
Write Cycle Time (Note 1)
Min
Min
80
5
AVAV
WC
Synchronous
Asynchronous
Synchronous
Asynchronous
ns
t
t
Address Setup Time (Notes 2, 3)
Address Hold Time (Notes 2, 3)
AVWL
AS
0
ns
9
t
t
Min
ns
WLAX
AH
20
8
t
AVD# Low Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
Max
Max
Max
Typ
Typ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
AVDP
t
t
t
Data Setup Time
45
20
DVWH
DS
t
Data Hold Time
0
0
WHDX
DH
t
t
Read Recovery Time Before Write
CE# Setup Time to AVD#
CE# Hold Time
GHWL
GHWL
t
0
CAS
t
t
0
WHEH
WLWH
WHWL
CH
t
t
t
Write Pulse Width
30
20
0
WP
t
Write Pulse Width High
WPH
t
Latency Between Read and Write Operations
SR/W
t
V
V
Rise and Fall Time
500
1
VID
ACC
ACC
t
Setup Time (During Accelerated Programming)
VIDS
t
t
CE# Setup Time to WE#
5
ELWL
CS
t
AVD# Setup Time to WE#
5
AVSW
AVHW
t
AVD# Hold Time to WE#
5
t
AVD# Setup Time to CLK
5
AVSC
t
AVD# Hold Time to CLK
5
AVHC
t
Clock Setup Time to WE#
5
CSW
t
Noise Pulse Margin on WE#
3
WEP
t
Sector Erase Accept Time-out
Erase Suspend Latency
50
20
20
0
SEA
t
ESL
PSL
ASP
t
Program Suspend Latency
t
Toggle Time During Erase within a Protected Sector
Toggle Time During Programming Within a Protected Sector
t
0
PSP
Notes:
1. Not 100% tested.
2. Asynchronous read mode allows Asynchronous program operation only. Synchronous read mode allows both Asynchronous and
Synchronous program operation.
3. In asynchronous program operation timing, addresses are latched on the falling edge of WE#. In synchronous program operation timing,
addresses are latched on the rising edge of CLK.
4. See the Erase and Programming Performance section for more information.
5. Does not include the preprogramming time.
6. The content in this document is Advance information for the S29WS128N. Content in this document is Preliminary for the S29W256N.
September 15, 2005 S71WS-N_01_A4
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A d v a n c e I n f o r m a t i o n
Erase Command Sequence (last two cycles)
Read Status Data
V
IH
CLK
V
IL
tAVDP
AVD#
tAH
tAS
SA
VA
VA
Addresses
Data
2AAh
555h for
chip erase
10h for
chip erase
In
Complete
55h
30h
Progress
tDS
tDH
CE#
tCH
OE#
WE#
tWP
tWHWH2
tCS
tWPH
tWC
tVCS
VCC
Figure 14.13 Chip/Sector Erase Operation Timings
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A d v a n c e I n f o r m a t i o n
Program Command Sequence (last two cycles)
Read Status Data
V
IH
CLK
V
IL
tAVSW
tAVHW
tAVDP
AVD#
tAS
tAH
Addresses
Data
555h
VA
VA
PA
In
A0h
tDS
Complete
PD
Progress
tCAS
tDH
CE#
tCH
OE#
WE#
tWP
tWHWH1
tCS
tWPH
tWC
tVCS
VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A23–A14 for the WS256N (A22–A14 for the WS128N) are don’t care during command sequence unlock cycles.
4. CLK can be either VIL or VIH
.
5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the
Configuration Register.
Figure 14.14 Program Operation Timing Using AVD#
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A d v a n c e I n f o r m a t i o n
Program Command Sequence (last two cycles)
Read Status Data
tAVCH
CLK
tAS
tAH
tAVSC
AVD#
tAVDP
Addresses
Data
PA
VA
VA
555h
In
Complete
A0h
PD
tDS
tDH
Progress
tCAS
CE#
tCH
OE#
WE#
tCSW
tWP
tWHWH1
tWPH
tWC
tVCS
VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A23–A14 for the WS256N (A22–A14 for the WS128N) are don’t care during command sequence unlock cycles.
4. Addresses are latched on the first rising edge of CLK.
5. Either CE# or AVD# is required to go from low to high in between programming command sequences.
6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration
Register. The Configuration Register must be set to the Synchronous Read Mode.
Figure 14.15 Program Operation Timing Using CLK in Relationship to AVD#
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A d v a n c e I n f o r m a t i o n
CE#
AVD#
WE#
Addresses
Data
PA
Don't Care
Don't Care
A0h
PD
Don't Care
OE#
ACC
tVIDS
V
V
ID
tVID
or V
IL
IH
Note: Use setup and hold times from conventional program operation.
Figure 14.16 Accelerated Unlock Bypass Programming Timing
AVD#
CE#
tCEZ
tCE
tOEZ
tCH
tOE
OE#
WE#
tOEH
tACC
High Z
Addresses
VA
VA
High Z
Status Data
Status Data
Data
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is completeData# Polling
outputs true data.
Figure 14.17 Data# Polling Timings (During Embedded Algorithm)
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A d v a n c e I n f o r m a t i o n
AVD#
CE#
tCEZ
tCE
tOEZ
tCH
tOE
OE#
WE#
tOEH
tACC
VA
High Z
High Z
Addresses
Data
VA
Status Data
Status Data
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, .
Figure 14.18 Toggle Bit Timings (During Embedded Algorithm)
CE#
CLK
AVD#
Addresses
OE#
VA
VA
tIACC
tIACC
Data
Status Data
Status Data
RDY
Notes:
1. The timings are similar to synchronous read timings.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, .
3. RDY is active with data (D8 = 1 in the Configuration Register). When D8 = 0 in the Configuration Register, RDY is active one clock cycle before
data.
Figure 14.19 Synchronous Data Polling Timings/Toggle Bit Timings
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A d v a n c e I n f o r m a t i o n
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#
to toggle DQ2 and DQ6.
Figure 14.20 DQ2 vs. DQ6
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
C124
C125
7D
C126
7E
C127
7F
C127
7F
C128
80
C129
81
C130
82
C131
83
CLK
7C
Address (hex)
(stays high)
AVD#
tRACC
tRACC
RDY(1)
latency
tRACC
tRACC
RDY(2)
Data
latency
D124
D125
D126
D127
D128
D129
D130
OE#,
CE#
(stays low)
Notes:
1. RDY(1) active with data (D8 = 1 in the Configuration Register).
2. RDY(2) active one clock cycle before data (D8 = 0 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.
4. Figure shows the device not crossing a bank in the process of performing an erase or program.
5. RDY does not go low and no additional wait states are required for WS ≤ 5.
Figure 14.21 Latency with Boundary Crossing when Frequency > 66 MHz
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A d v a n c e I n f o r m a t i o n
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
C124
C125
7D
C126
7E
C127
7F
C127
7F
CLK
7C
Address (hex)
(stays high)
AVD#
tRACC
tRACC
RDY(1)
latency
tRACC
tRACC
RDY(2)
Data
latency
D124
D125
D126
D127
Read Status
OE#,
CE#
(stays low)
Notes:
1. RDY(1) active with data (D8 = 1 in the Configuration Register).
2. RDY(2) active one clock cycle before data (D8 = 0 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.
4. Figure shows the device crossing a bank in the process of performing an erase or program.
5. RDY does not go low and no additional wait states are required for WS ≤ 5.
Figure 14.22 Latency with Boundary Crossing into Program/Erase Bank
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A d v a n c e I n f o r m a t i o n
Data
D0
D1
Rising edge of next clock cycle
following last wait state triggers
next burst data
AVD#
OE#
total number of clock cycles
following addresses being latched
1
2
0
3
1
4
5
6
4
7
5
CLK
2
3
number of clock cycles
programmed
Wait State Configuration Register Setup:
D13, D12, D11 = “111” ⇒ Reserved
D13, D12, D11 = “110” ⇒ Reserved
D13, D12, D11 = “101” ⇒ 5 programmed, 7 total
D13, D12, D11 = “100” ⇒ 4 programmed, 6 total
D13, D12, D11 = “011” ⇒ 3 programmed, 5 total
Note: Figure assumes address D0 is not at an address boundary, and wait state is set to “101”.
Figure 14.23 Example of Wait States Insertion
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A d v a n c e I n f o r m a t i o n
Last Cycle in
Program or
Sector Erase
Read status (at least two cycles) in same bank
and/or array data from other bank
Begin another
write or program
command sequence
Command Sequence
tWrite Cycle
tWrite Cycle
tRead Cycle
tRead Cycle
CE#
OE#
tOE
tGHWL
tOEH
WE#
Data
tWPH
tOEZ
tWP
tDS
tACC
tOEH
tDH
PD/30h
RD
RD
AAh
tSR/W
RA
Addresses
PA/SA
tAS
RA
555h
AVD#
tAH
Note: Breakpoints in waveforms indicate that system may alternately read array data from the “non-busy bank” while
checking the status of the program or erase operation in the “busy” bank. The system should read status twice to ensure
valid information.
Figure 14.24 Back-to-Back Read/Write Cycle Timings
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14.8.7 Erase and Programming Performance
Parameter
Typ (Note 1)
0.6
Max (Note 2)
Unit
Comments
64 Kword
16 Kword
VCC
VCC
3.5
2
Sector Erase Time
s
<0.15
Excludes 00h
programming prior
to erasure (Note 4)
153.6 (WS256N)
77.4 (WS128N)
308 (WS256N)
154 (WS128N)
VCC
Chip Erase Time
s
130.6 (WS256N)
65.8 (WS128N)
262 (WS256N)
132 (WS128N)
ACC
VCC
ACC
VCC
ACC
VCC
ACC
40
24
400
240
94
Single Word Programming Time
(Note 8)
µs
µs
µs
9.4
6
Effective Word Programming Time
utilizing Program Write Buffer
60
300
192
3000
1920
Total 32-Word Buffer Programming
Time
157.3 (WS256N)
78.6 (WS128N)
314.6 (WS256N)
157.3 (WS128N)
VCC
Excludes system
level overhead
(Note 5)
Chip Programming Time (Note 3)
s
100.7 (WS256N)
50.3 (WS128N)
201.3 (WS256N)
100.7 (WS128N)
ACC
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 1.8 V VCC, 10,000
cycles; checkerboard data pattern.
2. Under worst case conditions of 90°C, VCC = 1.70 V, 100,000 cycles.
3. Typical chip programming time is considerably less than the maximum chip programming time listed, and is
based on utilizing the Write Buffer.
4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before
erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program
command. See the Appendix for further information on command definitions.
6. Contact the local sales office for minimum cycling endurance values in specific applications and operating
conditions.
7. Refer to Application Note “Erase Suspend/Resume Timing” for more details.
8. Word programming specification is based upon a single word programming operation not utilizing the write
buffer.
9. The content in this document is Advance information for the S29WS128N. Content in this document is
Preliminary for the S29W256N.
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14.8.8 BGA Ball Capacitance
Parameter
Symbol
Parameter Description
Te st S e tup
VIN = 0
Typ.
5.3
5.8
6.3
Max
6.3
6.8
7.3
Unit
pF
CIN
Input Capacitance
Output Capacitance
Control Pin Capacitance
COUT
CIN2
VOUT = 0
VIN = 0
pF
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25 C; f = 1.0 MHz.
°
3. The content in this document is Advance information for the S29WS128N. Content in this document is
Preliminary for the S29W256N.
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A d v a n c e I n f o r m a t i o n
15 Appendix
This section contains information relating to software control or interfacing with the Flash device.
For additional information and assistance regarding software, see the Additional Resources sec-
tion on page 23, or explore the Web at www.amd.com and www.fujitsu.com.
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A d v a n c e I n f o r m a t i o n
Table 15.1 Memory Array Commands
Bus Cycles (Notes 1–5)
First
Addr
Second
Third
Addr
Fourth
Addr Data
Fifth
Addr
Sixth
Addr Data
Command Sequence
(Notes)
Data
RD
Addr
Data
Data
Data
Asynchronous Read (6)
Reset (7)
Manufacturer ID
1
1
4
6
RA
XXX
555
555
F0
AA
2AA
2AA
55
55
[BA]555
[BA]555
90
90
[BA]X00 0001
[BA]X01 227E
Device ID (9)
AA
BA+X0E
PA
Data
PD
BA+X0F 2200
Indicator Bits (10)
4
555
AA
2AA
55
[BA]555
90
[BA]X03
Data
Program
4
6
1
3
6
6
1
1
4
4
1
3
2
1
555
555
SA
555
555
555
BA
AA
AA
29
AA
AA
AA
B0
30
AA
AA
98
AA
A0
98
2AA
2AA
55
55
555
PA
A0
25
PA
PA
PD
Write to Buffer (11)
Program Buffer to Flash
Write to Buffer Abort Reset (12)
Chip Erase
WC
WBL
PD
2AA
2AA
2AA
55
55
55
555
555
555
F0
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Erase/Program Suspend (13)
Erase/Program Resume (14)
Set Configuration Register (18)
Read Configuration Register
CFI Query (15)
BA
555
555
[BA]555
555
XXX
XXX
2AA
2AA
55
55
555
555
D0
C6
X00
X00
CR
CR
Entry
Program (16)
2AA
PA
55
PD
555
20
CFI (16)
Reset
2
XXX
90
XXX
00
Entry
3
4
1
555
555
00
AA
AA
Data
2AA
2AA
55
55
555
555
88
A0
Program (17)
Read (17)
PA
PD
00
Exit (17)
4
555
AA
2AA
55
555
90
XXX
Legend:
X = Don’t care.
RA = Read Address.
RD = Read Data.
SA = Sector Address. WS256N = A23–A14; WS128N = A22–A14.
BA = Bank Address. WS256N = A23–A20; WS128N = A22–A20.
CR = Configuration Register data bits D15–D0.
PA = Program Address. Addresses latch on the rising edge of the
AVD# pulse or active edge of CLK, whichever occurs first.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
PD = Program Data. Data latches on the rising edge of WE# or CE#
pulse, whichever occurs first.
WC = Word Count. Number of write buffer locations to load minus 1.
Notes:
1. See Table 10.1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells indicate read cycles.
4. Address and data bits not specified in table, legend, or notes are
don’t cares (each hex digit implies 4 bits of data).
5. Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
6. No unlock or command cycles required when bank is reading
array data.
7. Reset command is required to return to reading array data (or to
the erase-suspend-read mode if previously in Erase Suspend)
when a bank is in the autoselect mode, or if DQ5 goes high
(while the bank is providing status information) or performing
sector lock/unlock.
13. System may read and program in non-erasing sectors, or enter
the autoselect mode, when in the Erase Suspend mode. The
Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
14. Erase Resume command is valid only during the Erase Suspend
mode, and requires the bank address.
15. Command is valid when device is ready to read array data or
when device is in autoselect mode. Address equals 55h on all
future devices, but 555h for WS256N/128N.
16. Requires Entry command sequence prior to execution. Unlock
Bypass Reset command is required to return to reading array
data.
17. Requires Entry command sequence prior to execution. Secured
Silicon Sector Exit Reset command is required to exit this mode;
device may otherwise be placed in an unknown state.
18. Requires reset command to configure the Configuration Register.
8. The system must provide the bank address. See Autoselect
section for more information.
9. Data in cycle 5 is 2230 (WS256N) or 2231 (WS128N).
10. See Table 10.9 for indicator bit values.
11. Total number of cycles in the command sequence is determined
by the number of words written to the write buffer.
12. Command sequence resets device for next command after write-
to-buffer operation.
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A d v a n c e I n f o r m a t i o n
Table 15.2 Sector Protection Commands
Bus Cycles (Notes 1–4)
First
Second
Third
Fourth
Fifth
Sixth
Seventh
Command Sequence
(Notes)
Addr
555
XX
Data
AA
Addr
2AA
Data
55
Addr
Data
Addr Data Addr Data Addr Data Addr Data
Command Set Entry (5)
3
2
1
2
3
2
4
7
2
3
2
2
1
2
3
2
1
555
40
Lock
Register
Bits
Program (6, 12)
A0
77/00
data
Read (6)
77
XX
data
90
Command Set Exit (7)
Command Set Entry (5)
Program [0-3] (8)
Read (9)
XX
2AA
00
00
55
555
XX
AA
555
60
A0
PWD[0-3]
PWD1
03
Password
Protection
0...00 PWD0 0...01
0...02
00
PWD2 0...03 PWD3
Unlock
00
XX
555
XX
XX
SA
XX
555
XX
BA
25
90
AA
00
XX
PWD0
01
PWD1
02
PWD2
03
PWD3
00
29
Command Set Exit (7)
Command Set Entry (5)
PPB Program (10)
All PPB Erase (10, 11)
PPB Status Read
00
2AA
SA
55
[BA]555
C0
A0
00
Non-Volatile
Sector
Protection (PPB)
80
00
30
RD(0)
90
Command Set Exit (7)
Command Set Entry (5)
PPB Lock Bit Set
XX
2AA
XX
00
55
00
Global
Volatile Sector
Protection
Freeze
AA
A0
[BA]555
[BA]555
50
E0
PPB Lock Bit Status Read
RD(0)
Command Set Exit (7)
2
XX
90
XX
00
(PPB Lock)
Command Set Entry (5)
DYB Set
3
2
2
1
2
555
XX
XX
SA
XX
AA
A0
2AA
SA
55
00
01
Volatile Sector
Protection
(DYB)
DYB Clear
A0
SA
DYB Status Read
Command Set Exit (7)
RD(0)
90
XX
00
Legend:
X = Don’t care.
BA = Bank Address. WS256N = A23–A20; WS128N = A22–A20.
RA = Address of the memory location to be read.
PD(0) = Secured Silicon Sector Lock Bit. PD(0), or bit[0].
PD(1) = Persistent Protection Mode Lock Bit. PD(1), or bit[1], must
be set to ‘0’ for protection while PD(2), bit[2] must be left as ‘1’.
PD(2) = Password Protection Mode Lock Bit. PD(2), or bit[2], must
be set to ‘0’ for protection while PD(1), bit[1] must be left as ‘1’.
PD(3) = Protection Mode OTP Bit. PD(3) or bit[3].
PWD3–PWD0 = Password Data. PD3–PD0 present four 16 bit
combinations that represent the 64-bit Password
PWA = Password Address. Address bits A1 and A0 are used to select
each 16-bit portion of the 64-bit entity.
PWD = Password Data.
RD(0), RD(1), RD(2) = DQ0, DQ1, or DQ2 protection indicator bit. If
protected, DQ0, DQ1, or DQ2 = 0. If unprotected, DQ0, DQ1,
DQ2 = 1.
SA = Sector Address. WS256N = A23–A14; WS128N = A22–A14.
Notes:
1. All values are in hexadecimal.
2. Shaded cells indicate read cycles.
8. Entire two bus-cycle sequence must be entered for each portion
of the password.
9. Full address range is required for reading password.
10. See Figure 11.2 for details.
3. Address and data bits not specified in table, legend, or notes are
don’t cares (each hex digit implies 4 bits of data).
4. Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
5. Entry commands are required to enter a specific mode to enable
instructions only available within that mode.
11. “All PPB Erase” command pre-programs all PPBs before erasure
to prevent over-erasure.
12. The second cycle address for the lock register program operation
is 77 for S29WS256N; however, for WS128N this address is 00.
6. If both the Persistent Protection Mode Locking Bit and the
Password Protection Mode Locking Bit are set at the same time,
the command operation aborts and returns the device to the
default Persistent Sector Protection Mode during 2nd bus cycle.
Note that on all future devices, addresses equal 00h, but is
currently 77h for the WS256N only. See Tables 11.1 and 11.2 for
explanation of lock bits.
7. Exit command must be issued to reset the device into read
mode; device may otherwise be placed in an unknown state.
September 15, 2005 S71WS-N_01_A4
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A d v a n c e I n f o r m a t i o n
15.1 Common Flash Memory Interface
The Common Flash Interface (CFI) specification outlines device and host system software inter-
rogation handshake, which allows specific vendor-specified soft-ware algorithms to be used for
entire families of devices. Software support can then be device-independent, JEDEC ID-indepen-
dent, and forward- and back-ward-compatible for the specified flash device families. Flash
vendors can standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to
address (BA)555h any time the device is ready to read array data. The system can read CFI in-
formation at the addresses given in Tables 15.3–15.6) within that bank. All reads outside of the
CFI address range, within the bank, returns non-valid data. Reads from other banks are allowed,
writes are not. To terminate reading CFI data, the system must write the reset command.
The following is a C source code example of using the CFI Entry and Exit functions. Refer to
the Spansion Low Level Driver User’s Guide (available on www.amd.com and
www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
/* Example: CFI Entry command */
*( (UINT16 *)bank_addr + 0x555 ) = 0x0098;
/* write CFI entry command
/* write cfi exit command
*/
*/
/* Example: CFI Exit command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x00F0;
For further information, please refer to the CFI Specification (see JEDEC publications JEP137-A
and JESD68.01and CFI Publication 100). Please contact your sales office for copies of these
documents.
Table 15.3 CFI Query Identification String
Addresses
Data
Description
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
0000h
0000h
Table 15.4 System Interface String
Addresses
Data
Description
V
Min. (write/erase)
CC
1Bh
1Ch
0017h
D7–D4: volt, D3–D0: 100 millivolt
V
Max. (write/erase)
CC
0019h
D7–D4: volt, D3–D0: 100 millivolt
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
0000h
0000h
0006h
0009h
000Ah
0000h
0004h
0004h
0003h
0000h
V
Min. voltage (00h = no V pin present)
PP
PP
V
Max. voltage (00h = no V pin present)
PP
PP
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
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A d v a n c e I n f o r m a t i o n
Table 15.5 Device Geometry Definition
Addresses
Data
Description
0019h (WS256N)
0018h (WS128N)
Device Size = 2N byte
27h
28h
29h
0001h
0000h
Flash Device Interface description (refer to CFI publication 100)
Max. number of bytes in multi-byte write = 2N
(00h = not supported)
2Ah
2Bh
0006h
0000h
2Ch
0003h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
0003h
0000h
0080h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
00FDh (WS256N)
007Dh (WS128N)
31h
Erase Block Region 2 Information
32h
33h
34h
0000h
0000h
0002h
35h
36h
37h
38h
0003h
0000h
0080h
0000h
Erase Block Region 3 Information
Erase Block Region 4 Information
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
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A d v a n c e I n f o r m a t i o n
Table 15.6 Primary Vendor-Specific Extended Query
Addresses
Data
Description
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
0031h
0034h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
0100h
Silicon Technology (Bits 5-2) 0100 = 0.11 µm
Erase Suspend
46h
47h
48h
49h
4Ah
4Bh
0002h
0001h
0000h
0008h
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
08 = Advanced Sector Protection
Simultaneous Operation
Number of Sectors in all banks except boot bank
00F3h (WS256N)
007Bh (WS128N)
Burst Mode Type
00 = Not Supported, 01 = Supported
0001h
0000h
Page Mode Type
4Ch
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 04 = 16 Word
Page
ACC (Acceleration) Supply Minimum
4Dh
4Eh
0085h
0095h
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
0001h = Dual Boot Device
4Fh
50h
51h
0001h
0001h
0001h
Program Suspend. 00h = not supported
Unlock Bypass
00 = Not Supported, 01=Supported
52h
53h
0007h
0014h
Secured Silicon Sector (Customer OTP Area) Size 2N bytes
Hardware Reset Low Time-out during an embedded algorithm to read
mode Maximum 2N ns
Hardware Reset Low Time-out not during an embedded algorithm to read
mode Maximum 2N ns
54h
0014h
Erase Suspend Time-out Maximum 2N ns
Program Suspend Time-out Maximum 2N ns
Bank Organization: X = Number of banks
55h
56h
57h
0005h
0005h
0010h
0013h (WS256N)
000Bh (WS128N)
58h
59h
Bank 0 Region Information. X = Number of sectors in bank
Bank 1 Region Information. X = Number of sectors in bank
0010h (WS256N)
0008h (WS128N)
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A d v a n c e I n f o r m a t i o n
Table 15.6 Primary Vendor-Specific Extended Query (Continued)
Addresses
Data
Description
0010h (WS256N)
0008h (WS128N)
5Ah
Bank 2 Region Information. X = Number of sectors in bank
0010h (WS256N)
0008h (WS128N)
5Bh
5Ch
5Dh
5Eh
5Fh
60h
61h
62h
63h
64h
65h
66h
67h
Bank 3 Region Information. X = Number of sectors in bank
Bank 4 Region Information. X = Number of sectors in bank
Bank 5 Region Information. X = Number of sectors in bank
Bank 6 Region Information. X = Number of sectors in bank
Bank 7 Region Information. X = Number of sectors in bank
Bank 8 Region Information. X = Number of sectors in bank
Bank 9 Region Information. X = Number of sectors in bank
Bank 10 Region Information. X = Number of sectors in bank
Bank 11 Region Information. X = Number of sectors in bank
Bank 12 Region Information. X = Number of sectors in bank
Bank 13 Region Information. X = Number of sectors in bank
Bank 14 Region Information. X = Number of sectors in bank
Bank 15 Region Information. X = Number of sectors in bank
0010h (WS256N)
0008h (WS128N)
0010h (WS256N)
0008h (WS128N)
0010h (WS256N)
0008h (WS128N)
0010h (WS256N)
0008h (WS128N)
0010h (WS256N)
0008h (WS128N)
0010h (WS256N)
0008h (WS128N)
0010h (WS256N)
0008h (WS128N)
0010h (WS256N)
0008h (WS128N)
0010h (WS256N)
0008h (WS128N)
0010h (WS256N)
0008h (WS128N)
0010h (WS256N)
0008h (WS128N)
0013h (WS256N)
000Bh (WS128N)
September 15, 2005 S71WS-N_01_A4
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97
A d v a n c e I n f o r m a t i o n
16 Commonly Used Terms
Ter m
D efi niti on
ACCelerate. A special purpose input signal which allows for faster programming or
erase operation when raised to a specified voltage above VCC. In some devices ACC
may protect all sectors when at a low voltage.
ACC
Most significant bit of the address input [A23 for 256Mbit, A22 for128Mbit, A21 for
64Mbit]
Amax
Amin
Least significant bit of the address input signals (A0 for all devices in this document).
Operation where signal relationships are based only on propagation delays and are
unrelated to synchronous control (clock) signal.
Asynchronous
Read mode for obtaining manufacturer and device information as well as sector
protection status.
Autoselect
Bank
Section of the memory array consisting of multiple consecutive sectors. A read
operation in one bank, can be independent of a program or erase operation in a
different bank for devices that offer simultaneous read and write feature.
Smaller size sectors located at the top and or bottom of Flash device address space.
The smaller sector size allows for finer granularity control of erase and protection for
code or parameters used to initiate system operation after power-on or reset.
Boot sector
Boundary
Burst Read
Byte
Location at the beginning or end of series of memory locations.
See synchronous read.
8 bits
Common Flash Interface. A Flash memory industry standard specification [JEDEC 137-
A and JESD68.01] designed to allow a system to interrogate the Flash to determine its
size, type and other performance parameters.
CFI
Clear
Zero (Logic Low Level)
Special purpose register which must be programmed to enable synchronous read
mode
Configuration Register
Synchronous method of burst read whereby the device reads continuously until it is
stopped by the host, or it has reached the highest address of the memory array, after
which the read address wraps around to the lowest memory array address
Continuous Read
Erase
Returns bits of a Flash memory array to their default state of a logical One (High Level).
Halts an erase operation to allow reading or programming in any sector that is not
selected for erasure
Erase Suspend/Erase Resume
Ball Grid Array package. Spansion LLC offers two variations: Fortified Ball Grid Array
and Fine-pitch Ball Grid Array. See the specific package drawing or connection diagram
for further details.
BGA
Synchronous (burst) read operation in which 8, 16, or 32 words of sequential data with
Linear Read
or without wraparound before requiring a new initial address
.
Multi-Chip Package. A method of combining integrated circuits in a single package by
stacking multiple die of the same or different devices.
MCP
Memory Array
MirrorBit™ Technology
The programmable area of the product available for data storage.
Spansion™ trademarked technology for storing multiple bits of data in the same
transistor.
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A d v a n c e I n f o r m a t i o n
Ter m
D efi niti on
Group of words that may be accessed more rapidly as a group than if the words were
accessed individually.
Page
Asynchronous read operation of several words in which the first word of the group
takes a longer initial access time and subsequent words in the group take less page
access time to be read. Different words in the group are accessed by changing only the
least significant address lines.
Page Read
Sector protection method which uses a programmable password, in addition to the
Password Protection
Persistent Protection
Program
Persistent Protection method, for protection of sectors in the Flash memory device
.
Sector protection method that uses commands and only the standard core voltage
supply to control protection of sectors in the Flash memory device. This method
replaces a prior technique of requiring a 12V supply to control the protection method.
Stores data into a Flash memory by selectively clearing bits of the memory array in
order to leave a data pattern of ones and zeros.
Program Suspend/Program
Resume
Halts a programming operation to read data from any location that is not selected for
programming or erase.
Read
Host bus cycle that causes the Flash to output data onto the data bus.
Dynamic storage bits for holding device control information or tracking the status of
an operation.
Registers
Secured Silicon. An area consisting of 256 bytes in which any word may be
programmed once, and the entire area may be protected once from any future
programming. Information in this area may be programmed at the factory or by the
user. Once programmed and protected there is no way to change the secured
information. This area is often used to store a software readable identification such as
a serial number.
Secured Silicon
Use of one or more control bits per sector to indicate whether each sector may be
programmed or erased. If the Protection bit for a sector is set the embedded
algorithms for program or erase ignores program or erase commands related to that
sector.
Sector Protection
Sector
An Area of the memory array in which all bits must be erased together by an erase
operation.
Mode of operation in which a host system may issue a program or erase command to
one bank, that embedded algorithm operation may then proceed while the host
immediately follows the embedded algorithm command with reading from another
bank. Reading may continue concurrently in any bank other than the one executing
the embedded algorithm operation.
Simultaneous Operation
Synchronous Operation
Operation that progresses only when a timing signal, known as a clock, transitions
between logic levels (that is, at a clock edge).
Separate power supply or voltage reference signal that allows the host system to set
the voltage levels that the device generates at its data outputs and the voltages
tolerated at its data inputs.
VersatileIO™ (VIO
Unlock Bypass
Word
)
Mode that facilitates faster program times by reducing the number of command bus
cycles required to issue a write operation command. In this mode the initial two Unlock
write cycles, of the usual 4 cycle Program command, are not required – reducing all
Program commands to two bus cycles while in this mode.
Two contiguous bytes (16 bits) located at an even byte boundary. A double word is two
contiguous words located on a two word boundary. A quad word is four contiguous
words located on a four word boundary.
September 15, 2005 S71WS-N_01_A4
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99
A d v a n c e I n f o r m a t i o n
Ter m
D efi niti on
Special burst read mode where the read address wraps or returns back to the lowest
address boundary in the selected range of words, after reading the last Byte or Word
in the range, e.g. for a 4 word range of 0 to 3, a read beginning at word 2 would read
words in the sequence 2, 3, 0, 1.
Wraparound
Interchangeable term for a program/erase operation where the content of a register
and or memory location is being altered. The term write is often associated with writing
command cycles to enter or exit a particular mode of operation.
Write
Multi-word area in which multiple words may be programmed as a single operation. A
Write Buffer
Write Buffer may be 16 to 32 words long and is located on a 16 or 32 word boundary
respectively.
Method of writing multiple words, up to the maximum size of the Write Buffer, in one
Write Buffer Programming
Write Operation Status
operation. Using Write Buffer Programming results in
time than by using single word at a time programming commands.
≥
8 times faster programming
Allows the host system to determine the status of a program or erase operation by
reading several special purpose register bits
.
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1.8V pSRAM Type 4
4M x 16-bit Synchronous Burst pSRAM
ADVANCE
INFORMATION
Features
Process Technology: CMOS
Organization: 4M x16 bit
Power Supply Voltage: 1.7~2.0V
Three State Outputs
Supports MRS (Mode Register Set)
MRS control - MRS Pin Control
Supports Power Saving modes - Partial Array Refresh mode Internal TCSR
Supports Driver Strength Optimization for system environment power saving
Supports Asynchronous 4-Page Read and Asynchronous Write Operation
Supports Synchronous Burst Read and Asynchronous Write Operation (Address Latch Type
and Low ADV# Type)
Supports Synchronous Burst Read and Synchronous Burst Write Operation
Synchronous Burst (Read/Write) Operation
— Supports 4 word / 8 word / 16 word and Full Page(256 word) burst
— Supports Linear Burst type & Interleave Burst type
— Latency support:
Latency 5 @ 66 MHz(tCD 10ns)
Latency 4 @ 54 MHz(tCD 10ns)
— Supports Burst Read Suspend in No Clock toggling
— Supports Burst Write Data Masking by /UB & /LB pin control
— Supports WAIT# pin function for indicating data availability.
Max. Burst Clock Frequency: 66 MHz
Publication Number S71WS-N_01 Revision A Amendment 4 Issue Date September 15, 2005
A d v a n c e I n f o r m a t i o n
17 Pin Description
Pin Name
CLK
Function
Clock
Type
Description
Commands, Data are referenced to CLK
ADV#
Address Valid
Address valid from ADV# falling edge to ADV# rising edge
MRS# enables Mode Register to be set.
Addresses are loaded as Mode setting is Low
MRS#
Mode Register set
CS# enables the chip to start operating when Low
CS#
Chip Select
CS# disables the chip and puts it into standby mode when High
CS# stops burst operating.during burst operation when High
Input
OE#
WE#
Output Enable
Write Enable
OE# enables the chip to output the data when Low
WE# enables the chip to start writing the data when Low
LB#
UB#
Lower Byte (I/O
)
0~7
UB# (or LB#) enables upper byte (or lower byte) to be
operated when Low
Upper Byte (I/O
)
8~15
Valid addresses input when ADV# is low.
Mode setting inputs during MRS# Low.
A0-A21
Address 0 ~ Address 21
Data Inputs / Outputs
Depending on UB# or LB# status, word (16-bit,
UB#, and LB# low) data, upper byte (8-bit, UB#
low & LB# high) data or lower byte (8-bit, LB# low,
and UB# high) data is loaded
I/O0-I/O15
Input/Output
V
Core Voltage Source
I/O Voltage Source
Core Ground Source
I/O Ground Source
Valid Data Indicator
Do Not Use
Power
Power
GND
Power supply for cells and circuits except for I/O buffer circuits
Power supply for I/O buffer circuits
CC
V
CCQ
V
Ground for cells and circuits except for I/O buffer circuits
Ground for I/O buffer circuits
SS
V
GND
SSQ
WAIT#
DNU
Output
—
WAIT# indicates that output data is invalid when Low
—
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A d v a n c e I n f o r m a t i o n
18 Functional Block Diagram
Precharge circuit.
CLK generator
Vcc
Vss
Row
Addresses
Row
select
Memory array
Data
controller
I/O Circuit
I/O0~I/O7
Column select
Data
controller
I/O8~I/O15
Data
controller
Column Addresses
CLK
ADV#
MRS#
CS#
Control Logic
OE#
WE#
UB#
LB#
WAIT#
19 Power Up Sequence
After applying VCC up to minimum operating voltage (1.7 V), drive CS# high first and then drive
MRS# high. This gets the device into power up mode. Wait for a minimum of 200 µs to get into
the normal operation mode. During power up mode, the standby current cannot be guaranteed.
To obtain stable standby current levels, at least one cycle of active operation should be imple-
mented regardless of wait time duration. To obtain appropriate device operation, be sure to follow
the power up sequence.
1. Apply power.
2. Maintain stable power (VCC min.=1.7 V) for a minimum 200 µs with CS# and MRS# high.
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103
A d v a n c e I n f o r m a t i o n
20 Power Up and Standby Mode Timing Diagrams
20.1 Power Up
200 µs
VCC(Min)
V
CC
Min. 0ns
Min. 0ns
MRS#
CS#
Min. 200 µs
PowerUp Mode
Normal Operation
Note: After V reaches V (Min.), wait 200 µs with CS# and MRS# high. This puts the device into normal operation.
CC
CC
Figure 20.1 Power Up Timing
20.2 Standby Mode
CS# = V
CS# = UB# = LB# = V
CS# = V , UB# or LB# = V
IL IL
IH
IL
MRS# = V
IH
WE# = V , MRS# = V
IL
MRS# = V
CS# = V
IH
IH
IH
MRS# = V
IH
Initial State
(wait 200µs)
Standby
Mode
PAR
Mode
Power On
MRS Setting
Active
MRS# = V
IL
MRS Setting
CS# = V
IL
WE# = V , MRS#=V
IL IL
Figure 20.2 Standby Mode State Machines
The default mode after power up is Asynchronous mode (4 Page Read and Asynchronous Write).
But this default mode is not 100% guaranteed, so the MRS# setting sequence is highly recom-
mended after power up.
For entry to PAR mode, drive the MRS# pin into VIL for over 0.5µs (suspend period) during
standby mode after the MRS# setting has been completed (A4=1, A3=0). If the MRS# pin is
driven into VIH during PAR mode, the device reverts to standby mode without the wake up
sequence.
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A d v a n c e I n f o r m a t i o n
21 Functional Description
Table 21.1 Asynchronous 4 Page Read & Asynchronous Write Mode (A15/A14=0/0)
Mode
Deselected
CS#
H
H
L
MRS#
H
OE#
X
WE#
X
LB#
X
X
X
H
L
UB#
X
I/O
I/O
Power
Standby
PAR
0-7
8-15
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Deselected
L
X
X
X
Output Disabled
Outputs Disabled
Lower Byte Read
Upper Byte Read
Word Read
H
H
X
H
X
X
Active
Active
Active
Active
Active
Active
Active
Active
Active
L
H
H
H
L
L
H
L
H
H
H
L
D
OUT
L
H
L
H
L
High-Z
D
D
OUT
OUT
L
H
L
L
D
OUT
Lower Byte Write
Upper Byte Write
Word Write
L
H
H
H
H
H
L
H
L
D
High-Z
IN
L
H
L
H
L
High-Z
D
D
IN
IN
L
H
L
L
D
IN
Mode Register Set
L
L
L
L
L
High-Z
High-Z
Legend: X = Don’t care (must be low or high state).
Notes:
1. In asynchronous mode, Clock and ADV# are ignored.
2. The WAIT# pin is High-Z in asynchronous mode.
Table 21.2 Synchronous Burst Read & Asynchronous Write Mode (A15/A14=0/1)
Mode
CS# MRS#
OE#
WE#
LB#
UB#
I/O
I/O
CLK
ADV#
Power
0-7
8-15
X
X
X
X
High- High-
X
X
Deselected
H
H
L
H
L
Standby
(Note 1) (Note 1) (Note 1) (Note 1)
Z
Z
(note 2)
(note 2)
X
X
X
X
High- High-
X
X
Deselected
PAR
(Note 1) (Note 1) (Note 1) (Note 1)
Z
Z
(note 2)
(note 2)
Output
Disabled
X
X
High- High-
X
H
H
H
H
H
H
Active
Active
(Note 1) (Note 1)
Z
Z
(note 2)
Outputs
Disabled
X
X
High- High-
X
L
H
H
(Note 1) (Note 1)
Z
Z
(note 2)
Read
X
X
X
High- High-
L
L
L
H
H
H
H
Active
Active
Active
Command
(Note 1)
(Note 1) (Note 1)
Z
Z
Lower Byte
Read
High-
Z
L
L
H
H
L
H
L
D
H
H
OUT
Upper Byte
Read
High-
Z
H
D
D
OUT
OUT
Word Read
L
H
L
H
L
L
D
H
Active
OUT
Lower Byte
Write
High-
Z
X
L
L
L
H
H
H
H
H
H
L
L
L
L
H
L
H
L
D
Active
Active
Active
IN
or
or
or
(note 2)
Upper Byte
Write
High-
Z
X
D
D
IN
IN
(note 2)
X
Word Write
L
D
IN
(note 2)
Mode
Register
Set
High- High-
X
L
L
H
L
L
L
Active
or
Z
Z
(note 2)
Notes:
1. X must be low or high state.
2. X means Don’t care (can be low, high or toggling).
3. WAIT# is the device output signal and does not have any affect on the mode definition. Please refer to each timing
diagram for Wait# pin function.
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105
A d v a n c e I n f o r m a t i o n
Table 21.3 Synchronous Burst Read & Synchronous Burst Write Mode(A15/A14 = 1/0)
Mode
CS# MRS#
OE#
WE#
LB#
UB#
I/O
I/O
CLK
ADV#
Power
0-7
8-15
X
X
X
X
X
X
Deselected
H
H
L
H
L
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
Standby
(Note 1)
(Note 1)
(Note 1) (Note 1)
(Note 2) (Note 2)
X
X
X
X
X
X
Deselected
PAR
(Note 1)
(Note 1)
(Note 1) (Note 1)
(Note 2) (Note 2)
Output
Disabled
X
H
H
H
H
X
H
X
H
H
H
Active
Active
(Note 2)
Outputs
Disabled
X
X
X
L
(Note 1)
(Note 1)
(Note 2)
Read
X
L
L
L
H
H
H
H
H
H
X
L
X
H
L
High-Z High-Z
Active
Active
Active
Command
(Note 1)
Lower Byte
Read
L
L
D
High-Z
H
H
OUT
Upper Byte
Read
H
High-Z
D
OUT
OUT
Word Read
L
H
L
H
L
L
D
D
H
Active
OUT
Write
X
L
L
L
H
H
H
High-Z High-Z
Active
Active
Active
L
or
Command
(Note 1)
Lower Byte
Write
X
H
H
L
H
L
D
High-Z
H
H
IN
(Note 1)
Upper Byte
Write
X
H
High-Z
D
IN
IN
(Note 1)
X
Word Write
L
L
H
L
H
H
L
L
L
L
D
D
H
Active
Active
IN
(Note 1)
Mode
Register
Set
High-Z High-Z
L
or
Notes:
1. X must be low or high state.
2. X means “Don’t care” (can be low, high or toggling).
3. WAIT# is the device output signal and does not have any affect on the mode definition. Please refer to each timing
diagram for WAIT# pin function.
4. The last data written in the previous Asynchronous write mode is not valid. To make the lastly written data valid,
implement at least one dummy write cycle before change mode into synchronous burst read and synchronous burst
write mode.
5. The data written in Synchronous burst write operation can be corrupted by the next Asynchronous write operation. So
the transition from Synchronous burst write operation to Asynchronous write operation is prohibited.
106
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22 Mode Register Setting Operation
The device has several modes:
Asynchronous Page Read mode
Asynchronous Write mode
Synchronous Burst Read mode
Synchronous Burst Write mode
Standby mode
Partial Array Refresh (PAR) mode.
Partial Array Refresh (PAR) mode is defined through the Mode Register Set (MRS) option. The MRS
option also defines burst length, burst type, wait polarity and latency count at synchronous burst
read/write mode.
22.1 Mode Register Set (MRS)
The mode register stores the data for controlling the various operation modes of this device. It
programs Partial Array Refresh (PAR), burst length, burst type, latency count and various vendor
specific options to make pSRAM Type 4 useful for a variety of different applications. The default
values of mode register are defined, therefore when the reserved address is input, the device runs
at default modes.
The mode register is written by driving CS#, ADV#, WE#, UB#, LB# and MRS# to VIL and driving
OE# to VIH during valid addressing. The mode register is divided into various fields depending on
the fields of functions. The PAR field uses A0~A4, Burst Length field uses A5~A7, Burst Type uses
A8, Latency Count uses A9~A11, Wait Polarity uses A13, Operation Mode uses A14~A15 and
Driver Strength uses A16~A17.
Refer to Table 22.1 for detailed Mode Register Settings. A18~A22 addresses are Don’t care in the
Mode Register Setting.
Table 22.1 Mode Register Setting According to Field of Function
Address
Function
A17 – A16
A15 – A14
A13
A12
A11 – A9
A8
A7 – A5
A4 – A3
A2
A1 – A0
DS
MS
WP
RFU
Latency
BT
BL
PAR
PARA
PARS
Note: DS (Driver Strength), MS (Mode Select), WP (Wait Polarity), Latency (Latency Count), BT (Burst Type), BL (Burst
Length), PAR (Partial Array Refresh), PARA (Partial Array Refresh Array), PARS (Partial Array Refresh Size), RFU (Reserved
for Future Use).
Table 22.2 Mode Register Set
Driver Strength
DS
Mode Select
MS
A17
0
A16
0
A15
0
A14
0
Full Drive (default)
1/2 Drive
Async. 4 Page Read / Async. Write (default)
Sync. Burst Read / Async. Write
0
1
0
1
1
0
1/4 Drive
1
0
Sync. Burst Read / Sync. Burst Write
WAIT# Polarity
WP
RFU
RFU
Latency Count
Burst Type
BT
Burst Length
A7 A6 A5 BL
A13
A12
0
A11 A10 A9 Latency A8
Must
(default)
0
1
Low Enable (default)
High Enable
0
0
0
0
0
0
1
1
0
1
0
1
3
4
0
1
Linear (default)
Interleave
0
0
1
1
1
1
0
1
0
1
0
1
4 word
8 word
1
—
5
16 word
(default)
(default)
6
Full (256 word)
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Partial Array Refresh
PAR
PAR Array
PAR Size
PARS
A4
1
A3
0
A2
0
PARA
Bottom Array (default)
Top Array
A1
0
A0
0
PAR Enable
Full Array (default)
3/4 Array
1
1
PAR Disable (default)
1
0
1
1
0
1/2 Array
1
1
1/4 Array
Note: The address bits other than those listed in the table above are reserved. For example, Burst Length address
bits(A7:A6:A5) have 4 sets of reserved bits like 0:0:0, 0:0:1, 1:0:1 and 1:1:0. If the reserved address bits are input, then
the mode will be set to the default mode. Each field has its own default mode as indicated. A12 is a reserved bit for future
use. A12 must be set as 0. Not all the mode settings are tested. Per the mode settings to be tested, please contact Spansion.
The 256 word Full page burst mode needs to meet t (Burst Cycle time) parameter as max. 2500 ns.
BC
The last data written in the previous Asynchronous write mode is not valid. To make the lastly written data valid, implement
at least one dummy write cycle before change mode into synchronous burst read and synchronous burst write mode.
The data written in Synchronous burst write operation can be corrupted by the next Asynchronous write operation. So the
transition from Synchronous burst write operation to Asynchronous write operation is prohibited.
22.2 Mode Register Setting Timing
In this device, the MRS# pin is used for two purposes. One is to get into the mode register setting
and the other one is to execute Partial Array Refresh mode. To get into the Mode Register Setting,
the system must drive MRS# pin to VIL and immediately (within 0.5µs) issue a write command
(drive CS#, ADV#, UB#, LB# and WE# to VIL and drive OE# to VIH during valid address). If the
subsequent write command (WE# signal input) is not issued within 0.5µs, then the device might
get into the PAR mode. This device supports software access control type mode register setting
timing. This timing consists of 5 cycles of Read operation. Each cycle of Read Operation is normal
asynchronous read operation. Clock and ADV# are don’t care and WAIT# signal is High-Z. CS#
should be toggling between cycles. The address for 1st, 2nd and 3rd cycle should be 3FFFFF(h)
and the address for 4th cycle should be 3FFEFF. The address for 5th cycle should be MRS code
(Register setting values).
ADV#
tWC
Address
tCW
CS#
tAW
tBW
UB#, LB#
tWP
WE#
tAS
Register Write Complete
Register Update Complete
Register Write Start
tWU
tMW
MRS#
Figure 22.1 Pin MRS Timing Waveform (OE# = V
)
IH
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Address
3FFFFF
3FFEFF
MRS CODE
3FFFFF
tRCM
3FFFFF
tCLM
CS#
OE#
tCHM
WE#
Notes:
1. MRS#= VIH, CLK = ADV# = UB# = LB# = Don’t care, WAIT# = High-Z.
2. Do not allow this timing to occur during normal operation.
Figure 22.2 Software MRS Timing Waveform
Table 22.3 MRS AC Characteristics
Speed
Parameter List
MRS# Enable to Register Write Start
End of Write to MRS# Disable
Symbol
tMW
Min
Max
500
—
Units
ns
0
tWU
0
ns
MRS Read Cycle time
tRCM
tCHM
tCLM
70
10
60
—
ns
CS# High pulse width
CS# Low pulse width
—
ns
—
ns
Note:
V
=1.7~2.0V, T =-40 to 85°C, Maximum Main Clock Frequency=66MHz.
CC
A
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23 Asynchronous Operation
23.1 Asynchronous 4 Page Read Operation
Asynchronous normal read operation starts when CS#, OE# and UB# or LB# are driven to VIL
under the valid address without toggling page addresses (A0, A1). If the page addresses (A0, A1)
are toggled under the other valid address, the first data will be out with the normal read cycle
time (tRC) and the second, the third and the fourth data will be out with the page cycle time (tPC).
(MRS# and WE# should be driven to VIH during the asynchronous (page) read operation) Clock,
ADV#, WAIT# signals are ignored during the asynchronous (page) read operation.
23.2 Asynchronous Write Operation
Asynchronous write operation starts when CS#, WE# and UB# or LB# are driven to VIL under the
valid address. MRS# and OE# should be driven to VIH during the asynchronous write operation.
Clock, ADV#, WAIT# signals are ignored during the asynchronous (page) read operation.
23.3 Asynchronous Write Operation in Synchronous Mode
A write operation starts when CS#, WE# and UB# or LB# are driven to VIL under the valid ad-
dress. Clock input does not have any affect to the write operation (MRS# and OE# should be
driven to VIH during write operation. ADV# can be either toggling for address latch or held in VIL).
Clock, ADV#, and WAIT# signals are ignored during the asynchronous (page) read operation.
A22~A2
A1~A0
CS#
UB#, LB#
OE#
Data Out
Figure 23.1 Asynchronous 4-Page Read
Address
CS#
UB#, LB#
WE#
High-Z
Data in
High-Z
High-Z
Data out
Figure 23.2 Asynchronous Write
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24 Synchronous Burst Operation
Burst mode operations enable the system to get high performance read and write operation. The
address to be accessed is latched on the rising edge of clock or ADV# (whichever occurs first).
CS# should be setup before the address latch. During this first clock rising edge, WE# indicates
whether the operation is going to be a Read (WE# High) or a Write (WE# Low).
For the optimized Burst Mode of each system, the system should determine how many clock cy-
cles are required for the first data of each burst access (Latency Count), how many words the
device outputs during an access (Burst Length) and which type of burst operation (Burst Type:
Linear or Interleave) is needed. The Wait Polarity should also be determined (See Table 22.2).
24.1 Synchronous Burst Read Operation
The Synchronous Burst Read command is implemented when the clock rising is detected during
the ADV# low pulse. ADV# and CS# should be set up before the clock rising. During the Read
command, WE# should be held in VIH. The multiple clock risings (during the low ADV# period)
are allowed, but the burst operation starts from the first clock rising. The first data will be out
with Latency count and tCD
.
24.2 Synchronous Burst Write Operation
The Synchronous Burst Write command is implemented when the clock rising is detected during
the ADV# and WE# low pulse. ADV#, WE# and CS# should be set up before the clock rising. The
multiple clock risings (during the low ADV# period) are allowed but, the burst operation starts
from the first clock rising. The first data will be written in the Latency clock with tDS
.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
CLK
ADV#
Addr.
CS#
UB#, LB#
OE#
Data Out
WAIT#
Note: Latency 5, BL 4, WP: Low Enable
Figure 24.1 Synchronous Burst Read
0
1
2
3
4
5
6
7
8
9
10 11 12 13
CLK
ADV#
Addr.
CS#
UB#, LB#
WE#
Data in
WAIT#
Note: Latency 5, BL 4, WP: Low Enable
Figure 24.2 Synchronous Burst Write
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25 Synchronous Burst Operation Terminology
25.1 Clock (CLK)
The clock input is used as the reference for synchronous burst read and write operation of the
pSRAM Type 4. The synchronous burst read and write operations are synchronized to the rising
edge of the clock. The clock transitions must swing between VIL and VIH.
25.2 Latency Count
The Latency Count configuration tells the device how many clocks must elapse from the burst
command before the first data should be available on its data pins. This value depends on the
input clock frequency. Table 25.1 shows the supported Latency Count.
Table 25.1 Latency Count Support
Clock Frequency
Latency Count
Up to 66 MHz
Up to 54 MHz
Up to 40 MHz
5
4
3
Table 25.2 Number of CLocks for 1st Data
Set Latency
Latency 3
Latency 4
Latency 5
# of Clocks for 1st data (Read)
# of Clocks for 1st data (Write)
4
2
5
3
6
4
T
Clock
ADV#
Address
Latency 3
DQ1
DQ2
DQ3
DQ2
DQ1
DQ4
DQ3
DQ2
DQ1
DQ5
DQ4
DQ3
DQ2
DQ6
DQ5
DQ4
DQ3
DQ7
DQ6
DQ5
DQ4
DQ8
DQ7
DQ6
DQ5
DQ9
DQ8
DQ7
DQ6
Data out
Data out
Data out
Data out
Latency 4
Latency 5
Latency 6
DQ1
Note: The first data will always keep the Latency. From the second data on, some period of wait time may be caused by
WAIT# pin.
Figure 25.1 Latency Configuration (Read)
25.3 Burst Length
Burst Length identifies how many data the device outputs during an access. The device supports
4 word, 8 word, 16 word and 256 word burst read or write. 256 word Full page burst mode needs
to meet tBC (Burst Cycle time) parameter as 2500 ns max.
The first data will be output with the set Latency + tCD. From the second data on, the data will be
output with tCD from each clock.
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25.4 Burst Stop
Burst stop is used when the system wants to stop burst operation on purpose. If driving CS# to
VIH during the burst read operation, then the burst operation is stopped. During the burst read
operation, the new burst operation cannot be issued. The new burst operation can be issued only
after the previous burst operation is finished.
The burst stop feature is very useful because it enables the user to utilize the unsupported burst
length such as 1 burst or 2 burst, used mostly in the mobile handset application environment.
25.5 Wait Control (WAIT#)
The WAIT# signal indicates to the host system when it’s data-out or data-in is valid.
To be compatible with the Flash interfaces of various microprocessor types, the WAIT# polarity
(WP) can be configured. The polarity can be programmed to be either low enable or high enable.
For the timing of the WAIT# signal, it should be set active one clock prior to the data regardless
of Read or Write cycle.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
CLK
ADV#
CS#
Latency 5
Read
Data out
DQ0 DQ1
DQ2
DQ3
High-Z
High-Z
WAIT#
Latency 5
Write
Data in
D0
D1
D2
D3
WAIT#
Note: LATENCY: 5, Burst Length: 4, WP: Low Enable
Figure 25.2 WAIT# and Read/Write Latency Control
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25.6 Burst Type
The device supports Linear type burst sequence and Interleave type burst sequence. Linear type
burst sequentially increments the burst address from the starting address. The detailed Linear
and Interleave type burst address sequence is shown in Table 25.3.
Table 25.3 Burst Sequence
Burst Address Sequence (Decimal)
Wrap (Note 1)
16 word Burst
Interleave
Start
Address
4 word Burst
8 word Burst
Linear Interleave
Full Page(256 word)
Linear
Linear Interleave
Linear
0
1
0-1-2-3 0-1-2-3 0-1-...-5-6-7 0-1-2-...-6-7 0-1-2-...-14-15 0-1-2-3-4...14-15
0-1-2-...-254-255
1-2-3-...-255-0
2-3-4-...-255-0-1
3-4-5-...-255-0-1-2
1-2-3-0 1-0-3-2 1-2-...-6-7-0 1-0-3-...-7-6
2-3-0-1 2-3-0-1 2-3-...-7-0-1 2-3-0-...-4-5
3-0-1-2 3-2-1-0 3-4-...-0-1-2 3-2-1-...-5-4
4-5-...-1-2-3 4-5-6-...-2-3
1-2-3-...-15-0
2-3-4-...-0-1
3-4-5-...-1-2
4-5-6-...-2-3
5-6-7-...-3-4
6-7-8-...-4-5
7-8-9-...-5-6
~
1-0-3-2-5...15-14
2-3-0-1-6...12-13
3-2-1-0-7...13-12
2
3
4
4-5-6-7-0...10-11 4-5-6-...-255-0-1-2-3
5
5-6-...-2-3-4 5-4-7-...-3-2
5-4-7-6-1...11-10
6-7-4-5-2...8-9
7-6-5-4-3...9-8
~
5-6-7-...-255-...-3-4
6-7-8-...-255-...-4-5
7-8-9-...-255-...-5-6
~
6
6-7-...-3-4-5 6-7-4-...-0-1
7
7-0-...-4-5-6 7-6-5-...-1-0
~
14
15
~
14-15-0-...-12-13 14-15-12-...-0-1 14-15-...-255-...-12-13
15-0-1-...-13-14 15-14-13-...-1-0 15-16-...-255-...-13-14
~
255
255-0-1-...-253-254
Notes:
1. Wrap: Burst Address wraps within word boundary and ends after fulfilled the burst length.
2. 256 word Full page burst mode needs to meet t (Burst Cycle time) parameter as max. 2500 ns.
BC
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26 Low Power Features
26.7 Partial Array Refresh (PAR) mode
The PAR mode enables the user to specify the active memory array size. This device consists of
4 blocks and the user can select 1 block, 2 blocks, 3 blocks or all blocks as active memory arrays
through the Mode Register Setting. The active memory array is periodically refreshed whereas
the disabled array is not refreshed, so the previously stored data is lost. Even though PAR mode
is enabled through the Mode Register Setting, PAR mode execution by the MRS# pin is still
needed.
The normal operation can be executed even in refresh-disabled array as long as the MRS# pin is
not driven to the Low condition for over 0.5 µs. Driving the MRS# pin to the High condition puts
the device back to the normal operation mode from the PAR executed mode. Refer to Figure 26.1
and Table 26.1 for PAR operation and PAR address mapping.
0.5 µs
MRS#
Normal
Operation
Normal
Operation
Suspend
PAR mode
MODE
CS#
Figure 26.1 PAR Mode Execution and Exit
Table 26.1 PAR Mode Characteristics
Address
(Bottom Array)
(Note 2)
Address
(Top Array)
(Note 2)
Memory Cell
Data
Standby Current Wait Time
Power Mode
(µA, Max)
(µs)
Standby (Full Array)
Partial Refresh(3/4 Block)
Partial Refresh(1/2 Block)
Partial Refresh(1/4 Block)
000000h ~ 3FFFFFh
000000h ~ 2FFFFFh
000000h ~ 1FFFFFh
000000h ~ 0FFFFFh
000000h ~ 3FFFFFh
100000h ~ 3FFFFFh
200000h ~ 3FFFFFh
300000h ~ 3FFFFFh
TBD
TBD
TBD
TBD
Valid (Note 1)
0
Notes:
1. Only the data in the refreshed block are valid.
2. The PAR Array can be selected through Mode Register Set (see Mode Register Setting Operation).
26.8 Driver Strength Optimization
The optimization of output driver strength is possible through the mode register setting to adjust
for the different data loadings. Through this driver strength optimization, the device can minimize
the noise generated on the data bus during read operation. The device supports full drive, 1/2
drive and 1/4 drive.
26.1 Internal TCSR
The internal Temperature Compensated Self Refresh (TCSR) feature is a very useful tool for re-
ducing standby current at room temperature (below 40°C). DRAM cells have weak refresh
characteristics in higher temperatures. High temperatures require more refresh cycles, which can
lead to standby current increase.
Without the internal TCSR, the refresh cycle should be set at worst condition so as to cover the
high temperature (85°C) refresh characteristics. But with internal TCSR, a refresh cycle below
40°C can be optimized, so the standby current at room temperature can be greatly reduced. This
feature is beneficial since most mobile phones are used at or below 40°C in the phone standby
mode.
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27 Absolute Maximum Ratings
Item
Voltage on any pin relative to VSS
Power supply voltage relative to VSS
Power Dissipation
Symbol
VIN , VOUT
VCC
Ratings
-0.2 V to VCC+0.3 V
-0.2 V to 2.5V
1.0
Unit
V
V
PD
W
Storage temperature
TSTG
-65 to 150
°C
°C
Operating Temperature
TA
-40 to 85
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Functional operation should be restricted to use under recommended operating conditions only. Exposure to absolute maxi-
mum rating conditions longer than one second may affect reliability.
28 DC Recommended Operating Conditions
Symbol
VCC
Parameter
Power Supply Voltage
Ground
Min
1.7
Typ
1.85
0
Max
Unit
2.0
VSS
0
0
V
VIH
Input High Voltage
0.8 x VCC
—
VCC + 0.2 (note 2)
-0.2 (note
3)
VIL
Input Low Voltage
—
0.4
Notes:
1. TA=-40 to 85°C, unless otherwise specified.
2. Overshoot: V +1.0V in case of pulse width ≤ 20ns.
CC
3. Undershoot: -1.0V in case of pulse width ≤ 20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
29 Capacitance (Ta = 25°C, f = 1 MHz)
Symbol
CIN
Parameter
Test Condition
VIN = 0V
VOUT = 0V
Min
—
Max
8
Unit
Input Capacitance
pF
pF
CIO
Input/Output Capacitance
—
10
Note: Capacitance is sampled, not 100% tested.
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30 DC and Operating Characteristics
30.1 Common
Item
Symbol
Test Conditions
Min Typ Max Unit
Input Leakage Current
I
V
=V to V
CC
-1
—
1
µA
LI
IN
SS
CS#=V , MRS#=V , OE#=V or
IH
IH
IH
Output Leakage Current
I
LO
-1
—
1
µA
WE#=V , V =V to V
IL
IO
SS
CC
Average Operating
Current
Cycle time=t +3t , I =0mA, 100% duty,
RC
PC IO
I
I
—
—
40
40
mA
mA
CC2
CC3
CS#=V , MRS#=V , V =V or V
IL
IH
IN
IL
IH
Average Operating
Current (Sync)
Burst Length 4, Latency 5, 66MHz, IIO=0mA, Address
transition 1 time, CS#=V , MRS#=V , V =V or V
IH
IL
IH
IN
IL
Output Low Voltage
Output High Voltage
V
I
I
=0.1mA
—
1.4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.2
—
V
V
OL
OL
V
=-0.1mA
OH
OH
< 40°C
< 85°C
120 µA
180 µA
120
I
CS# ≥ V -0.2V, MRS# ≥ V -0.2V,
Other inputs = V to V
SB1
CC
CC
Standby Current (CMOS)
(Note 2)
SS
CC
3/4 Block
< 40°C 1/2 Block
1/4 Block
115 µA
115
MRS# ≤ 0.2V, CS# ≥ V -0.2V
Other inputs = V to V
CC
CC
Partial Refresh Current
I
(Note 1)
SBP
SS
3/4 Block
180
< 85°C 1/2 Block
1/4 Block
165 µA
165
Notes:
1. Full Array Partial Refresh Current (I
) is the same as Standby Current (I
).
SBP
SB1
2. Standby mode is supposed to be set up after at least one active operation after
power up. ISB1 is measured 60 ms from the time when standby mode is set up.
31 AC Operating Conditions
31.1 Test Conditions (Test Load and Test Input/Output Reference)
Input pulse level: 0.2 to VCC -0.2V
Input rising and falling time: 3ns
Input and output reference voltage: 0.5 x VCC
Output load (See Figure 31.1): CL=30pF
Vtt = 0.5 x V
DDQ
50
Dout
Z0=50
30pF
Figure 31.1 PAR Mode Execution and Exit
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31.2 Asynchronous AC Characteristics
(VCC=1.7~2.0V, TA=–40 to 85 °C)
Speed
Symbol
Parameter
Unit
Min
Max
—
t
Read Cycle Time
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
RC
t
Page Read Cycle Time
25
—
PC
t
Address Access Time
—
70
20
70
35
35
—
AA
t
Page Access Time
—
PA
t
Chip Select to Output
—
CO
t
t
Output Enable to Valid Output
UB#, LB# Access Time
—
OE
BA
—
t
Chip Select to Low-Z Output
UB#, LB# Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
UB#, LB# Disable to High-Z Output
Output Disable to High-Z Output
Output Hold
10
LZ
t
5
—
BLZ
OLZ
CHZ
BHZ
OHZ
t
5
—
t
t
0
12
12
12
—
0
t
0
t
3
OH
WC
CW
t
Write Cycle Time
70
—
t
Chip Select to End of Write
ADV# Minimum Low Pulse Width
Address Set-up Time to Beginning of Write
Address Set-up Time to ADV# Falling
Address Hold Time from ADV# Rising
CS# Setup Time to ADV# Rising
Address Valid to End of Write
UB#, LB# Valid to End of Write
Write Pulse Width
60
—
t
7
—
ADV
t
0
—
AS
t
0
—
AS(A)
AH(A)
t
7
—
t
10
—
CSS(A)
t
t
60
—
AW
BW
60
—
t
55 (Note 1)
—
WP
t
WE# High Pulse Width
5 ns
0
Latency-1 clock
WHP
t
Write Recovery Time
—
—
—
—
ns
clock
ns
ns
WR
t
WE# Low to Read Latency
Data to Write Time Overlap
Data Hold from Write Time
1
WLRL
t
30
0
DW
t
DH
Note:
t
(min)=70ns for continuous write operation over 50 times.
WP
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31.3 Timing Diagrams
31.3.1 Asynchronous Read Timing Waveform
MRS# = VIH, WE# = VIH, WAIT# = High-Z
tRC
Address
tAA
tOH
tCO
CS#
tCHZ
tBHZ
tBA
UB#, LB#
tOE
OE#
tOLZ
tBLZ
tLZ
tOHZ
Data out
High-Z
Data Valid
Notes:
1.
t
and t
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
OHZ
CHZ
to output voltage levels.
2. At any given temperature and voltage condition, t
to device interconnection.
is less than t
both for a given device and from device
LZ(Min.)
CHZ(Max.)
3. In asynchronous read cycle, Clock, ADV# and WAIT# signals are ignored.
Figure 31.2 Timing Waveform Of Asynchronous Read Cycle
Table 31.1 Asynchronous Read AC Characteristics
Speed
Speed
Symbol
tRC
Min
70
—
—
—
—
3
Max
—
Units
Symbol
tOLZ
tBLZ
Min
5
Max
—
—
—
7
Units
tAA
70
70
35
35
—
5
tCO
tLZ
10
0
ns
ns
tBA
tCHZ
tBHZ
tOHZ
tOE
0
7
tOH
0
7
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A d v a n c e I n f o r m a t i o n
31.3.1.1 Page Read
MRS# = VIH, WE# = VIH, WAIT# = High-Z
t
RC
Valid
Address
A22~A2
tOH
tAA
Valid
Valid
Valid
Valid
A1~A0
CS#
Address
Address Address Address
tPC
tCO
tBA
UB#, LB#
OE#
t
BHZ
t
OE
tCHZ
tBOLZLZ
t
OHZ
t
t
PA
t
LZ
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data out
High Z
Notes:
1.
t
and t
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
OHZ
CHZ
to output voltage levels.
2. At any given temperature and voltage condition, t
to device interconnection.
is less than t
both for a given device and from device
LZ(Min.)
CHZ(Max.)
3. In asynchronous 4 page read cycle, Clock, ADV# and WAIT# signals are ignored.
Figure 31.3 Timing Waveform Of Page Read Cycle
Table 31.2 Asynchronous Page Read AC Characteristics
Speed
Speed
Symbol
tRC
Min
70
—
Max
—
Units
Symbol
tOH
Min
3
Max
—
—
—
—
7
Units
tAA
70
—
tOLZ
tBLZ
tLZ
5
tPC
25
—
5
tPA
20
70
35
35
ns
10
0
ns
tCO
tBA
—
tCHZ
tBHZ
tOHZ
—
0
7
tOE
—
0
7
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31.3.2 Asynchronous Write Timing Waveform
Asynchronous Write Cycle - WE# Controlled
tWC
tWC
Address
tCSHP
tWR
tAW
tAW
tCW
tWR
tCW
CS#
tBW
tBW
UB#, LB#
tWHP
tAS
tWP
tWP
WE#
tAS
tDH
tDH
tDW
tDW
Data in
Data Valid
Data Valid
Data out
High-Z
High-Z
Notes:
1. A write occurs during the overlap (t ) of low CS# and low WE#. A write begins when CS# goes low and WE# goes
WP
low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte
operation. A write ends at the earliest transition when CS# goes high or WE# goes high. The t
beginning of write to the end of write.
is measured from the
WP
2.
3.
4.
t
t
t
is measured from the CS# going low to the end of write.
is measured from the address valid to the beginning of write.
CW
AS
is measured from the end of write to the address change. t
is applied in case a write ends with CS# or WE#
WR
WR
going high.
5. In asynchronous write cycle, Clock, ADV# and WAIT# signals are ignored.
6. Condition for continuous write operation over 50 times: t =70ns.
WP(min)
Figure 31.4 Timing Waveform Of Write Cycle
Table 31.3 Asynchronous Write AC Characteristics
Speed
Speed
Symbol
tWC
Min
70
60
60
60
Max
—
Units
Symbol
tAS
Min
0
Max
—
Units
tCW
—
tWR
0
—
tAW
—
ns
tDW
30
0
—
ns
tBW
—
tDH
—
tWP
55 (note 1)
—
tCHSP
10
Note:
t
= 70ns for continuous write operation over 50 times.
WP(min)
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A d v a n c e I n f o r m a t i o n
31.3.2.1 Write Cycle 2
MRS# = VIH, OE# = VIH, WAIT# = High-Z, UB# & LB# Controlled
tWC
Address
tWR
tCW
CS#
tAW
tBW
UB#, LB#
tAS
tWP
WE#
tDH
tDW
Data Valid
Data in
High-Z
Data out
High-Z
Notes:
1. A write occurs during the overlap (t ) of low CS# and low WE#. A write begins when CS# goes low and WE# goes
WP
low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte
operation. A write ends at the earliest transition when CS# goes high or WE# goes high. The t
beginning of write to the end of write.
is measured from the
WP
2.
3.
4.
t
t
t
is measured from the CS# going low to the end of write.
is measured from the address valid to the beginning of write.
CW
AS
is measured from the end of write to the address change. t
is applied in case a write ends with CS# or WE#
WR
WR
going high.
5. In asynchronous write cycle, Clock, ADV# and WAIT# signals are ignored.
Figure 31.5 Timing Waveform of Write Cycle(2)
Table 31.4 Asynchronous Write AC Characteristics (UB# & LB# Controlled)
Speed
Speed
Max
Symbol
tWC
Min
70
60
60
60
Max
—
Units
Symbol
tAS
Min
0
Units
—
—
—
—
tCW
—
tWR
0
ns
tAW
—
ns
tDW
30
0
tBW
—
tDH
tWP
55 (note 1)
—
Note:
t
= 70ns for continuous write operation over 50 times.
WP(min)
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A d v a n c e I n f o r m a t i o n
31.3.2.1 Write Cycle (Address Latch Type)
MRS# = VIH, OE# = VIH, WAIT# = High-Z, WE# Controlled
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK
tADV
ADV#
tAS(A)
tAH(A)
Address
Valid
tCSS(A)
tCW
CS#
tAW
tBW
UB#, LB#
tWLRL
tWP
WE#
tAS
tDW
tDH
Data in
Data Valid
Read Latency5
High-Z
High-Z
Data out
Notes:
1. A write occurs during the overlap (t ) of low CS# and low WE#. A write begins when CS# goes low and WE# goes
WP
low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for word operation.
A write ends at the earliest transition when CS# goes high or WE# goes high. The t
of write to the end of write.
is measured from the beginning
WP
2.
3.
4.
t
t
t
is measured from the address valid to the end of write. In this address latch type write timing, t
is measured from the CS# going low to the end of write.
is measured from the UB# and LB# going low to the end of write.
is same as t
.
AW
AW
CW
BW
WC
5. Clock input does not have any affect to the write operation if the parameter t
is met.
WLRL
Figure 31.6 Timing Waveform Of Write Cycle (Address Latch Type)
Table 31.5 Asynchronous Write in Synchronous Mode AC Characteristics
Speed
Max
Speed
Symbol
tADV
Min
7
Units
Symbol
tBW
Min
Max
—
Units
ns
—
—
—
—
—
—
60
tAS(A)
tAH(A)
tCSS(A)
tCW
0
tWP
55 (note 2)
—
7
tWLRL
tAS
1
0
—
clock
ns
10
60
60
—
tDW
30
0
—
ns
tAW
tDH
—
Notes:
1. Address Latch Type, WE# Controlled.
2.
t
= 70ns for continuous write operation over 50 times.
WP(min)
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A d v a n c e I n f o r m a t i o n
31.3.3 Asynchronous Write Timing Waveform in Synchronous Mode
31.3.3.1 Write Cycle (Address Latch Type)
MRS# = VIH, OE# = VIH, WAIT# = High-Z, UB# and LB# Controlled
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK
tADV
ADV#
tAS(A)
tAH(A)
Address
Valid
tAS
tCSS(A)
tCW
CS#
tAW
tBW
UB#, LB#
WE#
tWLRL
tWP
tDW
tDH
Data in
Data Valid
Read Latency 5
High-Z
High-Z
Data out
Notes:
1. A write occurs during the overlap (t ) of low CS# and low WE#. A write begins when CS# goes low and WE# goes
WP
low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for word operation.
A write ends at the earliest transition when CS# goes or and WE# goes high. The t
of write to the end of write.
is measured from the beginning
WP
2.
3.
4.
t
t
t
is measured from the address valid to the end of write. In this address latch type write timing, t
is measured from the CS# going low to the end of write.
is measured from the UB# and LB# going low to the end of write.
is same as t
.
AW
AW
CW
BW
WC
5. Clock input does not have any affect to the write operation if the parameter t
is met.
WLRL
Figure 31.7 Timing Waveform Of Write Cycle (Low ADV# Type)
Table 31.6 Asynchronous Write in Synchronous Mode AC Characteristics
Speed
Speed
Symbol
tADV
Min
7
Max
—
Units
Symbol
tBW
Min
Max
—
Units
ns
60
tAS(A)
tAH(A)
tCSS(A)
tCW
0
—
tWP
55 (Note 2)
—
ns
7
—
tWLRL
tAS
1
0
—
clock
ns
10
60
60
—
—
—
tDW
30
0
—
ns
tAW
—
tDH
—
Notes:
1. Address Latch Type, UB#, LB# Controlled.
2.
t
= 70ns for continuous write operation over 50 times.
WP(min)
124
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A d v a n c e I n f o r m a t i o n
31.3.4 Asynchronous Write Timing Waveform in Synchronous Mode
31.3.4.1 Write Cycle (Low ADV# Type)
MRS# = VIH, OE# = VIH, WAIT# = High-Z, WE# Controlled
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK
ADV#
tWC
Address
tWR
tCW
tAW
CS#
tBW
UB#, LB#
tWLRL
tWP
WE#
tAS
tDH
tDW
Data in
Data Valid
Read Latency 5
High-Z
Data out
High-Z
Notes:
1. A write occurs during the overlap (t ) of low CS# and low WE#. A write begins when CS# goes low and WE# goes low
WP
with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation.
A write ends at the earliest transition when CS# goes high or WE# goes high. The t
of write to the end of write.
is measured from the beginning
WP
2.
3.
4.
t
t
t
is measured from the CS# going low to the end of write.
is measured from the address valid to the beginning of write.
CW
AS
is measured from the end of write to the address change. t
is applied in case a write ends with CS# or WE#
WR
WR
going high.
5. Clock input does not have any affect to the write operation if the parameter t
is met.
WLRL
Figure 31.8 Timing Waveform Of Write Cycle (Low ADV# Type)
Table 31.7 Asynchronous Write in Synchronous Mode AC Characteristics
Speed
Speed
Max
Symbol
tWC
Min
70
60
60
60
Max
—
Units
Symbol
tWLRL
tAS
Min
1
Units
—
—
—
—
—
clock
tCW
—
0
tAW
—
ns
tWR
0
ns
tBW
—
tDW
30
0
tWP
55 (note 2)
—
tDH
Notes:
1. Low ADV# Type, WE# Controlled.
2. tWP(min) = 70ns for continuous write operation over 50 times.
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A d v a n c e I n f o r m a t i o n
31.3.4.2 Write Cycle (Low ADV# Type)
MRS# = VIH, OE# = VIH, WAIT# = High-Z, UB# & LB# Controlled
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK
ADV#
tWC
Address
CS#
tWR
tCW
tAW
tBW
UB#, LB#
WE#
tAS
tWLRL
tWP
tDH
tDW
Data Valid
Data in
Read Latency 5
High-Z
Data out
High-Z
Notes:
1. A write occurs during the overlap (t ) of low CS# and low WE#. A write begins when CS# goes low and WE# goes low
WP
with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation.
A write ends at the earliest transition when CS# goes high or WE# goes high. The t
of write to the end of write.
is measured from the beginning
WP
2.
3.
4.
t
t
t
is measured from the CS# going low to the end of write.
is measured from the address valid to the beginning of write.
CW
AS
is measured from the end of write to the address change. t
is applied in case a write ends with CS# or WE#
WR
WR
going high.
5. Clock input does not have any affect to the write operation if the parameter t
is met.
WLRL
Figure 31.9 Timing Waveform Of Write Cycle (Low ADV# Type)
Table 31.8 Asynchronous Write in Synchronous Mode AC Characteristics
Speed
Speed
Max
Symbol
tWC
Min
70
60
60
60
Max
—
Units
Symbol
tWLRL
tAS
Min
1
Units
—
—
—
—
—
clock
tCW
—
0
tAW
—
ns
tWR
0
ns
tBW
—
tDW
30
0
tWP
55 (note 2)
—
tDH
Notes:
1. Low ADV# type multiple write, UB#, LB# controlled.
2.
t
= 70ns for continuous write operation over 50 times.
WP(min)
126
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31.3.4.3 Multiple Write Cycle (Low ADV# Type)
MRS# = VIH, OE# = VIH, WAIT# = High-Z, WE# Controlled
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK
ADV#
Address
tWC
tWC
tWR
tWR
t
AW
tCW
t
AW
tCW
CS#
tBW
tBW
UB#, LB#
tWHP
tWP
tWP
WE#
tAS
tAS
tDH
tDH
tDW
tDW
Data in
Data Valid
DataValid
Data out
High-Z
High-Z
Notes:
1. A write occurs during the overlap (t ) of low CS# and low WE#. A write begins when CS# goes low and WE# goes low
WP
with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation.
A write ends at the earliest transition when CS# goes high or WE# goes high. The t
of write to the end of write.
is measured from the beginning
WP
2.
3.
4.
t
t
t
is measured from the CS# going low to the end of write.
is measured from the address valid to the beginning of write.
CW
AS
is measured from the end of write to the address change. t
is applied in case a write ends with CS# or WE#
WR
WR
going high.
5. Clock input does not have any affect on the asynchronous multiple write operation if t
Latency - 1) clock duration.
is shorter than the (Read
WHP
6.
t
= 70ns for continuous write operation over 50 times.
WP(min)
Figure 31.10 Timing Waveform Of Multiple Write Cycle (Low ADV# Type)
Table 31.9 Asynchronous Write in Synchronous Mode AC Characteristics
Speed
Speed
Max
Symbol
Units
Symbol
Units
Min
70
60
60
60
Max
—
Min
5ns
0
t
t
t
t
t
Latency-1 clock
—
WC
CW
AW
BW
WHP
—
t
—
—
—
—
AS
—
ns
t
0
WR
DW
ns
—
t
30
0
t
55 (note 2)
—
t
DH
WP
Notes:
1. Low ADV# type multiple write, WE# Controlled.
2.
t
= 70ns for continuous write operation over 50 times.
WP(min)
September 15, 2005 S71WS-N_01_A4
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A d v a n c e I n f o r m a t i o n
32 AC Operating Conditions
32.1 Test Conditions (Test Load and Test Input/Output Reference)
Input pulse level: 0.2 to VCC-0.2V
Input rising and falling time: 3ns
Input and output reference voltage: 0.5 x VCC
Output load (See Figure 32.1): CL = 30pF
Vtt = 0.5 x V
DDQ
50
Ω
Dout
Z0=50
Ω
30pF
Figure 32.1 AC Output Load Circuit
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32.2 Synchronous AC Characteristics
Speed
Max
Parameter List
Symbol
Units
Min
15
—
0
Clock Cycle Time
T
200
2500
—
—
—
—
—
—
—
—
—
—
10
10
12
7
Burst Cycle Time
t
BC
Address Set-up Time to ADV# Falling (Burst)
Address Hold Time from ADV# Rising (Burst)
ADV# Setup Time
t
AS(B)
AH(B)
t
7
t
5
ADVS
ADV# Hold Time
t
7
ADVH
CS# Setup Time to Clock Rising (Burst)
Burst End to New ADV# Falling
Burst Stop to New ADV# Falling
CS# Low Hold Time from Clock
CS# High Pulse Width
t
5
CSS(B)
t
7
Burst Operation
(Common)
BEADV
ns
t
12
7
BSADV
t
t
CSLH
CSHP
ADHP
5
ADV# High Pulse Width
t
5
Chip Select to WAIT# Low
t
—
—
—
—
1
WL
ADV# Falling to WAIT# Low
Clock to WAIT# High
t
AWL
t
WH
Chip De-select to WAIT# High-Z
UB#, LB# Enable to End of Latency Clock
Output Enable to End of Latency Clock
UB#, LB# Valid to Low-Z Output
Output Enable to Low-Z Output
Latency Clock Rising Edge to Data Output
Output Hold
t
WZ
BEL
OEL
BLZ
OLZ
t
—
—
—
—
10
—
10
7
clock
clock
t
t
1
5
t
5
t
—
3
CD
Burst Read Operation
t
OH
ns
Burst End Clock to Output High-Z
Chip De-select to Output High-Z
Output Disable to Output High-Z
UB#, LB# Disable to Output High-Z
WE# Set-up Time to Command Clock
WE# Hold Time from Command Clock
WE# High Pulse Width
t
—
—
—
—
5
HZ
t
CHZ
OHZ
t
7
t
7
BHZ
WES
WEH
WHP
t
t
t
—
—
—
—
—
—
—
—
—
5
5
UB#, LB# Set-up Time to Clock
UB#, LB# Hold Time from Clock
Byte Masking Set-up Time to Clock
Byte Masking Hold Time from Clock
Data Set-up Time to Clock
t
5
BS
Burst Write Operation
t
5
ns
BH
t
7
BMS
BMH
t
7
t
5
DS
Data Hold Time from Clock
t
3
DHC
Note: (V = 1.7~2.0V, T =-40 to 85 °C, Maximum Main Clock Frequency = 66MHz.
CC
A
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A d v a n c e I n f o r m a t i o n
32.3 Timing Diagrams
32.3.1 Synchronous Burst Operation Timing Waveform
Latency = 5, Burst Length = 4 (MRS# = VIH)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
T
CLK
tADVH
tADVS
ADV#
tBEADV
tBEADV
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
Valid
tCSS(B)
tBC
Undefined
Data out
Data in
DQ0 DQ1 DQ2 DQ3
D0
D1
D2
D3
D0
Burst Command Clock
Burst Read End Clock
Burst Write End Clock
Figure 32.2 Timing Waveform Of Basic Burst Operation
Table 32.1 Burst Operation AC Characteristics
Speed
Speed
Symbol
Min
15
—
5
Max
Units
Symbol
tAS(B)
Min
0
Max
—
Units
T
200
tBC
2500
—
tAH(B)
7
—
ns
ns
tADVS
tADVH
tCSS(B)
tBEADV
5
—
7
—
7
—
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A d v a n c e I n f o r m a t i o n
32.3.2 Synchronous Burst Read Timing Waveforms
32.3.2.1 Read Timings
Latency = 5, Burst Length = 4, WP = Low enable (WE# = VIH, MRS# = VIH).
CS# Toggling Consecutive Burst Read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
T
CLK
t
ADVH
ADVS
t
ADV#
tBEADV
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
Valid
t
CSHP
tCSS(B)
tBC
tBHZ
tBEL
LB#, UB#
OE#
tBLZ
tOHZ
tOEL
t
t
CHZ
t
OLZ
Latency 5
tCD
tOH
HZ
Undefined
Data out
DQ0 DQ1 DQ2 DQ3
tWZ
tWL
tWH
tWH
tWL
WAIT#
High-Z
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
should be met.
BEADV
2. /WAIT Low (t
or t
WH
WZ
): Data not available (driven by CS# low going edge or ADV# low going edge)
AWL
WL
/WAIT High (t ): Data available (driven by Latency-1 clock)
/WAIT High-Z (t ): Data don’t care (driven by CS# high going edge).
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (t ) should not be over 2.5µs.
BC
Figure 32.3 Timing Waveform of Burst Read Cycle (1)
Table 32.2 Burst Read AC Characteristics
Speed
Speed
Symbol
tCSHP
tBEL
Min
5
Max
—
Units
Symbol
tOHZ
tBHZ
tCD
Min
—
—
—
3
Max
7
Units
ns
1
—
7
clock
ns
tOEL
1
—
10
—
10
12
7
tBLZ
5
—
tOH
ns
tOLZ
tHZ
5
—
tWL
—
—
—
—
—
10
7
tWH
tCHZ
tWZ
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A d v a n c e I n f o r m a t i o n
Latency = 5, Burst Length = 4, WP = Low enable (WE# = VIH, MRS# = VIH).
CS# Low Holding Consecutive Burst Read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
T
CLK
t
ADVH
ADVS
t
ADV#
tBEADV
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
Valid
tCSS(B)
tBC
tBEL
LB#, UB#
OE#
tBLZ
tOEL
t
OLZ
Latency 5
tCD
tOH
tHZ
Undefined
Data out
DQ0 DQ1 DQ2 DQ3
tAWL
tWH
tWL
tWH
WAIT#
High-Z
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
should be met.
BEADV
2. /WAIT Low (t
or t
WH
WZ
): Data not available (driven by CS# low going edge or ADV# low going edge)
AWL
WL
/WAIT High (t ): Data available (driven by Latency-1 clock)
/WAIT High-Z (t ): Data don’t care (driven by CS# high going edge).
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. The consecutive multiple burst read operation with holding CS# low is possible only through issuing a new ADV# and
address.
5. Burst Cycle Time (t ) should not be over 2.5µs.
BC
Figure 32.4 Timing Waveform of Burst Read Cycle (2)
Table 32.3 Burst Read AC Characteristics
Speed
Speed
Symbol
tBEL
Min
1
Max
—
Units
Symbol
tCD
Min
—
3
Max
10
—
Units
clock
tOEL
tBLZ
tOLZ
tHZ
1
—
tOH
5
—
tWL
—
—
—
10
10
12
ns
5
—
ns
tAWL
tWH
—
10
132
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Latency = 5, Burst Length = 4, WP = Low enable (WE# = VIH, MRS# = VIH).
Last data sustaining
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
T
CLK
tADVH
tADVS
ADV#
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
tCSS(B)
tBC
tBEL
tOEL
LB#, UB#
OE#
tBLZ
tOLZ
Latency 5
tOH
tCD
Undefined
Data out
DQ0 DQ1 DQ2 DQ3
tWL
tWH
High-Z
WAIT#
Notes:
1. /WAIT Low (t
or t
WH
WZ
): Data not available (driven by CS# low going edge or ADV# low going edge)
AWL
WL
/WAIT High (t ): Data available (driven by Latency-1 clock)
/WAIT High-Z (t ): Data don’t care (driven by CS# high going edge).
2. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
3. Burst Cycle Time (t ) should not be over 2.5µs.
BC
Figure 32.5 Timing Waveform of Burst Read Cycle (3)
Table 32.4 Burst Read AC Characteristics
Speed
Speed
Symbol
tBEL
Min
1
Max
—
Units
Symbol
tCD
Min
—
3
Max
10
—
Units
clock
tOEL
1
—
tOH
ns
tBLZ
5
—
tWL
—
—
10
12
ns
tOLZ
5
—
tWH
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A d v a n c e I n f o r m a t i o n
32.3.2.1 Write Timings
Latency = 5, Burst Length = 4, WP = Low enable (OE# = VIH, MRS# = VIH).
CS# Toggling Consecutive Burst Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
T
CLK
tADVH
tADVS
ADV#
tBEADV
tCSHP
tAH(B)
tAS(B)
Address
CS#
Valid
Valid
Don’t Care
tBC
tCSS(B)
tBS
tBMS
tBH
tBMH
LB#, UB#
WE#
tWEH
tWHP
tWES
tDS
tDHC
tDHC
Latency 5
tWH
Latency 5
tWH
Data in
D0
D1
D2
D3
D0
tWZ
tWL
tWL
High-Z
WAIT#
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
should be met.
BEADV
2. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
3. /WAIT Low (t or t ): Data not available (driven by CS# low going edge or ADV# low going edge)
WL
AWL
/WAIT High (t ): Data available (driven by Latency-1 clock)
WH
/WAIT High-Z (t ): Data don’t care (driven by CS# high going edge)
WZ
4. D2 is masked by UB# and LB#.
5. Burst Cycle Time (t ) should not be over 2.5µs.
BC
Figure 32.6 Timing Waveform of Burst Write Cycle (1)
Table 32.5 Burst Write AC Characteristics
Speed
Speed
Symbol
tCSHP
tBS
Min
5
Max
—
Units
Symbol
tWHP
tDS
Min
5
Max
—
Units
5
—
5
—
tBH
5
—
tDHC
tWL
3
—
ns
tBMS
tBMH
tWES
tWEH
7
—
ns
—
—
—
10
12
7
7
—
tWH
5
—
tWZ
5
—
134
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Latency = 5, Burst Length = 4, WP = Low enable (OE# = VIH, MRS# = VIH).
CS# Low Holding Consecutive Burst Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
T
CLK
ADV
tADVH
tADVS
tBEADV
tAH(B)
tAS(B)
Address
CS#
Valid
Valid
Don’t Care
tBC
tCSS(B)
tBS
tBMS
tBH
tBMH
LB#, UB#
WE#
tWEH
tWHP
tWES
tDS
tDHC
tDHC
Latency 5
tWH
Latency 5
tWH
Data in
D0
D1
D2
D3
D0
tWL
tAWL
High-Z
WAIT#
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
should be met.
BEADV
2. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
3. /WAIT Low (t or t ): Data not available (driven by CS# low going edge or ADV# low going edge)
WL
AWL
/WAIT High (t ): Data available (driven by Latency-1 clock)
WH
/WAIT High-Z (t ): Data don’t care (driven by CS# high going edge)
WZ
4. D2 is masked by UB# and LB#.
5. The consecutive multiple burst read operation with holding CS# low is possible only through issuing a new ADV# and
address.
6. Burst Cycle Time (t ) should not be over 2.5µs.
BC
Figure 32.7 Timing Waveform of Burst Write Cycle (2)
Table 32.6 Burst Write AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
5
Max
—
Min
5
Max
—
t
t
WHP
BS
t
5
—
t
5
—
BH
DS
t
7
—
t
3
—
BMS
BMH
WES
WEH
DHC
ns
ns
t
t
7
—
t
—
—
—
10
10
12
WL
5
—
t
AWL
t
5
—
t
WH
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A d v a n c e I n f o r m a t i o n
32.3.3 Synchronous Burst Read Stop Timing Waveform
Latency = 5, Burst Length = 4, WP = Low enable (WE#= VIH, MRS# = VIH).
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
T
CLK
tADVH
tADVS
ADV#
tBSADV
tCSHP
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
Valid
tCSS(B)
tCSLH
tBEL
tOEL
LB#, UB#
OE#
tBLZ
tOLZ
Latency 5
tOH
tCHZ
tCD
Undefined
Data
DQ0
DQ1
tWZ
tWL
tWL
tWH
High-Z
High-Z
WAIT#
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished.
2. /WAIT Low (t or t ): Data not available (driven by CS# low going edge or ADV# low going edge)
WL
AWL
/WAIT High (t ): Data available (driven by Latency-1 clock)
WH
/WAIT High-Z (t ): Data don’t care (driven by CS# high going edge)
WZ
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. The burst stop operation should not be repeated for over 2.5µs.
Figure 32.8 Timing Waveform of Burst Read Stop by CS#
Table 32.7 Burst Read Stop AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
12
7
Max
—
Min
—
3
Max
10
—
t
t
BSADV
CD
t
t
—
ns
t
CSLH
CSHP
OH
5
—
t
—
—
—
—
7
CHZ
ns
t
1
—
t
10
12
7
BEL
OEL
WL
clock
ns
t
1
—
t
WH
t
5
—
t
WZ
BLZ
OLZ
t
5
—
136
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32.3.4 Synchronous Burst Write Stop Timing Waveform
Latency = 5, Burst Length = 4, WP = Low enable (OE#= VIH, MRS# = VIH).
0
1
2
3
4
5
6
7
8
9
10
11
12
13
T
CLK
t
ADVH
ADVS
t
ADV#
tBSADV
tAH(B)
tAS(B)
Don’t Care
Address
CS#
Valid
Valid
tCSHP
t
CSS(B)
tCSLH
tBS
tBH
LB#, UB#
WE#
tWHP
t
WEH
t
WES
tDS
tDHC
Latency 5
Latency 5
Data in
D0
D1
D0
D1
D2
tWZ
t
WL
t
WL
tWH
tWH
High-Z
High-Z
WAIT#
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished.
2. /WAIT Low (t or t ): Data not available (driven by CS# low going edge or ADV# low going edge)
WL
AWL
/WAIT High (t ): Data available (driven by Latency-1 clock)
WH
/WAIT High-Z (t ): Data don’t care (driven by CS# high going edge)
WZ
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. The burst stop operation should not be repeated for over 2.5µs.
Figure 32.9 Timing Waveform of Burst Write Stop by CS#
Table 32.8 Burst Write Stop AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
12
7
Max
—
Min
5
Max
—
t
t
WHP
BSADV
t
t
—
t
5
—
CSLH
DS
5
—
t
3
—
CSHP
DHC
ns
t
5
—
t
—
—
—
10
12
7
ns
BS
WL
t
5
—
t
WH
BH
t
5
—
t
WZ
WES
WEH
t
5
—
September 15, 2005 S71WS-N_01_A4
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A d v a n c e I n f o r m a t i o n
32.3.5 Synchronous Burst Read Suspend Timing Waveform
Latency = 5, Burst Length = 4, WP = Low enable (WE#= VIH, MRS# = VIH).
0
1
2
3
4
5
6
7
8
9
10
11
T
CLK
tADVH
tADVS
ADV#
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
tCSS(B)
tBC
tBEL
tOEL
LB#, UB#
OE#
tBLZ
tOLZ
Latency 5
tOHZ
tOLZ
tOH
tCD
tHZ
High-Z
Undefined
Data out
DQ0 DQ1
DQ1 DQ2 DQ3
tWZ
tWL
tWH
WAIT#
High-Z
Notes:
1. If the clock input is halted during burst read operation, the data output is suspended. During the burst read suspend
period, OE# high drives data output to high-Z. If the clock input is resumed, the suspended data is output first.
2. /WAIT Low (t
or t
WH
WZ
): Data not available (driven by CS# low going edge or ADV# low going edge)
AWL
WL
/WAIT High (t ): Data available (driven by Latency-1 clock)
/WAIT High-Z (t ): Data don’t care (driven by CS# high going edge)
3. During the suspend period, OE# high drives DQ to High-Z and OE# low drives DQ to Low-Z. If OE# stays low during
suspend period, the previous data is sustained.
4. Burst Cycle Time (t ) should not be over 2.5µs.
BC
Figure 32.10 Timing Waveform of Burst Read Suspend Cycle (1)
Table 32.9 Burst Read Suspend AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
1
Max
—
Min
—
Max
10
7
t
t
HZ
BEL
clock
t
1
—
t
—
OEL
OHZ
t
5
—
t
—
10
12
7
BLZ
OLZ
WL
ns
t
5
—
t
—
WH
ns
t
—
3
10
—
t
—
CD
OH
WZ
t
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A d v a n c e I n f o r m a t i o n
33 Transition Timing Waveform Between Read And Write
Latency = 5, Burst Length = 4 (MRS# = VIH).
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
T
CLK
tADVH
tADVS
ADV#
tADV
tAH(A)
tBEADV
tAS(A)
tAH(B)
tAS(B)
Valid
Don’t Care
Valid
Address
CS#
tCSS(B)
tAW
tCW
tBC
tCSS(A)
tWLRL
tWP
WE#
OE#
tAS
tOEL
tBEL
tBW
LB#, UB#
Data in
tDH
tDW
Data Valid
Latency 5
High-Z
tCD
tOH
DQ0 DQ1 DQ2 DQ3
tHZ
High-Z
Data out
tWL
tWZ
tWH
High-Z
High-Z
WAIT#
Read Latency 5
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
should be met.
BEADV
2. /WAIT Low (t
or t
WH
WZ
): Data not available (driven by CS# low going edge or ADV# low going edge)
AWL
WL
/WAIT High (t ): Data available (driven by Latency-1 clock)
/WAIT High-Z (t ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (t ) should not be over 2.5µs.
BC
Figure 33.1 Synchronous Burst Read to Asynchronous Write (Address Latch Type)
Table 33.1 Burst Read to Asynchronous Write (Address Latch Type) AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
Max
Min
Max
t
7
—
ns
t
1
—
clock
BEADV
WLRL
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A d v a n c e I n f o r m a t i o n
Latency = 5, Burst Length = 4 (MRS# = VIH).
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
21
T
CLK
tADVH
tADVS
ADV#
tBEADV
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
Valid Adderss
tWR
tAW
tCW
tCSS(B)
tBC
tWLRL
tWP
WE#
OE#
tAS
tOEL
tBEL
tBW
LB#, UB#
Data in
tDH
tDW
Data Valid
Latency 5
High-Z
tCD
tOH
DQ0 DQ1 DQ2 DQ3
tHZ
High-Z
Data out
tWL
tWZ
tWH
High-Z
High-Z
WAIT#
Read Latency 5
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
should be met.
BEADV
2. /WAIT Low (t
or t
WH
WZ
): Data not available (driven by CS# low going edge or ADV# low going edge)
AWL
WL
/WAIT High (t ): Data available (driven by Latency-1 clock)
/WAIT High-Z (t ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (t ) should not be over 2.5µs.
BC
Figure 33.2 Synchronous Burst Read to Asynchronous Write (Low ADV# Type)
Table 33.2 Burst Read to Asynchronous Write (Low ADV# Type) AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
Max
Min
Max
t
7
—
ns
t
1
—
clock
BEADV
WLRL
140
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
A d v a n c e I n f o r m a t i o n
Latency = 5, Burst Length = 4 (MRS# = VIH).
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
T
0
CLK
tADVH
tAH(B)
tADVS
ADV#
tADV
tAH(A)
tAS(A)
tAS(B)
Address
CS#
Don’t Care
tAW
tCW
Don’t Care
tBC
Valid
Valid
tCSS(A)
tCSS(B)
tWLRL
tWP
WE#
OE#
tAS
tOEL
tBEL
tBW
LB#, UB#
Data in
tDH
tDW
Data Valid
Latency 5
tCD
tOH
tHZ
Data out
High-Z
Read Latency 5
DQ0 DQ1 DQ2 DQ3
tWH
tWL
tWZ
High-Z
WAIT#
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
should be met.
BEADV
2. /WAIT Low (t
or t
WH
WZ
): Data not available (driven by CS# low going edge or ADV# low going edge)
AWL
WL
/WAIT High (t ): Data available (driven by Latency-1 clock)
/WAIT High-Z (t ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (t ) should not be over 2.5µs.
BC
Figure 33.3 Asynchronous Write (Address Latch Type) to Synchronous Burst Read Timing
Table 33.3 Asynchronous Write (Address Latch Type) to Burst Read AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
Max
Min
Max
t
1
—
clock
WLRL
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A d v a n c e I n f o r m a t i o n
Latency = 5, Burst Length = 4 (MRS# = VIH).
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
T
0
CLK
tADVH
tAH(B)
tADtHAPDVS
ADV#
Address
CS#
tAS(B)
tWC
Valid
Valid
Don’t Care
tBC
tAW
tCW
tWR
tCSS(B)
tWLRL
tWP
tBW
WE#
OE#
tAS
tOEL
tBEL
LB#, UB#
Data in
tDH
tDW
Data Valid
Latency 5
tCD
tOH
tHZ
Data out
High-Z
DQ0 DQ1 DQ2 DQ3
tWH
tWL
tWZ
High-Z
Read Latency 5
WAIT#
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
should be met.
BEADV
2. /WAIT Low (t
or t
WH
WZ
): Data not available (driven by CS# low going edge or ADV# low going edge)
AWL
WL
/WAIT High (t ): Data available (driven by Latency-1 clock)
/WAIT High-Z (t ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (t ) should not be over 2.5µs.
BC
Figure 33.4 Asynchronous Write (Low ADV# Type) to Synchronous Burst Read Timing
Table 33.4 Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
Max
Min
Max
t
1
—
clock
t
5
—
ns
WLRL
ADHP
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A d v a n c e I n f o r m a t i o n
Latency = 5, Burst Length = 4 (MRS# = VIH).
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
T
CLK
tADVH
tADVS
ADV#
tBEADV
tAH(B)
tAH(B)
tAS(B)
tAS(B)
Valid
Don’t Care
Valid
Address
CS#
tCSS(B)
tBC
tBC
tCSS(B)
tWES
tWEH
WE#
OE#
tOEL
tBEL
tBS
tBH
LB#, UB#
Data in
tDS
Latency 5
tDHC
tWZ
D0 D1 D2 D3
High-Z
Latency 5
High-Z
tCD
tOH
DQ0 DQ1 DQ2 DQ3
tWZ
tHZ
High-Z
Data out
tWH
tWL
tWH
tWL
High-Z
WAIT#
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
should be met.
BEADV
2. /WAIT Low (t
or t
WH
WZ
): Data not available (driven by CS# low going edge or ADV# low going edge)
AWL
WL
/WAIT High (t ): Data available (driven by Latency-1 clock)
/WAIT High-Z (t ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (t ) should not be over 2.5µs.
BC
Figure 33.5 Synchronous Burst Read to Synchronous Burst Write Timing
Table 33.5 Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
Max
Min
Max
t
7
—
ns
BEADV
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143
A d v a n c e I n f o r m a t i o n
Latency = 5, Burst Length = 4 (MRS# = VIH).
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
T
CLK
tADVH
tADVS
ADV#
tBEADV
tAH(B)
tAH(B)
tAS(B)
tAS(B)
Valid
Don’t Care
Valid
Address
CS#
tCSS(B)
tBC
tBC
tCSS(B)
tWES
tWEH
WE#
OE#
tOEL
tBS
tBH
tBEL
LB#, UB#
Data in
tDS
Latency 5
tDHC
D0 D1 D2
D3
High-Z
Latency 5
tCD
tOH
tHZ
DQ0 DQ1 DQ2 DQ3
High-Z
Data out
tWL
tWH
tWZ
tWH
tWL
High-Z
WAIT#
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
should be met.
BEADV
2. /WAIT Low (t
or t
WH
WZ
): Data not available (driven by CS# low going edge or ADV# low going edge)
AWL
WL
/WAIT High (t ): Data available (driven by Latency-1 clock)
/WAIT High-Z (t ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (t ) should not be over 2.5µs.
BC
Figure 33.6 Synchronous Burst Write to Synchronous Burst Read Timing
Table 33.6 Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
Max
Min
Max
t
7
—
ns
BEADV
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1.8V pSRAM Type 4
8M x 16-bit Synchronous Burst pSRAM
ADVANCE
INFORMATION
Features
Process Technology: CMOS
Organization: 8M x16 bit Power Supply Voltage: 1.7–2.0V
Three State Outputs
Supports MRS (Mode Register Set)
MRS control - MRS Pin Control
Supports Power Saving modes - Partial Array Refresh mode Internal TCSR
Supports Driver Strength Optimization for system environment power saving
Supports Asynchronous 4-Page Read and Asynchronous Write Operation
Supports Synchronous Burst Read and Asynchronous Write Operation (Address Latch Type
and Low ADV Type)
Supports Synchronous Burst Read and Synchronous Burst Write Operation
Synchronous Burst (Read/Write) Operation
— Supports 4 word / 8 word / 16 word and Full Page(256 word) burst
— Supports Linear Burst type & Interleave Burst type
— Latency support:
Latency 5 @ 66MHz(tCD 10ns)
Latency 4 @ 54MHz(tCD 10ns)
— Supports Burst Read Suspend in No Clock toggling
— Supports Burst Write Data Masking by /UB & /LB pin control
— Supports WAIT pin function for indicating data availability.
Max. Burst Clock Frequency: 66MHz
Publication Number S71WS-N_01 Revision A Amendment 4 Issue Date September 15, 2005
A d v a n c e I n f o r m a t i o n
34 Pin Description
Pin Name
CLK
Function
Clock
Type
Description
Commands are referenced to CLK
ADV#
MRS#
Address Valid
Mode Register set
Valid Address is latched by ADV falling edge
MRS# low enables Mode Register to be set
CS# low enables the chip to be active
CS# high disables the chip and puts it
into standby mode
CS#
Chip Select
Input
OE#
WE#
LB#
Output Enable
Write Enable
OE# low enables the chip to output the data
WE# low enables the chip to
start writing the data
Lower Byte (I/O
– )
7
0
UB# (LB#) low enables upper byte
(lower byte) to start operating
UB#
Upper Byte (I/O – )
8 15
Valid addresses input when ADV is low
Mode setting input when MRS is low
A0-A22
Address 0 – Address 22
Depending on UB# or LB# status, word (16-bit,
UB#, and LB# low) data, upper byte (8-bit, UB#
low & LB# high) data or lower byte (8-bit, LB# low,
and UB# high) data is loaded
I/O0-I/O15
Data Inputs / Outputs
Input/Output
V
Voltage Source
Voltage Source
Power
Power
GND
Core Power supply
CC
V
I/O Power supply
CCQ
V
Ground Source
Core ground Source
SS
V
I/O Ground Source
Valid Data Indicator
GND
I/O Ground Source
SSQ
WAIT#
Output
WAIT# indicates whether data is valid or not
35 Power Up Sequence
After applying VCC up to minimum operating voltage (1.7V), drive CS# high first and then drive
MRS# high. This gets the device into power up mode. Wait 200 µs minimum to get into the normal
operation mode. During power up mode, the standby current cannot be guaranteed. To obtain
stable standby current levels, at least one cycle of active operation should be implemented re-
gardless of wait time duration. To obtain appropriate device operation, be sure to follow the
proper power up sequence.
1. Apply power.
2. Maintain stable power (VCC min.=1.7V) for a minimum 200 µs with CS# and MRS# high.
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A d v a n c e I n f o r m a t i o n
36 Power Up and Standby Mode Timing Diagrams
36.1 Power Up
200 µs
VCC(Min)
V
CC
Min. 0ns
Min. 0ns
MRS#
CS#
Min. 200 µs
PowerUp Mode
Normal Operation
Note: After V reaches V (Min.), wait 200 µs with CS# and MRS# high. This puts the device into normal operation.
CC
CC
Figure 36.1 Power Up Timing
36.2 Standby Mode
CS# = V
IH
MRS# = V
CS# = UB# = LB# = V
CS# = V , UB# or LB# = V
IL
MRS# = V
IL
IL
IL
WE# = V , MRS# = V
IL
CS# = V
IH
IH
IH
MRS# = V
IH
Initial State
(wait 200µs)
Standby
Mode
PAR
Mode
Power On
MRS Setting
Active
MRS# = V
IL
MRS Setting
CS# = V
IL
WE# = V , MRS#=V
IL IL
Figure 36.2 Standby Mode State Machines
The default mode after power up is Asynchronous mode (4 Page Read and Asynchronous Write).
But this default mode is not 100% guaranteed, so the MRS# setting sequence is highly recom-
mended after power up.
For entry to PAR mode, drive the MRS# pin into VIL for over 0.5µs or longer (suspend period)
during standby mode after the MRS# setting has been completed (A4=1, A3=0). If the MRS# pin
is driven into VIH during PAR mode, the device reverts to standby mode without the wake up
sequence.
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A d v a n c e I n f o r m a t i o n
37 Functional Description
Table 37.1 Asynchronous 4 Page Read & Asynchronous Write Mode (A15/A14=0/0)
Mode
CS#
H
H
L
MRS#
H
OE#
X
WE#
X
LB#
X
X
X
H
L
UB#
X
I/O
I/O
Power
Standby
PAR
0-7
8-15
Deselected
Deselected
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
L
X
X
X
Output Disabled
Outputs Disabled
Lower Byte Read
Upper Byte Read
Word Read
H
H
X
H
X
X
Active
Active
Active
Active
Active
Active
Active
Active
Active
L
H
H
H
L
L
H
L
H
H
H
L
D
OUT
L
H
L
H
L
High-Z
D
D
OUT
OUT
L
H
L
L
D
OUT
Lower Byte Write
Upper Byte Write
Word Write
L
H
H
H
H
H
L
H
L
D
High-Z
IN
L
H
L
H
L
High-Z
D
D
IN
IN
L
H
L
L
D
IN
Mode Register Set
L
L
L
L
L
High-Z
High-Z
Legend: X = Don’t care (must be low or high state).
Notes:
1. In asynchronous mode, Clock and ADV# are ignored.
2. The WAIT# pin is High-Z in asynchronous mode.
Table 37.2 Synchronous Burst Read & Asynchronous Write Mode (A15/A14=0/1)
Mode
Deselected
CS# MRS# OE# WE# LB# UB#
I/O
I/O
CLK
ADV#
Power
0-7
8-15
X
X
H
H
L
H
L
X
X
H
X
X
X
H
X
X
X
X
H
X
X
X
H
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
Standby
(note 2)
(note 2)
X
X
Deselected
PAR
(note 2)
(note 2)
X
Output Disabled
Outputs Disabled
H
H
H
H
Active
Active
(note 2)
X
L
(note 2)
Read Command
Lower Byte Read
Upper Byte Read
L
L
L
H
H
H
X
L
L
H
H
H
X
L
X
H
L
High-Z High-Z
Active
Active
Active
D
High-Z
H
H
OUT
H
High-Z
D
D
OUT
OUT
Word Read
L
H
L
H
L
L
D
H
Active
OUT
X
Lower Byte Write
Upper Byte Write
Word Write
L
L
L
L
H
H
H
L
H
H
H
H
L
L
L
L
L
H
L
H
L
L
L
D
High-Z
Active
Active
Active
Active
IN
or
or
or
or
(note 2)
X
High-Z
D
D
IN
IN
(note 2)
X
D
IN
(note 2)
X
Mode Register Set
L
High-Z High-Z
(note 2)
Notes:
1. X must be low or high state.
2. X means “Don’t care” (can be low, high or toggling).
3. WAIT# is the device output signal and does not have any affect on the mode definition. Please refer to each timing
diagram for Wait# pin function.
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A d v a n c e I n f o r m a t i o n
Table 37.3 Synchronous Burst Read & Synchronous Burst Write Mode(A15/A14 = 1/0)
Mode
CS# MRS#
OE#
WE#
LB#
UB#
I/O
I/O
CLK
ADV#
Power
0-7
8-15
X
X
X
X
X
X
Deselected
H
H
L
H
L
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
Standby
(note1)
(note1)
(note1) (note1)
(note 2) (note 2)
X
X
X
X
X
X
Deselected
PAR
(note1)
(note1)
(note1) (note1)
(note 2) (note 2)
Output
Disabled
X
H
H
H
H
X
H
X
H
H
H
Active
Active
(note 2)
Outputs
Disabled
X
X
X
L
(note1)
(note1)
(note 2)
X
Read Command
L
L
L
H
H
H
H
H
H
X
L
X
H
L
High-Z High-Z
Active
Active
Active
(note1)
Lower Byte
Read
L
L
D
High-Z
H
H
OUT
Upper Byte
Read
H
High-Z
D
D
OUT
OUT
Word Read
L
H
L
H
L
L
D
H
Active
OUT
X
Write Command
L
L
L
H
H
H
High-Z High-Z
Active
Active
Active
L
or
(note1)
Lower Byte
Write
X
H
H
L
H
L
D
High-Z
H
H
IN
(note1)
Upper Byte
Write
X
H
High-Z
D
D
IN
IN
(note1)
X
Word Write
L
L
H
L
H
H
L
L
L
L
D
H
Active
Active
IN
(note1)
Mode Register
Set
High-Z High-Z
L
or
Notes:
1. X must be low or high state.
2. X means “Don’t care” (can be low, high or toggling).
3. WAIT# is the device output signal and does not have any affect on the mode definition. Please refer to each timing
diagram for WAIT# pin function.
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A d v a n c e I n f o r m a t i o n
38 Mode Register Setting Operation
The device has several modes:
Asynchronous Page Read mode
Asynchronous Write mode
Synchronous Burst Read mode
Synchronous Burst Write mode
Standby mode and Partial Array Refresh (PAR) mode.
Partial Array Refresh (PAR) mode is defined through the Mode Register Set (MRS) option. The MRS
option also defines burst length, burst type, wait polarity and latency count at synchronous burst
read/write mode.
38.1 Mode Register Set (MRS)
The mode register stores the data for controlling the various operation modes of the pSRAM. It
programs Partial Array Refresh (PAR), burst length, burst type, latency count and various vendor
specific options to make pSRAM useful for a variety of different applications. The default values
of mode register are defined, therefore when the reserved address is input, the device runs at
default modes.
The mode register is written by driving CS#, ADV#, WE#, UB#, LB# and MRS# to VIL and driving
OE# to VIH during valid addressing. The mode register is divided into various fields depending on
the fields of functions. The PAR field uses A0–A4, Burst Length field uses A5–A7, Burst Type uses
A8, Latency Count uses A9–A11, Wait Polarity uses A13, Operation Mode uses A14–A15 and
Driver Strength uses A16–A17.
Refer to the Table below for detailed Mode Register Settings. A18–A22 addresses are “Don’t care”
in the Mode Register Setting.
Table 38.1 Mode Register Setting According to Field of Function
Address
Function
A17 – A16
A15 – A14
A13
A12
A11 – A19
A8
A7 – A5
A4 – A3
A2
A1 – A0
DS
MS
WP
RFU
Latency
BT
BL
PAR
PARA
PARS
Note: DS (Driver Strength), MS (Mode Select), WP (Wait Polarity), Latency (Latency Count), BT (Burst Type), BL (Burst
Length), PAR (Partial Array Refresh), PARA (Partial Array Refresh Array), PARS (Partial Array Refresh Size), RFU (Reserved
for Future Use).
Table 38.2 Mode Register Set
Driver Strength
DS
Mode Select
MS
A17
0
A16
0
A15
0
A14
0
Full Drive (note 1)
1/2 Drive
Async. 4 Page Read / Async. Write (note 1)
Sync. Burst Read / Async. Write
0
1
0
1
1
0
1/4 Drive
1
0
Sync. Burst Read / Sync. Burst Write
WAIT# Polarity
WP
RFU
RFU
Latency Count
Burst Type
BT
Burst Length
A7 A6 A5 BL
A13
A12
0
A11 A10 A9 Latency A8
Must
(note 1)
0
1
Low Enable (note 1)
High Enable
0
0
0
3
0
1
Linear (note 1)
Interleave
0
1
0
4 word
1
—
0
0
0
0
1
1
1
0
1
4
5
6
0
1
1
1
0
1
1
0
1
8 word
16 word (note 1)
Full (256 word)
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A d v a n c e I n f o r m a t i o n
Partial Array Refresh
PAR
PAR Array
PAR Size
PARS
A4
1
A3
0
A2
0
PARA
Bottom Array (note 1)
Top Array
A1
0
A0
0
PAR Enable
Full Array (note 1)
3/4 Array
1
1
PAR Disable (note 1)
1
0
1
1
0
1/2 Array
1
1
1/4 Array
Note: Default mode. The address bits other than those listed in the table above are reserved. For example, Burst Length
address bits(A7:A6:A5) have 4 sets of reserved bits like 0:0:0, 0:0:1, 1:0:1 and 1:1:0. If the reserved address bits are input,
then the mode will be set to the default mode. Each field has its own default mode, but this default mode is not 100% guar-
anteed, so the MRS setting sequence is highly recommended after power up. A12 is a reserved bit for future use. A12 must
be set as “0”. Not all the mode settings are tested. Per the mode settings to be tested, please contact Spansion. The 256
word Full page burst mode needs to meet t (Burst Cycle time) parameter as max. 2500ns.
BC
38.2 MRS Pin Control Type Mode Register Setting Timing
In this device, the MRS pin is used for two purposes. One is to get into the mode register setting
and the other is to execute Partial Array Refresh mode.
To get into the Mode Register Setting, the system must drive the MRS# pin to VIL and immediately
(within 0.5µs) issue a write command (drive CS#, ADV#, UB#, LB# and WE# to VIL and drive
OE# to VIH during valid address). If the subsequent write command (WE# signal input) is not
issued within 0.5µs, then the device may get into the PAR mode.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
CLK
ADV#
tWC
Address
CS#
tCW
tAW
tBW
UB#, LB#
WE#
tWP
tAS
tWU
tMW
MRS#
Register Update Complete
Register Write Complete
Register Write Start
(MRS SETTING TIMING)
1. Clock input is ignored.
Figure 38.1 Mode Register Setting Timing (OE# = V
Table 38.3 MRS AC Characteristics
)
IH
Speed
Parameter List
MRS# Enable to Register Write Start
End of Write to MRS# Disable
Symbol
tMW
Min
Max
500
—
Units
ns
0
0
MRS
Note:
tWU
ns
V
=1.7
–
2.0V, T =-40 to 85°C, Maximum Main Clock Frequency=66MHz
CC
A
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A d v a n c e I n f o r m a t i o n
39 Asynchronous Operation
39.1 Asynchronous 4 Page Read Operation
Asynchronous normal read operation starts when CS#, OE# and UB# or LB# are driven to VIL
under the valid address without toggling page addresses (A0, A1). If the page addresses (A0, A1)
are toggled under the other valid address, the first data will be out with the normal read cycle
time (tRC) and the second, the third and the fourth data will be out with the page cycle time (tPC).
(MRS# and WE# should be driven to VIH during the asynchronous (page) read operation) Clock,
ADV#, WAIT# signals are ignored during the asynchronous (page) read operation.
39.2 Asynchronous Write Operation
Asynchronous write operation starts when CS#, WE# and UB# or LB# are driven to VIL under the
valid address. MRS# and OE# should be driven to VIH during the asynchronous write operation.
Clock, ADV#, WAIT# signals are ignored during the asynchronous (page) read operation.
39.3 Asynchronous Write Operation in Synchronous Mode
A write operation starts when CS#, WE# and UB# or LB# are driven to VIL under the valid ad-
dress. Clock input does not have any affect to the write operation (MRS# and OE# should be
driven to VIH during write operation. ADV# can be either toggling for address latch or held in VIL).
Clock, ADV#, WAIT# signals are ignored during the asynchronous (page) read operation.
A22~A2
A1~A0
CS#
UB#, LB#
OE#
Data Out
Figure 39.1 Asynchronous 4-Page Read
Address
CS#
UB#, LB#
WE#
High-Z
Data in
High-Z
High-Z
Data out
Figure 39.2 Asynchronous Write
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A d v a n c e I n f o r m a t i o n
40 Synchronous Burst Operation
Burst mode operations enable the system to get high performance read and write operation. The
address to be accessed is latched on the rising edge of clock or ADV# (whichever occurs first).
CS# should be setup before the address latch. During this first clock rising edge, WE# indicates
whether the operation is going to be a Read (WE# High) or a Write (WE# Low).
For the optimized Burst Mode of each system, the system should determine how many clock cy-
cles are required for the first data of each burst access (Latency Count), how many words the
device outputs during an access (Burst Length) and which type of burst operation (Burst Type:
Linear or Interleave) is needed. The Wait Polarity should also be determined (See Table 38.2).
40.1 Synchronous Burst Read Operation
The Synchronous Burst Read command is implemented when the clock rising is detected during
the ADV# low pulse. ADV# and CS# should be set up before the clock rising. During the Read
command, WE# should be held in VIH. The multiple clock risings (during the low ADV# period)
are allowed, but the burst operation starts from the first clock rising. The first data will be out
with Latency count and tCD
.
40.2 Synchronous Burst Write Operation
The Synchronous Burst Write command is implemented when the clock rising is detected during
the ADV# and WE# low pulse. ADV#, WE# and CS# should be set up before the clock rising. The
multiple clock risings (during the low ADV# period) are allowed but, the burst operation starts
from the first clock rising. The first data will be written in the Latency clock with tDS
.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
CLK
ADV#
Addr.
CS#
UB#, LB#
OE#
Data Out
WAIT#
Note: Latency 5, BL 4, WP: Low Enable
Figure 40.1 Synchronous Burst Read
0
1
2
3
4
5
6
7
8
9
10 11 12 13
CLK
ADV#
Addr.
CS#
UB#, LB#
WE#
Data in
WAIT#
Note: Latency 5, BL 4, WP: Low Enable
Figure 40.2 Synchronous Burst Write
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A d v a n c e I n f o r m a t i o n
41 Synchronous Burst Operation Terminology
41.1 Clock (CLK)
The clock input is used as the reference for synchronous burst read and write operation of the
pSRAM. The synchronous burst read and write operations are synchronized to the rising edge of
the clock. The clock transitions must swing between VIL and VIH.
41.2 Latency Count
The Latency Count configuration tells the device how many clocks must elapse from the burst
command before the first data should be available on its data pins. This value depends on the
input clock frequency. Table 41.1 shows the supported Latency Count.
Table 41.1 Latency Count Support
Clock Frequency
Latency Count
Up to 66 MHz
Up to 54 MHz
Up to 40 MHz
5
4
3
Table 41.2 Number of CLocks for 1st Data
Set Latency
Latency 3
Latency 4
Latency 5
# of Clocks for 1st data (Read)
# of Clocks for 1st data (Write)
4
2
5
3
6
4
T
Clock
ADV#
Address
Latency 3
DQ1
DQ2
DQ3
DQ2
DQ1
DQ4
DQ3
DQ2
DQ1
DQ5
DQ4
DQ3
DQ2
DQ6
DQ5
DQ4
DQ3
DQ7
DQ6
DQ5
DQ4
DQ8
DQ7
DQ6
DQ5
DQ9
DQ8
DQ7
DQ6
Data out
Data out
Data out
Data out
Latency 4
Latency 5
Latency 6
DQ1
Note: The first data will always keep the Latency. From the second data on, some period of wait time may be caused by
WAIT# pin.
Figure 41.1 Latency Configuration (Read)
41.3 Burst Length
Burst Length identifies how many data the device outputs during an access. The device supports
4 word, 8 word, 16 word and 256 word burst read or write. 256 word Full page burst mode needs
to meet tBC (Burst Cycle time) parameter as 2500ns max.
The first data will be output with the set Latency + tCD. From the second data on, the data will be
output with tCD from each clock.
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41.4 Burst Stop
Burst stop is used when the system wants to stop burst operation on purpose. If driving CS# to
VIH during the burst read operation, the burst operation is stopped. During the burst read oper-
ation, the new burst operation cannot be issued. The new burst operation can be issued only after
the previous burst operation is finished.
The burst stop feature is very useful because it enables the user to utilize the un-supported burst
length such as 1 burst or 2 burst, used mostly in the mobile handset application environment.
41.5 Wait Control (WAIT#)
The WAIT# signal is the device’s output signal that indicates to the host system when it’s data-
out or data-in is valid.
To be compatible with the Flash interfaces of various microprocessor types, the WAIT# polarity
(WP) can be configured. The polarity can be programmed to be either low enable or high enable.
For the timing of WAIT# signal, the WAIT# signal should be set active one clock prior to the data
regardless of Read or Write cycle.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
CLK
ADV#
CS#
Latency 5
Read
Data out
DQ0 DQ1
DQ2
DQ3
High-Z
High-Z
WAIT#
Latency 5
Write
Data in
D0
D1
D2
D3
WAIT#
Note: LATENCY: 5, Burst Length: 4, WP: Low Enable
Figure 41.2 WAIT# and Read/Write Latency Control
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41.6 Burst Type
The device supports Linear type burst sequence and Interleave type burst sequence. Linear type
burst sequentially increments the burst address from the starting address. The detailed Linear
and Interleave type burst address sequence is shown in Table 41.3.
Table 41.3 Burst Sequence
Burst Address Sequence (Decimal)
Wrap (note 1)
16 word Burst
Interleave
Start
Address
4 word Burst
8 word Burst
Linear Interleave
Full Page(256 word)
Linear
Linear Interleave
Linear
0
1
2
3
4
5
6
7
0-1-2-3 0-1-2-3 0-1-...-5-6-7 0-1-2-...-6-7 0-1-2-...-14-15 0-1-2-3-4...14-15
0-1-2-...-254-255
1-2-3-...-255-0
2-3-4-...-255-0-1
3-4-5-...-255-0-1-2
1-2-3-0 1-0-3-2 1-2-...-6-7-0 1-0-3-...-7-6
2-3-0-1 2-3-0-1 2-3-...-7-0-1 2-3-0-...-4-5
3-0-1-2 3-2-1-0 3-4-...-0-1-2 3-2-1-...-5-4
4-5-...-1-2-3 4-5-6-...-2-3
1-2-3-...-15-0
2-3-4-...-0-1
3-4-5-...-1-2
4-5-6-...-2-3
5-6-7-...-3-4
6-7-8-...-4-5
7-8-9-...-5-6
1-0-3-2-5...15-14
2-3-0-1-6...12-13
3-2-1-0-7...13-12
4-5-6-7-0...10-11 4-5-6-...-255-0-1-2-3
5-6-...-2-3-4 5-4-7-...-3-2
5-4-7-6-1...11-10
6-7-4-5-2...8-9
7-6-5-4-3...9-8
5-6-7-...-255-...-3-4
6-7-8-...-255-...-4-5
7-8-9-...-255-...-5-6
6-7-...-3-4-5 6-7-4-...-0-1
7-0-...-4-5-6 7-6-5-...-1-0
–
–
–
–
14
14-15-0-...-12-13 14-15-12-...-0-1 14-15-...-255-...-12-13
15
15-0-1-...-13-14 15-14-13-...-1-0 15-16-...-255-...-13-14
–
–
255
255-0-1-...-253-254
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42 Low Power Features
42.1 Internal TCSR
The internal Temperature Compensated Self Refresh (TCSR) feature is a very useful tool for re-
ducing standby current at room temperature (below 40°C). DRAM cells have weak refresh
characteristics in higher temperatures. High temperatures require more refresh cycles, which can
lead to standby current increase.
Without the internal TCSR, the refresh cycle should be set at worst condition so as to cover the
high temperature (85°C) refresh characteristics. But with internal TCSR, a refresh cycle below
40°C can be optimized, so the standby current at room temperature can be greatly reduced. This
feature is beneficial since most mobile phones are used at or below 40°C in the phone standby
mode.
0.5 µs
MRS#
Normal
Operation
Normal
Operation
Suspend
PAR mode
MODE
CS#
Figure 42.1 PAR Mode Execution and Exit
Table 42.1 PAR Mode Characteristics
Address
(Bottom Array)
(note 2)
Address
(Top Array)
(note 2)
Memory Cell
Data
Standby Current Wait Time
Power Mode
(µA, Max)
(µs)
Standby (Full Array)
Partial Refresh(3/4 Block)
Partial Refresh(1/2 Block)
Partial Refresh(1/4 Block)
000000h
–
–
–
–
7FFFFFh
000000h
–
–
–
–
7FFFFFh
200
170
150
140
000000h
000000h
000000h
5FFFFFh
3FFFFFh
1FFFFFh
200000h
400000h
600000h
7FFFFFh
7FFFFFh
7FFFFFh
Valid (note 1)
0
Notes:
1. Only the data in the refreshed block are valid.
2. The PAR Array can be selected through Mode Register Set (see Mode Register Setting Operation).
42.2 Driver Strength Optimization
The optimization of output driver strength is possible through the mode register setting to adjust
for the different data loadings. Through this driver strength optimization, the device can minimize
the noise generated on the data bus during read operation. The device supports full drive, 1/2
drive and 1/4 drive.
42.3 Partial Array Refresh (PAR) mode
The PAR mode enables the user to specify the active memory array size. The pSRAM consists of
4 blocks and the user can select 1 block, 2 blocks, 3 blocks or all blocks as active memory arrays
through the Mode Register Setting. The active memory array is periodically refreshed whereas
the disabled array is not refreshed, so the previously stored data is lost. Even though PAR mode
is enabled through the Mode Register Setting, PAR mode execution by the MRS# pin is still
needed. The normal operation can be executed even in refresh-disabled array as long as the
MRS# pin is not driven to the Low condition for over 0.5µs. Driving the MRS# pin to the High
condition puts the device back to the normal operation mode from the PAR executed mode. Refer
to Figure 42.1 and Table 42.1 for PAR operation and PAR address mapping.
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43 Absolute Maximum Ratings
Item
Voltage on any pin relative to VSS
Power supply voltage relative to VSS
Power Dissipation
Symbol
VIN , VOUT
VCC
Ratings
-0.2 to VCC+0.3V
-0.2 to 2.5V
1.0
Unit
V
V
PD
W
Storage temperature
TSTG
-65 to 150
-40 to 85
°C
°C
Operating Temperature
TA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Functional operation should be restricted to use under recommended operating conditions only. Exposure to absolute maxi-
mum rating conditions longer than one second may affect reliability.
44 DC Recommended Operating Conditions
Symbol
VCC
Parameter
Power Supply Voltage
Ground
Min
1.7
Typ
1.85
0
Max
Unit
2.0
VSS
0
0
V
VIH
Input High Voltage
0.8 x VCC
—
VCC + 0.2 (note 2)
-0.2 (note
3)
VIL
Input Low Voltage
—
0.4
Notes:
1. TA=-40 to 85°C, unless otherwise specified.
2. Overshoot: V +1.0V in case of pulse width ≤ 20ns.
CC
3. Undershoot: -1.0V in case of pulse width ≤ 20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
45 Capacitance (Ta = 25°C, f = 1 MHz)
Symbol
CIN
Parameter
Test Condition
VIN = 0V
VOUT = 0V
Min
—
Max
8
Unit
Input Capacitance
pF
pF
CIO
Input/Output Capacitance
—
10
Note: This parameter is sampled periodically and is not 100% tested.
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46 DC and Operating Characteristics
46.1 Common
Item
Symbol
Test Conditions
Min Typ Max Unit
Input Leakage Current
I
V
=V to V
CC
-1
—
1
µA
LI
IN
SS
CS#=V , MRS#=V , OE#=V or
IH
IH
IH
Output Leakage Current
I
LO
-1
—
1
µA
WE#=V , V =V to V
IL
IO
SS
CC
Average Operating
Current
Cycle time=t +3t , I =0mA, 100% duty,
RC
PC IO
I
—
—
40
mA
CC2
CS#=V , MRS#=V , V =V or V
IL
IH
IN
IL
IH
Output Low Voltage
Output High Voltage
V
I
I
=0.1mA
—
1.4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.2
—
V
V
OL
OL
V
=-0.1mA
OH
OH
< 40°C
< 85°C
TBD µA
200 µA
TBD
CS# ≥ V -0.2V, MRS# ≥ V -0.2V,
Other inputs = V to V
CC
CC
Standby Current (CMOS)
I
SB1
SS
CC
3/4 Block
< 40°C 1/2 Block
1/4 Block
TBD µA
TBD
MRS# ≤ 0.2V, CS# ≥ V -0.2V
Other inputs = V to V
CC
CC
Partial Refresh Current
I
(note 1)
SBP
SS
3/4 Block
170
< 85°C 1/2 Block
1/4 Block
150 µA
140
Notes:
1. Full Array Partial Refresh Current (I
) is same as Standby Current (I
).
SBP
SB1
47 AC Operating Conditions
47.1 Test Conditions (Test Load and Test Input/Output Reference)
Input pulse level: 0.2 to VCC -0.2V
Input rising and falling time: 3ns
Input and output reference voltage: 0.5 x VCC
Output load (See Figure 47.1): CL=50pF
Vtt = 0.5 x V
DDQ
50
Dout
Z0=50
30pF
Figure 47.1 PAR Mode Execution and Exit
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47.2 Asynchronous AC Characteristics
(VCC=1.7–2.0V, TA=–40 to 85 °C)
Speed Bins
Symbol
Parameter
Unit
Min
Max
—
—
70
20
70
35
35
—
—
—
7
t
Read Cycle Time
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
RC
t
Page Read Cycle Time
25
PC
t
Address Access Time
—
AA
t
Page Access Time
—
PA
t
Chip Select to Output
—
CO
t
t
Output Enable to Valid Output
UB#, LB# Access Time
—
OE
BA
—
t
Chip Select to Low-Z Output
UB#, LB# Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
UB#, LB# Disable to High-Z Output
Output Disable to High-Z Output
Output Hold
10
LZ
t
5
BLZ
OLZ
CHZ
BHZ
OHZ
t
5
t
t
0
0
7
t
0
7
t
3
—
—
—
—
—
—
—
—
—
—
—
OH
WC
CW
t
Write Cycle Time
70
t
Chip Select to End of Write
ADV# Minimum Low Pulse Width
Address Set-up Time to Beginning of Write
Address Set-up Time to ADV# Falling
Address Hold Time from ADV# Rising
CS# Setup Time to ADV# Rising
Address Valid to End of Write
UB#, LB# Valid to End of Write
Write Pulse Width
60
t
7
ADV
t
0
AS
t
0
AS(A)
AH(A)
t
7
t
10
CSS(A)
t
t
60
AW
BW
60
t
55 (Note 1)
WP
t
WE# High Pulse Width
5 ns
0
Latency-1 clock
WHP
t
Write Recovery Time
—
—
—
—
ns
clock
ns
ns
WR
t
WE# Low to Read Latency
Data to Write Time Overlap
Data Hold from Write Time
1
WLRL
t
30
0
DW
t
DH
Note:
t
(min)=70ns for continuous write operation over 50 times.
WP
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47.3 Timing Diagrams
47.3.1 Asynchronous Read Timing Waveform
MRS# = VIH, WE# = VIH, WAIT# = High-Z
tRC
Address
tAA
tOH
tCO
CS#
tCHZ
tBHZ
tBA
UB#, LB#
tOE
OE#
tOLZ
tBLZ
tLZ
tOHZ
Data out
High-Z
Data Valid
Notes:
1.
t
and t
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
OHZ
CHZ
to output voltage levels.
2. At any given temperature and voltage condition, t
to device interconnection.
is less than t
both for a given device and from device
LZ(Min.)
CHZ(Max.)
3. In asynchronous read cycle, Clock, ADV# and WAIT# signals are ignored.
Figure 47.2 Timing Waveform Of Asynchronous Read Cycle
Table 47.1 Asynchronous Read AC Characteristics
Speed
Speed
Symbol
tRC
Min
70
—
—
—
—
3
Max
—
Units
Symbol
tOLZ
tBLZ
Min
5
Max
—
—
—
7
Units
tAA
70
70
35
35
—
5
tCO
tLZ
10
0
ns
ns
tBA
tCHZ
tBHZ
tOHZ
tOE
0
7
tOH
0
7
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47.3.1.1 Page Read
MRS# = VIH, WE# = VIH, WAIT# = High-Z
t
RC
Valid
Address
A22~A2
tOH
tAA
Valid
Valid
Valid
Valid
A1~A0
CS#
Address
Address Address Address
tPC
tCO
tBA
UB#, LB#
OE#
t
BHZ
t
OE
tCHZ
tBOLZLZ
t
OHZ
t
t
PA
t
LZ
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data out
High Z
Notes:
1.
t
and t
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
OHZ
CHZ
to output voltage levels.
2. At any given temperature and voltage condition, t
to device interconnection.
is less than t
both for a given device and from device
LZ(Min.)
CHZ(Max.)
3. In asynchronous 4 page read cycle, Clock, ADV# and WAIT# signals are ignored.
Figure 47.3 Timing Waveform Of Page Read Cycle
Table 47.2 Asynchronous Page Read AC Characteristics
Speed
Speed
Symbol
tRC
Min
70
—
Max
—
Units
Symbol
tOH
Min
3
Max
—
—
—
—
7
Units
tAA
70
—
tOLZ
tBLZ
tLZ
5
tPC
25
—
5
tPA
20
70
35
35
ns
10
0
ns
tCO
tBA
—
tCHZ
tBHZ
tOHZ
—
0
7
tOE
—
0
7
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47.3.2 Asynchronous Write Timing Waveform
Asynchronous Write Cycle - WE# Controlled
tWC
tCW
Address
CS#
tWR
tAW
tBW
UB#, LB#
WE#
tWP
tAS
tDW
tDH
High-Z
High-Z
Data in
Data Valid
High-Z
Data out
High-Z
Notes:
1. A write occurs during the overlap (t ) of low CS# and low WE#. A write begins when CS# goes low and WE# goes
WP
low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte
operation. A write ends at the earliest transition when CS# goes high or WE# goes high. The t
beginning of write to the end of write.
is measured from the
WP
2.
3.
4.
t
t
t
is measured from the CS# going low to the end of write.
is measured from the address valid to the beginning of write.
CW
AS
is measured from the end of write to the address change. t
is applied in case a write ends with CS# or WE#
WR
WR
going high.
5. In asynchronous write cycle, Clock, ADV# and WAIT# signals are ignored.
Figure 47.4 Timing Waveform Of Write Cycle
Table 47.3 Asynchronous Write AC Characteristics
Speed
Speed
Symbol
tWC
Min
70
60
60
60
Max
—
Units
Symbol
tAS
Min
0
Max
—
Units
tCW
—
tWR
0
—
ns
tAW
—
ns
tDW
30
0
—
tBW
—
tDH
—
tWP
55 (note 1)
—
Note:
t
= 70ns for continuous write operation over 50 times.
WP(min)
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47.3.2.1 Write Cycle 2
MRS# = VIH, OE# = VIH, WAIT# = High-Z, UB# & LB# Controlled
tWC
Address
tWR
tCW
CS#
tAW
tBW
UB#, LB#
tAS
tWP
WE#
tDH
tDW
Data Valid
Data in
High-Z
Data out
High-Z
Notes:
1. A write occurs during the overlap (t ) of low CS# and low WE#. A write begins when CS# goes low and WE# goes
WP
low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte
operation. A write ends at the earliest transition when CS# goes high or WE# goes high. The t
beginning of write to the end of write.
is measured from the
WP
2.
3.
4.
t
t
t
is measured from the CS# going low to the end of write.
is measured from the address valid to the beginning of write.
CW
AS
is measured from the end of write to the address change. t
is applied in case a write ends with CS# or WE#
WR
WR
going high.
5. In asynchronous write cycle, Clock, ADV# and WAIT# signals are ignored.
Figure 47.5 Timing Waveform of Write Cycle(2)
Table 47.4 Asynchronous Write AC Characteristics (UB# & LB# Controlled)
Speed
Speed
Max
Symbol
tWC
Min
70
60
60
60
Max
—
Units
Symbol
tAS
Min
0
Units
—
—
—
—
tCW
—
tWR
0
ns
tAW
—
ns
tDW
30
0
tBW
—
tDH
tWP
55 (note 1)
—
Note:
t
= 70ns for continuous write operation over 50 times.
WP(min)
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47.3.2.1 Write Cycle (Address Latch Type)
MRS# = VIH, OE# = VIH, WAIT# = High-Z, WE# Controlled
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK
tADV
ADV#
tAS(A)
tAH(A)
Address
Valid
tCSS(A)
tCW
CS#
tAW
tBW
UB#, LB#
tWLRL
tWP
WE#
tAS
tDW
tDH
Data in
Data Valid
Read Latency5
High-Z
High-Z
Data out
Notes:
1. A write occurs during the overlap (t ) of low CS# and low WE#. A write begins when CS# goes low and WE# goes
WP
low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for word operation.
A write ends at the earliest transition when CS# goes high or WE# goes high. The t
of write to the end of write.
is measured from the beginning
WP
2.
3.
4.
t
t
t
is measured from the address valid to the end of write. In this address latch type write timing, t
is measured from the CS# going low to the end of write.
is measured from the UB# and LB# going low to the end of write.
is same as t
.
AW
AW
CW
BW
WC
5. Clock input does not have any affect to the write operation if the parameter t
is met.
WLRL
Figure 47.6 Timing Waveform Of Write Cycle (Address Latch Type)
Table 47.5 Asynchronous Write in Synchronous Mode AC Characteristics
Speed
Max
Speed
Symbol
tADV
Min
7
Units
Symbol
tBW
Min
Max
—
Units
ns
—
—
—
—
—
—
60
tAS(A)
tAH(A)
tCSS(A)
tCW
0
tWP
55 (note 2)
—
7
tWLRL
tAS
1
0
—
clock
ns
10
60
60
—
tDW
30
0
—
ns
tAW
tDH
—
Notes:
1. Address Latch Type, WE# Controlled.
2.
t
= 70ns for continuous write operation over 50 times.
WP(min)
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47.3.1 Asynchronous Write Timing Waveform in Synchronous Mode
47.3.1.1 Write Cycle (Low ADV# Type)
MRS# = VIH, OE# = VIH, WAIT# = High-Z, WE# Controlled
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK
ADV#
tWC
Address
tWR
tCW
tAW
CS#
tBW
UB#, LB#
tWLRL
tWP
WE#
tAS
tDH
tDW
Data in
Data Valid
Read Latency 5
High-Z
Data out
High-Z
Notes:
1. Low ADV# type write cycle - WE# Controlled.
2. A write occurs during the overlap (tWP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes
low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte
operation. A write ends at the earliest transition when CS# goes high or WE# goes high. The t
beginning of write to the end of write.
is measured from the
WP
3.
4.
5.
t
t
t
is measured from the CS# going low to the end of write.
is measured from the address valid to the beginning of write.
CW
AS
is measured from the end of write to the address change. t
is applied in case a write ends with CS# or WE#
WR
WR
going high.
6. Clock input does not have any affect to the write operation if the parameter t
is met.
WLRL
Figure 47.7 Timing Waveform Of Write Cycle (Low ADV# Type)
Table 47.6 Asynchronous Write in Synchronous Mode AC Characteristics
Speed
Speed
Max
Symbol
tWC
Min
70
60
60
60
Max
—
Units
Symbol
tWLRL
tAS
Min
1
Units
—
—
—
—
—
clock
tCW
—
0
tAW
—
ns
tWR
0
ns
tBW
—
tDW
30
0
tWP
55 (note 2)
—
tDH
Notes:
1. Low ADV# Type, WE# Controlled.
2. tWP(min) = 70ns for continuous write operation over 50 times.
166
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A d v a n c e I n f o r m a t i o n
47.3.1.2 Write Cycle (Low ADV# Type)
MRS# = VIH, OE# = VIH, WAIT# = High-Z, UB# & LB# Controlled
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK
ADV#
tWC
Address
CS#
tWR
tCW
tAW
tBW
UB#, LB#
WE#
tAS
tWLRL
tWP
tDH
tDW
Data Valid
Data in
Read Latency 5
High-Z
Data out
High-Z
Notes:
1. Low ADV# type write cycle - UB# and LB# Controlled.
2. A write occurs during the overlap (t ) of low CS# and low WE#. A write begins when CS# goes low and WE# goes
WP
low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte
operation. A write ends at the earliest transition when CS# goes high or WE# goes high. The t
beginning of write to the end of write.
is measured from the
WP
3.
4.
5.
t
t
t
is measured from the CS# going low to the end of write.
is measured from the address valid to the beginning of write.
CW
AS
is measured from the end of write to the address change. t
is applied in case a write ends with CS# or WE#
WR
WR
going high.
6. Clock input does not have any affect to the write operation if the parameter t
is met.
WLRL
Figure 47.8 Timing Waveform Of Write Cycle (Low ADV# Type)
Table 47.7 Asynchronous Write in Synchronous Mode AC Characteristics
Speed
Speed
Max
Symbol
tWC
Min
70
60
60
60
Max
—
Units
Symbol
tWLRL
tAS
Min
1
Units
—
—
—
—
—
clock
tCW
—
0
tAW
—
ns
tWR
0
ns
tBW
—
tDW
30
0
tWP
55 (note 2)
—
tDH
Notes:
1. Low ADV# type multiple write, UB#, LB# controlled.
2.
t
= 70ns for continuous write operation over 50 times.
WP(min)
September 15, 2005 S71WS-N_01_A4
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A d v a n c e I n f o r m a t i o n
47.3.1.3 Multiple Write Cycle (Low ADV# Type)
MRSE = VIH, OE# = VIH, WAIT# = High-Z, WE# Controlled\
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK
ADV#
Address
tWC
tWC
tWR
tWR
t
AW
tCW
t
AW
tCW
CS#
tBW
tBW
UB#, LB#
tWHP
tWP
tWP
WE#
tAS
tAS
tDH
tDH
tDW
tDW
Data in
Data Valid
DataValid
Data out
High-Z
High-Z
Notes:
1. Low ADV# type multiple write cycle.
2. A write occurs during the overlap (t ) of low CS# and low WE#. A write begins when CS# goes low and WE# goes
WP
low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte
operation. A write ends at the earliest transition when CS# goes high or WE# goes high. The t
beginning of write to the end of write.
is measured from the
WP
3.
4.
5.
t
t
t
is measured from the CS# going low to the end of write.
is measured from the address valid to the beginning of write.
CW
AS
is measured from the end of write to the address change. t
is applied in case a write ends with CS# or WE#
WR
WR
going high.
6. Clock input does not have any affect on the asynchronous multiple write operation if t
Latency - 1) clock duration.
is shorter than the (Read
WHP
7.
t
= 70ns for continuous write operation over 50 times.
WP(min)
Figure 47.9 Timing Waveform Of Multiple Write Cycle (Low ADV# Type)
Table 47.8 Asynchronous Write in Synchronous Mode AC Characteristics
Speed
Speed
Max
Symbol
Units
Symbol
Units
Min
70
60
60
60
Max
—
Min
5ns
0
t
t
t
t
t
Latency-1 clock
—
WC
CW
AW
BW
WHP
—
t
—
—
—
—
AS
—
ns
t
0
WR
DW
ns
—
t
30
0
t
55 (note 2)
—
t
DH
WP
Notes:
1. Low ADV# type multiple write, WE# Controlled.
2.
t
= 70ns for continuous write operation over 50 times.
WP(min)
168
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
A d v a n c e I n f o r m a t i o n
48 AC Operating Conditions
48.1 Test Conditions (Test Load and Test Input/Output Reference)
Input pulse level: 0.2 to VCC-0.2V
Input rising and falling time: 3ns
Input and output reference voltage: 0.5 x VCC
Output load (See Figure 48.1): CL = 30pF
Vtt = 0.5 x V
DDQ
50
Ω
Dout
Z0=50
Ω
30pF
Figure 48.1 AC Output Load Circuit
September 15, 2005 S71WS-N_01_A4
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169
A d v a n c e I n f o r m a t i o n
48.2 Synchronous AC Characteristics
Speed
Max
Parameter List
Symbol
Units
Min
15
—
0
Clock Cycle Time
T
200
2500
—
—
—
—
—
—
—
—
—
—
10
10
12
7
Burst Cycle Time
t
BC
Address Set-up Time to ADV# Falling (Burst)
Address Hold Time from ADV# Rising (Burst)
ADV# Setup Time
t
AS(B)
AH(B)
t
7
t
5
ADVS
ADV# Hold Time
t
7
ADVH
CS# Setup Time to Clock Rising (Burst)
Burst End to New ADV# Falling
Burst Stop to New ADV# Falling
CS# Low Hold Time from Clock
CS# High Pulse Width
t
5
CSS(B)
t
7
Burst Operation
(Common)
BEADV
ns
t
12
7
BSADV
t
t
CSLH
CSHP
ADHP
55
—
—
—
—
—
1
ADV# High Pulse Width
t
Chip Select to WAIT# Low
t
WL
ADV# Falling to WAIT# Low
Clock to WAIT# High
t
AWL
t
WH
Chip De-select to WAIT# High-Z
UB#, LB# Enable to End of Latency Clock
Output Enable to End of Latency Clock
UB#, LB# Valid to Low-Z Output
Output Enable to Low-Z Output
Latency Clock Rising Edge to Data Output
Output Hold
t
WZ
BEL
OEL
BLZ
OLZ
t
—
—
—
—
10
—
10
7
clock
clock
t
t
1
5
t
5
t
—
3
CD
Burst Read Operation
t
OH
ns
Burst End Clock to Output High-Z
Chip De-select to Output High-Z
Output Disable to Output High-Z
UB#, LB# Disable to Output High-Z
WE# Set-up Time to Command Clock
WE# Hold Time from Command Clock
WE# High Pulse Width
t
—
—
—
—
5
HZ
t
CHZ
OHZ
t
7
t
7
BHZ
WES
WEH
WHP
t
t
t
—
—
—
—
—
—
—
—
—
5
5
UB#, LB# Set-up Time to Clock
UB#, LB# Hold Time from Clock
Byte Masking Set-up Time to Clock
Byte Masking Hold Time from Clock
Data Set-up Time to Clock
t
5
BS
Burst Write Operation
t
5
ns
BH
t
7
BMS
BMH
t
7
t
5
DS
Data Hold Time from Clock
t
3
DHC
Note: 3.(V = 1.7–2.0V, TA=-40 to 85 °C, Maximum Main Clock Frequency = 66MHz.
CC
48.3 Timing Diagrams
48.3.1 Synchronous Burst Operation Timing Waveform
Latency = 5, Burst Length = 4 (MRS# = VIH)
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A d v a n c e I n f o r m a t i o n
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
T
CLK
tADVH
tADVS
ADV#
tBEADV
tBEADV
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
Valid
tCSS(B)
tBC
Undefined
Data out
Data in
DQ0 DQ1 DQ2 DQ3
D0
D1
D2
D3
D0
Burst Command Clock
Burst Read End Clock
Burst Write End Clock
Figure 48.2 Timing Waveform Of Basic Burst Operation
Table 48.1 Burst Operation AC Characteristics
Speed
Speed
Symbol
Min
15
—
5
Max
Units
Symbol
tAS(B)
Min
0
Max
—
Units
T
200
tBC
2500
—
tAH(B)
7
—
ns
ns
tADVS
tADVH
tCSS(B)
tBEADV
5
—
7
—
7
—
September 15, 2005 S71WS-N_01_A4
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171
A d v a n c e I n f o r m a t i o n
48.3.2 Synchronous Burst Read Timing Waveforms
48.3.2.1 Read Timings
Latency = 5, Burst Length = 4, WP = Low enable (WE# = VIH, MRS# = VIH).
CS# Toggling Consecutive Burst Read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
T
CLK
tADVH
tADVS
ADV#
tBEADV
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
Valid
tCSHP
tCSS(B)
tBC
tBHZ
tOHZ
tBEL
LB#, UB#
OE#
tBLZ
tOEL
tCHZ
tHZ
tOLZ
Latency 5
tCD
tOH
Undefined
Data out
DQ0 DQ1 DQ2 DQ3
tWZ
tWL
tWH
tWH
tWL
WAIT#
High-Z
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
should be met.
BEADV
2. /WAIT Low (t
or t
WH
WZ
): Data not available (driven by CS# low going edge or ADV# low going edge)
AWL
WL
/WAIT High (t ): Data available (driven by Latency-1 clock)
/WAIT High-Z (t ): Data don’t care (driven by CS# high going edge).
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (t ) should not be over 2.5µs.
BC
Figure 48.3 Timing Waveform of Burst Read Cycle (1)
Table 48.2 Burst Read AC Characteristics
Speed
Speed
Symbol
tCSHP
tBEL
Min
5
Max
—
Units
Symbol
tOHZ
tBHZ
tCD
Min
—
—
—
3
Max
7
Units
ns
1
—
7
clock
ns
tOEL
1
—
10
—
10
12
7
tBLZ
5
—
tOH
ns
tOLZ
tHZ
5
—
tWL
—
—
—
—
—
10
7
tWH
tCHZ
tWZ
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A d v a n c e I n f o r m a t i o n
Latency = 5, Burst Length = 4, WP = Low enable (WE# = VIH, MRS# = VIH).
CS# Low Holding Consecutive Burst Read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
T
CLK
t
ADVH
ADVS
t
ADV#
tBEADV
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
Valid
tCSS(B)
tBC
tBEL
LB#, UB#
OE#
tBLZ
tOEL
t
OLZ
Latency 5
tCD
tOH
tHZ
Undefined
Data out
DQ0 DQ1 DQ2 DQ3
tAWL
tWH
tWL
tWH
WAIT#
High-Z
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
should be met.
BEADV
2. /WAIT Low (t
or t
WH
WZ
): Data not available (driven by CS# low going edge or ADV# low going edge)
AWL
WL
/WAIT High (t ): Data available (driven by Latency-1 clock)
/WAIT High-Z (t ): Data don’t care (driven by CS# high going edge).
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. The consecutive multiple burst read operation with holding CS# low is possible only through issuing a new ADV# and
address.
5. Burst Cycle Time (t ) should not be over 2.5µs.
BC
Figure 48.4 Timing Waveform of Burst Read Cycle (2)
Table 48.3 Burst Read AC Characteristics
Speed
Speed
Symbol
tBEL
Min
1
Max
—
Units
Symbol
tCD
Min
—
3
Max
10
—
Units
clock
tOEL
tBLZ
tOLZ
tHZ
1
—
tOH
5
—
tWL
—
—
—
10
10
12
ns
5
—
ns
tAWL
tWH
—
10
September 15, 2005 S71WS-N_01_A4
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173
A d v a n c e I n f o r m a t i o n
Latency = 5, Burst Length = 4, WP = Low enable (WE# = VIH, MRS# = VIH).
Last data sustaining
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
T
CLK
tADVH
tADVS
ADV#
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
tCSS(B)
tBC
tBEL
tOEL
LB#, UB#
OE#
tBLZ
tOLZ
Latency 5
tOH
tCD
Undefined
Data out
DQ0 DQ1 DQ2 DQ3
tWL
tWH
High-Z
WAIT#
Notes:
1. /WAIT Low (t
or t
WH
WZ
): Data not available (driven by CS# low going edge or ADV# low going edge)
AWL
WL
/WAIT High (t ): Data available (driven by Latency-1 clock)
/WAIT High-Z (t ): Data don’t care (driven by CS# high going edge).
2. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
3. Burst Cycle Time (t ) should not be over 2.5µs.
BC
Figure 48.5 Timing Waveform of Burst Read Cycle (3)
Table 48.4 Burst Read AC Characteristics
Speed
Speed
Symbol
tBEL
Min
1
Max
—
Units
Symbol
tCD
Min
—
3
Max
10
—
Units
clock
tOEL
1
—
tOH
ns
tBLZ
5
—
tWL
—
—
10
12
ns
tOLZ
5
—
tAWL
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A d v a n c e I n f o r m a t i o n
48.3.2.1 Write Timings
Latency = 5, Burst Length = 4, WP = Low enable (OE# = VIH, MRS# = VIH).
CS# Toggling Consecutive Burst Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
T
CLK
tADVH
tADVS
ADV#
tBEADV
tCSHP
tAH(B)
tAS(B)
Address
CS#
Valid
Valid
Don’t Care
tBC
tCSS(B)
tBS
tBMS
tBH
tBMH
LB#, UB#
WE#
tWEH
tWHP
tWES
tDS
tDHC
tDHC
Latency 5
tWH
Latency 5
tWH
Data in
D0
D1
D2
D3
D0
tWZ
tWL
tWL
High-Z
WAIT#
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
should be met.
BEADV
2. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
3. /WAIT Low (t or t ): Data not available (driven by CS# low going edge or ADV# low going edge)
WL
AWL
/WAIT High (t ): Data available (driven by Latency-1 clock)
WH
/WAIT High-Z (t ): Data don’t care (driven by CS# high going edge)
WZ
4. D2 is masked by UB# and LB#.
5. Burst Cycle Time (t ) should not be over 2.5µs.
BC
Figure 48.6 Timing Waveform of Burst Write Cycle (1)
Table 48.5 Burst Write AC Characteristics
Speed
Speed
Symbol
tCSHP
tBS
Min
5
Max
—
Units
Symbol
tWHP
tDS
Min
5
Max
—
Units
5
—
5
—
tBH
5
—
tDHC
tWL
3
—
ns
tBMS
tBMH
tWES
tWEH
7
—
ns
—
—
—
10
12
7
7
—
tWH
5
—
tWZ
5
—
September 15, 2005 S71WS-N_01_A4
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A d v a n c e I n f o r m a t i o n
Latency = 5, Burst Length = 4, WP = Low enable (OE# = VIH, MRS# = VIH).
CS# Low Holding Consecutive Burst Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
T
CLK
t
ADVH
ADVS
t
ADV#
tBEADV
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
Valid
tCSS(B)
tBC
tBEL
LB#, UB#
OE#
tBLZ
tOEL
t
OLZ
Latency 5
tCD
tOH
tHZ
Undefined
Data out
DQ0 DQ1 DQ2 DQ3
tAWL
tWH
tWL
tWH
WAIT#
High-Z
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
should be met.
BEADV
2. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
3. /WAIT Low (t or t ): Data not available (driven by CS# low going edge or ADV# low going edge)
WL
AWL
/WAIT High (t ): Data available (driven by Latency-1 clock)
WH
/WAIT High-Z (t ): Data don’t care (driven by CS# high going edge)
WZ
4. D2 is masked by UB# and LB#.
5. The consecutive multiple burst read operation with holding CS# low is possible only through issuing a new ADV# and
address.
6. Burst Cycle Time (t ) should not be over 2.5µs.
BC
Figure 48.7 Timing Waveform of Burst Write Cycle (2)
Table 48.6 Burst Write AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
5
Max
—
Min
5
Max
—
t
t
WHP
BS
t
5
—
t
5
—
BH
DS
t
7
—
t
3
—
BMS
BMH
WES
WEH
DHC
ns
ns
t
t
7
—
t
—
—
—
10
10
12
WL
5
—
t
AWL
t
5
—
t
WH
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S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
A d v a n c e I n f o r m a t i o n
48.3.3 Synchronous Burst Read Stop Timing Waveform
Latency = 5, Burst Length = 4, WP = Low enable (WE#= VIH, MRS# = VIH).
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
T
CLK
tADVH
tADVS
ADV#
tBSADV
tCSHP
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
Valid
tCSS(B)
tCSLH
tBEL
tOEL
LB#, UB#
OE#
tBLZ
tOLZ
Latency 5
tOH
tCHZ
tCD
Undefined
Data
DQ0
DQ1
tWZ
tWL
tWL
tWH
High-Z
High-Z
WAIT#
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished.
2. /WAIT Low (t or t ): Data not available (driven by CS# low going edge or ADV# low going edge)
WL
AWL
/WAIT High (t ): Data available (driven by Latency-1 clock)
WH
/WAIT High-Z (t ): Data don’t care (driven by CS# high going edge)
WZ
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. The burst stop operation should not be repeated for over 2.5µs.
Figure 48.8 Timing Waveform of Burst Read Stop by CS#
Table 48.7 Burst Read Stop AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
12
7
Max
—
Min
—
3
Max
10
—
t
t
BSADV
CD
t
t
—
ns
t
CSLH
CSHP
OH
5
—
t
—
—
—
—
7
CHZ
ns
t
1
—
t
10
12
7
BEL
OEL
WL
clock
ns
t
1
—
t
WH
t
5
—
t
WZ
BLZ
OLZ
t
5
—
September 15, 2005 S71WS-N_01_A4
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177
A d v a n c e I n f o r m a t i o n
48.3.4 Synchronous Burst Write Stop Timing Waveform
Latency = 5, Burst Length = 4, WP = Low enable (OE#= VIH, MRS# = VIH).
0
1
2
3
4
5
6
7
8
9
10
11
12
13
T
CLK
t
ADVH
ADVS
t
ADV#
tBSADV
tAH(B)
tAS(B)
Don’t Care
Address
CS#
Valid
Valid
tCSHP
t
CSS(B)
tCSLH
tBS
tBH
LB#, UB#
WE#
tWHP
t
WEH
t
WES
tDS
tDHC
Latency 5
Latency 5
Data in
D0
D1
D0
D1
D2
tWZ
t
WL
t
WL
tWH
tWH
High-Z
High-Z
WAIT#
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished.
2. /WAIT Low (t or t ): Data not available (driven by CS# low going edge or ADV# low going edge)
WL
AWL
/WAIT High (t ): Data available (driven by Latency-1 clock)
WH
/WAIT High-Z (t ): Data don’t care (driven by CS# high going edge)
WZ
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. The burst stop operation should not be repeated for over 2.5µs.
Figure 48.9 Timing Waveform of Burst Write Stop by CS#
Table 48.8 Burst Write Stop AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
12
7
Max
—
Min
5
Max
—
t
t
WHP
BSADV
t
t
—
t
5
—
CSLH
DS
5
—
t
3
—
CSHP
DHC
ns
t
5
—
t
—
—
—
10
12
7
ns
BS
WL
t
5
—
t
WH
BH
t
5
—
t
WZ
WES
WEH
t
5
—
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A d v a n c e I n f o r m a t i o n
48.3.5 Synchronous Burst Read Suspend Timing Waveform
Latency = 5, Burst Length = 4, WP = Low enable (WE#= VIH, MRS# = VIH).
0
1
2
3
4
5
6
7
8
9
10
11
T
CLK
tADVH
tADVS
ADV#
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
tCSS(B)
tBC
tBEL
tOEL
LB#, UB#
OE#
tBLZ
tOLZ
Latency 5
tOHZ
tOLZ
tOH
tCD
tHZ
High-Z
Undefined
Data out
DQ0 DQ1
DQ1 DQ2 DQ3
tWZ
tWL
tWH
WAIT#
High-Z
Notes:
1. If the clock input is halted during burst read operation, the data output will be suspended. During the burst read
suspend period, OE# high drives data output to high-Z. If the clock input is resumed, the suspended data will be
output first.
2. /WAIT Low (t
or t
WH
WZ
): Data not available (driven by CS# low going edge or ADV# low going edge)
WL
AWL
/WAIT High (t ): Data available (driven by Latency-1 clock)
/WAIT High-Z (t ): Data don’t care (driven by CS# high going edge)
3. During the suspend period, OE# high drives DQ to High-Z and OE# low drives DQ to Low-Z. If OE# stays low during
suspend period, the previous data will be sustained.
4. Burst Cycle Time (t ) should not be over 2.5µs.
BC
Figure 48.10 Timing Waveform of Burst Read Suspend Cycle (1)
Table 48.9 Burst Read Suspend AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
1
Max
—
Min
—
Max
10
7
t
t
HZ
BEL
clock
t
1
—
t
—
OEL
OHZ
t
5
—
t
—
10
12
7
BLZ
OLZ
WL
ns
t
5
—
t
—
WH
ns
t
—
3
10
—
t
—
CD
OH
WZ
t
September 15, 2005 S71WS-N_01_A4
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A d v a n c e I n f o r m a t i o n
49 Transition Timing Waveform Between Read And Write
Latency = 5, Burst Length = 4, WP = Low enable (MRS# = VIH).
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
T
CLK
tADVH
tADVS
ADV#
tADV
tAH(A)
tBEADV
tAS(A)
tAH(B)
tAS(B)
Valid
Don’t Care
Valid
Address
CS#
tCSS(B)
tAW
tCW
tBC
tCSS(A)
tWLRL
tWP
WE#
OE#
tAS
tOEL
tBEL
tBW
LB#, UB#
Data in
tDH
tDW
Data Valid
Latency 5
High-Z
tCD
tOH
DQ0 DQ1 DQ2 DQ3
tHZ
High-Z
Data out
tWL
tWZ
tWH
High-Z
High-Z
WAIT#
Read Latency 5
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
should be met.
BEADV
2. /WAIT Low (t
or t
WH
WZ
): Data not available (driven by CS# low going edge or ADV# low going edge)
AWL
WL
/WAIT High (t ): Data available (driven by Latency-1 clock)
/WAIT High-Z (t ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (t ) should not be over 2.5µs.
BC
Figure 49.1 Synchronous Burst Read to Asynchronous Write (Address Latch Type)
Table 49.1 Burst Read to Asynchronous Write (Address Latch Type) AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
Max
Min
Max
t
7
—
ns
t
1
—
clock
BEADV
WLRL
180
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
A d v a n c e I n f o r m a t i o n
Latency = 5, Burst Length = 4 (MRS# = VIH).
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
21
T
CLK
tADVH
tADVS
ADV#
tBEADV
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
Valid Adderss
tWR
tAW
tCW
tCSS(B)
tBC
tWLRL
tWP
WE#
OE#
tAS
tOEL
tBEL
tBW
LB#, UB#
Data in
tDH
tDW
Data Valid
Latency 5
High-Z
tCD
tOH
DQ0 DQ1 DQ2 DQ3
tHZ
High-Z
Data out
tWL
tWZ
tWH
High-Z
High-Z
WAIT#
Read Latency 5
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
should be met.
BEADV
2. /WAIT Low (t
or t
WH
WZ
): Data not available (driven by CS# low going edge or ADV# low going edge)
AWL
WL
/WAIT High (t ): Data available (driven by Latency-1 clock)
/WAIT High-Z (t ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (t ) should not be over 2.5µs.
BC
Figure 49.2 Synchronous Burst Read to Asynchronous Write (Low ADV# Type)
Table 49.2 Burst Read to Asynchronous Write (Low ADV# Type) AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
Max
Min
Max
t
7
—
ns
t
1
—
clock
BEADV
WLRL
September 15, 2005 S71WS-N_01_A4
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181
A d v a n c e I n f o r m a t i o n
Latency = 5, Burst Length = 4 (MRS# = VIH).
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
T
0
CLK
tADVH
tAH(B)
tADVS
ADV#
tADV
tAH(A)
tAS(A)
tAS(B)
Address
CS#
Don’t Care
tAW
tCW
Don’t Care
tBC
Valid
Valid
tCSS(A)
tCSS(B)
tWLRL
tWP
WE#
OE#
tAS
tOEL
tBEL
tBW
LB#, UB#
Data in
tDH
tDW
Data Valid
Latency 5
tCD
tOH
tHZ
Data out
High-Z
Read Latency 5
DQ0 DQ1 DQ2 DQ3
tWH
tWL
tWZ
High-Z
WAIT#
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
should be met.
BEADV
2. /WAIT Low (t
or t
WH
WZ
): Data not available (driven by CS# low going edge or ADV# low going edge)
AWL
WL
/WAIT High (t ): Data available (driven by Latency-1 clock)
/WAIT High-Z (t ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (t ) should not be over 2.5µs.
BC
Figure 49.3 Asynchronous Write (Address Latch Type) to Synchronous Burst Read Timing
Table 49.3 Asynchronous Write (Address Latch Type) to Burst Read AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
Max
Min
Max
t
1
—
clock
WLRL
182
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S71WS-N_01_A4 September 15, 2005
A d v a n c e I n f o r m a t i o n
Latency = 5, Burst Length = 4 (MRS# = VIH).
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
T
0
CLK
tADVH
tAH(B)
tADtHAPDVS
ADV#
Address
CS#
tAS(B)
tWC
Valid
Valid
Don’t Care
tBC
tAW
tCW
tWR
tCSS(B)
tWLRL
tWP
tBW
WE#
OE#
tAS
tOEL
tBEL
LB#, UB#
Data in
tDH
tDW
Data Valid
Latency 5
tCD
tOH
tHZ
Data out
High-Z
DQ0 DQ1 DQ2 DQ3
tWH
tWL
tWZ
High-Z
Read Latency 5
WAIT#
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
should be met.
BEADV
2. /WAIT Low (t
or t
WH
WZ
): Data not available (driven by CS# low going edge or ADV# low going edge)
AWL
WL
/WAIT High (t ): Data available (driven by Latency-1 clock)
/WAIT High-Z (t ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (t ) should not be over 2.5µs.
BC
Figure 49.4 Asynchronous Write (Low ADV# Type) to Synchronous Burst Read Timing
Table 49.4 Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
Max
Min
Max
t
1
—
clock
t
—
ns
WLRL
ADHP
September 15, 2005 S71WS-N_01_A4
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183
A d v a n c e I n f o r m a t i o n
Latency = 5, Burst Length = 4 (MRS# = VIH).
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
T
CLK
tADVH
tADVS
ADV#
tBEADV
tAH(B)
tAH(B)
tAS(B)
tAS(B)
Valid
Don’t Care
Valid
Address
CS#
tCSS(B)
tBC
tBC
tCSS(B)
tWES
tWEH
WE#
OE#
tOEL
tBEL
tBS
tBH
LB#, UB#
Data in
tDS
Latency 5
tDHC
tWZ
D0 D1 D2 D3
High-Z
Latency 5
High-Z
tCD
tOH
DQ0 DQ1 DQ2 DQ3
tWZ
tHZ
High-Z
Data out
tWH
tWL
tWH
tWL
High-Z
WAIT#
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
should be met.
BEADV
2. /WAIT Low (t
or t
WH
WZ
): Data not available (driven by CS# low going edge or ADV# low going edge)
AWL
WL
/WAIT High (t ): Data available (driven by Latency-1 clock)
/WAIT High-Z (t ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (t ) should not be over 2.5µs.
BC
Figure 49.5 Synchronous Burst Read to Synchronous Burst Write Timing
Table 49.5 Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
Max
Min
Max
t
7
—
ns
BEADV
184
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
A d v a n c e I n f o r m a t i o n
Latency = 5, Burst Length = 4 (MRS# = VIH).
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
T
CLK
tADVH
tADVS
ADV#
tBEADV
tAH(B)
tAH(B)
tAS(B)
tAS(B)
Valid
Don’t Care
Valid
Address
CS#
tCSS(B)
tBC
tBC
tCSS(B)
tWES
tWEH
WE#
OE#
tOEL
tBS
tBH
tBEL
LB#, UB#
Data in
tDS
Latency 5
tDHC
D0 D1 D2
D3
High-Z
Latency 5
tCD
tOH
tHZ
DQ0 DQ1 DQ2 DQ3
High-Z
Data out
tWL
tWH
tWZ
tWH
tWL
High-Z
WAIT#
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
should be met.
BEADV
2. /WAIT Low (t
or t
WH
WZ
): Data not available (driven by CS# low going edge or ADV# low going edge)
AWL
WL
/WAIT High (t ): Data available (driven by Latency-1 clock)
/WAIT High-Z (t ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (t ) should not be over 2.5µs.
BC
Figure 49.6 Synchronous Burst Write to Synchronous Burst Read Timing
Table 49.6 Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
Max
Min
Max
t
7
—
ns
BEADV
September 15, 2005 S71WS-N_01_A4
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185
A d v a n c e I n f o r m a t i o n
50 Revisions
Revision A (February 1, 2004)
Initial Release
Revision A1 (February 9, 2005)
Updated document to include Burst Speed of 66 Mhz
Updated Publication Number
Revision A2 (April 11, 2005)
Updated Product Selector Guide and Ordering Information tables
Revision A3 (May 13, 2005)
Updated the entire utRAM module
Revision A4 (September 15, 2005)
Added 128-MB module.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with above-
mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels
and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on ex-
port under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development
by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.
Copyright ©2004-2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and
product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
186
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S71WS-N_01_A4 September 15, 2005
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