S71NS064NA0BJWVN3_技术文档

S71NS-N MCP Products

MirrorBit^TM1.8 Volt-only Simultaneous Read/Write,

Burst-mode Multiplexed Flash Memory:

256 Mb (16 Mb x 16-bit), 128 Mb (8 Mb x 16-bit) and

64 Mb (4 Mb x 16-bit) with Burst-mode Multiplexed

pSRAM: 64 Mb (4 Mb x 16-bit), 32 Mb (2 Mb x 16-bit)

and 16 Mb (1 Mb x 16-bit)

ADVANCE

INFORMATION

Data Sheet

Notice to Readers: The Advance Information status indicates that this

document contains information on one or more products under development

at Spansion Inc. The information is intended to help you evaluate this product.

Do not design in this product without contacting the factory. Spansion Inc.

reserves the right to change or discontinue work on this proposed product

without notice.

Publication Number S71NS-N_00 Revision A Amendment 3 Issue Date October 10, 2006

A d v a n c e I n f o r m a t i o n

Notice On Data Sheet Designations

Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise

readers of product information or intended specifications throughout the product life cycle, in-

cluding development, qualification, initial production, and full production. In all cases, however,

readers are encouraged to verify that they have the latest information before finalizing their de-

sign. The following descriptions of Spansion data sheet designations are presented here to high-

light their presence and definitions.

Advance Information

The Advance Information designation indicates that Spansion Inc. is developing one or more

specific products, but has not committed any design to production. Information presented in a

document with this designation is likely to change, and in some cases, development on the prod-

uct may discontinue. Spansion Inc. therefore places the following conditions upon Advance Infor-

mation content:

“This document contains information on one or more products under development at Spansion Inc. The

information is intended to help you evaluate this product. Do not design in this product without con-

tacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed

product without notice.”

Preliminary

The Preliminary designation indicates that the product development has progressed such that a

commitment to production has taken place. This designation covers several aspects of the prod-

uct life cycle, including product qualification, initial production, and the subsequent phases in the

manufacturing process that occur before full production is achieved. Changes to the technical

specifications presented in a Preliminary document should be expected while keeping these as-

pects of production under consideration. Spansion places the following conditions upon Prelimi-

nary content:

“This document states the current technical specifications regarding the Spansion product(s) described

herein. The Preliminary status of this document indicates that product qualification has been completed,

and that initial production has begun. Due to the phases of the manufacturing process that require

maintaining efficiency and quality, this document may be revised by subsequent versions or modifica-

tions due to changes in technical specifications.”

Combination

Some data sheets will contain a combination of products with different designations (Advance In-

formation, Preliminary, or Full Production). This type of document will distinguish these products

and their designations wherever necessary, typically on the first page, the ordering information

page, and pages with DC Characteristics table and AC Erase and Program table (in the table

notes). The disclaimer on the first page refers the reader to the notice on this page.

Full Production (No Designation on Document)

When a product has been in production for a period of time such that no changes or only nominal

changes are expected, the Preliminary designation is removed from the data sheet. Nominal

changes may include those affecting the number of ordering part numbers available, such as the

addition or deletion of a speed option, temperature range, package type, or V range. Changes

IO

may also include those needed to clarify a description or to correct a typographical error or incor-

rect specification. Spansion Inc. applies the following conditions to documents in this category:

“This document states the current technical specifications regarding the Spansion product(s) described

herein. Spansion Inc. deems the products to have been in sufficient production volume such that sub-

sequent versions of this document are not expected to change. However, typographical or specification

corrections, or modifications to the valid combinations offered may occur.”

Questions regarding these document designations may be directed to your local AMD or Fujitsu

sales office.

ii

S71NS-N_00_A3 October 10, 2006

S71NS-N MCP Products

MirrorBit^TM1.8 Volt-only Simultaneous Read/Write,

Burst-mode Multiplexed Flash Memory:

256 Mb (16 Mb x 16-bit), 128 Mb (8 Mb x 16-bit) and

64 Mb (4 Mb x 16-bit) with Burst-mode Multiplexed

pSRAM: 64 Mb (4 Mb x 16-bit), 32 Mb (2 Mb x 16-bit)

and 16 Mb (1 Mb x 16-bit)

ADVANCE

INFORMATION

General Description

The S71NS-N Series is a product line of stacked Multi-Chip Product (MCP) packages and consists

of the following items:

One or more S29NS-N flash memory die

Mux burst-mode pSRAM

The products covered by this document are listed in the table below. For details about their spec-

ifications, please refer to their individual datasheet for further details.

pSRAM

Density

64 Mb

16 Mb

32 Mb

64 Mb

S71NS064NA0

S71NS128NA0

Flash

128 Mb

256 Mb

S71NS128NB0

S71NS256NB0

S71NS128NC0

S71NS256NC0

Distinctive Characteristics

MCP Features

Power supply voltage of 1.7 V to 1.95 V

Burst Speed: 66 MHz

Package - MCP BGA: 0.5 mm ball pitch

— 8.0 x 9.2 mm, 56 ball for NS064N and NS128N based MCPs

— 10.0 x 11.0 mm, 60 ball for NS256N based MCPs

Operating Temperature

— Wireless, –25°C to +85°C

For detailed specifications, please refer to the individual data sheets:

Document

Publication Identification Number

S29NS-N

S29NS-N_00

muxpsram_05

muxpsram_03

muxpsram_04

muxpsram_01

16 M Multiplexed pSRAM Type 2

16 M Multiplexed pSRAM Type 3

32 M Multiplexed pSRAM Type 3

64 M Multiplexed pSRAM Type 3

Publication Number S71NS-N_00 Revision A Amendment 3 Issue Date October 10, 2006

A d v a n c e I n f o r m a t i o n

1 Ordering Information

The ordering part number is formed by a valid combination of the following:

S71NS 128

N

C

0

BJ

W

R

N

0

Packing Type

0

2

3

=

Tray

7-inch Tape and Reel

13-inch Tape and Reel

RAM Supplier and Speed Combinations

N

T

=

pSRAM Type 3, 70 ns, 66 MHz

pSRAM Type 2, 70 ns, 66 MHz

Package Modifier

R

V

=

1.2 mm, 8.0 x 9.2, 56-ball VFBGA

1.2 mm, 11 x 10 mm, 60-ball VFBGA

Temperature Range

Wireless (-25°C to +85°C)

W

=

Package Type

BJ

=

Very Thin Fine-Pitch Ball Grid Array (VFBGA)

Lead (Pb)-free Package (LF35)

Chip Contents—2

No content

pSRAM Density

C = 64 Mb

B = 32 Mb

A = 16 Mb

Process Technology

N

=

110 nm MirrorBit Technology

Flash Density

256

128

064

=

256 Mb

128 Mb

64 Mb

Device Family

S71NS = Multi-Chip Product

1.8 Volt-only Simultaneous Read/Write Burst Mode

Multiplexed Flash Memory + pSRAM

Table 1.1 MCP Configurations and Valid Combinations

Base Ordering Part

Number (Note 2)

Package &

Temperature

Model

Number

Packing

Type

Flash Speed

Options

pSRAM Speed

Options

pSRAM Type

RT

RN

VN

pSRAM Type 2

pSRAM Type 3

66 MHz

S71NS064NA0

S71NS128NA0

S71NS128NB0

S71NS128NC0

S71NS256NB0

S71NS256NC0

BJW

0, 1, 2

Package Marking Note:

The package marking omits the leading S from the ordering part number.

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult

your local sales office to confirm availability of specific valid combinations and to check on newly

released combinations.

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S71NS-N MCP Products

S71NS-N_00_A3 October 10, 2006

A d v a n c e I n f o r m a t i o n

2 Input/Output Descriptions

Table 2.1 identifies the input and output package connections provided on the device.

Table 2.1 Input/Output Descriptions

Symbol

AMAX – A16

ADQ15 – ADQ0

OE#

Description

Flash

RAM

X

Address inputs

X

Multiplexed Address/Data

X

Output Enable input. Asynchronous relative to CLK for the Burst mode.

X

WE#

Write Enable input.

X

V

Ground

X

SS

NC

No Connect; not connected internally

X

Ready output. Indicates the status of the Burst read. The WAIT# pin of the

pSRAM is tied to RDY.

RDY

X

Clock input. In burst mode, after the initial word is output, subsequent

active edges of CLK increment the internal address counter. Should be at

CLK

X

V

or V while in asynchronous mode

IL

IH

Address Valid input. Indicates to device that the valid address is present

on the address inputs.

AVD#

Low = for asynchronous mode, indicates valid address; for burst mode,

causes starting address to be latched.

X

High = device ignores address inputs

Hardware reset input. Low = device resets and returns to reading array

data

F-RST#

F-WP#

X

Hardware write protect input. At V , disables program and erase functions

IL

in the four outermost sectors. Should be at V for all other conditions.

IH

Accelerated input. At V , accelerates programming; automatically places

HH

F-ACC

device in unlock bypass mode. At V , disables all program and erase

X

IL

functions. Should be at V for all other conditions.

IH

R-CE1#

F-CE#

R-CRE

F-VCC

R-VCC

R-UB#

R-LB#

DNU

Chip-enable input for pSRAM.

X

Chip-enable input for Flash. Asynchronous relative to CLK for Burst Mode.

Control Register Enable (pSRAM).

Flash 1.8 Volt-only single power supply.

pSRAM Power Supply.

X

Upper Byte Control (pSRAM).

Lower Byte Control (pSRAM)

Do Not Use

October 10, 2006 S71NS-N_00_A3

S71NS-N MCP Products

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A d v a n c e I n f o r m a t i o n

3 MCP Block Diagram

Figure 3.1 MCP Block Diagram

F-RST#

RST#

F-ACC

F-WP#

F-CE#

OE#

WE#

AVD#

CLK

ACC

WP#

CE#

OE#

WE#

AVD#

CLK

RDY/

RDY

WAIT

NS

AD15-AD0

Amax-A16

OE#

WE#

AVD#

CLK

WAIT

pSRAM

R-CE#

R-CRE

CE#

CRE

AD15-AD0

R-UB#

R-LB#

UB#

LB#

Amax-A16

Note: The CLK and WAIT signals on the pSRAM are not present on the pSRAM Type 2; therefore, for those

MCP's, those signals will only be connected to the NS flash, but not to the pSRAM. Also, on this pSRAM,

the CRE signal will not be present at all.

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S71NS-N MCP Products

S71NS-N_00_A3 October 10, 2006

A d v a n c e I n f o r m a t i o n

4 Connection Diagrams/Physical Dimensions

This section contains the I/O designations and package specifications for the S71NS-N.

4.1

Special Handling Instructions for FBGA Packages

Special handling is required for Flash Memory products in FBGA packages.

Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning meth-

ods. The package and/or data integrity may be compromised if the package body is exposed to

temperatures above 150°C for prolonged periods of time.

4.2 Connection Diagrams

4.2.1

pSRAM Based Pinout, 56-Ball, VFBGA

56-ball Fine-Pitch Ball Grid Array

pSRAM-Based Pinout

Legend

(Top View, Balls Facing Down)

No Connect

(Distance between

outer NC balls

is 2x pitch)

A1

NC

A14

NC

C3

NC

C4

C7

C8

C11

RFU

C12

NC

Reserved for

Future Use

RFU

R-LB#

R-UB#

D3

D4

D5

D6

D7

D8

D9

D10

A19

D11

A17

D12

Flash/RAM

Shared Only

F-RDY/

R-WAIT

A21

V_SS

CLK

V_CC

WE#

F-ACC

A22

E3

E4

E5

E6

E7

E8

E9

E10

A18

E11

E12

Flash Only

RAM Only

V_CCQ

A16

A20

AVD#

DNU

F-RST# F-WP#

F-CE#

V_SSQ

F3

F4

F5

F6

F7

F8

F9

F10

F11

F12

V_SS

A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8

OE#

G3

G4

G5

G6

G7

G8

G9

G10

G11

G12

A/DQ14

A/DQ15

V_SSQ

A/DQ10 V_CCQ

A/DQ1 A/DQ0

A/DQ11

A/DQ5 A/DQ4

H3

NC

H4

H7

H8

H11

RFU

H12

NC

RFU

R-CE#

R-CRE

K3

NC

K14

NC

Notes:

1. Addresses are shared between Flash and RAM depending on the density of the pSRAM.

2. CLK and WAIT signals are Flash only for the S71NS064NA0-RT, while on that MCP, the CRE signal won't exist.

MCP

Flash-Only Addresses

A22

Shared Addresses

A21-A16

Shared ADQ Pins

ADQ15 – ADQ0

S71NS128NC0

S71NS128NB0

S71NS128NA0

S71NS064NA0

A22-A21

A20-A16

A22-A20

A19-A16

A21-A20

A19-A16

Figure 4.1 pSRAM Based Pinout, 56-Ball, VFBGA

October 10, 2006 S71NS-N_00_A3

S71NS-N MCP Products

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A d v a n c e I n f o r m a t i o n

4.2.2

pSRAM Based Pinout, 60-Ball, VFBGA

A1

NC

A18

NC

Legend

No Connect

(Distance between

outer NC balls

is 2x pitch)

C3

NC

C16

NC

E5

E6

E9

E10

E13

RFU

E14

NC

Reserved for

Future Use

NC

RFU

R-LB#

R-UB#

F5

F6

F7

F8

F9

F10

F11

F12

A19

F13

A17

F14

A22

Flash/RAM

Shared Only

F-RDY/

R-WAIT

A21

V_SS

CLK

V_CC

WE#

F-ACC

G5

G6

G7

G8

G9

G10

G11

G12

A18

G13

G14

V_CCQ

A16

A20

AVD#

A23

F-RST# F-WP#

F-CE#

V_SSQ

Flash Only

RAM Only

H5

H6

H7

H8

H9

H10

H11

H12

H13

H14

V_SS

A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8

OE#

J5

J6

J7

J8

J9

J10

J11

J12

J13

J14

A/DQ14

A/DQ15

V_SSQ

A/DQ10 V_CCQ

A/DQ1 A/DQ0

A/DQ11

A/DQ5 A/DQ4

K5

NC

K6

K9

K10

K13

RFU

K14

NC

RFU

R-CE#

R-CRE

M3

NC

M16

NC

P1

P18

NC

Note: Addresses are shared between Flash and RAM depending on the density of the pSRAM.

MCP

Flash-Only Addresses

A23-A22

Shared Addresses

A21–A16

Shared ADQ Pins

ADQ15 – ADQ0

S71NS256NC0

S71NS256NB0

A23-A21

A20-A16

Figure 4.2 pSRAM Based Pinout, 60-Ball, VFBGA

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S71NS-N MCP Products

S71NS-N_00_A3 October 10, 2006

A d v a n c e I n f o r m a t i o n

4.2.3

Look Ahead Connection Diagram

112-ball x16 MUX NOR Flash + x16 MUX pSRAM on Shared Bus and x16 NAND

Interface ORNAND on Bus 2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

NC

Legend

A

B

C

D

E

F

NC

NOR Flash/pSRAM

Shared Only

No Connect

Do Not Use

NC

DNU

N-IO7 N-IO15

NOR Flash 1 Only

pSRAM Only

DNU N-RDY N2-CE# F2-CE#

R-LB# R-UB#

N-IO5 N-IO13 N-IO6 N-IO14

N1-CE# N-RE# F-RDY/

R-WAIT

A21

A16

VSS

A20

CLK

VCC

WE# F-ACC

A19

A17

A22

N-IO4 N-IO12

G

ORNAND Flash Only

NOR Flash 2 Only

N-VCC N-VCC VCCQ

AVD#

A23 F-RST# F-WP#

A18 F1-CE# VSSQ N-IO11 N-PRE

H

J

N-VSS N-VSS

VSS

A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8

OE#

VCC

VSS

NOR Flash Shared Only

N-CLE N-ALE A/DQ15 A/DQ14 VSSQ A/DQ5 A/DQ4 A/DQ11 A/DQ10 VCCQ A/DQ1 A/DQ0 N-IO18 N-IO3

K

L

DNU N-WE# N-WP#

A24

R-CE# R-CRE

VSS

N-IO1 N-IO9 N-IO2

NC

DNU

NC

DNU

N-IO0 N-IO8

NC

M

N

NC

P

Figure 4.3 Look Ahead Connection Diagram

112-ball x16 MUX NOR Flash + x16 MUX pSRAM on Shared Bus and x16 NAND Interface

ORNAND on Bus 2

October 10, 2006 S71NS-N_00_A3

S71NS-N MCP Products

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A d v a n c e I n f o r m a t i o n

4.3 Physical Dimensions

4.3.1

NLB056—9.2 x 8.0 mm, 56-ball VFBGA

D1

A

D

eD

0.10

(2X)

C

14

13

12

11

10

9

SE

7

8

7

6

5

E

E1

eE

4

3

2

1

K

J H G F E D C B A

INDEX MARK

9

PIN A1

CORNER

PIN A1

CORNER

B

7

SD

0.10

(2X)

C

TOP VIEW

BOTTOM VIEW

0.20

0.08

C

A2

A

A1

C

SIDE VIEW

6

56X

b

0.15

0.08

M

C

A

B

NOTES:

1. DIMENSIONING AND TOLERANCING METHODS PER

ASME Y14.5M-1994.

PACKAGE

JEDEC

NLB 056

N/A

2. ALL DIMENSIONS ARE IN MILLIMETERS.

D x E

9.20 mm x 8.00 mm

PACKAGE

3. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3,

SPP-010.

SYMBOL

MIN

NOM

---

MAX

NOTE

4.

e REPRESENTS THE SOLDER BALL GRID PITCH.

A

A1

---

1.20

---

PROFILE

5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"

DIRECTION.

0.20

0.85

---

BALL HEIGHT

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE

"E" DIRECTION.

A2

---

0.97

BODY THICKNESS

BODY SIZE

D

9.20 BSC.

8.00 BSC.

4.50 BSC.

6.50 BSC.

10

n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS

FOR MATRIX SIZE MD X ME.

E

BODY SIZE

D1

E1

MATRIX FOOTPRINT

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

AND B AND DEFINE THE POSITION OF THE CENTER SOLDER

BALL IN THE OUTER ROW.

MD

ME

n

MATRIX SIZE D DIRECTION

MATRIX SIZE E DIRECTION

BALL COUNT

14

56

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE

OUTER ROW SD OR SE = 0.000.

Øb

eE

0.25

0.30

0.35

BALL DIAMETER

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE

OUTER ROW, SD OR SE = e/2

0.50 BSC.

0.50 BSC

BALL PITCH

eD

SD / SE

BALL PITCH

8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

0.25 BSC.

SOLDER BALL PLACEMENT

A2 ~ A13,B1 ~ B14

DEPOPULATED SOLDER BALLS

9

A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

C1,C2,C5,C6,C9,C10,C13,C14

D1,D2,D13,D14,E1,E2,E13,E14,F1,F2,F13,F14

G1,G2,G13,G14,H1,H2,H5,H6,H9,H10,H13,H14

J1 ~ J14, K2 ~ K13

10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.

3507\ 16-038.22 \ 7.14.5

Figure 4.4 Physical Dimensions, NLB056—56-ball VFBGA

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S71NS-N MCP Products

S71NS-N_00_A3 October 10, 2006

A d v a n c e I n f o r m a t i o n

4.3.1

NLA060—11.0 x 10.0 mm, 60-ball VFBGA

A

D1

D

eD

0.15

(2X)

C

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

SE

7

E

B

E1

eE

P

N M L

K

J

H G F E D C B A

INDEX MARK

9

PIN A1

CORNER

PIN A1

CORNER

7

SD

0.15

(2X)

C

TOP VIEW

BOTTOM VIEW

0.20

C

A2

A

A1

0.08

C

SIDE VIEW

6

60X

0.15

0.08

b

M

C

A B

M

NOTES:

PACKAGE

JEDEC

NLA 060

N/A

1. DIMENSIONING AND TOLERANCING METHODS PER

ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

D x E

10.95 mm x 9.95 mm

PACKAGE

3. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3,

SPP-010.

SYMBOL

MIN

---

NOM

---

MAX

1.20

---

NOTE

4.

e REPRESENTS THE SOLDER BALL GRID PITCH.

A

A1

PROFILE

5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"

DIRECTION.

0.20

0.85

---

BALL HEIGHT

A2

---

0.97

BODY THICKNESS

BODY SIZE

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE

"E" DIRECTION.

D

10.95 BSC.

9.95 BSC.

6.50 BSC.

8.50 BSC.

14

E

BODY SIZE

n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS

FOR MATRIX SIZE MD X ME.

D1

E1

MATRIX FOOTPRINT

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

MD

ME

n

MATRIX SIZE D DIRECTION

MATRIX SIZE E DIRECTION

BALL COUNT

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

AND B AND DEFINE THE POSITION OF THE CENTER SOLDER

BALL IN THE OUTER ROW.

18

60

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE

OUTER ROW SD OR SE = 0.000.

Øb

eE

0.25

0.30

0.35

BALL DIAMETER

0.50 BSC.

0.50 BSC

0.25 BSC.

BALL PITCH

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE

OUTER ROW, SD OR SE = e/2

eD

SD / SE

BALL PITCH

SOLDER BALL PLACEMENT

DEPOPULATED SOLDER BALLS

8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

A2~A17,B1~B18,C1,C2,C4~C15,C17,C18

D1~D18,E1,E2,E3,E4,E7,E8,E11,E12,E15,E16,E17,E18

F1,F2,F3,F4,F15,F16,F17,F18,G1,G2,G3,G4,G15,G16,G17,G18

H1,H2,H3,H4,H15,H16,H17,H18,J1,J2,J3,J4,J15,J16,J17,J18

K1,K2,K3,K4,K7,K8,K11,K12,K15,K16,K17,K18

9. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

L1 ~L18,M1,M2,M4~M15,M17,M18,N1~N18,P2~P17

10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.

3483 \ 16-038.22 \ 3.11.5

Figure 4.5 Physical Dimensions, NLA060—60-ball VFBGA

October 10, 2006 S71NS-N_00_A3

S71NS-N MCP Products

9

A d v a n c e I n f o r m a t i o n

5 Revisions

Revision A0 (January 3, 2006)

Initial Release under Publication Identification Number S71NS128NC0_01

Revision A1 (March 1, 2006)

Changed the Publication Identification Number from S71NS128NC0_01 to S71NS-N_00

Added the MCP S71NS064NA0

Revision A2 (June 13, 2006)

Corrected the grid reference for 56-ball connection diagram

Revision A3 (October 10, 2006)

Added the S71NS064NA0-RT - the one using pSRAM Type 2

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary

industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that

includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal

injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,

medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and

artificial satellite). Please note that Spansion Inc. will not be liable to you and/or any third party for any claims or damages arising in connection with above-

mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such

failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels

and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on ex-

port under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the

prior authorization by the respective government entity will be required for export of those products.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a Spansion Inc. product under development

by Spansion Inc. Spansion Inc. reserves the right to change or discontinue work on any product without notice. The information in this document is provided

as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement

of third-party rights, or any other warranty, express, implied, or statutory. Spansion Inc. assumes no liability for any damages of any kind arising out of the

use of the information in this document.

of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.

10

S71NS-N MCP Products

S71NS-N_00_A3 October 10, 2006


型号：	S71NS064NA0BJWVN3
厂家：	SPANSION
描述：	MirrorBit 1.8 Volt-only Simultaneous Read/Write, Burst-mode Multiplexed Flash Memory 的MirrorBit 1.8伏特，只有同步读/写，突发模式复用闪存闪存
文件：	总12页 (文件大小：352K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S71NS064NA0BJWVN3 [SPANSION]

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