S71AL016D02BFWTF2 [SPANSION]
Stacked Multi-Chip Product (MCP) Flash Memory and RAM; 堆叠式多芯片产品（ MCP ）闪存和RAM
| 型号： | S71AL016D02BFWTF2 |
| 厂家： | 
SPANSION |
| 描述： | Stacked Multi-Chip Product (MCP) Flash Memory and RAM |
| 文件： | 总76页 (文件大小：1444K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S71AL016D based MCPs
Stacked Multi-Chip Product (MCP) Flash Memory and
RAM
16 Megabit (1 M x 16-bit) CMOS 3.0 Volt-only
Flash Memory and 2 Megabit (128K x 16-bit) Static RAM/
Pseudo Static RAM
ADVANCE
INFORMATION
Distinctive Characteristics
Packages
— 7 x 9 x 1.2 mm 56 ball FBGA
MCP Features
Power supply voltage of 2.7 to 3.1 volt
Operating Temperature
High performance
— –25°C to +85°C (Wireless)
— 70 ns
General Description
The S71AL series is a product line of stacked Multi-Chip Product (MCP) packages
and consists of:
One S29AL Flash memory die
pSRAM or SRAM
The products covered by this document are listed in the table below:
Flash Memory Density
16Mb
SRAM Density
2Mb
S71AL016D02
Publication Number S71AL016D_02_04_00 Revision A Amendment 1 Issue Date November 11, 2004
P r e l i m i n a r y
Product Selector Guide
16 Mb Flash Memory
Device-Model#
S71AL016D02-TF
S71AL016D02-BF
S71AL016D02-T7
S71AL016D02-B7
Flash Access time (ns)
SRAM density
2 M SRAM
2 M SRAM
2 M SRAM
2 M SRAM
(p)SRAM Access time (ns) SRAM type
Package
TLC056
TLC056
TLC056
TLC056
70
70
70
70
70
70
70
70
SRAM2
SRAM2
SRAM1
SRAM1
2
S71AL016D based MCPs
S71AL016D_02_04_00_A1 November 11, 2004
A d v a n c e I n f o r m a t i o n
TABLE OF CONTENTS
Write Operation Status . . . . . . . . . . . . . . . . . . . . 34
S71AL016D based MCPs
DQ7: Data# Polling ............................................................................................34
Figure 5. Data# Polling Algorithm........................................ 35
RY/BY#: Ready/Busy# ....................................................................................... 35
DQ6: Toggle Bit I ............................................................................................... 36
DQ2: Toggle Bit II .............................................................................................. 36
Reading Toggle Bits DQ6/DQ2 ..................................................................... 37
Figure 6. Toggle Bit Algorithm............................................. 38
DQ5: Exceeded Timing Limits ........................................................................38
DQ3: Sector Erase Timer ................................................................................ 39
Table 10. Write Operation Status ......................................... 39
Figure 7. Maximum Negative Overshoot Waveform ................ 40
Figure 8. Maximum Positive Overshoot Waveform.................. 40
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1
MCP Features ........................................................................................................ 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .2
16 Mb Flash Memory .............................................................................................2
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .6
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .8
Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . .9
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 10
TLC056—56-ball Fine-Pitch Ball Grid Array (FBGA)
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 9. ICC1 Current vs. Time (Showing Active and
9 x 7 mm Package ...............................................................................................10
Automatic Sleep Currents).................................................. 42
Figure 10. Typical ICC1 vs. Frequency................................... 43
Figure 11. Test Setup......................................................... 44
Table 11. Test Specifications ............................................... 44
Figure 12. Input Waveforms and Measurement Levels............ 45
Read Operations .................................................................................................46
Figure 13. Read Operations Timings..................................... 46
Hardware Reset (RESET#) ..............................................................................47
Figure 14. RESET# Timings................................................. 47
Word/Byte Configuration (BYTE#) ...........................................................48
Figure 15. BYTE# Timings for Read Operations...................... 48
Figure 16. BYTE# Timings for Write Operations ..................... 49
Erase/Program Operations ..............................................................................50
Figure 17. Program Operation Timings ................................. 51
Figure 18. Chip/Sector Erase Operation Timings .................... 52
Figure 19. Data# Polling Timings (During Embedded Algorithms)..
53
S29AL016D
General Description 12
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 1. S29AL016D Device Bus Operations .......................... 15
Word/Byte Configuration .................................................................................15
Requirements for Reading Array Data ..........................................................15
Writing Commands/Command Sequences ................................................. 16
Program and Erase Operation Status ........................................................... 16
Standby Mode ....................................................................................................... 16
Automatic Sleep Mode .......................................................................................17
RESET#: Hardware Reset Pin ..........................................................................17
Output Disable Mode .........................................................................................17
Table 2. Sector Address Tables (Top Boot Device) ................. 18
Table 3. Sector Address Tables (Bottom Boot Device) ............ 19
Autoselect Mode ................................................................................................20
Table 4. S29AL016D Autoselect Codes (High Voltage Method) . 20
Sector Protection/Unprotection ...................................................................20
Temporary Sector Unprotect ......................................................................... 21
Figure 1. Temporary Sector Unprotect Operation.................... 21
Figure 2. In-System Sector Protect/Unprotect Algorithms........ 22
Figure 20. Toggle Bit Timings (During Embedded Algorithms).. 53
Figure 21. DQ2 vs. DQ6 for Erase and Erase Suspend Operations .
54
Figure 22. Temporary Sector Unprotect/Timing Diagram......... 54
Figure 23. Sector Protect/Unprotect Timing Diagram.............. 55
Figure 24. Alternate CE# Controlled Write Operation Timings.. 57
TSOP and BGA Pin Capacitance . . . . . . . . . . . . 58
Common Flash Memory Interface (CFI) . . . . . . .23
Table 5. CFI Query Identification String ................................ 23
Table 6. System Interface String ......................................... 24
Table 7. Device Geometry Definition .................................... 24
Table 8. Primary Vendor-Specific Extended Query ................. 25
Hardware Data Protection ..............................................................................25
2Mbit Type 1 SRAM
Common Features . . . . . . . . . . . . . . . . . . . . . . . . 59
Functional Description . . . . . . . . . . . . . . . . . . . . . 60
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
These parameters are verified in device
Low V Write Inhibit ..................................................................................25
CC
Write Pulse “Glitch” Protection ................................................................25
Logical Inhibit .................................................................................................. 26
Power-Up Write Inhibit ............................................................................... 26
Reading Array Data ............................................................................................27
Reset Command ..................................................................................................27
Autoselect Command Sequence ....................................................................27
Word/Byte Program Command Sequence ................................................28
Unlock Bypass Command Sequence ........................................................ 28
Figure 3. Program Operation................................................ 29
Chip Erase Command Sequence ................................................................... 29
Sector Erase Command Sequence ................................................................ 30
Erase Suspend/Erase Resume Commands ....................................................31
Figure 4. Erase Operation.................................................... 32
Command Definitions ........................................................................................33
Table 9. S29AL016D Command Definitions ........................... 33
characterization and are not 100% tested. . . . . . 60
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 60
Operating Characteristics (Over Specified
Temperature Range) . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 1. Power Savings with Page Mode (WE# = VIH) ........... 62
Timing Test Conditions . . . . . . . . . . . . . . . . . . . . 62
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 2. Timing of Read Cycle (CE# = OE# = VIL, WE# = CE2=
VIH)................................................................................. 64
Figure 3. Timing Waveform of Read Cycle (WE# = VIH).......... 64
Figure 4. Timing Waveform of Write Cycle (WE# Control) ....... 65
Figure 5. Timing Waveform of Write Cycle (CE1# Control) ...... 65
November 11, 2004 S71AL016D_02_04_00_A1
3
A d v a n c e I n f o r m a t i o n
Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . 71
2Mbit Type 2 SRAM
Figure 3. Read Cycle 1 (Address Transition Controlled)........... 71
Figure 4. Read Cycle 2 (OE# Controlled)............................... 71
Figure 5. Write Cycle 1 (WE# Controlled).............................. 72
Figure 6. Write Cycle 2 (CE# Controlled) .............................. 73
Figure 7. Write Cycle 3 (WE# Controlled, OE# LOW).............. 73
Figure 8. Write Cycle 4 (BHE#/BLE# Controlled, OE# Low)..... 74
Common Features . . . . . . . . . . . . . . . . . . . . . . . . 66
Functional Description . . . . . . . . . . . . . . . . . . . . . 66
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . 66
Operating Range ..................................................................................................67
Product Portfolio ................................................................................................67
Electrical Characteristics ..................................................................................67
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
AC Test Loads and Waveforms . . . . . . . . . . . . . 68
Figure 1. AC Test Loads and Waveforms................................ 68
Data Retention Characteristics (Over the
Typical DC and AC Parameters . . . . . . . . . . . . . 74
Figure 9. Operating Current vs. Supply Voltage ..................... 74
Figure 10. Standby Current vs. Supply Voltage...................... 74
Figure 11. Access Time vs. Supply Voltage............................ 75
Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 1. Truth Table ........................................................... 75
Operation Range) . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 2. Data Retention Waveform...................................... 69
Switching Characteristics . . . . . . . . . . . . . . . . . . 70
Revision Summary
4
S71AL016D_02_04_00_A1 November 11, 2004
P r e l i m i n a r y
MCP Block Diagram
VCC
f
VCC
CE#f
RST#f
Flash 1
A19-A0
Shared Address
OE#
WE#
RY/BY#
DQ15 to DQ0
VCCS
VCC
A16-A0
pSRAM/SRAM
IO15-IO0
CE1#s
UB#
CE1#
UB#
LB#
LB#
CE2s
CE2
November 11, 2004 S71AL016D_02_04_00_A1
5
P r e l i m i n a r y
Connection Diagram
56-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
Legend
A2
A7
A3
LB#
B3
A4
RFU
B4
A5
WE#
B5
A6
A8
A7
A11
B7
B1
A3
B2
B6
B8
A15
C8
Flash only
RAM only
A6
UB#
C3
RST#f
C4
CE2s
C5
A19
C6
A12
C7
C1
C2
A2
A5
A18
D3
RY/BY#
RFU
A9
A13
D7
RFU
D8
D1
D2
D6
A1
A4
A17
E3
A10
E6
A14
E7
RFU
E8
Reserved for
Future Use
E1
E2
A0
VSS
F2
DQ1
F3
DQ6
F6
RFU
F7
A16
F8
F1
F4
DQ3
G4
F5
DQ4
G5
CE1#f
G1
OE#
G2
DQ0
H2
DQ9
G3
DQ13
G6
DQ15
G7
RFU
G8
CE1#s
DQ10
H3
VCCf
H4
VCCs
H5
DQ12
H6
DQ7
H7
VSS
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
MCP
Flash Only Address
Shared Addresses
A16-A0
S71AL016D02
A19-A17
6
S71AL016D_02_04_00_A1 November 11, 2004
P r e l i m i n a r y
Pin Description
A –A
=
=
=
=
=
=
=
=
=
=
=
=
=
17 Address Inputs (Common)
3 Address Inputs (Flash)
16 Data Inputs/Outputs (Common)
Chip Enable 1 (Flash)
Chip Enable 1 (SRAM)
Chip Enable 2 (SRAM)
Output Enable (Common)
Write Enable (Common)
Ready/Busy Output (Flash)
Upper Byte Control (SRAM)
Lower Byte Control (SRAM)
Hardware Reset Pin, Active Low (Flash)
Flash 3.0 volt-only single power supply (see Product
Selector Guide for speed options and voltage supply
tolerances)
16
0
A –A
19
17
DQ –DQ
15
0
CE1#f
CE1#s
CE2s
OE#
WE#
RY/BY#
UB#
LB#
RST#f
V
f
CC
V
V
NC
s
=
=
=
=
pSRAM Power Supply
CC
Device Ground (Common)
Pin Not Connected Internally
Reserved for Future Use
SS
RFU
Logic Symbol
20
A19–A0
16
DQ15–DQ0
CE#
CE1#s
CE2s
RY/BY#
OE#
WE#
RST#f
UB#
LB#
November 11, 2004 S71AL016D_02_04_00_A1
7
P r e l i m i n a r y
Ordering Information
The order number is formed by a valid combinations of the following:
S71AL
016
D
02 BA
W
T
F
0
PACKING TYPE
0
2
3
=
=
=
Tray
7” Tape and Reel
13” Tape and Reel
MODEL NUMBER
See the Valid Combinations table.
BOOT TYPE
T
B
=
=
Top Boot
Bottom Boot
TEMPERATURE RANGE
Wireless (-25 C to +85°C)
W
=
°
PACKAGE TYPE
BA
BF
=
=
Fine-pitch BGA Lead (Pb)-free compliant package
Fine-pitch BGA Lead (Pb)-free package
SRAM DENSITY
02 2Mb SRAM
=
PROCESS TECHNOLOGY
200 nm, Floating Gate Technology
D
=
FLASH DENSITY
016 16Mb
=
PRODUCT FAMILY
S71AL Multi-chip Product (MCP)
3.0-volt Flash Memory and RAM
8
S71AL016D_02_04_00_A1 November 11, 2004
P r e l i m i n a r y
Valid Combinations
S71AL016D Valid Combinations
(p)SRAM
Type/Access
Time (ns)
Base Ordering
Part Number
Package &
Package Modifier/
Model Number
Speed Options
(ns)
Package
Marking
Temperature
Packing Type
S71AL016D02
S71AL016D02
S71AL016D02
S71AL016D02
TF
BF
T7
B7
SRAM2/ 70
SRAM2 / 70
SRAM1 / 70
SRAM1 / 70
(Note 2)
BAW
BFW
0, 2, 3 (Note 1)
70
Notes:
Valid Combinations
1. Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading “S” and packing type
designator from ordering part number.
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult your local sales office to confirm avail-
ability of specific valid combinations and to check on newly released
combinations.
November 11, 2004 S71AL016D_02_04_00_A1
9
P r e l i m i n a r y
Physical Dimensions
TLC056—56-ball Fine-Pitch Ball Grid Array (FBGA)
9 x 7 mm Package
A
D1
D
eD
0.15
(2X)
C
8
7
6
5
4
3
2
1
SE
7
E
B
E1
eE
H
G
F
E
D
C
B
A
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
0.08
C
C
A2
A
C
A1
SIDE VIEW
6
56X
b
0.15
M
C
C
A
B
0.08
M
NOTES:
PACKAGE
JEDEC
TLC 056
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
9.00 mm x 7.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
1.20
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.20
0.81
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.97
BODY THICKNESS
BODY SIZE
D
9.00 BSC.
7.00 BSC.
5.60 BSC.
5.60 BSC.
8
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
8
56
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
φb
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eE
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
A1,A8,D4,D5,E4,E5,H1,H8
DEPOPULATED SOLDER BALLS
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3348 \ 16-038.22a
10
S71AL016D_02_04_00_A1 November 11, 2004
S29AL016D
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory
ADVANCE
INFORMATION
Datasheet
Distinctive Characteristics
Architectural Advantages
Performance Characteristics
Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write op-
erations for battery-powered applications
High performance
— Access times as fast as 70 ns
Ultra low power consumption (typical values
at 5 MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 9 mA read current
Manufactured on 200nm process technology
— Fully compatible with 0.23 µm Am29LV160D and
MBM29LV160E devices
Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-
one 64 Kbyte sectors (byte mode)
— 20 mA program/erase current
Cycling endurance: 1,000,000 cycles per
sector typical
Data retention: 20 years typical
— One 8 Kword, two 4 Kword, one 16 Kword, and thirty-
one 32 Kword sectors (word mode)
Sector Protection features
Software Features
— A hardware method of locking a sector to prevent any
program or erase operations within that sector
— Sectors can be locked in-system or via programming
equipment
CFI (Common Flash Interface) compliant
— Provides device-specific information to the system,
allowing host software to easily reconfigure for
different Flash devices
— Temporary Sector Unprotect feature allows code
changes in previously locked sectors
Erase Suspend/Erase Resume
Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
— Suspends an erase operation to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation
Top or bottom boot block configurations
available
Data# Polling and toggle bits
— Provides a software method of detecting program or
erase operation completion
Compatibility with JEDEC standards
— Pinout and software compatible with single-power
supply Flash
Hardware Features
Ready/Busy# pin (RY/BY#)
— Superior inadvertent write protection
— Provides a hardware method of detecting program or
erase cycle completion
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading array
data
Publication Number S29AL016D_00 Revision A Amendment 1 Issue Date August 4, 2004
A d v a n c e I n f o r m a t i o n
General Description
The S29AL016D is a 16 Mbit, 3.0 Volt-only Flash memory organized as 2,097,152
bytes or 1,048,576 words. The device is offered in 48-ball FBGA, and 48-pin TSOP
packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8)
data appears on DQ7–DQ0. This device is designed to be programmed in-system
with the standard system 3.0 volt V
supply. A 12.0 V V or 5.0 V
are not
CC
PP
CC
required for write or erase operations. The device can also be programmed in
standard EPROM programmers.
The device offers access times of 70 ns and 90 ns allowing high speed micropro-
cessors to operate without wait states. To eliminate bus contention the device has
separate chip enable (CE#), write enable (WE#) and output enable (OE#)
controls.
The device requires only a single 3.0 volt power supply for both read and write
functions. Internally generated and regulated voltages are provided for the pro-
gram and erase operations.
The S29AL016D is entirely command set compatible with the JEDEC single-
power-supply Flash standard. Commands are written to the command regis-
ter using standard microprocessor write timings. Register contents serve as input
to an internal state-machine that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data needed for the programming
and erase operations. Reading data out of the device is similar to reading from
other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This
initiates the Embedded Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies proper cell margin. The
Unlock Bypass mode facilitates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates
the Embedded Erase algorithm—an internal algorithm that automatically pre-
programs the array (if it is not already programmed) before executing the erase
operation. During erase, the device automatically times the erase pulse widths
and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by
observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (tog-
gle) status bits. After a program or erase cycle has been completed, the device
is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low V detector that automat-
CC
ically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase operations in any combina-
tion of the sectors of memory. This can be achieved in-system or via
programming equipment.
The Erase Suspend/Erase Resume feature enables the user to put erase on
hold for any period of time to read data from, or program data to, any sector that
is not selected for erasure. True background erase can thus be achieved.
12
S29AL016D
S29AL016D_00_A1_E August 4, 2004
A d v a n c e I n f o r m a t i o n
The hardware RESET# pin terminates any operation in progress and resets the
internal state machine to reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also reset the device, enabling
the system microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses have been stable
for a specified amount of time, the device enters the automatic sleep mode.
The system can also place the device into the standby mode. Power consump-
tion is greatly reduced in both these modes.
Spansion’s Flash technology combines years of Flash memory manufacturing ex-
perience to produce the highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector simultaneously via
Fowler-Nordheim tunneling. The data is programmed using hot electron
injection.
August 4, 2004 S29AL016D_00_A1_E
S29AL016D
13
A d v a n c e I n f o r m a t i o n
Product Selector Guide
Family Part Number
S29AL016D
Speed Option
Voltage Range: VCC = 2.7–3.6 V
70
70
70
30
90
90
90
35
Max access time, ns (tACC
)
Max CE# access time, ns (tCE
)
Max OE# access time, ns (tOE
)
Note: See “AC Characteristics” for full specifications.
Block Diagram
DQ0–DQ15 (A-1)
RY/BY#
VCC
Sector Switches
VSS
Erase Voltage
Generator
Input/Output
RESET#
Buffers
State
Control
WE#
BYTE#
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
VCC Detector
Timer
Cell Matrix
X-Decoder
A0–A19
14
S29AL016D
S29AL016D_00_A1_E August 4, 2004
A d v a n c e I n f o r m a t i o n
Device Bus Operations
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is com-
posed of latches that store the commands, along with the address and data
information needed to execute the command. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the
function of the device. Table 1 lists the device bus operations, the inputs and con-
trol levels they require, and the resulting output. The following subsections
describe each of these operations in further detail.
Table 1. S29AL016D Device Bus Operations
DQ8–DQ15
BYTE#
= V
Addresses
(Note 1)
DQ0– BYTE#
Operation
CE# OE# WE# RESET#
DQ7
DOUT
DIN
= V
IH
IL
Read
Write
L
L
L
H
L
H
H
AIN
AIN
DOUT
DIN
DQ8–DQ14 = High-Z,
DQ15 = A-1
H
VCC
0.3 V
±
VCC ±
0.3 V
Standby
X
X
X
High-Z High-Z
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
X
X
High-Z High-Z
High-Z High-Z
High-Z
High-Z
X
Sector Address,
A6 = L, A1 = H,
A0 = L
Sector Protect (Note 2)
L
H
L
VID
DIN
X
X
Sector Address,
A6 = H, A1 = H,
A0 = L
Sector Unprotect (Note 2)
L
H
X
L
VID
VID
DIN
DIN
X
X
Temporary Sector
Unprotect
X
X
AIN
DIN
High-Z
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT
= Data Out
Notes:
1. Addresses are A19:A0 in word mode (BYTE# = VIH), A19:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the
“Sector Protection/Unprotection” section.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in
the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only
data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/
O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the
LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins
to V . CE# is the power control and selects the device. OE# is the output control
IL
August 4, 2004 S29AL016D_00_A1_E
S29AL016D
15
A d v a n c e I n f o r m a t i o n
and gates array data to the output pins. WE# should remain at V . The BYTE#
IH
pin determines whether the device outputs array data in words or bytes.
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No command is necessary in
this mode to obtain array data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs produce valid data on the
device data outputs. The device remains enabled for read access until the com-
mand register contents are altered.
See “Reading Array Data” for more information. Refer to the AC Read Operations
table for timing specifications and to Figure 13 for the timing diagram. I
in the
CC1
DC Characteristics table represents the active current specification for reading ar-
ray data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data
to the device and erasing sectors of memory), the system must drive WE# and
CE# to V , and OE# to V .
IL
IH
For program operations, the BYTE# pin determines whether the device accepts
program data in bytes or words. Refer to “Word/Byte Configuration” for more
information.
The device features an Unlock Bypass mode to facilitate faster programming.
Once the device enters the Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four. The “Word/Byte Program
Command Sequence” section has details on programming data to the device
using both standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device.
Tables 2 and 3 indicate the address space that each sector occupies. A “sector
address” consists of the address bits required to uniquely select a sector. The
“Command Definitions” section has details on erasing a sector or the entire chip,
or suspending/resuming the erase operation.
After the system writes the autoselect command sequence, the device enters the
autoselect mode. The system can then read autoselect codes from the internal
register (which is separate from the memory array) on DQ7–DQ0. Standard read
cycle timings apply in this mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
I
in the DC Characteristics table represents the active current specification for
CC2
the write mode. The “AC Characteristics” section contains timing specification ta-
bles and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may check the status of the
operation by reading the status bits on DQ7–DQ0. Standard read cycle timings
and I read specifications apply. Refer to “Write Operation Status” for more in-
CC
formation, and to “AC Characteristics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the device, it can place the device
in the standby mode. In this mode, current consumption is greatly reduced, and
16
S29AL016D
S29AL016D_00_A1_E August 4, 2004
A d v a n c e I n f o r m a t i o n
the outputs are placed in the high impedance state, independent of the OE#
input.
The device enters the CMOS standby mode when the CE# and RESET# pins are
both held at V ± 0.3 V. (Note that this is a more restricted voltage range than
CC
V .) If CE# and RESET# are held at V , but not within V ± 0.3 V, the device
IH
IH
CC
will be in the standby mode, but the standby current will be greater. The device
requires standard access time (t ) for read access when the device is in either
CE
of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
In the DC Characteristics table, I
specification.
and I
represents the standby current
CC4
CC3
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The de-
vice automatically enables this mode when addresses remain stable for t + 30
ACC
ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control
signals. Standard address access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and always available to the
system. I
in the DC Characteristics table represents the automatic sleep mode
CC4
current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the system drives the RESET# pin to V for at least a period of
IL
t , the device immediately terminates any operation in progress, tristates all
RP
data output pins, and ignores all read/write attempts for the duration of the RE-
SET# pulse. The device also resets the internal state machine to reading array
data. The operation that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at V ±0.3 V, the device draws CMOS standby current (I
). If RESET# is held
SS
CC4
at V but not within V ±0.3 V, the standby current will be greater.
IL
SS
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin re-
mains a “0” (busy) until the internal reset operation is complete, which requires
a time of t
(during Embedded Algorithms). The system can thus monitor RY/
READY
BY# to determine whether the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing (RY/BY# pin is “1”), the reset
operation is completed within a time of t
(not during Embedded Algorithms).
READY
The system can read data t
after the RESET# pin returns to V .
IH
RH
Refer to the AC Characteristics tables for RESET# parameters and to Figure 14
for the timing diagram.
Output Disable Mode
When the OE# input is at V , output from the device is disabled. The output pins
IH
are placed in the high impedance state.
August 4, 2004 S29AL016D_00_A1_E
S29AL016D
17
A d v a n c e I n f o r m a t i o n
Table 2. Sector Address Tables (Top Boot Device)
Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecimal)
Sector A19 A18 A17 A16 A15 A14 A13 A12
Byte Mode (x8)
000000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1F7FFF
1F8000–1F9FFF
1FA000–1FBFFF
1FC000–1FFFFF
Word Mode (x16)
00000–07FFF
08000–0FFFF
10000–17FFF
18000–1FFFF
20000–27FFF
28000–2FFFF
30000–37FFF
38000–3FFFF
40000–47FFF
48000–4FFFF
50000–57FFF
58000–5FFFF
60000–67FFF
68000–6FFFF
70000–77FFF
78000–7FFFF
80000–87FFF
88000–8FFFF
90000–97FFF
98000–9FFFF
A0000–A7FFF
A8000–AFFFF
B0000–B7FFF
B8000–BFFFF
C0000–C7FFF
C8000–CFFFF
D0000–D7FFF
D8000–DFFFF
E0000–E7FFF
E8000–EFFFF
F0000–F7FFF
F8000–FBFFF
FC000–FCFFF
FD000–FDFFF
FE000–FFFFF
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
X
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
32/16
8/4
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
8/4
16/8
Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See “Word/Byte Configuration” section.
18
S29AL016D
S29AL016D_00_A1_E August 4, 2004
A d v a n c e I n f o r m a t i o n
Table 3. Sector Address Tables (Bottom Boot Device)
Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecimal)
Sector A19 A18 A17 A16 A15 A14 A13 A12
Byte Mode (x8)
000000–003FFF
004000–005FFF
006000–007FFF
008000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1FFFFF
Word Mode (x16)
00000–01FFF
02000–02FFF
03000–03FFF
04000–07FFF
08000–0FFFF
10000–17FFF
18000–1FFFF
20000–27FFF
28000–2FFFF
30000–37FFF
38000–3FFFF
40000–47FFF
48000–4FFFF
50000–57FFF
58000–5FFFF
60000–67FFF
68000–6FFFF
70000–77FFF
78000–7FFFF
80000–87FFF
88000–8FFFF
90000–97FFF
98000–9FFFF
A0000–A7FFF
A8000–AFFFF
B0000–B7FFF
B8000–BFFFF
C0000–C7FFF
C8000–CFFFF
D0000–D7FFF
D8000–DFFFF
E0000–E7FFF
E8000–EFFFF
F0000–F7FFF
F8000–FFFFF
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
16/8
8/4
SA2
8/4
SA3
32/16
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
August 4, 2004 S29AL016D_00_A1_E
S29AL016D
19
A d v a n c e I n f o r m a t i o n
Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See the “Word/Byte Configuration” section.
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector
protection verification, through identifier codes output on DQ7–DQ0. This mode
is primarily intended for programming equipment to automatically match a device
to be programmed with its corresponding programming algorithm. However, the
autoselect codes can also be accessed in-system through the command register.
When using programming equipment, the autoselect mode requires V (11.5 V
ID
to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in
Table 4. In addition, when verifying sector protection, the sector address must
appear on the appropriate highest order address bits (see Tables 2 and 3). Table
4 shows the remaining address bits that are don’t care. When all necessary bits
have been set as required, the programming equipment may then read the cor-
responding identifier code on DQ7-DQ0.
To access the autoselect codes in-system, the host system can issue the autose-
lect command via the command register, as shown in Table 9. This method does
not require V . See “Command Definitions” for details on using the autoselect
ID
mode.
Table 4. S29AL016D Autoselect Codes (High Voltage Method)
A19 A11
to to
Mode CE# OE# WE# A12 A10 A9
A8
to
A7
A3
to
DQ8
to
DQ7
to
DQ0
Description
A6
A2 A1 A0 DQ15
Manufacturer ID
:
Spansion
Word
L
L
L
L
H
H
X
X
VID
X
L
L
L
L
X
01h
C4h
Device ID:
S29AL016D
(Top Boot Block)
22h
X
X
VID
X
L
L
L
L
H
Byte
L
L
L
L
H
H
X
C4h
49h
Device ID:
S29AL016D
(Bottom Boot
Block)
Word
22h
X
X
X
VID
X
X
L
L
L
H
L
Byte
L
L
H
X
49h
01h
(protected)
X
X
Sector Protection Verification
L
L
H
SA
VID
L
H
00h
(unprotected)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Note: The autoselect codes may also be accessed in-system via command sequences. See Table 9.
Sector Protection/Unprotection
The hardware sector protection feature disables both program and erase opera-
tions in any sector. The hardware sector unprotection feature re-enables both
program and erase operations in previously protected sectors.
The device is shipped with all sectors unprotected. Spansion offers the option of
programming and protecting sectors at its factory prior to shipping the device
through Spansion’s ExpressFlash™ Service. Contact a Spansion representative
for details.
20
S29AL016D
S29AL016D_00_A1_E August 4, 2004
A d v a n c e I n f o r m a t i o n
It is possible to determine whether a sector is protected or unprotected. See “Au-
toselect Mode” for details.
Sector protection/unprotection can be implemented via two methods.
The primary method requires V on the RESET# pin only, and can be imple-
ID
mented either in-system or via programming equipment. Figure 2 shows the
algorithms and Figure 23 shows the timing diagram. This method uses standard
microprocessor bus cycle timing. For sector unprotect, all unprotected sectors
must first be protected prior to the first sector unprotect write cycle.
The alternate method intended only for programming equipment requires V on
ID
address pin A9 and OE#. This method is compatible with programmer routines
written for earlier 3.0 volt-only Spansion flash devices. Details on this method are
provided in a supplement, publication number 21468. Contact a Spansion repre-
sentative to request a copy.
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to
change data in-system. The Sector Unprotect mode is activated by setting the
RESET# pin to V . During this mode, formerly protected sectors can be pro-
ID
grammed or erased by selecting the sector addresses. Once V is removed from
ID
the RESET# pin, all the previously protected sectors are protected again. shows
the algorithm, and Figure 22 shows the timing diagrams, for this feature.
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
Figure 1. Temporary Sector Unprotect Operation
August 4, 2004 S29AL016D_00_A1_E
S29AL016D
21
A d v a n c e I n f o r m a t i o n
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
PLSCNT = 1
PLSCNT = 1
RESET# = VID
RESET# = VID
unprotected sectors
prior to issuing the
first sector
Wait 4 µs
Wait 4 µs
unprotect address
No
No
First Write
Cycle = 60h?
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A7-A0 =
Yes
Set up first sector
address
00000010
Sector Unprotect:
Wait 100 µs
Write 60h to sector
address with
A7-A0 =
Verify Sector
Protect: Write 40h
to sector address
with A7-A0 =
01000010
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 1.2 ms
00000010
Verify Sector
Unprotect: Write
40h to sector
address with
A7-A0 =
Read from
sector address
with A7-A0 =
00000010
Increment
PLSCNT
No
00000010
No
PLSCNT
= 25?
Read from
sector address
with A7-A0 =
00000010
Data = 01h?
Yes
No
Yes
Set up
next sector
address
Yes
Remove VID
from RESET#
No
PLSCNT
= 1000?
Protect another
sector?
Data = 00h?
Yes
No
Write reset
command
Yes
Remove VID
from RESET#
Remove VID
from RESET#
No
Last sector
verified?
Sector Protect
complete
Write reset
command
Yes
Write reset
command
Remove VID
from RESET#
Device failed
Sector Protect
complete
Sector Unprotect
complete
Write reset
command
Sector Protect
Algorithm
Device failed
Sector Unprotect
complete
Sector Unprotect
Algorithm
Figure 2. In-System Sector Protect/Unprotect Algorithms
22
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A d v a n c e I n f o r m a t i o n
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system
software interrogation handshake, which allows specific vendor-specified soft-
ware algorithms to be used for entire families of devices. Software support can
then be device-independent, JEDEC ID-independent, and forward- and back-
ward-compatible for the specified flash device families. Flash vendors can
standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query
command, 98h, to address 55h in word mode (or address AAh in byte mode), any
time the device is ready to read array data. The system can read CFI information
at the addresses given in Tables 5–8. In word mode, the upper address bits (A7–
MSB) must be all zeros. To terminate reading CFI data, the system must write
the reset command.
The system can also write the CFI query command when the device is in the au-
toselect mode. The device enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 5–8. The system must write the reset
command to return the device to the autoselect mode.
For further information, please refer to the CFI Specification and CFI Publication
100, available via the World Wide Web at http://www.amd.com/products/nvd/
overview/cfi.html. Alternatively, contact a Spansion representative for copies of
these documents.
Table 5. CFI Query Identification String
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
August 4, 2004 S29AL016D_00_A1_E
S29AL016D
23
A d v a n c e I n f o r m a t i o n
Table 6. System Interface String
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Bh
1Ch
36h
38h
0027h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
0036h
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
0000h
0000h
0004h
0000h
000Ah
0000h
0005h
0000h
0004h
0000h
VPP Min. voltage (00h = no VPP pin present)
VPP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 7. Device Geometry Definition
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
27h
4Eh
0015h
Device Size = 2N byte
28h
29h
50h
52h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
54h
56h
0000h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
58h
0004h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
0000h
0000h
0040h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
62h
64h
66h
68h
0001h
0000h
0020h
0000h
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0080h
0000h
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
001Eh
0000h
0000h
0001h
24
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A d v a n c e I n f o r m a t i o n
Table 8. Primary Vendor-Specific Extended Query
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
86h
88h
0031h
0030h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock
0 = Required, 1 = Not Required
45h
46h
47h
48h
8Ah
8Ch
8Eh
90h
0000h
0002h
0001h
0001h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
49h
92h
0004h
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode
Simultaneous Operation
00 = Not Supported, 01 = Supported
4Ah
4Bh
4Ch
94h
96h
98h
0000h
0000h
0000h
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing
provides data protection against inadvertent writes (refer to Table 9 for command
definitions). In addition, the following hardware data protection measures pre-
vent accidental erasure or programming, which might otherwise be caused by
spurious system level signals during V power-up and power-down transitions,
CC
or from system noise.
Low V
Write Inhibit
CC
When V is less than V
, the device does not accept any write cycles. This pro-
LKO
CC
tects data during V power-up and power-down. The command register and all
CC
internal program/erase circuits are disabled, and the device resets. Subsequent
writes are ignored until V
is greater than V
. The system must provide the
CC
LKO
proper signals to the control pins to prevent unintentional writes when V
is
CC
greater than V
.
LKO
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write
cycle.
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A d v a n c e I n f o r m a t i o n
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V , CE# = V or WE# =
IL
IH
V . To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a
IH
logical one.
Power-Up Write Inhibit
If WE# = CE# = V and OE# = V during power up, the device does not accept
IL
IH
commands on the rising edge of WE#. The internal state machine is automatically
reset to reading array data on power-up.
26
S29AL016D
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A d v a n c e I n f o r m a t i o n
Command Definitions
Writing specific address and data commands or sequences into the command
register initiates device operations. Table 9 defines the valid register command
sequences. Writing incorrect address and data values or writing them in the
improper sequence resets the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens
later. All data is latched on the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the “AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data after device power-up. No
commands are required to retrieve data. The device is also ready to read array
data after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase
Suspend mode. The system can read array data using the standard read timings,
except that if it reads at an address within erase-suspended sectors, the device
outputs status data. After completing a programming operation in the Erase Sus-
pend mode, the system may once again read array data with the same exception.
See “Erase Suspend/Erase Resume Commands” for more information on this
mode.
The system must issue the reset command to re-enable the device for reading
array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Com-
mand” section, next.
See also “Requirements for Reading Array Data” in the “Device Bus Operations”
section for more information. The Read Operations table provides the read pa-
rameters, and Figure 13 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the device to reading array data.
Address bits are don’t care for this command.
The reset command may be written between the sequence cycles in an erase
command sequence before erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the sequence cycles in a program
command sequence before programming begins. This resets the device to read-
ing array data (also applies to programming in Erase Suspend mode). Once
programming begins, however, the device ignores reset commands until the op-
eration is complete.
The reset command may be written between the sequence cycles in an autoselect
command sequence. Once in the autoselect mode, the reset command must be
written to return to reading array data (also applies to autoselect during Erase
Suspend).
If DQ5 goes high during a program or erase operation, writing the reset command
returns the device to reading array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manu-
facturer and devices codes, and determine whether or not a sector is protected.
August 4, 2004 S29AL016D_00_A1_E
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A d v a n c e I n f o r m a t i o n
Table 9 shows the address and data requirements. This method is an alternative
to that shown in Table 4, which is intended for PROM programmers and requires
V
on address bit A9.
ID
The autoselect command sequence is initiated by writing two unlock cycles, fol-
lowed by the autoselect command. The device then enters the autoselect mode,
and the system may read at any address any number of times, without initiating
another command sequence.
A read cycle at address XX00h retrieves the manufacturer code. A read cycle at
address XX01h returns the device code. A read cycle containing a sector address
(SA) and the address 02h in word mode (or 04h in byte mode) returns 01h if that
sector is protected, or 00h if it is unprotected. Refer to Tables 2 and 3 for valid
sector addresses.
The system must write the reset command to exit the autoselect mode and return
to reading array data.
Word/Byte Program Command Sequence
The system may program the device by word or byte, depending on the state of
the BYTE# pin. Programming is a four-bus-cycle operation. The program com-
mand sequence is initiated by writing two unlock write cycles, followed by the
program set-up command. The program address and data are written next, which
in turn initiate the Embedded Program algorithm. The system is not required to
provide further controls or timings. The device automatically generates the pro-
gram pulses and verifies the programmed cell margin. Table 9 shows the address
and data requirements for the byte program command sequence.
When the Embedded Program algorithm is complete, the device then returns to
reading array data and addresses are no longer latched. The system can deter-
mine the status of the program operation by using DQ7, DQ6, or RY/BY#. See
“Write Operation Status” for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm
are ignored. Note that a hardware reset immediately terminates the program-
ming operation. The Byte Program command sequence should be reinitiated once
the device has reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries. A bit
cannot be programmed from a “0” back to a “1”. Attempting to do so may
halt the operation and set DQ5 to “1,” or cause the Data# Polling algorithm to
indicate the operation was successful. However, a succeeding read will show that
the data is still “0”. Only erase operations can convert a “0” to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes or words to the
device faster than using the standard program command sequence. The unlock
bypass command sequence is initiated by first writing two unlock cycles. This is
followed by a third write cycle containing the unlock bypass command, 20h. The
device then enters the unlock bypass mode. A two-cycle unlock bypass program
command sequence is all that is required to program in this mode. The first cycle
in this sequence contains the unlock bypass program command, A0h; the second
cycle contains the program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two unlock cycles required
in the standard program command sequence, resulting in faster total program-
ming time. Table 9 shows the requirements for the command sequence.
28
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A d v a n c e I n f o r m a t i o n
During the unlock bypass mode, only the Unlock Bypass Program and Unlock By-
pass Reset commands are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. The first cycle
must contain the data 90h; the second cycle the data 00h. Addresses are don’t
care for both cycles. The device then returns to reading array data.
Figure 3 illustrates the algorithm for the program operation. See the Erase/Pro-
gram Operations table in “AC Characteristics” for parameters, and to Figure 17
for timing diagrams.
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
No
Increment Address
Last Address?
Yes
Programming
Completed
NOTE: See Table 9 for program command sequence.
Figure 3. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is ini-
tiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does not require
the system to preprogram prior to erase. The Embedded Erase algorithm auto-
matically preprograms and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide any controls or tim-
ings during these operations. Table 9 shows the address and data requirements
for the chip erase command sequence.
August 4, 2004 S29AL016D_00_A1_E
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29
A d v a n c e I n f o r m a t i o n
Any commands written to the chip during the Embedded Erase algorithm are ig-
nored. Note that a hardware reset during the chip erase operation immediately
terminates the operation. The Chip Erase command sequence should be reiniti-
ated once the device has returned to reading array data, to ensure data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6,
DQ2, or RY/BY#. See “Write Operation Status” for information on these status
bits. When the Embedded Erase algorithm is complete, the device returns to
reading array data and addresses are no longer latched.
Figure 4 illustrates the algorithm for the erase operation. See the Erase/Program
Operations tables in “AC Characteristics” for parameters, and to Figure 18 for tim-
ing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is
initiated by writing two unlock cycles, followed by a set-up command. Two addi-
tional unlock write cycles are then followed by the address of the sector to be
erased, and the sector erase command. Table 9 shows the address and data re-
quirements for the sector erase command sequence.
The device does not require the system to preprogram the memory prior to erase.
The Embedded Erase algorithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 µs begins.
During the time-out period, additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector to all sectors. The
time between these additional cycles must be less than 50 µs, otherwise the last
address and command might not be accepted, and erasure may begin. It is rec-
ommended that processor interrupts be disabled during this time to ensure all
commands are accepted. The interrupts can be re-enabled after the last Sector
Erase command is written. If the time between additional sector erase commands
can be assumed to be less than 50 µs, the system need not monitor DQ3. Any
command other than Sector Erase or Erase Suspend during the time-out
period resets the device to reading array data. The system must rewrite the
command sequence and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed
out. (See the “DQ3: Sector Erase Timer” section.) The time-out begins from the
rising edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the Erase Suspend command is
valid. All other commands are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the operation. The Sector Erase
command sequence should be reinitiated once the device has returned to reading
array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the device returns to reading
array data and addresses are no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer to
“Write Operation Status” for information on these status bits.)
Figure 4 illustrates the algorithm for the erase operation. Refer to the Erase/Pro-
gram Operations tables in the “AC Characteristics” section for parameters, and to
Figure 18 for timing diagrams.
30
S29AL016D
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A d v a n c e I n f o r m a t i o n
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase oper-
ation and then read data from, or program data to, any sector not selected for
erasure. This command is valid only during the sector erase operation, including
the 50 µs time-out period during the sector erase command sequence. The Erase
Suspend command is ignored if written during the chip erase operation or Em-
bedded Program algorithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the time-out period and suspends
the erase operation. Addresses are “don’t-cares” when writing the Erase Suspend
command.
When the Erase Suspend command is written during a sector erase operation, the
device requires a maximum of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during the sector erase time-out,
the device immediately terminates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the system can read array data
from or program data to any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal read and write timings and
command definitions apply. Reading at any address within erase-suspended sec-
tors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and
DQ2 together, to determine if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these status bits.
After an erase-suspended program operation is complete, the system can once
again read array data within non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or DQ6 status bits, just as in
the standard program operation. See “Write Operation Status” for more
information.
The system may also write the autoselect command sequence when the device
is in the Erase Suspend mode. The device allows reading autoselect codes even
at addresses within erasing sectors, since the codes are not stored in the memory
array. When the device exits the autoselect mode, the device reverts to the Erase
Suspend mode, and is ready for another valid operation. See “Autoselect Com-
mand Sequence” for more information.
The system must write the Erase Resume command (address bits are “don’t
care”) to exit the erase suspend mode and continue the sector erase operation.
Further writes of the Resume command are ignored. Another Erase Suspend
command can be written after the device has resumed erasing.
August 4, 2004 S29AL016D_00_A1_E
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A d v a n c e I n f o r m a t i o n
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 9 for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 4. Erase Operation
32
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A d v a n c e I n f o r m a t i o n
Command Definitions
Table 9. S29AL016D Command Definitions
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Second
Third
Addr
Fourth
Data Addr Data
Fifth
Sixth
Addr Data Addr Data
Addr Data Addr Data
Read (Note 6)
Reset (Note 7)
1
1
RA
RD
F0
XXX
555
AAA
555
AAA
555
AAA
Word
2AA
555
2AA
555
2AA
555
555
AAA
555
AAA
555
AAA
4
4
4
AA
AA
AA
55
55
55
90
90
90
X00
01
Manufacturer ID
Byte
Word
Byte
Word
Byte
X01
X02
X01
X02
22C4
C4
Device ID,
Top Boot Block
2249
49
Device ID,
Bottom Boot Block
XX00
XX01
00
(SA)
X02
Word
Byte
555
AAA
2AA
555
555
AAA
Sector Protect Verify
(Note 9)
4
AA
55
90
(SA)
X04
01
Word
Byte
Word
Byte
Word
Byte
55
CFI Query (Note 10)
1
4
3
98
AA
AA
AA
555
AAA
555
AAA
XXX
XXX
555
AAA
555
AAA
XXX
XXX
2AA
555
2AA
555
PA
555
AAA
555
AAA
Program
55
55
A0
20
PA
PD
Unlock Bypass
Unlock Bypass Program (Note 11)
Unlock Bypass Reset (Note 12)
2
2
A0
90
PD
F0
XXX
2AA
555
2AA
555
Word
555
AAA
555
AAA
555
AAA
555
AAA
2AA
555
2AA
555
555
AAA
Chip Erase
6
6
AA
AA
55
55
80
80
AA
AA
55
55
10
30
Byte
Word
Byte
Sector Erase
SA
Erase Suspend (Note 13)
Erase Resume (Note 14)
1
1
B0
30
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever
happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19–A12 uniquely select any sector.
Note:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles.
4. Data bits DQ15–DQ8 are don’t cares for unlock and command cycles.
5. Address bits A19–A11 are don’t cares for unlock and command cycles, unless SA or PA required.
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device
is providing status data).
8. The fourth cycle of the autoselect command sequence is a read cycle.
9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more information.
10. Command is valid when device is ready to read array data or when device is in autoselect mode.
11. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
12. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. F0 is also
acceptable.
13. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase
Suspend command is valid only during a sector erase operation.
14. The Erase Resume command is valid only during the Erase Suspend mode.
August 4, 2004 S29AL016D_00_A1_E
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A d v a n c e I n f o r m a t i o n
Write Operation Status
The device provides several bits to determine the status of a write operation:
DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 10 and the following subsections
describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method
for determining whether a program or erase operation is complete or in progress.
These three bits are discussed first.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded
Algorithm is in progress or completed, or whether the device is in Erase Suspend.
Data# Polling is valid after the rising edge of the final WE# pulse in the program
or erase command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the com-
plement of the datum programmed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to DQ7. The system must
provide the program address to read valid status information on DQ7. If a pro-
gram address falls within a protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then the device returns to reading array data.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7.
When the Embedded Erase algorithm is complete, or if the device enters the
Erase Suspend mode, Data# Polling produces a “1” on DQ7. This is analogous to
the complement/true datum output described for the Embedded Program algo-
rithm: the erase function changes all the bits in a sector to “1”; prior to this, the
device outputs the “complement,” or “0.” The system must provide an address
within any of the sectors selected for erasure to read valid status information on
DQ7.
After an erase command sequence is written, if all sectors selected for erasing
are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the
device returns to reading array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
When the system detects DQ7 has changed from the complement to true data,
it can read valid data at DQ7–DQ0 on the following read cycles. This is because
DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is
asserted low. Figure 19, Data# Polling Timings (During Embedded Algorithms),
in the “AC Characteristics” section illustrates this.
Table 10 shows the outputs for Data# Polling on DQ7. Figure 6 shows the Data#
Polling algorithm.
34
S29AL016D
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A d v a n c e I n f o r m a t i o n
START
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within
any sector selected for erasure. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
Figure 5. Data# Polling Algorithm
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Em-
bedded Algorithm is in progress or complete. The RY/BY# status is valid after the
rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an
open-drain output, several RY/BY# pins can be tied together in parallel with a
pull-up resistor to V
.
CC
August 4, 2004 S29AL016D_00_A1_E
S29AL016D
35
A d v a n c e I n f o r m a t i o n
If the output is low (Busy), the device is actively erasing or programming. (This
includes programming in the Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during the Erase Suspend
mode), or is in the standby mode.
Table 10 shows the outputs for RY/BY#. Figures 13, 14, 17 and 18 shows RY/BY#
for read, reset, program, and erase operations, respectively.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm
is in progress or complete, or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is valid after the rising edge
of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cy-
cles to any address cause DQ6 to toggle. (The system may use either OE# or CE#
to control the read cycles.) When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing
are protected, DQ6 toggles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is ac-
tively erasing or is erase-suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6 toggles. When the device en-
ters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alter-
natively, the system can use DQ7 (see the subsection on “DQ7: Data# Polling”).
If a program address falls within a protected sector, DQ6 toggles for approxi-
mately 1 µs after the program command sequence is written, then returns to
reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling
once the Embedded Program algorithm is complete.
Table 10 shows the outputs for Toggle Bit I on DQ6. Figure 6 shows the toggle bit
algorithm in flowchart form, and the section “Reading Toggle Bits DQ6/DQ2” ex-
plains the algorithm. Figure 20 in the “AC Characteristics” section shows the
toggle bit timing diagrams. Figure 21 shows the differences between DQ2 and
DQ6 in graphical form. See also the subsection on “DQ2: Toggle Bit II”.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular
sector is actively erasing (that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have
been selected for erasure. (The system may use either OE# or CE# to control the
read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or
is erase-suspended. DQ6, by comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected
for erasure. Thus, both status bits are required for sector and mode information.
Refer to Table 10 to compare outputs for DQ2 and DQ6.
36
S29AL016D
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A d v a n c e I n f o r m a t i o n
Figure 6 shows the toggle bit algorithm in flowchart form, and the section “Read-
ing Toggle Bits DQ6/DQ2” explains the algorithm. See also the DQ6: Toggle Bit I
subsection. Figure 20 shows the toggle bit timing diagram. Figure 21 shows the
differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the following discussion. Whenever the system initially be-
gins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the system would note and
store the value of the toggle bit after the first read. After the second read, the
system would compare the new value of the toggle bit with the first. If the toggle
bit is not toggling, the device has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle
bit is still toggling, the system also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer toggling, the device has suc-
cessfully completed the program or erase operation. If it is still toggling, the
device did not complete the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit
is toggling and DQ5 has not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as de-
scribed in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algo-
rithm when it returns to determine the status of the operation (top of Figure 6).
August 4, 2004 S29AL016D_00_A1_E
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37
A d v a n c e I n f o r m a t i o n
START
Read Byte
(DQ7–DQ0)
Address =VA
Read Byte
(DQ7–DQ0)
Address =VA
(Note 1)
No
Toggle Bit
= Toggle?
Yes
No
DQ5 = 1?
Yes
Read Byte Twice
(DQ7–DQ0)
Address = VA
(Notes
1,2)
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes:
1. Read toggle bit twice to determine whether or not it
is toggling. See text.
2. Recheck toggle bit because it may stop toggling as
DQ5 changes to “1”. See text.
Figure 6. Toggle Bit Algorithm
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified inter-
nal pulse count limit. Under these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was not successfully
completed.
38
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A d v a n c e I n f o r m a t i o n
The DQ5 failure condition may appear if the system tries to program a “1” to a
location that is previously programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the device halts the opera-
tion, and when the operation has exceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue the reset command to return
the device to reading array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to de-
termine whether or not an erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If additional sectors are selected for
erasure, the entire time-out also applies after each additional sector erase com-
mand. When the time-out is complete, DQ3 switches from “0” to “1.” The system
may ignore DQ3 if the system can guarantee that the time between additional
sector erase commands will always be less than 50 µs. See also the “Sector
Erase Command Sequence” section.
After the sector erase command sequence is written, the system should read the
status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has ac-
cepted the command sequence, and then read DQ3. If DQ3 is “1”, the internally
controlled erase cycle has begun; all further commands (other than Erase Sus-
pend) are ignored until the erase operation is complete. If DQ3 is “0”, the device
will accept additional sector erase commands. To ensure the command has been
accepted, the system software should check the status of DQ3 prior to and fol-
lowing each subsequent sector erase command. If DQ3 is high on the second
status check, the last command might not have been accepted. Table 10 shows
the outputs for DQ3.
Table 10. Write Operation Status
DQ7
DQ5
DQ2
Operation
(Note 2)
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
Standard
Mode
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Erase
Suspend Reading within Non-Erase
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Mode
Suspended Sector
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing
limits. See “DQ5: Exceeded Timing Limits” for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
August 4, 2004 S29AL016D_00_A1_E
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39
A d v a n c e I n f o r m a t i o n
Absolute Maximum Ratings
Storage Temperature
Plastic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +150°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +125°C
Voltage with Respect to Ground
V
(Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
CC
A9, OE#, and RESET# (Note 2) . . . . . . . . . . . . . . . .–0.5 V to +12.5 V
All other pins (Note 1). . . . . . . . . . . . . . . . . . . . . –0.5 V to V +0.5 V
CC
Output Short Circuit Current (Note 3). . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot VSS
to –2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During
voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8.
2. Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During voltage transitions, A9, OE#, and
RESET# may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC input voltage on pin
A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or any other conditions above those indicated in the op-
erational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for
extended periods may affect device reliability.
20 ns
20 ns
20 ns
+0.8 V
VCC
+2.0 V
–0.5 V
–2.0 V
VCC
+0.5 V
2.0 V
20 ns
20 ns
Figure 7. Maximum Negative
Overshoot Waveform
Figure 8. Maximum Positive Overshoot Waveform
Operating Ranges
Industrial (I) Devices
Ambient Temperature (T ) . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
A
V
Supply Voltages
CC
V
for standard voltage range . . . . . . . . . . . . . . . . . . . . . . . .2.7 V to 3.6 V
CC
Operating ranges define those limits between which the functionality of the device is
guaranteed.
40
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A d v a n c e I n f o r m a t i o n
DC Characteristics
CMOS Compatible
Parameter
Description
Test Conditions
VIN = VSS to VCC
Min
Typ
Max
1.0
35
Unit
µA
,
ILI
ILIT
ILO
Input Load Current
±
VCC = VCC max
A9 Input Load Current
Output Leakage Current
VCC = VCC max; A9 = 12.5 V
µA
VOUT = VSS to VCC
,
±
1.0
µA
VCC = VCC max
10 MHz
5 MHz
1 MHz
10 MHz
5 MHz
1 MHz
15
9
30
16
4
CE# = VIL, OE#= VIH,
Byte Mode
2
VCC Active Read Current
(Notes 1, 2)
ICC1
mA
18
9
35
16
4
CE# = VIL, OE#= VIH,
Word Mode
2
VCC Active Write Current
(Notes 2, 3, 5)
ICC2
ICC3
ICC4
CE# = VIL, OE# = VIH
20
0.2
0.2
35
5
mA
µA
µA
VCC Standby Current (Notes 2, 4) CE#, RESET# = VCC
±0.3 V
VCC Standby Current During Reset
(Notes 2, 4)
RESET# = VSS
±
0.3 V
5
Automatic Sleep Mode
(Notes 2, 4, 6)
VIH = VCC
VIL = VSS
±
0.3 V;
ICC5
0.2
5
µA
±
0.3 V
VIL
Input Low Voltage
Input High Voltage
–0.5
0.8
V
V
VIH
0.7 x VCC
VCC + 0.3
Voltage for Autoselect and
Temporary Sector Unprotect
VID
VCC = 3.3 V
11.5
12.5
0.45
V
VOL
Output Low Voltage
IOL = 4.0 mA, VCC = VCC min
IOH = -2.0 mA, VCC = VCC min
IOH = -100 µA, VCC = VCC min
V
V
V
V
VOH1
VOH2
VLKO
2.4
VCC–0.4
2.3
Output High Voltage
Low VCC Lock-Out Voltage (Note 4)
2.5
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. At extended temperature range (>+85°C), typical current is 5 µA and maximum current is 10 µA.
5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep
mode current is 200 nA.
6. Not 100% tested.
August 4, 2004 S29AL016D_00_A1_E
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41
A d v a n c e I n f o r m a t i o n
DC Characteristics (continued)
Zero Power Flash
25
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
42
S29AL016D
S29AL016D_00_A1_E August 4, 2004
A d v a n c e I n f o r m a t i o n
10
8
3.6 V
2.7 V
6
4
2
0
1
2
3
4
5
Frequency in MHz
Note: T = 25 °C
Figure 10. Typical ICC1 vs. Frequency
August 4, 2004 S29AL016D_00_A1_E
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43
A d v a n c e I n f o r m a t i o n
Test Conditions
3.3 V
2.7 kΩ
Device
Under
Test
C
6.2 kΩ
L
Note: Diodes are IN3064 or equivalent
Figure 11. Te st Se tu p
Table 11. Test Specifications
Test Condition
Output Load
70
90
Unit
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
30
100
5
pF
Input Rise and Fall Times
Input Pulse Levels
ns
V
0.0 or VCC
Input timing measurement
reference levels
0.5 VCC
0.5 VCC
V
V
Output timing measurement
reference levels
44
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A d v a n c e I n f o r m a t i o n
Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
VCC
0.0 V
0.5 VCC
0.5 VCC
Input
Measurement Level
Output
Figure 12. Input Waveforms and Measurement Levels
August 4, 2004 S29AL016D_00_A1_E
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45
A d v a n c e I n f o r m a t i o n
AC Characteristics
Read Operations
Parameter
Speed Options
JEDEC
Std
Description
Test Setup
70
90
Unit
tAVAV
tRC
Read Cycle Time (Note 1)
Min
70
90
ns
CE# = VIL
OE# = VIL
tAVQV
tACC
Address to Output Delay
Max
70
90
ns
tELQV
tGLQV
tEHQZ
tGHQZ
tCE
tOE
tDF
tDF
Chip Enable to Output Delay
OE# = VIL
Max
Max
Max
Max
Min
70
30
25
25
90
35
30
30
ns
ns
ns
ns
ns
Output Enable to Output Delay
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
Read
0
Output Enable
Hold Time (Note 1)
tOEH
Toggle and
Data# Polling
Min
Min
10
ns
ns
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First (Note 1)
tAXQX
tOH
0
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 11 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 13. Read Operations Timings
46
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A d v a n c e I n f o r m a t i o n
AC Characteristics
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
Test Setup
Max
All Speed Options
Unit
RESET# Pin Low (During Embedded Algorithms)
to Read or Write (See Note)
tREADY
20
µs
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
tREADY
Max
500
ns
tRP
tRH
tRPD
tRB
RESET# Pulse Width
Min
Min
Min
Min
500
50
20
0
ns
ns
µs
ns
RESET# High Time Before Read (See Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
Note: Not 100% tested.
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 14. RESET# Timings
August 4, 2004 S29AL016D_00_A1_E
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47
A d v a n c e I n f o r m a t i o n
AC Characteristics
Word/Byte Configuration (BYTE#)
Parameter
Speed Options
JEDEC
Std
tELFL/ ELFH
tFLQZ
Description
70
90
Unit
ns
t
CE# to BYTE# Switching Low or High
BYTE# Switching Low to Output HIGH Z
BYTE# Switching High to Output Active
Max
Max
Min
5
25
70
30
90
ns
tFHQV
ns
CE#
OE#
BYTE#
tELFL
Data Output
(DQ0–DQ14)
Data Output
(DQ0–DQ7)
BYTE#
DQ0–DQ14
Switching
from word
to byte
Address
Input
DQ15
Output
mode
DQ15/A-1
BYTE#
tFLQZ
tELFH
BYTE#
Switching
from byte
to word
Data Output
(DQ0–DQ7)
Data Output
DQ0–DQ14
DQ15/A-1
(DQ0–DQ14)
mode
Address
Input
DQ15
Output
tFHQV
Figure 15. BYTE# Timings for Read Operations
48
S29AL016D
S29AL016D_00_A1_E August 4, 2004
A d v a n c e I n f o r m a t i o n
CE#
The falling edge of the last WE# signal
WE#
BYTE#
tSET
(tAS
)
tHOLD (tAH
)
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.
Figure 16. BYTE# Timings for Write Operations
August 4, 2004 S29AL016D_00_A1_E
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49
A d v a n c e I n f o r m a t i o n
AC Characteristics
Erase/Program Operations
Parameter
Speed Options
JEDEC
tAVAV
Std
tWC
tAS
tAH
tDS
tDH
Description
70
90
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
70
90
tAVWL
tWLAX
tDVWH
tWHDX
0
ns
45
35
45
45
ns
ns
Data Hold Time
0
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHWL
tGHWL
Min
ns
tELWL
tWHEH
tWLWH
tWHWL
tCS
tCH
tWP
tWPH
CE# Setup Time
CE# Hold Time
Min
Min
Min
Min
Typ
Typ
Typ
Min
Min
Max
0
0
ns
ns
ns
ns
Write Pulse Width
Write Pulse Width High
35
35
30
5
Byte
tWHWH1
tWHWH2
tWHWH1 Programming Operation (Note 2)
µs
Word
7
tWHWH2 Sector Erase Operation (Note 2)
0.7
50
0
sec
µs
ns
tVCS
tRB
VCC Setup Time (Note 1)
Recovery Time from RY/BY#
Program/Erase Valid to RY/BY# Delay
tBUSY
90
ns
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
50
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A d v a n c e I n f o r m a t i o n
AC Characteristics
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#
OE#
tCH
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
Data
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 17. Program Operation Timings
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51
A d v a n c e I n f o r m a t i o n
AC Characteristics
Erase Command Sequence (last two cycles)
Read Status Data
tAS
SA
tWC
2AAh
VA
VA
Addresses
CE#
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
Data
Status
D
OUT
55h
30h
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
2. Illustration shows device in word mode.
Figure 18. Chip/Sector Erase Operation Timings
52
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A d v a n c e I n f o r m a t i o n
AC Characteristics
tRC
Addresses
VA
tACC
tCE
VA
VA
CE#
tCH
tOE
OE#
tOEH
WE#
tDF
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ6–DQ0
Status Data
True
Valid Data
Status Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle
after command sequence, last status read cycle, and array data read cycle.
Figure 19. Data# Polling Timings (During Embedded Algorithms)
tRC
VA
Addresses
CE#
VA
VA
VA
tACC
tCE
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
DQ6/DQ2
RY/BY#
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stops toggling)
tBUSY
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last
status read cycle, and array data read cycle.
Figure 20. Toggle Bit Timings (During Embedded Algorithms)
August 4, 2004 S29AL016D_00_A1_E
S29AL016D
53
A d v a n c e I n f o r m a t i o n
AC Characteristics
Enter
Erase
Suspend
Enter Erase
Suspend Program
Embedded
Erase
Resume
Erasing
Erase Erase Suspend
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
Read
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 21. DQ2 vs. DQ6 for Erase and Erase Suspend Operations
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
Min
500
ns
RESET# Setup Time for Temporary Sector
Unprotect
tRSP
4
µs
Note: Not 100% tested.
12 V
RESET#
0 or 3 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
Figure 22. Temporary Sector Unprotect/Timing Diagram
54
S29AL016D
S29AL016D_00_A1_E August 4, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
V
ID
V
IH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Valid*
Status
Sector Group Protect/Unprotect
Verify
40h
Data
60h
60h
1 µs
Sector Group Protect: 150 µs
Sector Group Unprotect: 15 ms
CE#
WE#
OE#
Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 23. Sector Protect/Unprotect Timing Diagram
August 4, 2004 S29AL016D_00_A1_E
S29AL016D
55
A d v a n c e I n f o r m a t i o n
AC Characteristics
Alternate CE# Controlled Erase/Program Operations
Parameter
Speed Options
JEDEC
tAVAV
tAVEL
Std
tWC
tAS
tAH
tDS
tDH
Description
70
90
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
70
90
0
ns
tELAX
45
35
45
45
ns
tDVEH
tEHDX
ns
Data Hold Time
0
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHEL
tGHEL
Min
ns
tWLEL
tEHWH
tELEH
tEHEL
tWS
tWH
tCP
WE# Setup Time
WE# Hold Time
Min
Min
Min
Min
Typ
Typ
Typ
0
0
ns
ns
ns
ns
CE# Pulse Width
CE# Pulse Width High
35
35
tCPH
30
5
Byte
tWHWH1
tWHWH2
tWHWH1
tWHWH2
Programming Operation (Note 2)
Sector Erase Operation (Note 2)
µs
Word
7
0.7
sec
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
56
S29AL016D
S29AL016D_00_A1_E August 4, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
555 for program
PA for program
2AA for erase
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data
written to the device.
2. Figure indicates the last two bus cycles of the command sequence.
3. Word mode address used as an example.
Figure 24. Alternate CE# Controlled Write Operation Timings
August 4, 2004 S29AL016D_00_A1_E
S29AL016D
57
A d v a n c e I n f o r m a t i o n
Erase and Programming Performance
Parameter
Typ (Note 1)
Max (Note 2)
Unit
s
Comments
Sector Erase Time
Chip Erase Time
0.7
25
5
10
Excludes 00h programming
prior to erasure (Note 4)
s
Byte Programming Time
Word Programming Time
150
210
33
µs
µs
s
7
Excludes system level
overhead (Note 5)
Byte Mode
Word Mode
11
7.2
Chip Programming Time
(Note 3)
21.6
s
Notes:
1. Typical program and erase times assume the following conditions: 25°C, VCC = 3.0 V, 100,000 cycles, checkerboard
data pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most
bytes program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program
command. See Table 9 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 100,000 cycles per sector.
TSOP and BGA Pin Capacitance
Parameter
Symbol
Parameter Description
Test Setup
Package
TSOP
BGA
Typ
6
Max
7.5
5.0
12
Unit
pF
CIN
Input Capacitance
VIN = 0
4.2
8.5
5.4
7.5
3.9
pF
TSOP
BGA
pF
COUT
Output Capacitance
VOUT = 0
VIN = 0
6.5
9
pF
TSOP
BGA
pF
CIN2
Control Pin Capacitance
4.7
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
58
S29AL016D
S29AL016D_00_A1_E August 4, 2004
P r e l i m i n a r y
2Mbit Type 1 SRAM
Common Features
Single Wide Power Supply Range
2.3 to 3.6 Volts
Very low standby current
2.0µA at 3.0V (Typical)
Very low operating current
2.0mA at 3.0V and 1µs (Typical)
Very low Page Mode operating current
0.8mA at 3.0V and 1µs (Typical)
Simple memory control
Dual Chip Enables (CE1# and CE2)
Byte control for independent byte operation
Output Enable (OE#) for memory expansion
Low voltage data retention
V
= 1.8V
CC
Very fast output enable access time
30ns OE# access time
Automatic power down to standby mode
TTL compatible three-state output driver
Tested wafers
August 4, 2004 SRAM_Type01_03A0
2Mbit Type 1 SRAM
59
P r e l i m i n a r y
Functional Description
CE# CE2 WE#
OE#
UB#
LB#
IO
(Note 1)
Mode
Standby (Note 2)
Standby (Note 2)
Standby
Power
Standby
Standby
Standby
Active
0~15
H
X
L
L
L
L
X
L
X
X
X
L
X
X
X
High-Z
X
X
X
High-Z
High-Z
Data In
H
H
H
H
X
H
H
X (Note 3)
L (Note 1)
L (Note 1)
L (Note 1)
L (Note 1)
L (Note 1)
L (Note 1)
Write (Note 3)
Read
H
H
L
Data Out
High-Z
Active
H
Active
Active
Notes:
1. When UB# and LB# are in select mode (low), I/O0 - I/O15 are affected as shown. When only LB# is in the select mode, only
I/O0 - I/O7 are affected as shown. When UB# is in the select mode only I/O8 - I/O15 are affected as shown.
2. When the device is in standby mode, control inputs (WE#, OE#, UB#, and LB#), address inputs and data input/outputs are
internally isolated from any external influence and disabled from exerting any influence externally.
3. When WE# is invoked, the OE# input is internally disabled and has no effect on the circuit.
Capacitance
Item
Symbol
CIN
Test Condition
Min
Max
8
Unit
pF
Input Capacitance
I/O Capacitance
VIN = 0V, f = 1 MHz, TA = 25°C
VIN = 0V, f = 1 MHz, TA = 25°C
CI/O
8
pF
Note: These parameters are verified in device characterization and are not 100% tested.
Absolute Maximum Ratings
Item
Symbol
VIN,VOUT
VCC
Ratings
–0.3 to VCC + 0.3
-0.3 to 4.5V
Unit
V
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Power Dissipation
V
PD
500
W
Storage Temperature
TSTG
–40 to 125
°
°
C
C
Operating Temperature
TA
-40 to 85
Soldering Temperature and Time
TSOLDER
240°C, 10sec (Lead only)
°C
Note: Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating section of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
60
2Mbit Type 1 SRAM
SRAM_Type01_03A0 August 4, 2004
P r e l i m i n a r y
Operating Characteristics (Over Specified Temperature Range)
Type
Item
Symbol
VCC
VDR
VIH
Test Conditions
Min
2.3
(Note1)
Max
3.6
Unit
Supply Voltage
3.0
Data Retention Voltage
Input High Voltage
Chip Disabled (Note 3)
1.8
3.6
1.8
VCC + 0.3
0.6
V
Input Low Voltage
VIL
-0.3
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
VOH
VOL
ILI
IOH = 0.2mA
IOL = -0.2mA
VCC - 0.2
0.2
0.5
0.5
VIN = 0 to VCC
µA
ILO
OE# = VIH or Chip Disabled
Read/Write Operating Supply Current
at 1 µs Cycle Time (Note 2)
VCC = 3.6 V, VIN = VIH or VIL
Chip Enabled, IOUT = 0
ICC1
ICC2
ICC3
ICC4
ISB1
IDR
2.0
12.0
4.0
4.0
Read/Write Operating Supply Current
at 70 ns Cycle Time (Note 2)
VCC = 3.6 V, VIN = VIH or VIL
Chip Enabled, IOUT = 0
16.0
mA
Page Mode Operating Supply Current
at 70ns Cycle Time (Note 2) (Figure 1)
VCC = 3.6 V, VIN = VIH or VIL
Chip Enabled, IOUT = 0
Read/Write Quiescent Operating
Supply Current (Note 3)
VCC = 3.6 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0, f = 0
3.0
VIN = VCC or 0V Chip Disabled
tA = 85°C, VCC = 3.6 V
Maximum Standby Current (Note 3)
2.0
20.0
10.0
µΑ
Maximum Data Retention Current
(Note 3)
VCC = 1.8V, VIN = VCC or 0
Chip Disabled, tA= 85°C
Notes:
1. Typical values are measured at VCC = VCC Typ., TA = 25°C and is not 100% tested.
2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to
drive output capacitance expected in the actual system.
3. This device assumes a standby mode if the chip is disabled (CE1# high or CE2 low). In order to achieve low standby current
all inputs must be within 0.2 volts of either VCC or VSS
.
August 4, 2004 SRAM_Type01_03A0
2Mbit Type 1 SRAM
61
P r e l i m i n a r y
Page Address (A4 -A16)
WordAddress (A0 -A3)
Openpage
...
Word 16
Word 1
Word 2
CE1#
CE2
OE#
LB#, UB#
Figure 1. Power Savings with Page Mode (WE# = VIH
)
Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal
organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power
saving feature.
The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open
and 16-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant
bits and addressing the 16 words within the open page, power is reduced to the page mode value which is
considerably lower than standard operating currents for low power SRAMs.
Timing Test Conditions
Item
Input Pulse Level
0.1VCC to 0.9 VCC
5ns
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
0.5 VCC
CL = 30pF
-40 to +85°C
Operating Temperature
62
2Mbit Type 1 SRAM
SRAM_Type01_03A0 August 4, 2004
P r e l i m i n a r y
Timing
2.3 - 3.6 V
Item
Symbol
tRC
Min
Max
Units
Read Cycle Time
70
Address Access Time
tAA
70
70
35
70
Chip Enable to Valid Output
Output Enable to Valid Output
Byte Select to Valid Output
Chip Enable to Low-Z output
Output Enable to Low-Z Output
Byte Select to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Byte Select Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
tCO
tOE
tLB, tUB
tLZ
10
5
tOLZ
tLBLZ, tUBLZ
tHZ
10
0
20
20
20
tOHZ
0
tLBHZ, tUBHZ
tOH
0
10
70
50
50
50
40
0
ns
tWC
Chip Enable to End of Write
Address Valid to End of Write
Byte Select to End of Write
Write Pulse Width
tCW
tAW
tLBW, tUBW
tWP
Address Setup Time
tAS
Write Recovery Time
tWR
0
Write to High-Z Output
tWHZ
tDW
20
Data to Write Time Overlap
Data Hold from Write Time
End Write to Low-Z Output
40
0
tDH
tOW
10
August 4, 2004 SRAM_Type01_03A0
2Mbit Type 1 SRAM
63
P r e l i m i n a r y
Timing Diagrams
t
RC
Address
t
AA
t
OH
DataValid
Data Out
Previous Data Valid
Figure 2. Timing of Read Cycle (CE# = OE# = VIL, WE# = CE2= VIH
)
t
RC
Address
t
AA
t
HZ
CE1#
CE2
t
CO
t
LZ
t
OHZ
t
OE
OE#
t
OLZ
t
t
LB, UB
LB#, UB#
Data Out
t
t
t
t
LBLZ, UBLZ
LBHZ, UBHZ
High-Z
Data Valid
Figure 3. Timing Waveform of Read Cycle (WE# = VIH
)
64
2Mbit Type 1 SRAM
SRAM_Type01_03A0 August 4, 2004
P r e l i m i n a r y
t
WC
Address
t
WR
t
AW
CE1#
CE2
t
CW
t
, t
LBW UBW
LB#, UB#
t
t
AS
WP
WE#
t
t
DH
DW
High-Z
Data Valid
Data In
Data Out
t
WHZ
t
OW
High-Z
Figure 4. Timing Waveform of Write Cycle (WE# Control)
t
WC
Address
t
t
AW
WR
t
CE1#
CW
(for CE2 Control, use
inverted signal)
t
AS
t
, t
LBW UBW
LB#, UB#
WE#
t
WP
t
t
DH
DW
Data Valid
Data In
t
LZ
t
WHZ
High-Z
Data Out
Figure 5. Timing Waveform of Write Cycle (CE1# Control)
August 4, 2004 SRAM_Type01_03A0
2Mbit Type 1 SRAM
65
P r e l i m i n a r y
2Mbit Type 2 SRAM
128K x 16 Static RAM
Common Features
High Speed
— 55ns and 70ns availability
Ultra-low active power
— Typical active current: 1.5 mA @ f = 1MHz
— Typical active current: 7 mA @ f = fmax (70ns speed)
Low standby power
Easy memory expansion with CE and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
Functional Description
The 2Mbit Type 2 SRAM is a family of high-performance CMOS static RAMs orga-
nized as 128K words by 16 bits. These devices feature advanced circuit design to
provide ultra-low active current. This is ideal for providing More Battery Life™
(MoBL™) in portable applications such as cellular telephones. The devices also
have an automatic power-down feature that significantly reduces power con-
sumption by 80% when addresses are not toggling. The device can also be put
into standby mode reducing power consumption by more than 99% when dese-
lected (CE# High). The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when: deselected (CE# High), outputs are disabled (OE#
High), both Byte High Enable and Byte Low Enable are disabled (BHE#, BLE#
High), or during a write operation (CE# Low, and WE# Low).
Writing to the device is accomplished by taking Chip Enable (CE#) and Write En-
able (WE#) inputs Low. If Byte Low Enable (BLE#) is Low, then data from I/O
pins (I/O0 through I/O7), is written into the location specified on the address pins
(A0 through A16). If Byte High Enable (BHE#) is Low, then data from I/O pins
(I/O8 through I/O15) is written into the location specified on the address pins (A0
through A16).
Reading from the device is accomplished by taking Chip Enable (CE#) and Output
Enable (OE#) Low while forcing the Write Enable (WE#) High. If Byte Low Enable
(BLE#) is Low, then data from the memory location specified by the address pins
will appear on I/O0 to I/O7. If Byte High Enable (BHE#) is Low, then data from
memory will appear on I/O8 to I/O15. See Table 1 for a complete description of
read and write modes.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested)
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Ambient Temperature with Power Applied . . . . . . . . . . . . . . -55°C to +125°C
Supply Voltage to Ground Potential . . . . . . . . . . . . . . -0.5V to V
+ 0.5V
CCmax
DC Voltage Applied to Outputs in High-Z State (note 2) . . -0.5V to V + 0.5V
CC
DC Input Voltage (note 2). . . . . . . . . . . . . . . . . . . . . . . -0.5V to V + 0.5V
CC
Output Current into Outputs (Low). . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
66
2Mbit Type 2 SRAM
SRAM_Type04_04A0 August 4, 2004
P r e l i m i n a r y
Operating Range
Product Portfolio
Range
Industrial
Ambient Temperature
V
CC
-40°C to +85°C
2.7V to 3.3V
Power Dissipation (Industrial)
Operating, I
CC
V
Range
f = 1 MHz
f = f
Standby (I
)
CC
max
SB2
V
V
(note 2)
V
Speed Typ. (note 2)
Max
Typ. (note 2)
12 mA
Max
Typ. (note 2)
Max
CC (min)
CC (typ.)
CC (max)
55 ns
70 ns
1.5 mA
1.5 mA
3 mA
3 mA
25 mA
15 mA
2.7V
3.0V
3.3V
2 µA
10 µA
7 mA
Notes:
1. VIL(min.) = –2.0V for pulse durations less than 20 ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC
=
VCC(typ.), TA = 25°C.
Electrical Characteristics
Voltage Range 2.7V - 3.3V
Test Conditions
Typ.
(note 1)
Parameter
Description
Output High Voltage
Min.
Max
Unit
V
V
V
V
I
I
= –1.0 mA
= 2.1mA
V
V
= 2.7V
= 2.7V
2.4
OH
OL
IH
IL
OH
OL
CC
Output Low Voltage
Input High Voltage
0.4
CC
V
2.2
-0.3
-1
V
+ 0.3V
0.8
+1
CC
Input Low Voltage
I
I
Input Leakage Current
Output Leakage Current
GND < V < V
I CC
IX
µA
GND < V < V , Output Disabled
-1
+1
OZ
CC
O
CC
f = f
= 1/t
V
= 3.3V
= 0 mA
7
15
MAX
RC
CC
I
I
I
V
Operating Supply Current
I
mA
CC
OUT
f = 1 MHz
CMOS Levels
1.5
3
CE# ≥ V – 0.2V
CC
Automatic CE Power-Down
Current—CMOS Inputs
V
≥ V
– 0.2V or V ≤ 0.2V,
IN
CC IN
SB1
SB2
f = fmax (Address and Data Only),
f=0 (OE#, WE#, BHE# and BLE#)
2
10
µA
CE# ≥ V – 0.2V
CC
Automatic CE Power-Down
Current—CMOS Inputs
V
≥ V
– 0.2V or V ≤ 0.2V,
IN
CC IN
f = 0, V = 3.3V
CC
Notes:
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC
VCC(typ.), TA = 25°C.
=
August 4, 2004 SRAM_Type04_04A0
2Mbit Type 2 SRAM
67
P r e l i m i n a r y
Capacitance
Parameter
Description
Test Condition
Max
6
Unit
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
pF
VCC = VCC(typ.)
COUT
8
Note: Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
R1
V
ALL INPUT PULSES
90%
10%
CC
V
Typ
CC
OUTPUT
90%
10%
GND
Rise Time: 1 V/ns
R2
30 pF
Fall Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENINEQUIVALENT
R
TH
OUTPUT
V
TH
Figure 1. AC Test Loads and Waveforms
Parameters
2.5V
16.6
15.4
8
3.0V
1.105
1.550
0.645
1.75
3.3V
Unit
K Ohms
Volts
R1
R2
1.216
1.374
0.645
1.75
RTH
VTH
1.20
Data Retention Characteristics (Over the Operation Range)
Typ
Parameter
VDR
Description
VCC for Data Retention
Conditions
Min. (note 1)
Max.
VCCMAX
4
Unit
1.5
V
ICCDR
Data Retention Current
VCC = 1.5V CE#
≥
VCC – 0.2V
1
µA
tCDR (note 2)
tR (note 3)
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
tRC
Notes:
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC
VCC(typ.), TA = 25°C.
=
2. Tested initially and after any design or process changes that may affect these parameters.
3. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 ms or stable at VCC(min.) > 100 ms.
68
2Mbit Type 2 SRAM
SRAM_Type04_04A0 August 4, 2004
P r e l i m i n a r y
DATA RETENTION MODE
> 1.5 V
VCC(min)
VCC(min)
V
V
DR
CC
t
t
R
CDR
CE#or
BHE#.BLE#
Figure 2. Data Retention Waveform
Note: BHE#.BLE# is the AND of both BHE# and BLE#. Chip can be deselected by either disabling the chip enable signals
or by disabling both BHE# and BLE#.
August 4, 2004 SRAM_Type04_04A0
2Mbit Type 2 SRAM
69
P r e l i m i n a r y
Switching Characteristics
55 ns
70 ns
Parameter
Read Cycle
Description
Unit
Min
Max
Min
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
55
10
70
10
RC
Address to Data Valid
55
70
AA
Data Hold from Address Change
CE# Low to Data Valid
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
55
25
70
35
OE# Low to Data Valid
OE# Low to Low Z (note 2)
OE# High to High Z (note 2, 4)
CE# Low to Low Z (note 2)
CE# High to High Z (note 2, 4)
CE# Low to Power-Up
5
10
0
5
10
0
20
20
25
25
ns
CE# High to Power-Down
55
55
70
70
PD
BHE# / BLE# Low to Data Valid
BHE# / BLE# Low to Low Z (note 2)
BHE# / BLE# High to High Z (note 2, 4)
DBE
LZBE
HZBE
(note 3)
5
5
20
25
Write Cycle (note 5)
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
55
45
45
0
70
60
60
0
WC
CE# Low to Write End
SCE
AW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE# Pulse Width
HA
0
0
SA
45
50
25
0
50
60
30
0
ns
PWE
BW
BHE# / BLE# Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE# Low to High Z (note 2, 4)
WE# High to Low Z (note 2)
SD
HD
20
25
HZWE
LZWE
5
5
Notes:
1. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.) /2, input pulse levels of 0 to
VCC(typ.), and output loading of the specified IOL/IOH and 30 pF load capacitance.
2. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and
tHZWE is less than tLZWE for any given device.
3. If both byte enables are toggled together this value is 10ns.
4. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
5. The internal write time of the memory is defined by the overlap of WE#, CE# = VIL, BHE# and/or BLE# = VIL. All signals
must be Active to initiate a write, and any of these signals can terminate a write by going Inactive. The data input set-up and
hold timing should be referenced to the edge of the signal that terminates the write.
70
2Mbit Type 2 SRAM
SRAM_Type04_04A0 August 4, 2004
P r e l i m i n a r y
Switching Waveforms
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 3. Read Cycle 1 (Address Transition Controlled)
Notes:
1. Device is continuously selected. OE#, CE# = VIL, BHE#, BLE# = VIL
.
2. WE# is High for read cycle.
ADDRESS
t
RC
CE#
OE#
tPD
tHZCE
tACE
tHZOE
t
DOE
BHE#/BLE#
t
Z
L OE
tHZBE
tDBE
tLZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
tLZCE
tPU
VCC
SUPPLY
CURRENT
ICC
ISB
50%
50%
Figure 4. Read Cycle 2 (OE# Controlled)
Notes:
1. WE# is High for read cycle.
2. Address valid prior to or coincident with CE#, BHE#, BLE# transition Low.
August 4, 2004 SRAM_Type04_04A0
2Mbit Type 2 SRAM
71
P r e l i m i n a r y
tWC
ADDRESS
CE#
tSCE
tAW
tHA
tSA
tPWE
WE#
t
BW
BHE#/BLE#
OE#
t
SD
tHD
DATA I/O
DATAIN VALID
NOTE4
tHZOE
Figure 5. Write Cycle 1 (WE# Controlled)
Notes:
1. The internal write time of the memory is defined by the overlap of WE#, CE# = VIL, BHE# and/or BLE# = VIL. All signals
must be Active to initiate a write, and any of these signals can terminate a write by going Inactive. The data input set-up and
hold timing should be referenced to the edge of the signal that terminates the write.
2. Data I/O is high-impedance if OE# = VIH
.
3. If CE# goes High simultaneously with WE# High, the output remains in a high-impedance state.
4. During this period, the I/Os are in output state and input signals should not be applied.
72
2Mbit Type 2 SRAM
SRAM_Type04_04A0 August 4, 2004
P r e l i m i n a r y
t
WC
ADDRESS
CE#
t
SCE
tSA
t
t
HA
AW
t
PWE
WE#
t
BW
BHE#/BLE#
OE#
t
SD
t
HD
VALID
DATA I/O
DATA
IN
NOTE4
t
HZOE
Figure 6. Write Cycle 2 (CE# Controlled)
Notes:
1. The internal write time of the memory is defined by the overlap of WE#, CE# = VIL, BHE# and/or BLE# = VIL. All signals
must be Active to initiate a write, and any of these signals can terminate a write by going Inactive. The data input set-up and
hold timing should be referenced to the edge of the signal that terminates the write.
2. Data I/O is high-impedance if OE# = VIH
.
3. If CE# goes High simultaneously with WE# High, the output remains in a high-impedance state.
4. During this period, the I/Os are in output state and input signals should not be applied.
t
WC
ADDRESS
CE#
t
SCE
t
BW
BHE#/BLE#
t
AW
t
HA
t
t
PWE
SA
WE#
t
SD
t
HD
NOTE 2
DATAI/O
DATA VALID
IN
t
LZWE
t
HZWE
Figure 7. Write Cycle 3 (WE# Controlled, OE# LOW)
Notes:
1. If CE# goes High simultaneously with WE# High, the output remains in a high-impedance state.
2. During this period, the I/Os are in output state and input signals should not be applied.
August 4, 2004 SRAM_Type04_04A0
2Mbit Type 2 SRAM
73
P r e l i m i n a r y
tWC
ADDRESS
CE#
tSCE
AW
t
t
HA
t
BW
BHE#/BLE#
t
SA
t
PWE
WE#
t
t
HD
SD
DATA I/O
VALID
DATA
NOTE 2
IN
Figure 8. Write Cycle 4 (BHE#/BLE# Controlled, OE# Low)
Notes:
1. If CE# goes High simultaneously with WE# High, the output remains in a high-impedance state.
2. During this period, the I/Os are in output state and input signals should not be applied.
Typical DC and AC Parameters
14.0
(f = f , 55ns)
12.0
10.0
max
MoBL
8.0
6.0
(f = f , 70ns)
max
4.0
2.0
0.0
(f = 1 MHz)
3.0
2.7
3.3
SUPPLY VOLTAGE (V)
Figure 9. Operating Current vs. Supply Voltage
12.0
10.0
MoBL
8.0
6.0
4.0
2.0
0
3.3
3.0
2.7
SUPPLY VOLTAGE (V)
Figure 10. Standby Current vs. Supply Voltage
74
2Mbit Type 2 SRAM
SRAM_Type04_04A0 August 4, 2004
P r e l i m i n a r y
60
MoBL
50
40
30
20
10
0
3.0
2.7
3.3
SUPPLY VOLTAGE (V)
Figure 11. Access Time vs. Supply Voltage
Truth Table
Table 1. Truth Table
CE# WE# OE# BHE#
BLE#
Inputs / Outputs
Mode
Power
H
L
X
X
H
X
X
L
X
H
L
X
H
L
High-Z
High-Z
Deselect/Power-Down
Output Disabled
Read
Standby (ISB)
L
Data Out (I/OO–I/O15)
Data Out (I/OO–I/O7);
I/O8–I/O15 in High Z
L
L
H
H
L
L
H
L
L
Read
Read
Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z
H
L
L
L
L
H
H
H
L
H
H
H
X
L
H
L
L
L
High-Z
Output Disabled
Output Disabled
Output Disabled
Write
Active (ICC
)
High-Z
H
L
High-Z
L
Data In (I/OO–I/O15)
Data In (I/OO–I/O7);
I/O8–I/O15 in High Z
L
L
L
L
X
X
H
L
L
Write
Write
Data In (I/O8–I/O15);
I/O0–I/O7 in High Z
H
August 4, 2004 SRAM_Type04_04A0
2Mbit Type 2 SRAM
75
A d v a n c e I n f o r m a t i o n
Revision Summary
Revision A (September 27, 2004)
Initial release.
Revision A+1 (November 11, 2004)
Deleted parameter "t
" at page 50,56.
OES
Changed the symbol of " tLBZ, tUBZ" to " tLBLZ, tUBLZ" at page 63.
Trademarks and Notice
The contents of this document are subject to change without notice.This document may contain information on a SpansionTM product under development
by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable ( i.e., submersible repeater and
artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-men-
tioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other
abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-
thorization by the respective government entity will be required for export of those products.
The contents of this document are subject to change without notice.This document may contain information on a SpansionTM product under development by
Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.
Copyright © 2004 Spansion LLC. All rights reserved.
SpansionTM, the SpansionTM logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of Spansion LLC. Other company and product names used
in this publication are for identification purposes only and may be trademarks of their respective companies.
76
Revision Summary
S71AL016D_02_04_00_A0 November 11, 2004
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