S29GL064A30BFIR23 [SPANSION]
64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology; 64兆, 32兆, 16兆3.0伏只页面模式闪存设有200纳米的MirrorBit工艺技术型号: | S29GL064A30BFIR23 |
厂家: | SPANSION |
描述: | 64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology |
文件: | 总95页 (文件大小:3604K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
S29GL-A MirrorBit® Flash Family
S29GL064A, S29GL032A, and S29GL016A
64 Megabit, 32 Megabit, and 16 Megabit
3.0-Volt only Page Mode Flash Memory
Featuring 200 nm MirrorBit Process Technology
S29GL-A Cover Sheet
Data Sheet
The S29GL064A and S29GL032A will not be offered for new designs. For new and current designs, the
S29GL064N and S29GL032N supersedes the S29GL064A and S29GL032A respectively and are the
factory-recommended migration path. Please refer to the S29GL064N and S29GL032N for specifications
and ordering information.
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume
such that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.
Publication Number S29GL-A_00
Revision A
Amendment 11
Issue Date September 10, 2007
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
2
S29GL-A
S29GL-A_00_A11 September 10, 2007
S29GL-A MirrorBit® Flash Family
S29GL064A, S29GL032A, and S29GL016A
64 Megabit, 32 Megabit, and 16 Megabit
3.0-Volt only Page Mode Flash Memory
featuring 200 nm MirrorBit Process Technology
Data Sheet
The S29GL064A and S29GL032A will not be offered for new designs. For new and current designs, the S29GL064N and
S29GL032N supersedes the S29GL064A and S29GL032A respectively and are the factory-recommended migration path.
Please refer to the S29GL064N and S29GL032N for specifications and ordering information.
Distinctive Characteristics
Low power consumption
Architectural Advantages
Single power supply operation
(typical values at 3.0 V, 5 MHz)
– 18 mA typical active read current
– 3-Volt read, erase, and program operations
– 50 mA typical erase/program current
Manufactured on 200 nm MirrorBit process technology
– 1 µA typical standby mode current
Secured Silicon Sector region
Package options
– 128-word/256-byte sector for permanent, secure identification
– 48-pin TSOP
through an 8-word/16-byte random Electronic Serial Number,
accessible through a command sequence
– May be programmed and locked at the factory or by the customer
– 56-pin TSOP
– 64-ball Fortified BGA
– 48-ball fine-pitch BGA
Flexible sector architecture
– 56-ball fine pitch BGA
– 64Mb (uniform sector models): 128 32 Kword (64 KB) sectors
(MCP-compatible for cellular handsets)
– 64 Mb (boot sector models): 127 32 Kword (64 KB) sectors
+ 8 4Kword (8KB) boot sectors
– 32 Mb (uniform sector models): 64 32Kword (64 KB) sectors
– 32 Mb (boot sector models): 63 32Kword (64 KB) sectors
Software & Hardware Features
Software features
– Program Suspend & Resume: read other sectors before
programming operation is completed
– Erase Suspend & Resume: read/program other sectors before an
erase operation is completed
+ 8 4Kword (8KB) boot sectors
– 16 Mb (boot sector models): 31 31Kword (64 KB) sectors
+ 8 4Kword (8 KB) boot sectors
Compatibility with JEDEC standards
– Data# polling & toggle bits provide status
– Provides pinout and software compatibility for single-power supply
flash, and superior inadvertent write protection
– CFI (Common Flash Interface) compliant: allows host system to
identify and accommodate multiple flash devices
– Unlock Bypass Program command reduces overall multiple-word
programming time
100,000 erase cycles typical per sector
20-year data retention typical
Hardware features
Performance Characteristics
High performance
– Sector Group Protection: hardware-level method of preventing write
operations within a sector group
– 90 ns access time
– Temporary Sector Unprotect: V -level method of charging code in
ID
locked sectors
– 4-word/8-byte page read buffer
– 25 ns page read times
– 16-word/32-byte write buffer which reduces overall programming
time for multiple-word updates
– WP#/ACC input accelerates programming time (when high voltage
is applied) for greater throughput during system production. Protects
first or last sector regardless of sector protection settings on uniform
sector models
– Hardware reset input (RESET#) resets device
– Ready/Busy# output (RY/BY#) detects program or erase cycle
completion
Publication Number S29GL-A_00
Revision A
Amendment 11
Issue Date September 10, 2007
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient pro-
duction volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid com-
binations offered may occur.
D a t a S h e e t
General Description
The S29GL-A family of devices are 3.0-Volt single-power Flash memory manufactured using 200 nm
MirrorBit technology. The S29GL064A is a 64-Mb device organized as 4,194,304 words or 8,388,608 bytes.
The S29GL032A is a 32-Mb device organized as 2,097,152 words or 4,194,304 bytes. The S29Gl016A is a
16-Mb device organized as 1,048,576 words or 2,097,152 bytes. Depending on the model number, the
devices have an 8-bit wide data bus only, 16-bit wide data bus only, or a 16-bit wide data bus that can also
function as an 8-bit wide data bus by using the BYTE# input. The devices can be programmed either in the
host system or in standard EPROM programmers.
Access times as fast as 90 ns are available. Note that each access time has a specific operating voltage
range (VCC) as specified in the Product Selector Guide on page 9 and the Ordering Information on page 19.
Package offerings include 48-pin TSOP, 56-pin TSOP, 48-ball fine-pitch BGA and 64-ball Fortified BGA,
depending on model number. Each device has separate chip enable (CE#), write enable (WE#) and output
enable (OE#) controls.
Each device requires only a single 3.0-Volt power supply for both read and write functions. In addition to a
VCC input, a high-voltage accelerated program (ACC) feature provides shorter programming times through
increased current on the WP#/ACC input. This feature is intended to facilitate factory throughput during
system production, but may also be used in the field if desired.
The device is entirely command set compatible with the JEDEC single-power-supply Flash standard.
Commands are written to the device using standard microprocessor write timing. Write cycles also internally
latch addresses and data needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully erased when shipped from the factory.
Device programming and erasure are initiated through command sequences. Once a program or erase
operation begins, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or
monitor the Ready/Busy# (RY/BY#) output to determine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write
cycles to program data instead of four.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations
during power transitions. The hardware sector protection feature disables both program and erase operations
in any combination of sectors of memory. This can be achieved in-system or via programming equipment.
The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given
sector to read or program any other sector and then complete the erase operation. The Program Suspend/
Program Resume feature enables the host system to pause a program operation in a given sector to read
any other sector and then complete the program operation.
The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device.
The device reduces power consumption in the standby mode when it detects specific voltage levels on CE#
and RESET#, or when addresses are stable for a specified period of time.
The Write Protect (WP#) feature protects the first or last sector by asserting a logic low on the WP#/ACC pin
or WP# pin, depending on model number. The protected sector is still protected even during accelerated
programming.
The Secured Silicon Sector provides a 128-word/256-byte area for code or data that can be permanently
protected. Once this sector is protected, no further changes within the sector can occur.
Spansion MirrorBit flash technology combines years of Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a
sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection.
4
S29GL-A
S29GL-A_00_A11 September 10, 2007
D a t a S h e e t
Table of Contents
Distinctive Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.
2.
3.
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
Special Package Handling Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.
5.
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Logic Symbol–S29GL064A (Models R1, R2, R8, R9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Logic Symbol–S29GL064A (Models R3, R4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Logic Symbol–S29GL064A (Model R5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Logic Symbol–S29GL064A (Models R6, R7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Logic Symbol–S29GL032A (Models R1, R2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Logic Symbol–S29GL032A (Models R3, R4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Logic Symbol–S29GL032A (Models W3, W4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Logic Symbol–S29GL016A (Models R1, R2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Logic Symbol–S29GL016A (Models W1, W2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.
7.
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1
6.2
6.3
S29GL016A Standard Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
S29GL032A Standard Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
S29GL064A Standard Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
Word/Byte Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Requirements for Reading Array Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Automatic Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
RESET#: Hardware Reset Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Sector Group Protection and Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.10 Temporary Sector Group Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.11 Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.12 Write Protect (WP#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.13 Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.
9.
Common Flash Memory Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.1
9.2
9.3
9.4
9.5
9.6
Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Autoselect Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Enter/Exit Secured Silicon Sector Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Program Suspend/Program Resume Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . 57
Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10. Sector Erase Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.1 Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
10.2 Command Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.3 Write Operation Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10.4 DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10.5 RY/BY#: Ready/Busy#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10.6 DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10.7 DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10.8 Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
10.9 DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
September 10, 2007 S29GL-A_00_A11
S29GL-A
5
D a t a S h e e t
10.10 DQ3: Sector Erase Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
10.11 DQ1: Write-to-Buffer Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
11. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
12. Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
13. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
13.1 CMOS Compatible. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
14. Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
15. Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
16. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
17. Erase And Programming Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
18. Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
18.1 TS048—48-Pin Standard Thin Small Outline Package (TSOP) . . . . . . . . . . . . . . . . . . . . . . 88
18.2 TS056—56-Pin Standard Thin Small Outline Package (TSOP) . . . . . . . . . . . . . . . . . . . . . . 89
18.3 LAA064—64-Ball Fortified Ball Grid Array (BGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
18.4 VBN048—48-Ball Fine-pitch Ball Grid Array (BGA) 10x 6 mm Package. . . . . . . . . . . . . . . . 91
18.5 VBK048—Ball Fine-pitch Ball Grid Array (BGA) 8.15x 6.15 mm Package . . . . . . . . . . . . . . 92
18.6 VBU056—Ball Fine-pitch Ball Grid Array (BGA) 9 x 7 mm Package. . . . . . . . . . . . . . . . . . . 93
19. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6
S29GL-A
S29GL-A_00_A11 September 10, 2007
D a t a S h e e t
Figures
Figure 3.1
Figure 3.2
Figure 3.3
Figure 3.4
Figure 3.5
Figure 7.1
Figure 7.2
Figure 9.1
Figure 9.2
Figure 9.3
48-Pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
56-Pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
64-ball Fortified BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
56-Ball Fine-Pitch Ball Grid Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
48-ball Fine-pitch BGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Temporary Sector Group Unprotect Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
In-System Sector Group Protect/Unprotect Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Write Buffer Programming Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Program Suspend/Program Resume. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 10.1 Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 10.2 Command Definitions (x16 Mode, BYTE# = VIH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 10.3 Data# Polling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 10.4 Toggle Bit Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 11.1 Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 11.2 Maximum Positive Overshoot Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 14.1 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 15.1 Input Waveforms and Measurement Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 16.1
VCC Power-up Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 16.2 Read Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 16.3 Page Read Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 16.4 Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 16.5 Program Operation Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 16.6 Accelerated Program Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 16.7 Chip/Sector Erase Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 16.8 Data# Polling Timings (During Embedded Algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 16.9 Toggle Bit Timings (During Embedded Algorithms). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 16.10 DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 16.11 Temporary Sector Group Unprotect Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 16.12 Sector Group Protect and Unprotect Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 16.13 Alternate CE# Controlled Write (Erase/Program) Operation Timings . . . . . . . . . . . . . . . . . . 86
September 10, 2007 S29GL-A_00_A11
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D a t a S h e e t
Tables
Table 1.1
Table 6.1
Table 6.2
Table 6.3
Table 7.1
Table 7.2
Table 7.3
Table 7.4
Table 7.5
Table 7.6
Table 7.7
Table 7.8
Table 7.9
Table 7.10
Table 7.11
Table 7.12
Table 7.13
Table 7.14
Table 7.15
Table 7.16
Table 7.17
Table 7.18
Table 7.19
Table 7.20
Table 7.21
Table 7.22
Table 8.1
Table 8.2
Table 8.3
Table 8.4
Table 10.1
Table 10.2
Table 14.1
Table 16.1
Table 16.2
Table 16.3
Table 16.4
Table 16.5
Table 16.6
Table 16.7
Table 16.8
Table 16.9
S29GL064A, S29GL032A, S29GL016A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
S29GL016A Ordering Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
S29GL032A Ordering Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
S29GL064A Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
S29GL016A (Model R1, W1) Top Boot Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . .25
S29GL016A (Model R2, W2) Bottom Boot Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . .26
S29GL032A (Models R1, R2) Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
S29GL032A (Model R3, W3) Top Boot Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . .28
S29GL032A (Model R4, W4) Bottom Boot Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . .29
S29GL064A (Models R1, R2, R8, R9) Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
S29GL064A (Model R3) Top Boot Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
S29GL064A (Model R4) Bottom Boot Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
S29GL064A (Model R5) Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
S29GL064A (Models R6, R7) Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Autoselect Codes, (High Voltage Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
S29GL016A (Model R1, 01) Sector Group Protection/Unprotection Addresses . . . . . . . . . . .41
S29GL016A (Model R2, 02) Sector Group Protection/Unprotection Addresses . . . . . . . . . . .41
S29GL032A (Models R1, R2) Sector Group Protection/Unprotection Addresses . . . . . . . . .42
S29GL032A (Model R3, W3) Sector Group Protection/Unprotection Address Table . . . . . . .42
S29GL032A (Model R4, W4) Sector Group Protection/Unprotection Address Table . . . . . . .42
S29GL064A (Models R1, R2, R8, R9) Sector Group Protection/Unprotection Addresses . . .43
S29GL064A (Model R3) Top Boot Sector Protection/Unprotection Addresses . . . . . . . . . . .43
S29GL064A (Model R4) Bottom Boot Sector Protection/Unprotection Addresses . . . . . . . . .44
S29GL064A (Model R5) Sector Group Protection/Unprotection Addresses . . . . . . . . . . . . . .44
S29GL064A (Models R6, R7) Sector Group Protection/Unprotection Addresses . . . . . . . . .45
CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Command Definitions (x8 Mode, BYTE# = VIL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Read-Only Operations-S29GL064A Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Read-Only Operations-S29GL032A Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Read-Only Operation-S29GL016A Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Erase and Program Operations-S29GL064A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Erase and Program Operations-S29GL032A Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Erase and Program Operations-S29GL016A Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Temporary Sector Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Alternate CE# Controlled Erase and Program Operations-S29GL064A . . . . . . . . . . . . . . . . .83
Table 16.10 Alternate CE# Controlled Erase and Program Operations-S29GL032A . . . . . . . . . . . . . . . . .84
Table 16.11 Alternate CE# Controlled Erase and Program Operations-S29GL016A . . . . . . . . . . . . . . . . .85
Table 17.1
TSOP Pin and BGA Package Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
8
S29GL-A
S29GL-A_00_A11 September 10, 2007
D a t a S h e e t
1. Product Selector Guide
Table 1.1 S29GL064A, S29GL032A, S29GL016A
Part Number
Speed Option
S29GL064A
S29GL032A
S29GL016A
90
90
90
25
25
10
100
100
30
11
110
110
30
90
90
90
25
25
10
100
100
30
11
110
110
30
90
90
90
25
25
10
100
100
30
Max. Access Time (ns)
Max. CE# Access Time (ns)
Max. Page Access Time (ns)
Max. OE# Access Time (ns)
30
30
30
30
30
2. Block Diagram
DQ15–DQ0 (A-1)
RY/BY#
VCC
VSS
Sector Switches
Erase Voltage
Generator
Input/Output
Buffers
RESET#
WE#
WP#/ACC
BYTE#
State
Control
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
X-Decoder
Y-Gating
STB
VCC Detector
Timer
Cell Matrix
AMax**–A0
Note
**A
**A
**A
GL064A = A21.
GL032A = A20.
GL016A = A19.
MAX
MAX
MAX
September 10, 2007 S29GL-A_00_A11
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3. Connection Diagrams
3.1
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages (TSOP and BGA). The package
and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for
prolonged periods of time.
Figure 3.1 48-Pin Standard TSOP
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
1
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
A8
1
3
48-Pin Standard TSOP
A19
A20
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE#
V
RESET#
CC
1,2
A21
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
1
1
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
V
SS
CE#
A0
Notes
1. Pin 9 is A21, Pin 13 is ACC, Pin 14 is WP#, Pin 15 is A19, and Pin 47 is V on S29GL064A (models R6, R7).
IO
2. Pin 13 is NC on S29GL032A, and S29GL016A.
3. Pin 10 is NC on S29GL016A.
10
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D a t a S h e e t
Figure 3.2 56-Pin Standard TSOP
NC on S29GL032A
NC
NC
1
2
3
4
5
6
7
8
9
56 NC
55 NC
A15
A14
A13
A12
A11
A10
A9
54 A16
53 BYTE#
52 VSS
51 DQ15/A-1
50 DQ7
49 DQ14
48 DQ6
47 DQ13
46 DQ5
45 DQ12
44 DQ4
43 VCC
42 DQ11
41 DQ3
40 DQ10
39 DQ2
38 DQ9
37 DQ1
36 DQ8
35 DQ0
34 OE#
33 VSS
56-Pin Standard TSOP
A8 10
A19 11
A20 12
WE# 13
RESET# 14
A21
15
WP#/ACC 16
RY/BY# 17
A18 18
A17 19
A7 20
A6 21
A5 22
A4 23
A3 24
A2 25
32 CE#
31 A0
30 NC
29 VIO
A1 26
NC 27
NC 28
September 10, 2007 S29GL-A_00_A11
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D a t a S h e e t
Figure 3.3 64-ball Fortified BGA
64-ball Fortified BGA
Top View, Balls Facing Down
A8
NC
B8
NC
C8
NC
D8
E8
F8
G8
NC
H8
NC
1
V
V
NC
IO
SS
A7
B7
C7
D7
E7
F7
G7
H7
2
V
SS
A13
A12
A14
A15
A16
BYTE# DQ15/A-1
A6
A9
B6
A8
C6
D6
E6
F6
G6
H6
A10
A11
DQ7
DQ14
DQ13
DQ6
A5
B5
C5
D5
E5
F5
G5
H5
3
V
CC
WE#
RESET#
A21
A19
DQ5
DQ12
DQ4
A4
B4
C4
D4
E4
F4
G4
H4
4
RY/BY# WP#/ACC
A18
A20
DQ2
DQ10
DQ11
DQ3
A3
A7
B3
C3
A6
D3
A5
E3
F3
G3
H3
A17
DQ0
DQ8
DQ9
DQ1
A2
A3
B2
A4
C2
A2
D2
A1
E2
A0
F2
G2
H2
V
SS
CE#
OE#
A1
NC
B1
NC
C1
NC
D1
NC
E1
F1
1
G1
NC
H1
NC
NC
V
IO
Notes
1. Ball D8 and Ball F1 are NC on S29GL064A (models R3, R4) and S29GL016A (Models 01, 02, R1, R2).
2. Ball F7 is NC on S29GL064A (model R5).
3. Ball C5 is NC on S29GL032A and S29GL016A.
4. Ball D4 is NC on S29GL016A.
12
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Figure 3.4 56-Ball Fine-Pitch Ball Grid Array
56-Ball Fine-Pitch Ball Grid Array
Top View, Balls Facing Down
A2
A7
B2
A6
C2
A5
D2
A4
A3
RFU
B3
A4
WP/ACC
B4
A5
WE#
B5
A6
A8
A7
A11
B7
B1
A3
B6
B8
A15
C8
Legend
RFU
RFU
C3
RST
RFU
C5
A19
C6
A12
C7
C1
A2
C4
A18
D3
RY/BY#
RFU
A9
D6
A13
D7
RFU
D8
D1
A1
A10
E6
A14
E7
RFU
E8
A17
E3
E1
E2
VSS
DQ6
RFU
A16
A0
DQ1
F3
F1
F2
F4
F5
F6
F7
F8
CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
RFU
G1
G2
G3
DQ10
H3
G4
G5
G6
G7
G8
RFU
DQ0
VCC
RFU
DQ12
DQ7
VSS
H2
H4
H5
H6
H7
DQ8
DQ2
DQ11
DQ5
DQ14
RFU
Note
MCP-compatible Connection Diagram for cellular handsets only.
September 10, 2007 S29GL-A_00_A11
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D a t a S h e e t
Figure 3.5 48-ball Fine-pitch BGA
48-ball Fine-pitch BGA
Top View, Balls Facing Down
A6
B6
C6
D6
E6
F6
G6
H6
1
V
SS
A13
A12
A14
A15
A16
BYTE#
DQ15/A-1
A5
A9
B5
A8
C5
D5
E5
F5
G5
H5
A10
A11
DQ7
DQ14
DQ13
DQ6
A4
B4
C4
D4
E4
F4
G4
H4
2
V
WE#
RESET#
A21
A19
DQ5
DQ12
CC
DQ4
A3
B3
C3
D3
E3
F3
G3
H3
3
RY/BY# WP#/ACC
A18
A20
DQ2
DQ10
DQ11
DQ3
A2
A7
B2
C2
A6
D2
A5
E2
F2
G2
H2
A17
DQ0
DQ8
DQ9
DQ1
A1
A3
B1
A4
C1
A2
D1
A1
E1
A0
F1
G1
H1
V
SS
CE#
OE#
Notes
1. Ball F6 is V on S29GL064A (model R5).
IO
2. Ball C4 is NC on S29GL032A and S29GL016A.
3. Ball D3 is NC on S29GL016A.
14
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S29GL-A_00_A11 September 10, 2007
D a t a S h e e t
4. Pin Descriptions
A21–A0
A20–A0
A19–A0
DQ7–DQ0
DQ14–DQ0
DQ15/A-1
CE#
22 Address inputs
21 Address inputs
20 Address inputs
8 Data inputs/outputs
15 Data inputs/outputs
DQ15 (Data input/output, word mode), A-1 (LSB Address input, byte mode)
Chip Enable input
OE#
Output Enable input
WE#
Write Enable input
WP#/ACC
ACC
Hardware Write Protect input/Programming Acceleration input
Acceleration input
WP#
Hardware Write Protect input
Hardware Reset Pin input
Ready/Busy output
RESET#
RY/BY#
BYTE#
Selects 8-bit or 16-bit mode
3.0 volt-only single power supply
V
CC
(See Product Selector Guide on page 9 for speed options and voltage supply tolerances)
V
Device Ground
SS
NC
Pin Not Connected Internally
Output Buffer Power
V
IO
5. Logic Symbols
5.1
Logic Symbol–S29GL064A (Models R1, R2, R8, R9)
22
A21–A0
16 or 8
DQ15–DQ0
(A-1)
CE#
OE#
WE#
WP#/ACC
RESET#
BYTE#
VIO
RY/BY#
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D a t a S h e e t
5.2
5.3
5.4
Logic Symbol–S29GL064A (Models R3, R4)
22
A21–A0
16 or 8
DQ15–DQ0
(A-1)
CE#
OE#
WE#
WP#/ACC
RESET#
BYTE#
RY/BY#
Logic Symbol–S29GL064A (Model R5)
22
A21–A0
16
DQ15–DQ0
CE#
OE#
WE#
ACC
RESET#
VIO
RY/BY#
Logic Symbol–S29GL064A (Models R6, R7)
22
A21–A0
16
DQ15–DQ0
CE#
OE#
WE#
WP#
ACC
RESET#
RESET#
VIO
16
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D a t a S h e e t
5.5
5.6
5.7
Logic Symbol–S29GL032A (Models R1, R2)
21
A20–A0
16 or 8
DQ15–DQ0
CE#
OE#
WE#
(A-1)
WP#/ACC
RESET#
BYTE#
RY/BY#
VIO
Logic Symbol–S29GL032A (Models R3, R4)
21
A20–A0
16 or 8
DQ15–DQ0
CE#
OE#
WE#
(A-1)
WP#/ACC
RESET#
RY/BY#
BYTE#
Logic Symbol–S29GL032A (Models W3, W4)
21
A20–A0
16
DQ15–DQ0
CE#
OE#
WE#
WP#/ACC
RESET#
RY/BY#
September 10, 2007 S29GL-A_00_A11
S29GL-A
17
D a t a S h e e t
5.8
Logic Symbol–S29GL016A (Models R1, R2)
20
A19–A0
16 or 8
DQ15–DQ0
(A-1)
CE#
OE#
WE#
WP#/ACC
RESET#
BYTE#
RY/BY#
5.9
Logic Symbol–S29GL016A (Models W1, W2)
20
A19–A0
16
DQ15–DQ0
CE#
OE#
WE#
WP#/ACC
RESET#
RY/BY#
18
S29GL-A
S29GL-A_00_A11 September 10, 2007
D a t a S h e e t
6. Ordering Information
6.1
S29GL016A Standard Products
Standard products are available in several packages and operating ranges. The order number (Valid
Combination) is formed by a combination of the following:
S29GL016A
10
T
A
I
R1
0
Packing Type
0
2
3
= Tray
= 7-inch Tape and Reel
= 13-inch Tape and Reel
Model Number
R1 = x8/x16, V =3.0 – 3.6 V, Top boot sector device, top two address sectors protected
CC
when WP#/ACC=V
IL
R2 = x8/x16, V =3.0 – 3.6 V, Bottom boot sector device, bottom two address sectors
CC
protected when WP#/ACC=V
IL
01 = x8/x16, Vcc = 2.7 - 3.6 V, Top boot sector device, top two address sectors protected
when WP#/ACC = V
IL
02 = x8/x16, Vcc = 2.7 - 3.6 V, Bottom boot sector device, bottom two address sectors
protected when WP#/ACC = V
IL
W1= x16, V =2.7 – 3.6 V, 56-ball FBGA, top boot sector device*
CC
W2= x16, V =2.7 – 3.6 V, 56-ball FBGA, bottom boot sector device*
CC
*W1 and W2 are MCP-compatible packages for cellular handsets only
Temperature Range
I
= Industrial (–40°C to +85°C)
Package Material Set
A
F
= Standard
= Pb-Free
Package Type
T
B
F
= Thin Small Outline Package (TSOP) Standard Pinout
= Fine-pitch Ball-Grid Array Package
= Fortified Ball-Grid Array Package
Speed Option
See Product Selector Guide on page 9 and Valid Combinations below
Device Number/Description
S29GL016A
3.0 Volt-only, 16 Megabit Page-Mode Flash Memory Manufactured on 200 nm MirrorBit® Process Technology.
Table 6.1 S29GL016A Ordering Options
S29GL016A Valid Combinations
Device
Number
Speed
Option
Package, Material,
& Temperature Range
Model
Number
Packing
Type (Note 1)
Package Description
(Notes)
TAI, TFI
BAI, BFI
FAI, FFI
0, 3
TS048 (Note 2)
TSOP
90, 10
10
R1, R2
W1, W2
01, 02
VBK048 (Note 3)
LAA064 (Note 3)
Fine-Pitch BGA
Fortified BGA
0, 2, 3
Fine-Pitch BGA
(For cellular handsets only)
S29GL016A
BAI, BFI
VBU056 (Note 3)
TAI, TFI
BAI, BFI
FAI, FFI
0, 3
TS048 (Note 2)
VBK048 (Note 3)
LAA064 (Note 3)
TSOP
10
Fine-Pitch BGA
Fortified BGA
0, 2, 3
Notes
1. Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3; BGAs can be packed in Types 0, 2, or 3.
2. TSOP package marking omits packing type designator from ordering part number.
3. BGA package marking omits leading S29 and packing type designator from ordering part number.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
September 10, 2007 S29GL-A_00_A11
S29GL-A
19
D a t a S h e e t
6.2
S29GL032A Standard Products
Standard products are available in several packages and operating ranges. The order number (Valid
Combination) is formed by a combination of the following:
S29GL032A
90
T
A
I
R1
0
Packing Type
0
2
3
= Tray
= 7-inch Tape and Reel
= 13-inch Tape and Reel
Model Number
R1 = x8/x16, V =3.0 – 3.6 V, Uniform sector device, highest address sector protected
CC
when WP#/ACC=V
IL
R2 = x8/x16, V =3.0 – 3.6 V, Uniform sector device, lowest address sector protected
CC
when WP#/ACC=V
IL
R3 = x8/x16, V =3.0 – 3.6 V, Top boot sector device, top two address sectors
CC
protected when WP#/ACC=V
IL
R4 = x8/x16, V =3.0 – 3.6 V, Bottom boot sector device, bottom two address sectors
CC
protected when WP#/ACC=V
IL
W3= x16, V =2.7 – 3.6 V, 56-ball FBGA, top boot sector device *
CC
W4= x16, V =2.7 – 3.6 V, 56-ball FBGA, bottom boot sector device*
CC
*W3 and W4 are MCP-compatible packages for cellular handsets only
Temperature Range
I
= Industrial (–40°C to +85°C)
Package Material Set
A
F
= Standard
= Pb-Free
Package Type
T
B
F
= Thin Small Outline Package (TSOP) Standard Pinout
= Fine-pitch Ball-Grid Array Package
= Fortified Ball-Grid Array Package
Speed Option
See Product Selector Guide on page 9 and Valid Combinations below
Device Number/Description
S29GL032A
32 Megabit Page-Mode Flash Memory Manufactured using 200 nm MirrorBit® Process Technology, 3.0 Volt-only Read,
Program, and Erase
Table 6.2 S29GL032A Ordering Options
S29GL032A Valid Combinations
Package, Material,
& Temperature
Range
Packin
g
Type
Device
Number
Speed
Option
Model
Number
Package Description
(Notes)
TAI,TFI
FAI,FFI
TAI,TFI
BAI,BFI
FAI,FFI
BAI,BFI
TS056 (Note 2)
LAA064 (Note 3)
TS048 (Note 2)
VBK048 (Note 3)
LAA064 (Note 3)
VBU056 (Note 3)
TSOP
R1, R2
Fortified BGA
90, 10, 11
TSOP
0,2,3
S29GL032A
(Note 1)
R3,R4
Fine-Pitch BGA
Fortified BGA
10, 11
W3,W4
Fine-Pitch BGA (For cellular handsets only)
Notes
1. Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3; BGAs can be packed in Types 0, 2, or 3.
2. TSOP package marking omits packing type designator from ordering part number.
3. BGA package marking omits leading S29 and packing type designator from ordering part number.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
20
S29GL-A
S29GL-A_00_A11 September 10, 2007
D a t a S h e e t
6.3
S29GL064A Standard Products
Standard products are available in several packages and operating ranges. The order number (Valid
Combination) is formed by a combination of the following:
S29GL064A
90
T
A
I
R1
2
Packing Type
0
2
3
= Tray
= 7-inch Tape and Reel
= 13-inch Tape and Reel
Model Number
R1 = x8/x16, V =3.0 – 3.6 V, Uniform sector device, highest address sector
CC
protected when WP#/ACC=V
IL
R2 = x8/x16, V =3.0 – 3.6 V, Uniform sector device, lowest address sector
CC
protected when WP#/ACC=V
IL
R3 = x8/x16, V =3.0 – 3.6 V, Top boot sector device, top two address sectors
CC
protected when WP#/ACC=V
IL
R4 = x8/x16, V =3.0 – 3.6 V, Bottom boot sector device, bottom two address
CC
sectors protected when WP#/ACC=V
IL
R5 = x16, V =3.0 – 3.6 V, Uniform sector device
CC
R6 = x16, V =3.0 – 3.6 V, Uniform sector device, highest address sector protected
CC
when WP#=V
IL
R7 = x16, V =3.0 – 3.6 V, Uniform sector device, lowest address sector protected
CC
when WP#=V
IL
R8 = x8/x16, V =3.0 – 3.6 V, Uniform sector device, highest address sector
CC
protected when WP#=V TSO48 only
IL,
R9 = x8/x16, V =3.0 – 3.6 V, Uniform sector device, lowest address sector
CC
protected when WP#=V TSO48 only
IL,
Temperature Range
= Industrial (–40°C to +85°C)
I
Package Material Set
A
= Standard
F
= Pb-Free
Package Type
T
B
F
= Thin Small Outline Package (TSOP) Standard Pinout
= Fine-pitch Ball-Grid Array Package
= Fortified Ball-Grid Array Package
Speed Option
See Product Selector Guide on page 9 and Valid Combinations below
Device Number/Description
S29GL064A, 64 Megabit Page-Mode Flash Memory Manufactured using 200 nm MirrorBit® Process Technology, 3.0 Volt-only Read,
Program, and Erase
Table 6.3 S29GL064A Valid Combinations
S29GL064A Valid Combinations
Packin
Device
Number
Speed
Option
Package, Material &
Temperature Range
g
Type
Model Number
R3, R4, R6, R7, R8, R9
R1, R2
Package Description
TS048 (Note 2)
TS056 (Note 2)
TSOP
TSOP
TAI, TFI
0, 2, 3
S29GL064A
90, 10, 11
(Note 1)
BAI, BFI
FAI, FFI
R3, R4, R5
VBN048 (Note 3) Fine-pitch BGA
LAA064 (Note 3) Fortified BGA
R1, R2, R3, R4, R5
Notes
1. Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3; BGAs can be packed in Types 0, 2, or 3.
2. TSOP package marking omits packing type designator from ordering part number.
3. BGA package marking omits leading S29 and packing type designator from ordering part number.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
September 10, 2007 S29GL-A_00_A11
S29GL-A
21
D a t a S h e e t
7. Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the
internal command register. The command register itself does not occupy any addressable memory location.
The register is a latch used to store the commands, along with the address and data information needed to
execute the command. The contents of the register serve as inputs to the internal state machine. The state
machine outputs dictate the function of the device. Table 7.1 lists the device bus operations, the inputs and
control levels they require, and the resulting output. The following subsections describe each of these
operations in further detail.
Table 7.1 Device Bus Operations
DQ8–DQ15
Addresses
(Note 1)
DQ0–
DQ7
BYTE#
BYTE#
= V
Operation
CE#
OE#
L
WE# RESET#
WP#
X
ACC
X
= V
IH
IL
Read
L
L
L
H
L
L
H
H
H
A
A
A
D
D
OUT
IN
IN
IN
OUT
DQ8–DQ14
= High-Z,
DQ15 = A-1
Write (Program/Erase)
Accelerated Program
H
(Note 3)
(Note 3)
X
(Note 4) (Note 4)
(Note 4) (Note 4)
H
V
HH
V
0.3 V
CC
Standby
V
0.3 V
X
X
X
H
X
High-Z
High-Z
High-Z
CC
Output Disable
Reset
L
H
X
H
X
H
L
X
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
X
SA, A6 =L,
A3=L, A2=L, (Note 4)
A1=H, A0=L
Sector Group Protect
(Note 2)
L
H
L
V
H
X
X
X
X
ID
SA, A6=H,
A3=L, A2=L, (Note 4)
A1=H, A0=L
Sector Group Unprotect
(Note 2)
L
H
X
L
V
V
H
H
X
X
X
ID
Temporary Sector Group
Unprotect
X
X
A
(Note 4) (Note 4)
High-Z
ID
IN
Legend
L = Logic Low = V , H = Logic High = V , X = Don’t Care, V = 11.5–12.5 V, V = 11.5–12.5 V, SA = Sector Address,
IL
IH
ID
HH
A
= Address In, D = Data In, D = Data Out
IN
IN
OUT
Notes
1. Addresses are Amax:A0 in word mode; Amax: A-1 in byte mode. Sector addresses are Amax:A15 in both modes.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See Sector Group Protection
and Unprotection on page 41.
3. If WP# = VIL, the first or last sector remains protected (for uniform sector devices), and the two outer boot sectors are protected (for boot
sector devices). If WP# = VIH, the first or last sector, or the two outer boot sectors are protected or unprotected as determined by the
method described in Sector Group Protection and Unprotection on page 41. All sectors are unprotected when shipped from the factory
(The Secured Silicon Sector may be factory protected depending on version ordered.)
4.
D
or D
as required by command sequence, data polling, or sector protect algorithm (see Figure 10.3 on page 64).
OUT
IN
22
S29GL-A
S29GL-A_00_A11 September 10, 2007
D a t a S h e e t
7.1
7.2
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the
BYTE# pin is set at logic 1, the device is in word configuration, DQ0–DQ15 are active and controlled by CE#
and OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used
as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control and gates array data to the output pins. WE# should
remain at VIH.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the device data outputs. The device remains enabled for
read access until the command register contents are altered.
See Reading Array Data on page 52 for more information. Refer to the AC Read-Only Operations table in AC
Characteristics on page 72 for timing specifications and the timing diagram. Refer to DC Characteristics
on page 70 for the active current specification on reading array data.
7.2.1
Page Mode Read
The device is capable of fast page mode read and is compatible with the page mode Mask ROM read
operation. This mode provides faster read access speed for random locations within a page. The page size of
the device is 4 words/8 bytes. The appropriate page is selected by the higher address bits A(max)–A2.
Address bits A1–A0 in word mode (A1–A-1 in byte mode) determine the specific word within a page. This is
an asynchronous operation; the microprocessor supplies the specific word location.
The random or initial page access is equal to tACC or tCE and subsequent page read accesses (as long as the
locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is
deasserted and reasserted for a subsequent access, the access time is tACC or tCE. Fast page mode
accesses are obtained by keeping the read-page addresses constant and changing the intra-read page
addresses.
7.3
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to program a word, instead of four. The Word
Program Command Sequence on page 53 contains details on programming data to the device using both
standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 7.4 on page 27 to
Table 7.22 on page 45 indicate the address space that each sector occupies.
Refer to DC Characteristics on page 70 for the active current specification for the write mode. AC
Characteristics on page 72 contains timing specification tables and timing diagrams for write operations.
September 10, 2007 S29GL-A_00_A11
S29GL-A
23
D a t a S h e e t
7.3.1
7.3.2
Write Buffer
Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming
operation. This results in faster effective programming time than the standard programming algorithms. See
Write Buffer on page 24 for more information.
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This is one of two functions
provided by the WP#/ACC or ACC pin, depending on model number. This function is primarily intended to
allow faster manufacturing throughput at the factory.
If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sector groups, and uses the higher voltage on the pin to reduce
the time required for program operations. The system would use a two-cycle program command sequence as
required by the Unlock Bypass mode. Removing VHH from the WP#/ACC or ACC pin, depending on model
number, returns the device to normal operation. Note that the WP#/ACC or ACC pin must not be at VHH for
operations other than accelerated programming, or device damage may result. WP# contains an internal pull-
up; when unconnected, WP# is at VIH.
7.3.3
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode. The system
can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–
DQ0. Standard read cycle timings apply in this mode. Refer to Autoselect Mode on page 40 and Autoselect
Command Sequence on page 53 for more information.
7.4
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state,
independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VIO 0.3 V.
(Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within
VIO 0.3 V, the device is in the standby mode, but the standby current is greater. The device requires
standard access time (tCE) for read access when the device is in either of these standby modes, before it is
ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation
is completed.
Refer to DC Characteristics on page 70 for the standby current specification.
7.5
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and always available to the system. Refer to DC
Characteristics on page 70 for the automatic sleep mode current specification.
24
S29GL-A
S29GL-A_00_A11 September 10, 2007
D a t a S h e e t
7.6
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the
RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in
progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The operation that was interrupted
should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS 0.3 V, the device
draws CMOS standby current (ICC5). If RESET# is held at VIL but not within VSS 0.3 V, the standby current is
greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
Refer to the tables in AC Characteristics on page 72 for RESET# parameters and to Figure 16.4 on page 75
for the timing diagram.
7.7
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high
impedance state.
Table 7.2 S29GL016A (Model R1, W1) Top Boot Sector Addresses
Sector
Size
(KB/
Sector
Size
(KB/
8-bit Address
Range
16-bit Address
Range
8-bit Address
Range
16-bit Address
Range
Sector
A19–A12
000000xxx
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
001000xxx
001001xxx
001010xxx
001011xxx
001100xxx
001101xxx
001101xxx
001111xxx
010000xxx
010001xxx
010010xxx
010011xxx
Kwords)
Sector A19–A12 Kwords)
SA0
SA1
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000h–00FFFFh
00000h–07FFFh
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
010100xxx
010101xxx
010110xxx
010111xxx
011000xxx
011001xxx
011010xxx
011011xxx
011000xxx
011101xxx
011110xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
1D0000h–1DFFFFh
1E0000h–1EFFFFh
1F0000h–1F1FFFh
1F2000h–1F3FFFh
1F4000h–1F5FFFh
1F6000h–1F7FFFh
1F8000h–1F9FFFh
1FA000h–1FBFFFh
1FC000h–1FDFFFh
1FE000h–1FFFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
0F8000h–0F8FFFh
0F9000h–0F9FFFh
0FA000h–0FAFFFh
0FB000h–0FBFFFh
0FC000h–0FCFFFh
0FD000h–0FDFFFh
0FE000h–0FEFFFh
0FF000h–0FFFFFh
010000h–01FFFFh 08000h–0FFFFh
020000h–02FFFFh 10000h–17FFFh
030000h–03FFFFh 18000h–1FFFFh
040000h–04FFFFh 20000h–27FFFh
050000h–05FFFFh 28000h–2FFFFh
060000h–06FFFFh 30000h–37FFFh
070000h–07FFFFh 38000h–3FFFFh
080000h–08FFFFh 40000h–47FFFh
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
090000h–09FFFFh 48000h–4FFFFh
0A0000h–0AFFFFh 50000h–57FFFh
0B0000h–0BFFFFh 58000h–5FFFFh
0C0000h–0CFFFFh 60000h–67FFFh
0D0000h–0DFFFFh 68000h–6FFFFh
0E0000h–0EFFFFh 70000h–77FFFh
0F0000h–0FFFFFh 78000h–7FFFFh
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA31 111111000
SA32 111111001
SA33 111111010
SA34 111111011
SA35 111111100
SA36 111111101
SA37 111111110
SA38 111111111
8/4
8/4
8/4
8/4
100000h–00FFFFh
110000h–11FFFFh 88000h–8FFFFh
120000h–12FFFFh 90000h–97FFFh
130000h–13FFFFh 98000h–9FFFFh
80000h–87FFFh
8/4
8/4
8/4
September 10, 2007 S29GL-A_00_A11
S29GL-A
25
D a t a S h e e t
Table 7.3 S29GL016A (Model R2, W2) Bottom Boot Sector Addresses
Sector
Size
Sector
Size
(KB/
Kwords)
8-bit Address
Range
16-bit Address
Range
(KB/
Kwords)
8-bit Address
Range
16-bit Address
Range
Sector
SA0
A19–A12
000000000
000000001
000000010
000000011
000000100
000000101
000000110
000000111
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
001000xxx
001001xxx
001010xxx
001011xxx
Sector
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
A19–A12
001100xxx
001101xxx
001101xxx
001111xxx
010000xxx
010001xxx
010010xxx
010011xxx
010100xxx
010101xxx
010110xxx
010111xxx
011000xxx
011001xxx
011010xxx
011011xxx
011000xxx
011101xxx
011110xxx
011111xxx
8/4
8/4
000000h–001FFFh
002000h–003FFFh
004000h–005FFFh
006000h–007FFFh
008000h–009FFFh
00A000h–00BFFFh
00C000h–00DFFFh
00000h–00FFFh
01000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–04FFFh
05000h–05FFFh
06000h–06FFFh
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–00FFFFh
110000h–11FFFFh
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
SA1
SA2
8/4
SA3
8/4
SA4
8/4
SA5
8/4
SA6
8/4
SA7
8/4
00E000h–00FFFFFh 07000h–07FFFh
SA8
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
1A0000h–1AFFFFh D0000h–D7FFFh
1B0000h–1BFFFFh D8000h–DFFFFh
1C0000h–1CFFFFh E0000h–E7FFFh
1D0000h–1DFFFFh E8000h–EFFFFh
1E0000h–1EFFFFh
1F0000h–1FFFFFh
F0000h–F7FFFh
F8000h–FFFFFh
26
S29GL-A
S29GL-A_00_A11 September 10, 2007
D a t a S h e e t
Table 7.4 S29GL032A (Models R1, R2) Sector Addresses
Sector
Size
(KB/
Sector
Size
(KB/
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
Sector
A20-A15
Kwords)
Sector
A20-A15
Kwords)
SA0 0 0 0 0 0 0
SA1 0 0 0 0 0 1
SA2 0 0 0 0 1 0
SA3 0 0 0 0 1 1
SA4 0 0 0 1 0 0
SA5 0 0 0 1 0 1
SA6 0 0 0 1 1 0
SA7 0 0 0 1 1 1
SA8 0 0 1 0 0 0
SA9 0 0 1 0 0 1
SA10 0 0 1 0 1 0
SA11 0 0 1 0 1 1
SA12 0 0 1 1 0 0
SA13 0 0 1 1 0 1
SA14 0 0 1 1 1 0
SA15 0 0 1 1 1 1
SA16 0 1 0 0 0 0
SA17 0 1 0 0 0 1
SA18 0 1 0 0 1 0
SA19 0 1 0 0 1 1
SA20 0 1 0 1 0 0
SA21 0 1 0 1 0 1
SA22 0 1 0 1 1 0
SA23 0 1 0 1 1 1
SA24 0 1 1 0 0 0
SA25 0 1 1 0 0 1
SA26 0 1 1 0 1 0
SA27 0 1 1 0 1 1
SA28 0 1 1 1 0 0
SA29 0 1 1 1 0 1
SA30 0 1 1 1 1 0
SA31 0 1 1 1 1 1
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1FFFFF
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
SA32 1 0 0 0 0 0
SA33 1 0 0 0 0 1
SA34 1 0 0 0 1 0
SA35 1 0 0 0 1 1
SA36 1 0 0 1 0 0
SA37 1 0 0 1 0 1
SA38 1 0 0 1 1 0
SA39 1 0 0 1 1 1
SA40 1 0 1 0 0 0
SA41 1 0 1 0 0 1
SA42 1 0 1 0 1 0
SA43 1 0 1 0 1 1
SA44 1 0 1 1 0 0
SA45 1 0 1 1 0 1
SA46 1 0 1 1 1 0
SA47 1 0 1 1 1 1
SA48 1 1 0 0 0 0
SA49 1 1 0 0 0 1
SA50 1 1 0 0 1 0
SA51 1 1 0 0 1 1
SA52 1 1 0 1 0 0
SA53 1 1 0 1 0 1
SA54 1 1 0 1 1 0
SA55 1 1 0 1 1 1
SA56 1 1 1 0 0 0
SA57 1 1 1 0 0 1
SA58 1 1 1 0 1 0
SA59 1 1 1 0 1 1
SA60 1 1 1 1 0 0
SA61 1 1 1 1 0 1
SA62 1 1 1 1 1 0
SA63 1 1 1 1 1 1
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
200000–20FFFF
210000–21FFFF
220000–22FFFF
230000–23FFFF
240000–24FFFF
250000–25FFFF
260000–26FFFF
270000–27FFFF
280000–28FFFF
290000–29FFFF
2A0000–2AFFFF
2B0000–2BFFFF
2C0000–2CFFFF
2D0000–2DFFFF
2E0000–2EFFFF
2F0000–2FFFFF
300000–30FFFF
310000–31FFFF
320000–32FFFF
330000–33FFFF
340000–34FFFF
350000–35FFFF
360000–36FFFF
370000–37FFFF
380000–38FFFF
390000–39FFFF
3A0000–3AFFFF
3B0000–3BFFFF
3C0000–3CFFFF
3D0000–3DFFFF
3E0000–3EFFFF
3F0000–3FFFFF
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
September 10, 2007 S29GL-A_00_A11
S29GL-A
27
D a t a S h e e t
Table 7.5 S29GL032A (Model R3, W3) Top Boot Sector Addresses
Sector
Size
(KB/
Sector
Size
(KB/
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
Sector
SA0
A20–A12
000000xxx
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
001000xxx
001001xxx
001010xxx
001011xxx
001100xxx
001101xxx
001101xxx
001111xxx
010000xxx
010001xxx
010010xxx
010011xxx
010100xxx
010101xxx
010110xxx
010111xxx
011000xxx
011001xxx
011010xxx
011011xxx
011100xxx
011101xxx
011110xxx
011111xxx
100000xxx
100001xxx
100010xxx
101011xxx
Kwords)
Sector A20–A12 Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000h–00FFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–00FFFFh
110000h–11FFFFh
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
1D0000h–1DFFFFh
1E0000h–1EFFFFh
1F0000h–1FFFFFh
200000h–20FFFFh
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
F8000h–FFFFFh
F9000h–107FFFh
SA36 100100xxx
SA37 100101xxx
SA38 100110xxx
SA39 100111xxx
SA40 101000xxx
SA41 101001xxx
SA42 101010xxx
SA43 101011xxx
SA44 101100xxx
SA45 101101xxx
SA46 101110xxx
SA47 101111xxx
SA48 110000xxx
SA49 110001xxx
SA50 110010xxx
SA51 110011xxx
SA52 100100xxx
SA53 110101xxx
SA54 110110xxx
SA55 110111xxx
SA56 111000xxx
SA57 111001xxx
SA58 111010xxx
SA59 111011xxx
SA60 111100xxx
SA61 111101xxx
SA62 111110xxx
SA63 111111000
SA64 111111001
SA65 111111010
SA66 111111011
SA67 111111100
SA68 111111101
SA69 111111110
SA70 111111111
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
240000h–24FFFFh
250000h–25FFFFh
260000h–26FFFFh
270000h–27FFFFh
280000h–28FFFFh
290000h–29FFFFh
2A0000h–2AFFFFh
2B0000h–2BFFFFh
2C0000h–2CFFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
2D0000h–2DFFFFh 168000h–16FFFFh
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
2E0000h–2EFFFFh
2F0000h–2FFFFFh
300000h–30FFFFh
310000h–31FFFFh
320000h–32FFFFh
330000h–33FFFFh
340000h–34FFFFh
350000h–35FFFFh
360000h–36FFFFh
370000h–37FFFFh
380000h–38FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
390000h–39FFFFh 1C8000h–1CFFFFh
3A0000h–3AFFFFh 1D0000h–1D7FFFh
3B0000h–3BFFFFh 1D8000h–1DFFFFh
3C0000h–3CFFFFh 1E0000h–1E7FFFh
3D0000h–3DFFFFh 1E8000h–1EFFFFh
3E0000h–3EFFFFh
3F0000h–3F1FFFh
3F2000h–3F3FFFh
3F4000h–3F5FFFh
1F0000h–1F7FFFh
1F8000h–1F8FFFh
1F9000h–1F9FFFh
1FA000h–1FAFFFh
8/4
8/4
8/4
3F6000h–3F7FFFh 1FB000h–1FBFFFh
3F8000h–3F9FFFh 1FC000h–1FCFFFh
3FA000h–3FBFFFh 1FD000h–1FDFFFh
3FC000h–3FDFFFh 1FE000h–1FEFFFh
3FE000h–3FFFFFh 1FF000h–1FFFFFh
8/4
8/4
210000h–21FFFFh 108000h–10FFFFh
220000h–22FFFFh 110000h–117FFFh
230000h–23FFFFh 118000h–11FFFFh
8/4
8/4
28
S29GL-A
S29GL-A_00_A11 September 10, 2007
D a t a S h e e t
Table 7.6 S29GL032A (Model R4, W4) Bottom Boot Sector Addresses
Sector
Size
(KB/
Sector
Size
(KB/
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
Sector
SA0
A20–A12
000000000
000000001
000000010
000000011
000000100
000000101
000000110
000000111
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
001000xxx
001001xxx
001010xxx
001011xxx
011111xxx
100000xxx
100001xxx
100010xxx
101011xxx
100100xxx
100101xxx
100110xxx
100111xxx
101000xxx
101001xxx
101010xxx
101011xxx
101100xxx
101101xxx
101110xxx
101111xxx
Kwords)
Sector A20–A12 Kwords)
8/4
000000h–001FFFh
002000h–003FFFh
004000h–005FFFh
006000h–007FFFh
008000h–009FFFh
00A000h–00BFFFh
00C000h–00DFFFh
00E000h–00FFFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
1F0000h–1FFFFFh
200000h–20FFFFh
210000h–21FFFFh
220000h–22FFFFh
230000h–23FFFFh
240000h–24FFFFh
250000h–25FFFFh
260000h–26FFFFh
270000h–27FFFFh
280000h–28FFFFh
290000h–29FFFFh
00000h–00FFFh
01000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–04FFFh
05000h–05FFFh
06000h–06FFFh
07000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
F8000h–FFFFFh
F9000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
SA19 001100xxx
SA20 001101xxx
SA21 001101xxx
SA22 001111xxx
SA23 010000xxx
SA24 010001xxx
SA25 010010xxx
SA26 010011xxx
SA27 010100xxx
SA28 010101xxx
SA29 010110xxx
SA30 010111xxx
SA31 011000xxx
SA32 011001xxx
SA33 011010xxx
SA34 011011xxx
SA35 011000xxx
SA36 011101xxx
SA37 011110xxx
SA55 110000xxx
SA56 110001xxx
SA57 110010xxx
SA58 110011xxx
SA59 100100xxx
SA60 110101xxx
SA61 110110xxx
SA62 110111xxx
SA63 111000xxx
SA64 111001xxx
SA65 111010xxx
SA66 111011xxx
SA67 111100xxx
SA68 111101xxx
SA69 111110xxx
SA70 111111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–00FFFFh
110000h–11FFFFh
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
1D0000h–1DFFFFh
1E0000h–1EFFFFh
300000h–30FFFFh
310000h–31FFFFh
320000h–32FFFFh
330000h–33FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
SA1
8/4
SA2
8/4
SA3
8/4
SA4
8/4
SA5
8/4
SA6
8/4
SA7
8/4
SA8
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
340000h–34FFFFh 1A0000h–1A7FFFh
350000h–35FFFFh 1A8000h–1AFFFFh
360000h–36FFFFh 1B0000h–1B7FFFh
370000h–37FFFFh 1B8000h–1BFFFFh
380000h–38FFFFh 1C0000h–1C7FFFh
390000h–39FFFFh 1C8000h–1CFFFFh
3A0000h–3AFFFFh 1D0000h–1D7FFFh
3B0000h–3BFFFFh 1D8000h–1DFFFFh
3C0000h–3CFFFFh 1E0000h–1E7FFFh
3D0000h–3DFFFFh 1E8000h–1EFFFFh
3E0000h–3EFFFFh 1F0000h–1F7FFFh
3F0000h–3FFFFFh 1F8000h–1FFFFFh
2A0000h–2AFFFFh 150000h–157FFFh
2B0000h–2BFFFFh 158000h–15FFFFh
2C0000h–2CFFFFh 160000h–167FFFh
2D0000h–2DFFFFh 168000h–16FFFFh
2E0000h–2EFFFFh 170000h–177FFFh
2F0000h–2FFFFFh
178000h–17FFFFh
September 10, 2007 S29GL-A_00_A11
S29GL-A
29
D a t a S h e e t
Table 7.7 S29GL064A (Models R1, R2, R8, R9) Sector Addresses (Sheet 1 of 2)
Sector
Size
(KB/
Sector
Size
(KB/
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
Sector A21–A15
Kwords)
Sector A21–A15
Kwords)
SA0
SA1
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001111
0010000
0010001
0010010
0010011
0010100
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011100
0011101
0011110
0011111
0100000
0100001
0100010
0100011
0100100
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1FFFFF
200000–20FFFF
210000–21FFFF
220000–22FFFF
230000–23FFFF
240000–24FFFF
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
0100101
0100110
0100111
0101000
0101001
0101010
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
250000–25FFFF
260000–26FFFF
270000–27FFFF
280000–28FFFF
290000–29FFFF
2A0000–2AFFFF
2B0000–2BFFFF
2C0000–2CFFFF
2D0000–2DFFFF
2E0000–2EFFFF
2F0000–2FFFFF
300000–30FFFF
310000–31FFFF
320000–32FFFF
330000–33FFFF
340000–34FFFF
350000–35FFFF
360000–36FFFF
370000–37FFFF
380000–38FFFF
390000–39FFFF
3A0000–3AFFFF
3B0000–3BFFFF
3C0000–3CFFFF
3D0000–3DFFFF
3E0000–3EFFFF
3F0000–3FFFFF
400000–40FFFF
410000–41FFFF
420000–42FFFF
430000–43FFFF
440000–44FFFF
450000–45FFFF
460000–46FFFF
470000–47FFFF
480000–48FFFF
490000–49FFFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
200000–207FFF
208000–20FFFF
210000–217FFF
218000–21FFFF
220000–227FFF
228000–22FFFF
230000–237FFF
238000–23FFFF
240000–247FFF
248000–24FFFF
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
30
S29GL-A
S29GL-A_00_A11 September 10, 2007
D a t a S h e e t
Table 7.7 S29GL064A (Models R1, R2, R8, R9) Sector Addresses (Sheet 2 of 2)
Sector
Size
(KB/
Sector
Size
(KB/
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
Sector A21–A15
Kwords)
Sector A21–A15
Kwords)
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
1001010
1001011
1001100
1001101
1001110
1001111
1010000
1010001
1010010
1010011
1010100
1010101
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
1100000
1100001
1100010
1100011
1100100
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
4A0000–4AFFFF
4B0000–4BFFFF
4C0000–4CFFFF
4D0000–4DFFFF
4E0000–4EFFFF
4F0000–4FFFFF
500000–50FFFF
510000–51FFFF
520000–52FFFF
530000–53FFFF
540000–54FFFF
550000–55FFFF
560000–56FFFF
570000–57FFFF
580000–58FFFF
590000–59FFFF
5A0000–5AFFFF
5B0000–5BFFFF
5C0000–5CFFFF
5D0000–5DFFFF
5E0000–5EFFFF
5F0000–5FFFFF
600000–60FFFF
610000–61FFFF
620000–62FFFF
630000–63FFFF
640000–64FFFF
250000–257FFF
258000–25FFFF
260000–267FFF
268000–26FFFF
270000–277FFF
278000–27FFFF
280000–287FFF
288000–28FFFF
290000–297FFF
298000–29FFFF
2A0000–2A7FFF
2A8000–2AFFFF
2B0000–2B7FFF
2B8000–2BFFFF
2C0000–2C7FFF
2C8000–2CFFFF
2D0000–2D7FFF
2D8000–2DFFFF
2E0000–2E7FFF
2E8000–2EFFFF
2F0000–2F7FFF
2F8000–2FFFFF
300000–307FFF
308000–30FFFF
310000–317FFF
318000–31FFFF
320000–327FFF
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
1111111
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
650000–65FFFF
660000–66FFFF
670000–67FFFF
680000–68FFFF
690000–69FFFF
6A0000–6AFFFF
6B0000–6BFFFF
6C0000–6CFFFF
6D0000–6DFFFF
6E0000–6EFFFF
6F0000–6FFFFF
700000–70FFFF
710000–71FFFF
720000–72FFFF
730000–73FFFF
740000–74FFFF
750000–75FFFF
760000–76FFFF
770000–77FFFF
780000–78FFFF
790000–79FFFF
7A0000–7AFFFF
7B0000–7BFFFF
7C0000–7CFFFF
7D0000–7DFFFF
7E0000–7EFFFF
7F0000–7FFFFF
328000–32FFFF
330000–337FFF
338000–33FFFF
340000–347FFF
348000–34FFFF
350000–357FFF
358000–35FFFF
360000–367FFF
368000–36FFFF
370000–377FFF
378000–37FFFF
380000–387FFF
388000–38FFFF
390000–397FFF
398000–39FFFF
3A0000–3A7FFF
3A8000–3AFFFF
3B0000–3B7FFF
3B8000–3BFFFF
3C0000–3C7FFF
3C8000–3CFFFF
3D0000–3D7FFF
3D8000–3DFFFF
3E0000–3E7FFF
3E8000–3EFFFF
3F0000–3F7FFF
3F8000–3FFFFF
September 10, 2007 S29GL-A_00_A11
S29GL-A
31
D a t a S h e e t
Table 7.8 S29GL064A (Model R3) Top Boot Sector Addresses (Sheet 1 of 2)
Sector
Size
(KB/
Sector
Size
(KB/
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
A21–A12
Kwords)
Sector
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
A21–A12
Kwords)
0000000xxx
0000001xxx
0000010xxx
0000011xxx
0000100xxx
0000101xxx
0000110xxx
0000111xxx
0001000xxx
0001001xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000h–00FFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–00FFFFh
110000h–11FFFFh
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
1D0000h–1DFFFFh
1E0000h–1EFFFFh
1F0000h–1FFFFFh
200000h–20FFFFh
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
F8000h–FFFFFh
F9000h–107FFFh
0100010xxx
0101011xxx
0100100xxx
0100101xxx
0100110xxx
0100111xxx
0101000xxx
0101001xxx
0101010xxx
0101011xxx
0101100xxx
0101101xxx
0101110xxx
0101111xxx
0110000xxx
0110001xxx
0110010xxx
0110011xxx
0100100xxx
0110101xxx
0110110xxx
0110111xxx
0111000xxx
0111001xxx
0111010xxx
0111011xxx
0111100xxx
0111101xxx
0111110xxx
0111111xxx
1000000xxx
1000001xxx
1000010xxx
1000011xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
220000h–22FFFFh 110000h–117FFFh
230000h–23FFFFh 118000h–11FFFFh
240000h–24FFFFh 120000h–127FFFh
250000h–25FFFFh 128000h–12FFFFh
260000h–26FFFFh 130000h–137FFFh
270000h–27FFFFh 138000h–13FFFFh
280000h–28FFFFh 140000h–147FFFh
290000h–29FFFFh 148000h–14FFFFh
2A0000h–2AFFFFh 150000h–157FFFh
2B0000h–2BFFFFh 158000h–15FFFFh
2C0000h–2CFFFFh 160000h–167FFFh
2D0000h–2DFFFFh 168000h–16FFFFh
2E0000h–2EFFFFh 170000h–177FFFh
2F0000h–2FFFFFh 178000h–17FFFFh
300000h–30FFFFh 180000h–187FFFh
310000h–31FFFFh 188000h–18FFFFh
320000h–32FFFFh 190000h–197FFFh
330000h–33FFFFh 198000h–19FFFFh
340000h–34FFFFh 1A0000h–1A7FFFh
350000h–35FFFFh 1A8000h–1AFFFFh
360000h–36FFFFh 1B0000h–1B7FFFh
370000h–37FFFFh 1B8000h–1BFFFFh
380000h–38FFFFh 1C0000h–1C7FFFh
390000h–39FFFFh 1C8000h–1CFFFFh
3A0000h–3AFFFFh 1D0000h–1D7FFFh
3B0000h–3BFFFFh 1D8000h–1DFFFFh
3C0000h–3CFFFFh 1E0000h–1E7FFFh
3D0000h–3DFFFFh 1E8000h–1EFFFFh
3E0000h–3EFFFFh 1F0000h–1F7FFFh
3F0000h–3FFFFFh 1F8000h–1FFFFFh
400000h–40FFFFh 200000h–207FFFh
410000h–41FFFFh 208000h–20FFFFh
420000h–42FFFFh 210000h–217FFFh
430000h–43FFFFh 218000h–21FFFFh
SA10 0001010xxx
SA11 0001011xxx
SA12 0001100xxx
SA13 0001101xxx
SA14 0001101xxx
SA15 0001111xxx
SA16 0010000xxx
SA17 0010001xxx
SA18 0010010xxx
SA19 0010011xxx
SA20 0010100xxx
SA21 0010101xxx
SA22 0010110xxx
SA23 0010111xxx
SA24 0011000xxx
SA25 0011001xxx
SA26 0011010xxx
SA27 0011011xxx
SA28 0011000xxx
SA29 0011101xxx
SA30 0011110xxx
SA31 0011111xxx
SA32 0100000xxx
SA33 0100001xxx
210000h–21FFFFh 108000h–10FFFFh
32
S29GL-A
S29GL-A_00_A11 September 10, 2007
D a t a S h e e t
Table 7.8 S29GL064A (Model R3) Top Boot Sector Addresses (Sheet 2 of 2)
Sector
Size
(KB/
Sector
Size
(KB/
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
Sector
A21–A12
Kwords)
Sector
A21–A12
Kwords)
SA68 1000100xxx
SA69 1000101xxx
SA70 1000110xxx
SA71 1000111xxx
SA72 1001000xxx
SA73 1001001xxx
SA74 1001010xxx
SA75 1001011xxx
SA76 1001100xxx
SA77 1001101xxx
SA78 1001110xxx
SA79 1001111xxx
SA80 1010000xxx
SA81 1010001xxx
SA82 1010010xxx
SA83 1010011xxx
SA84 1010100xxx
SA85 1010101xxx
SA86 1010110xxx
SA87 1010111xxx
SA88 1011000xxx
SA89 1011001xxx
SA90 1011010xxx
SA91 1011011xxx
SA92 1011100xxx
SA93 1011101xxx
SA94 1011110xxx
SA95 1011111xxx
SA96 1100000xxx
SA97 1100001xxx
SA98 1100010xxx
SA99 1100011xxx
SA100 1100100xxx
SA101 1100101xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
440000h–44FFFFh 220000h–227FFFh
450000h–45FFFFh 228000h–22FFFFh
460000h–46FFFFh 230000h–237FFFh
470000h–47FFFFh 238000h–23FFFFh
480000h–48FFFFh 240000h–247FFFh
490000h–49FFFFh 248000h–24FFFFh
4A0000h–4AFFFFh 250000h–257FFFh
4B0000h–4BFFFFh 258000h–25FFFFh
4C0000h–4CFFFFh 260000h–267FFFh
4D0000h–4DFFFFh 268000h–26FFFFh
4E0000h–4EFFFFh 270000h–277FFFh
4F0000h–4FFFFFh 278000h–27FFFFh
500000h–50FFFFh 280000h–28FFFFh
510000h–51FFFFh 288000h–28FFFFh
520000h–52FFFFh 290000h–297FFFh
530000h–53FFFFh 298000h–29FFFFh
540000h–54FFFFh 2A0000h–2A7FFFh
550000h–55FFFFh 2A8000h–2AFFFFh
560000h–56FFFFh 2B0000h–2B7FFFh
570000h–57FFFFh 2B8000h–2BFFFFh
580000h–58FFFFh 2C0000h–2C7FFFh
590000h–59FFFFh 2C8000h–2CFFFFh
5A0000h–5AFFFFh 2D0000h–2D7FFFh
5B0000h–5BFFFFh 2D8000h–2DFFFFh
5C0000h–5CFFFFh 2E0000h–2E7FFFh
5D0000h–5DFFFFh 2E8000h–2EFFFFh
5E0000h–5EFFFFh 2F0000h–2FFFFFh
5F0000h–5FFFFFh 2F8000h–2FFFFFh
600000h–60FFFFh 300000h–307FFFh
610000h–61FFFFh 308000h–30FFFFh
620000h–62FFFFh 310000h–317FFFh
630000h–63FFFFh 318000h–31FFFFh
640000h–64FFFFh 320000h–327FFFh
650000h–65FFFFh 328000h–32FFFFh
SA102 1100110xxx
SA103 1100111xxx
SA104 1101000xxx
SA105 1101001xxx
SA106 1101010xxx
SA107 1101011xxx
SA108 1101100xxx
SA109 1101101xxx
SA110 1101110xxx
SA111 1101111xxx
SA112 1110000xxx
SA113 1110001xxx
SA114 1110010xxx
SA115 1110011xxx
SA116 1110100xxx
SA117 1110101xxx
SA118 1110110xxx
SA119 1110111xxx
SA120 1111000xxx
SA121 1111001xxx
SA122 1111010xxx
SA123 1111011xxx
SA124 1111100xxx
SA125 1111101xxx
SA126 1111110xxx
SA127 1111111000
SA128 1111111001
SA129 1111111010
SA130 1111111011
SA131 1111111100
SA132 1111111101
SA133 1111111110
SA134 1111111111
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
660000h–66FFFFh 330000h–337FFFh
670000h–67FFFFh 338000h–33FFFFh
680000h–68FFFFh 340000h–347FFFh
690000h–69FFFFh 348000h–34FFFFh
6A0000h–6AFFFFh 350000h–357FFFh
6B0000h–6BFFFFh 358000h–35FFFFh
6C0000h–6CFFFFh 360000h–367FFFh
6D0000h–6DFFFFh 368000h–36FFFFh
6E0000h–6EFFFFh 370000h–377FFFh
6F0000h–6FFFFFh 378000h–37FFFFh
700000h–70FFFFh 380000h–387FFFh
710000h–71FFFFh 388000h–38FFFFh
720000h–72FFFFh 390000h–397FFFh
730000h–73FFFFh 398000h–39FFFFh
740000h–74FFFFh 3A0000h–3A7FFFh
750000h–75FFFFh 3A8000h–3AFFFFh
760000h–76FFFFh 3B0000h–3B7FFFh
770000h–77FFFFh 3B8000h–3BFFFFh
780000h–78FFFFh 3C0000h–3C7FFFh
790000h–79FFFFh 3C8000h–3CFFFFh
7A0000h–7AFFFFh 3D0000h–3D7FFFh
7B0000h–7BFFFFh 3D8000h–3DFFFFh
7C0000h–7CFFFFh 3E0000h–3E7FFFh
7D0000h–7DFFFFh 3E8000h–3EFFFFh
7E0000h–7EFFFFh 3F0000h–3F7FFFh
7F0000h–7F1FFFh 3F8000h–3F8FFFh
7F2000h–7F3FFFh 3F9000h–3F9FFFh
7F4000h–7F5FFFh 3FA000h–3FAFFFh
7F6000h–7F7FFFh 3FB000h–3FBFFFh
7F8000h–7F9FFFh 3FC000h–3FCFFFh
7FA000h–7FBFFFh 3FD000h–3FDFFFh
7FC000h–7FDFFFh 3FE000h–3FEFFFh
7FE000h–7FFFFFh 3FF000h–3FFFFFh
8/4
8/4
8/4
8/4
8/4
8/4
8/4
September 10, 2007 S29GL-A_00_A11
S29GL-A
33
D a t a S h e e t
Table 7.9 S29GL064A (Model R4) Bottom Boot Sector Addresses (Sheet 1 of 2)
Sector
Size
(KB/
Sector
Size
(KB/
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
A21–A12
Kwords)
Sector
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
A21–A12
Kwords)
0000000000
0000000001
0000000010
0000000011
0000000100
0000000101
0000000110
0000000111
0000001xxx
0000010xxx
8/4
000000h–001FFFh
002000h–003FFFh
004000h–005FFFh
006000h–007FFFh
008000h–009FFFh
00A000h–00BFFFh
00C000h–00DFFFh
00E000h–00FFFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–00FFFFh
110000h–11FFFFh
120000h–12FFFFh
130000h–13FFFFh
00000h–00FFFh
01000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–04FFFh
05000h–05FFFh
06000h–06FFFh
07000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
0010100xxx
0010101xxx
0010110xxx
0010111xxx
0011000xxx
0011001xxx
0011010xxx
0011011xxx
0011000xxx
0011101xxx
0011110xxx
0011111xxx
0100000xxx
0100001xxx
0100010xxx
0101011xxx
0100100xxx
0100101xxx
0100110xxx
0100111xxx
0101000xxx
0101001xxx
0101010xxx
0101011xxx
0101100xxx
0101101xxx
0101110xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
1D0000h–1DFFFFh
1E0000h–1EFFFFh
1F0000h–1FFFFFh
200000h–20FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
F8000h–FFFFFh
F9000h–107FFFh
8/4
8/4
8/4
8/4
8/4
8/4
8/4
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA10 0000011xxx
SA11 0000100xxx
SA12 0000101xxx
SA13 0000110xxx
SA14 0000111xxx
SA15 0001000xxx
SA16 0001001xxx
SA17 0001010xxx
SA18 0001011xxx
SA19 0001100xxx
SA20 0001101xxx
SA21 0001101xxx
SA22 0001111xxx
SA23 0010000xxx
SA24 0010001xxx
SA25 0010010xxx
SA26 0010011xxx
210000h–21FFFFh 108000h–10FFFFh
220000h–22FFFFh 110000h–117FFFh
230000h–23FFFFh 118000h–11FFFFh
240000h–24FFFFh 120000h–127FFFh
250000h–25FFFFh 128000h–12FFFFh
260000h–26FFFFh 130000h–137FFFh
270000h–27FFFFh 138000h–13FFFFh
280000h–28FFFFh 140000h–147FFFh
290000h–29FFFFh 148000h–14FFFFh
2A0000h–2AFFFFh 150000h–157FFFh
2B0000h–2BFFFFh 158000h–15FFFFh
2C0000h–2CFFFFh 160000h–167FFFh
2D0000h–2DFFFFh 168000h–16FFFFh
2E0000h–2EFFFFh 170000h–177FFFh
34
S29GL-A
S29GL-A_00_A11 September 10, 2007
D a t a S h e e t
Table 7.9 S29GL064A (Model R4) Bottom Boot Sector Addresses (Sheet 2 of 2)
Sector
Size
(KB/
Sector
Size
(KB/
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
Sector
A21–A12
Kwords)
Sector
SA95
SA96
SA97
SA98
SA99
A21–A12
Kwords)
SA54 0101111xxx
SA55 0110000xxx
SA56 0110001xxx
SA57 0110010xxx
SA58 0110011xxx
SA59 0100100xxx
SA60 0110101xxx
SA61 0110110xxx
SA62 0110111xxx
SA63 0111000xxx
SA64 0111001xxx
SA65 0111010xxx
SA66 0111011xxx
SA67 0111100xxx
SA68 0111101xxx
SA69 0111110xxx
SA70 0111111xxx
SA71 1000000xxx
SA72 1000001xxx
SA73 1000010xxx
SA74 1000011xxx
SA75 1000100xxx
SA76 1000101xxx
SA77 1000110xxx
SA78 1000111xxx
SA79 1001000xxx
SA80 1001001xxx
SA81 1001010xxx
SA82 1001011xxx
SA83 1001100xxx
SA84 1001101xxx
SA85 1001110xxx
SA86 1001111xxx
SA87 1010000xxx
SA88 1010001xxx
SA89 1010010xxx
SA90 1010011xxx
SA91 1010100xxx
SA92 1010101xxx
SA93 1010110xxx
SA94 1010111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
2F0000h–2FFFFFh
300000h–30FFFFh
310000h–31FFFFh
320000h–32FFFFh
330000h–33FFFFh
340000h–34FFFFh
350000h–35FFFFh
360000h–36FFFFh
370000h–37FFFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1011000xxx
1011001xxx
1011010xxx
1011011xxx
1011100xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
580000h–58FFFFh 2C0000h–2C7FFFh
590000h–59FFFFh 2C8000h–2CFFFFh
5A0000h–5AFFFFh 2D0000h–2D7FFFh
5B0000h–5BFFFFh 2D8000h–2DFFFFh
5C0000h–5CFFFFh 2E0000h–2E7FFFh
5D0000h–5DFFFFh 2E8000h–2EFFFFh
5E0000h–5EFFFFh 2F0000h–2FFFFFh
5F0000h–5FFFFFh 2F8000h–2FFFFFh
600000h–60FFFFh 300000h–307FFFh
610000h–61FFFFh 308000h–30FFFFh
620000h–62FFFFh 310000h–317FFFh
630000h–63FFFFh 318000h–31FFFFh
640000h–64FFFFh 320000h–327FFFh
650000h–65FFFFh 328000h–32FFFFh
660000h–66FFFFh 330000h–337FFFh
670000h–67FFFFh 338000h–33FFFFh
680000h–68FFFFh 340000h–347FFFh
690000h–69FFFFh 348000h–34FFFFh
6A0000h–6AFFFFh 350000h–357FFFh
6B0000h–6BFFFFh 358000h–35FFFFh
6C0000h–6CFFFFh 360000h–367FFFh
6D0000h–6DFFFFh 368000h–36FFFFh
6E0000h–6EFFFFh 370000h–377FFFh
6F0000h–6FFFFFh 378000h–37FFFFh
700000h–70FFFFh 380000h–387FFFh
710000h–71FFFFh 388000h–38FFFFh
720000h–72FFFFh 390000h–397FFFh
730000h–73FFFFh 398000h–39FFFFh
740000h–74FFFFh 3A0000h–3A7FFFh
750000h–75FFFFh 3A8000h–3AFFFFh
760000h–76FFFFh 3B0000h–3B7FFFh
770000h–77FFFFh 3B8000h–3BFFFFh
780000h–78FFFFh 3C0000h–3C7FFFh
790000h–79FFFFh 3C8000h–3CFFFFh
7A0000h–7AFFFFh 3D0000h–3D7FFFh
7B0000h–7BFFFFh 3D8000h–3DFFFFh
7C0000h–7CFFFFh 3E0000h–3E7FFFh
7D0000h–7DFFFFh 3E8000h–3EFFFFh
7E0000h–7EFFFFh 3F0000h–3F7FFFh
7F0000h–7FFFFFh 3F8000h–3FFFFFh
SA100 1011101xxx
SA101 1011110xxx
SA102 1011111xxx
SA103 1100000xxx
SA104 1100001xxx
SA105 1100010xxx
SA106 1100011xxx
SA107 1100100xxx
SA108 1100101xxx
SA109 1100110xxx
SA110 1100111xxx
SA111 1101000xxx
SA112 1101001xxx
SA113 1101010xxx
SA114 1101011xxx
SA115 1101100xxx
SA116 1101101xxx
SA117 1101110xxx
SA118 1101111xxx
SA119 1110000xxx
SA120 1110001xxx
SA121 1110010xxx
SA122 1110011xxx
SA123 1110100xxx
SA124 1110101xxx
SA125 1110110xxx
SA126 1110111xxx
SA127 1111000xxx
SA128 1111001xxx
SA129 1111010xxx
SA130 1111011xxx
SA131 1111100xxx
SA132 1111101xxx
SA133 1111110xxx
SA134 1111111000
380000h–38FFFFh 1C0000h–1C7FFFh
390000h–39FFFFh 1C8000h–1CFFFFh
3A0000h–3AFFFFh 1D0000h–1D7FFFh
3B0000h–3BFFFFh 1D8000h–1DFFFFh
3C0000h–3CFFFFh 1E0000h–1E7FFFh
3D0000h–3DFFFFh 1E8000h–1EFFFFh
3E0000h–3EFFFFh 1F0000h–1F7FFFh
3F0000h–3FFFFFh
400000h–40FFFFh
410000h–41FFFFh
420000h–42FFFFh
430000h–43FFFFh
440000h–44FFFFh
450000h–45FFFFh
460000h–46FFFFh
470000h–47FFFFh
480000h–48FFFFh
490000h–49FFFFh
4A0000h–4AFFFFh
1F8000h–1FFFFFh
200000h–207FFFh
208000h–20FFFFh
210000h–217FFFh
218000h–21FFFFh
220000h–227FFFh
228000h–22FFFFh
230000h–237FFFh
238000h–23FFFFh
240000h–247FFFh
248000h–24FFFFh
250000h–257FFFh
4B0000h–4BFFFFh 258000h–25FFFFh
4C0000h–4CFFFFh 260000h–267FFFh
4D0000h–4DFFFFh 268000h–26FFFFh
4E0000h–4EFFFFh
4F0000h–4FFFFFh
500000h–50FFFFh
510000h–51FFFFh
520000h–52FFFFh
530000h–53FFFFh
540000h–54FFFFh
550000h–55FFFFh
560000h–56FFFFh
570000h–57FFFFh
270000h–277FFFh
278000h–27FFFFh
280000h–28FFFFh
288000h–28FFFFh
290000h–297FFFh
298000h–29FFFFh
2A0000h–2A7FFFh
2A8000h–2AFFFFh
2B0000h–2B7FFFh
2B8000h–2BFFFFh
September 10, 2007 S29GL-A_00_A11
S29GL-A
35
D a t a S h e e t
Table 7.10 S29GL064A (Model R5) Sector Addresses (Sheet 1 of 2)
16-bit
16-bit
Sector
SA0
A21–A15
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001111
0010000
0010001
0010010
0010011
0010100
Address Range
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
Sector
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
A21–A15
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011100
0011101
0011110
0011111
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
Address Range
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
200000–207FFF
208000–20FFFF
210000–217FFF
218000–21FFFF
220000–227FFF
228000–22FFFF
230000–237FFF
238000–23FFFF
240000–247FFF
248000–24FFFF
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
36
S29GL-A
S29GL-A_00_A11 September 10, 2007
D a t a S h e e t
Table 7.10 S29GL064A (Model R5) Sector Addresses (Sheet 2 of 2)
16-bit
16-bit
Sector
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
A21–A15
0101010
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
1010000
1010001
1010010
1010011
1010100
Address Range
250000–257FFF
258000–25FFFF
260000–267FFF
268000–26FFFF
270000–277FFF
278000–27FFFF
280000–287FFF
288000–28FFFF
290000–297FFF
298000–29FFFF
2A0000–2A7FFF
2A8000–2AFFFF
2B0000–2B7FFF
2B8000–2BFFFF
2C0000–2C7FFF
2C8000–2CFFFF
2D0000–2D7FFF
2D8000–2DFFFF
2E0000–2E7FFF
2E8000–2EFFFF
2F0000–2F7FFF
2F8000–2FFFFF
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
Sector
SA85
A21–A15
1010101
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
1100000
1100001
1100010
1100011
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
1111111
Address Range
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
300000–307FFF
308000–30FFFF
310000–317FFF
318000–31FFFF
320000–327FFF
328000–32FFFF
330000–337FFF
338000–33FFFF
340000–347FFF
348000–34FFFF
350000–357FFF
358000–35FFFF
360000–367FFF
368000–36FFFF
370000–377FFF
378000–37FFFF
380000–387FFF
388000–38FFFF
390000–397FFF
398000–39FFFF
3A0000–3A7FFF
3A8000–3AFFFF
3B0000–3B7FFF
3B8000–3BFFFF
3C0000–3C7FFF
3C8000–3CFFFF
3D0000–3D7FFF
3D8000–3DFFFF
3E0000–3E7FFF
3E8000–3EFFFF
3F0000–3F7FFF
3F8000–3FFFFF
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
September 10, 2007 S29GL-A_00_A11
S29GL-A
37
D a t a S h e e t
Table 7.11 S29GL064A (Models R6, R7) Sector Addresses (Sheet 1 of 2)
16-bit
Address
Range
16-bit
Address
Range
Sector
SA0
A21–A15
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001111
0010000
0010001
0010010
0010011
0010100
Sector
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
A21–A15
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011100
0011101
0011110
0011111
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
38
S29GL-A
S29GL-A_00_A11 September 10, 2007
D a t a S h e e t
Table 7.11 S29GL064A (Models R6, R7) Sector Addresses (Sheet 2 of 2)
16-bit
Address
Range
16-bit
Address
Range
Sector
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
A21–A15
0101010
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
1010000
1010001
1010010
1010011
1010100
Sector
SA85
A21–A15
1010101
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
1100000
1100001
1100010
1100011
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
1111111
150000–157FFF
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
200000–207FFF
208000–20FFFF
210000–217FFF
218000–21FFFF
220000–227FFF
228000–22FFFF
230000–237FFF
238000–23FFFF
240000–247FFF
248000–24FFFF
250000–257FFF
258000–25FFFF
260000–267FFF
268000–26FFFF
270000–277FFF
278000–27FFFF
280000–287FFF
288000–28FFFF
290000–297FFF
298000–29FFFF
2A0000–2A7FFF
2A8000–2AFFFF
2B0000–2B7FFF
2B8000–2BFFFF
2C0000–2C7FFF
2C8000–2CFFFF
2D0000–2D7FFF
2D8000–2DFFFF
2E0000–2E7FFF
2E8000–2EFFFF
2F0000–2F7FFF
2F8000–2FFFFF
300000–307FFF
308000–30FFFF
310000–317FFF
318000–31FFFF
320000–327FFF
328000–32FFFF
330000–337FFF
338000–33FFFF
340000–347FFF
348000–34FFFF
350000–357FFF
358000–35FFFF
360000–367FFF
368000–36FFFF
370000–377FFF
378000–37FFFF
380000–387FFF
388000–38FFFF
390000–397FFF
398000–39FFFF
3A0000–3A7FFF
3A8000–3AFFFF
3B0000–3B7FFF
3B8000–3BFFFF
3C0000–3C7FFF
3C8000–3CFFFF
3D0000–3D7FFF
3D8000–3DFFFF
3E0000–3E7FFF
3E8000–3EFFFF
3F0000–3F7FFF
3F8000–3FFFFF
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
September 10, 2007 S29GL-A_00_A11
S29GL-A
39
D a t a S h e e t
7.8
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector group protection
verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming
equipment to automatically match a device to be programmed with its corresponding programming algorithm.
However, the autoselect codes can also be accessed in-system through the command register.
When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins A6,
A3, A2, A1, and A0 must be as shown in Table 7.12. In addition, when verifying sector protection, the sector
address must appear on the appropriate highest order address bits (see Table 7.4 on page 27 to Table 7.22
on page 45). Table 7.12 shows the remaining address bits that are don’t care. When all necessary bits are
set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host system can issue the autoselect command via the
command register, as shown in Table 10.2 on page 61 and Table 10.1 on page 62. This method does not
require VID. Refer to Autoselect Command Sequence on page 53 for more information.
Table 7.12 Autoselect Codes, (High Voltage Method)
DQ7 to DQ0
DQ8 to DQ15
A22 A14
A8
A5 A3
Model Number
X3, X4
to
Description
CE# OE# WE#
A9 to A6 to to A1 A0
to
A7
A4 A2
BYTE# BYTE#
X1, X2,
R8, R9
R5, R6,
R7
A15 A10
= V
= V
IH
IL
Manufacturer ID:
Spansion Products
L
L
L
L
H
H
X
X
X
X
V
V
X
L
L
X
X
L
L
L
00
X
01h
01h
01h
ID
ID
Cycle 1
Cycle 2
L
L
H
L
22
22
X
X
7Eh
0Ch
7Eh
10h
7Eh
13h
H
H
00h
X
(-R4, bottom boot)
Cycle 3
H
H
H
22
X
01h
01h
01h
(-R3, top boot)
Cycle 1
Cycle 2
L
L
H
L
22
22
X
X
7Eh
1Dh
7Eh
1Ah
H
H
00h
(-R4/W4,
bottom boot)
L
L
L
L
H
H
X
X
X
X
V
V
X
X
L
X
X
ID
Cycle 3
Cycle 1
H
X
H
L
H
H
22
22
X
X
00h
01h
(-R3/W3,
top boot)
49h
(-R2/02/W2,
bottom boot)
X
ID
C4h
(-R1/01/W1,
top boot)
Sector Group
Protection Verification
01h (protected),
00h (unprotected)
L
L
L
L
H
H
SA
X
X
X
V
V
X
X
L
L
X
X
L
L
H
H
L
X
X
X
X
ID
ID
For S29GL064A and S29GL032A:
99h (factory locked),
Secured Silicon Sector
Indicator Bit (DQ7),
WP# protects highest
address sector
19h (not factory locked)
H
For S29GL016A: 94h (factory locked),
14h (not factory locked)
For S29GL064A and S29GL032A:
89h (factory locked),
Secured Silicon Sector
Indicator Bit (DQ7),
WP# protects lowest
address sector
09h (not factory locked)
L
L
H
X
X
V
X
L
X
L
H
H
X
X
ID
For S29GL016A: 84h (factory locked),
04h (not factory locked)
Legend
L = Logic Low = V
IL
H = Logic High = V
IH
SA = Sector Address
X = Don’t care.
40
S29GL-A
S29GL-A_00_A11 September 10, 2007
D a t a S h e e t
7.9
Sector Group Protection and Unprotection
The hardware sector group protection feature disables both program and erase operations in any sector
group (see Table 7.11 on page 38 to Table 7.22 on page 45). The hardware sector group unprotection
feature re-enables both program and erase operations in previously protected sector groups. Sector group
protection/unprotection can be implemented via two methods.
Sector protection/unprotection requires VID on the RESET# pin only, and can be implemented either in-
system or via programming equipment. Figure 7.2 on page 46 shows the algorithms and Figure 16.13
on page 86 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For
sector group unprotect, all unprotected sector groups must first be protected prior to the first sector group
unprotect write cycle.
The device is shipped with all sector groups unprotected. Spansion offers the option of programming and
protecting sector groups at its factory prior to shipping the device through Spansion Programming Service.
Contact a Spansion representative for details.
It is possible to determine whether a sector group is protected or unprotected. See Autoselect Mode
on page 40 for details.
Table 7.13 S29GL016A (Model R1, 01) Sector Group Protection/Unprotection Addresses
Sector/Sector
Block Size
(Kbytes)
Sector/Sector
Block Size
(Kbytes)
Sector
A19–A12
Sector
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
A19–A12
11111000h
11111001h
11111010h
11111011h
11111100h
11111101h
11111110h
11111111h
SA0-SA3
000XXXXXh
001XXXXXh
010XXXXXh
011XXXXXh
100XXXXXh
101XXXXXh
110XXXXXh
11100XXXh
11101XXXh
11110XXXh
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
8
8
8
8
8
8
8
8
SA4-SA7
SA8-SA11
SA12-SA15
SA16-SA19
SA20-SA23
SA24-SA27
SA28-SA30
192 (3x64)
Table 7.14 S29GL016A (Model R2, 02) Sector Group Protection/Unprotection Addresses
Sector/Sector
Block Size
(Kbytes)
Sector/Sector
Block Size
(Kbytes)
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
A19–A12
00000000h
00000001h
00000010h
00000011h
00000100h
00000101h
00000110h
00000111h
Sector
A19–A12
8
8
8
8
8
8
8
8
00001XXXh
00010XXXh
00011XXXh
001XXXXXh
010XXXXXh
011XXXXXh
100XXXXXh
101XXXXXh
110XXXXXh
111XXXXXh
SA8–SA10
192 (3x64)
SA11–SA14
SA15–SA18
SA19–SA22
SA23–SA26
SA27-SA30
SA31-SA34
SA35-SA38
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
September 10, 2007 S29GL-A_00_A11
S29GL-A
41
D a t a S h e e t
Table 7.15 S29GL032A (Models R1, R2) Sector Group Protection/Unprotection Addresses
Sector
/Sector
Sector
/Sector
Sector
/Sector
Block Size
(Kbytes)
Block Size
(Kbytes)
Block Size
(Kbytes)
Sector
SA0
A20–A15
000000
000001
000010
000011
0001xx
0010xx
0011xx
0100xx
Sector
A20–A15
0101xx
0110xx
0111xx
1000xx
1001xx
1010xx
1011xx
Sector
SA48–SA51
SA52–SA55
SA56–SA59
SA60
A20–A15
1100xx
1101xx
1110xx
111100
111101
111110
111111
64
64
SA20–SA23
SA24–SA27
SA28–SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA1
256 (4x64)
SA2
64
256 (4x64)
SA3
64
64
64
64
64
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA61
SA62
SA63
Table 7.16 S29GL032A (Model R3, W3) Sector Group Protection/Unprotection Address Table
Sector/Sector
Block Size
(Kbytes)
Sector/Sector
Block Size
(Kbytes)
Sector
A20–A12
Sector
A20–A12
SA0-SA3
0000XXXXXh
0001XXXXXh
0010XXXXXh
0011XXXXXh
0100XXXXXh
0101XXXXXh
0110XXXXXh
0111XXXXXh
1000XXXXXh
1001XXXXXh
1010XXXXXh
1011XXXXXh
1100XXXXXh
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA52-SA55
SA56-SA59
1101XXXXXh
1110XXXXXh
111100XXXh
111101XXXh
111110XXXh
111111000h
111111001h
111111010h
111111011h
111111100h
111111101h
111111110h
111111111h
256 (4x64)
256 (4x64)
SA4-SA7
SA8-SA11
SA12-SA15
SA16-SA19
SA20-SA23
SA24-SA27
SA28-SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA60-SA62
192 (3x64)
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
8
8
8
8
8
8
8
8
Table 7.17 S29GL032A (Model R4, W4) Sector Group Protection/Unprotection Address Table
Sector/Sector
Block Size
(Kbytes)
Sector/Sector
Block Size
(Kbytes)
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
A20–A12
Sector
A20–A12
000000000h
000000001h
000000010h
000000011h
000000100h
000000101h
000000110h
000000111h
000001XXXh
000010XXXh
000011XXXh
0001XXXXXh
0010XXXXXh
8
8
8
8
8
8
8
8
SA19–SA22
SA23–SA26
SA27-SA30
SA31-SA34
SA35-SA38
SA39-SA42
SA43-SA46
SA47-SA50
SA51-SA54
SA55–SA58
SA59–SA62
SA63–SA66
SA67–SA70
0011XXXXXh
0100XXXXXh
0101XXXXXh
0110XXXXXh
0111XXXXXh
1000XXXXXh
1001XXXXXh
1010XXXXXh
1011XXXXXh
1100XXXXXh
1101XXXXXh
1110XXXXXh
1111XXXXXh
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA8–SA10
192 (3x64)
SA11–SA14
SA15–SA18
256 (4x64)
256 (4x64)
42
S29GL-A
S29GL-A_00_A11 September 10, 2007
D a t a S h e e t
Table 7.18 S29GL064A (Models R1, R2, R8, R9) Sector Group Protection/Unprotection Addresses
Sector/
Sector
Sector/
Sector
Sector/
Sector
Block Size
(Kbytes)
Block Size
(Kbytes)
Block Size
(Kbytes)
Sector
SA0
A21–A15
0000000
0000001
0000010
0000011
00001xx
00010xx
00011xx
00100xx
00101xx
00110xx
00111xx
01000xx
01001xx
Sector
A21–A15
01010xx
01011xx
01100xx
01101xx
01110xx
01111xx
10000xx
10001xx
10010xx
10011xx
10100xx
10101xx
10110xx
Sector
SA92–SA95
SA96–SA99
SA100–SA103
SA104–SA107
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA124
A21–A15
10111xx
11000xx
11001xx
11010xx
11011xx
11100xx
11101xx
11110xx
1111100
1111101
1111110
1111111
64
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
SA64–SA67
SA68–SA71
SA72–SA75
SA76–SA79
SA80–SA83
SA84–SA87
SA88–SA91
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
64
SA1
64
SA2
64
SA3
64
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
SA32–SA35
SA36–SA39
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA125
64
SA126
64
SA127
64
Table 7.19 S29GL064A (Model R3) Top Boot Sector Protection/Unprotection Addresses
Sector/Sector
Block Size
(Kbytes)
Sector/Sector
Block Size
(Kbytes)
Sector
A21–A12
Sector
A20–A12
SA0-SA3
00000XXXXX
00001XXXXX
00010XXXXX
00011XXXXX
00100XXXXX
00101XXXXX
00110XXXXX
00111XXXXX
01000XXXXX
01001XXXXX
01010XXXXX
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA80-SA83
SA84-SA87
SA88-SA91
SA92-SA95
SA96-SA99
SA100-SA103
SA104-SA107
SA108-SA111
SA112-SA115
SA116-SA119
SA120-SA123
10100XXXXX
10101XXXXX
10110XXXXX
10111XXXXX
11000XXXXX
11001XXXXX
11010XXXXX
11011XXXXX
11100XXXXX
11101XXXXX
11110XXXXX
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA4-SA7
SA8-SA11
SA12-SA15
SA16-SA19
SA20-SA23
SA24-SA27
SA28-SA31
SA32-SA35
SA36-SA39
SA40-SA43
1111100XXX
1111101XXX
1111110XXX
SA44-SA47
01011XXXXX
256 (4x64)
SA124-SA126
192 (3x64)
SA48-SA51
SA52-SA55
SA56-SA59
SA60-SA63
SA64-SA67
SA68-SA71
SA72-SA75
SA76-SA79
01100XXXXX
01101XXXXX
01110XXXXX
01111XXXXX
10000XXXXX
10001XXXXX
10010XXXXX
10011XXXXX
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
1111111000
1111111001
1111111010
1111111011
1111111100
1111111101
1111111110
1111111111
8
8
8
8
8
8
8
8
September 10, 2007 S29GL-A_00_A11
S29GL-A
43
D a t a S h e e t
Table 7.20 S29GL064A (Model R4) Bottom Boot Sector Protection/Unprotection Addresses
Sector/Sector
Block Size
(Kbytes)
Sector/Sector
Block Size
(Kbytes)
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
A21–A12
Sector
A20–A12
0000000000
0000000001
0000000010
0000000011
0000000100
0000000101
0000000110
0000000111
8
8
8
8
8
8
8
8
SA55–SA58
SA59–SA62
SA63–SA66
SA67–SA70
SA71–SA74
SA75–SA78
SA79–SA82
SA83–SA86
01100XXXXX
01101XXXXX
01110XXXXX
01111XXXXX
10000XXXXX
10001XXXXX
10010XXXXX
10011XXXXX
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
0000001XXX,
0000010XXX,
0000011XXX,
SA8–SA10
192 (3x64)
SA87–SA90
10100XXXXX
256 (4x64)
SA11–SA14
SA15–SA18
SA19–SA22
SA23–SA26
SA27-SA30
SA31-SA34
SA35-SA38
SA39-SA42
SA43-SA46
SA47-SA50
SA51-SA54
00001XXXXX
00010XXXXX
00011XXXXX
00100XXXXX
00101XXXXX
00110XXXXX
00111XXXXX
01000XXXXX
01001XXXXX
01010XXXXX
01011XXXXX
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA91–SA94
SA95–SA98
10101XXXXX
10110XXXXX
10111XXXXX
11000XXXXX
11001XXXXX
11010XXXXX
11011XXXXX
11100XXXXX
11101XXXXX
11110XXXXX
11111XXXXX
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA99–SA102
SA103–SA106
SA107–SA110
SA111–SA114
SA115–SA118
SA119–SA122
SA123–SA126
SA127–SA130
SA131–SA134
Table 7.21 S29GL064A (Model R5) Sector Group Protection/Unprotection Addresses
Sector/
Sector
Sector/
Sector
Sector/
Sector
Block Size
(Kbytes)
Block Size
(Kbytes)
Block Size
(Kbytes)
Sector
A21–A15
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
Sector
A21–A15
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
Sector
A21–A15
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
SA0–SA3
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
SA64–SA67
SA68–SA71
SA72–SA75
SA76–SA79
SA80–SA83
SA84–SA87
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA88–SA91
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA4–SA7
SA92–SA95
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA96–SA99
SA100–SA103
SA104–SA107
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA124–SA127
44
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Table 7.22 S29GL064A (Models R6, R7) Sector Group Protection/Unprotection Addresses
Sector/
Sector
Sector/
Sector
Sector/
Sector
Block Size
(Kbytes)
Block Size
(Kbytes)
Block Size
(Kbytes)
Sector
A21–A15
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
Sector
A21–A15
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
Sector
A21–A15
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
SA0–SA3
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
SA64–SA67
SA68–SA71
SA72–SA75
SA76–SA79
SA80–SA83
SA84–SA87
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA88–SA91
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA4–SA7
SA92–SA95
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA96–SA99
SA100–SA103
SA104–SA107
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA124–SA127
7.10 Temporary Sector Group Unprotect
This feature allows temporary unprotection of previously protected sector groups to change data in-system.
The Sector Group Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly
protected sector groups can be programmed or erased by selecting the sector group addresses. Once VID is
removed from the RESET# pin, all the previously protected sector groups are protected again. Figure 7.1
shows the algorithm, and Figure 16.11 on page 82 shows the timing diagrams, for this feature.
Figure 7.1 Temporary Sector Group Unprotect Operation
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Group Unprotect Completed
(Note 2)
Notes
1. All protected sector groups unprotected (If WP# = V , the highest or lowest address sector remains protected for uniform sector devices;
IL
the top or bottom two address sectors remains protected for boot sector devices).
2. All previously protected sector groups are protected once again.
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D a t a S h e e t
Figure 7.2 In-System Sector Group Protect/Unprotect Algorithms
START
START
PLSCNT = 1
PLSCNT = 1
RESET# = VID
Protect all sector
groups: The indicated
portion of the sector
group protect algorithm
must be performed for all
unprotected sector
groups prior to issuing
the first sector group
unprotect address
RESET# = VID
Wait 1 μs
Wait 1 μs
Temporary Sector
Group Unprotect
Mode
Temporary Sector
Group Unprotect
Mode
No
First Write
Cycle = 60h?
No
First Write
Cycle = 60h?
Yes
Yes
Set up sector
group address
All sector
groups
No
protected?
Yes
Sector Group Protect:
Write 60h to sector
group address with
A6–A0 = 0xx0010
Set up first sector
group address
Sector Group
Unprotect:
Wait 150 µs
Write 60h to sector
group address with
A6–A0 = 1xx0010
Verify Sector Group
Protect: Write 40h
to sector group
address with
A6–A0 = 0xx0010
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
Verify Sector Group
Unprotect: Write
40h to sector group
address with
Read from
sector group address
with A6–A0
= 0xx0010
Increment
PLSCNT
A6–A0 = 1xx0010
No
No
PLSCNT
= 25?
Read from
sector group
address with
Data = 01h?
Yes
A6–A0 = 1xx0010
No
Yes
Set up
next sector group
address
Protect
another
sector group?
Yes
No
PLSCNT
= 1000?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
Last sector
group
verified?
No
Device failed
Write reset
command
Yes
Remove VID
from RESET#
Sector Group
Unprotect
Sector Group
Protect
Sector Group
Protect complete
Write reset
command
Algorithm
Algorithm
Sector Group
Unprotect complete
46
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7.11 Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector feature provides a Flash memory region that enables permanent part
identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 bytes in length,
and uses a Secured Silicon Sector Indicator Bit (DQ7) to indicate whether or not the Secured Silicon Sector is
locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed,
which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is
shipped to the field.
The factory offers the device with the Secured Silicon Sector either customer lockable (standard shipping
option) or factory locked (contact a Spansion sales representative for ordering information). The customer-
lockable version is shipped with the Secured Silicon Sector unprotected, allowing customers to program the
sector after receiving the device. The customer-lockable version also contains the Secured Silicon Sector
Indicator Bit permanently set to a 0. The factory-locked version is always protected when shipped from the
factory, and has the Secured Silicon Sector Indicator Bit permanently set to a 1. Thus, the Secured Silicon
Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory
locked. Note that the ACC function and unlock bypass modes are not available when the Secured Silicon
Sector is enabled.
The Secured Silicon sector address space in this device is allocated as follows:
Secured Silicon Sector
Address Range
Standard Factory
Locked
ExpressFlash
Factory Locked
Customer
Lockable
x16
x8
ESN or determined
by customer
000000h–000007h
000000h-00000Fh
ESN
Determined by
customer
Determined by
customer
000008h–00007Fh
000010h-0000FFh
Unavailable
The system accesses the Secured Silicon Sector through a command sequence (see Write Protect (WP#)
on page 48). After the system writes the Enter Secured Silicon Sector command sequence, it may read the
Secured Silicon Sector by using the addresses normally occupied by the first sector (SA0). This mode of
operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until
power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending
commands to sector SA0.
7.11.1
Customer Lockable: Secured Silicon Sector NOT Programmed or Protected
At the Factory
Unless otherwise specified, the device is shipped such that the customer may program and protect the 256-
byte Secured Silicon sector.
The system may program the Secured Silicon Sector using the write-buffer, accelerated and/or unlock
bypass methods, in addition to the standard programming command sequence. See Command Definitions
on page 52.
Programming and protecting the Secured Silicon Sector must be used with caution since, once protected,
there is no procedure available for unprotecting the Secured Silicon Sector area and none of the bits in the
Secured Silicon Sector memory space can be modified in any way.
The Secured Silicon Sector area can be protected using one of the following procedures:
Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then follow the in-
system sector protect algorithm as shown in Figure 7.2 on page 46, except that RESET# may be at either
VIH or VID. This allows in-system protection of the Secured Silicon Sector without raising any device pin to
a high voltage. Note that this method is only applicable to the Secured Silicon Sector.
Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then use the alternate
method of sector protection described in Sector Group Protection and Unprotection on page 41.
Once the Secured Silicon Sector is programmed, locked and verified, the system must write the Exit Secured
Silicon Sector Region command sequence to return to reading and writing within the remainder of the array.
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D a t a S h e e t
7.11.2
Factory Locked: Secured Silicon Sector Programmed and Protected At the
Factory
In devices with an ESN, the Secured Silicon Sector is protected when the device is shipped from the factory.
The Secured Silicon Sector cannot be modified in any way. An ESN Factory Locked device has an 16-byte
random ESN at addresses 000000h–000007h. Please contact your sales representative for details on
ordering ESN Factory Locked devices.
Customers may opt to have their code programmed by the factory through the Spansion programming
service (Customer Factory Locked). The devices are then shipped from the factory with the Secured Silicon
Sector permanently locked. Contact your sales representative for details on using the Spansion programming
service.
7.12 Write Protect (WP#)
The Write Protect function provides a hardware method of protecting the first or last sector group without
using VID. Write Protect is one of two functions provided by the WP#/ACC input.
If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the first or
last sector group independently of whether those sector groups were protected or unprotected. Note that if
WP#/ACC is at VIL when the device is in the standby mode, the maximum input load current is increased. See
the table in DC Characteristics on page 70.
If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the first or last sector was
previously set to be protected or unprotected using the method described in Sector Group Protection
and Unprotection on page 41. Note that WP# contains an internal pull-up; when unconnected, WP# is
at VIH.
7.13 Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection
against inadvertent writes (refer to Table 10.2 on page 61 and Table 10.1 on page 62 for command
definitions). In addition, the following hardware data protection measures prevent accidental erasure or
programming, which might otherwise be caused by spurious system level signals during VCC power-up and
power-down transitions, or from system noise.
7.13.1
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC
power-up and power-down. The command register and all internal program/erase circuits are disabled, and
the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The
system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater
than VLKO
.
7.13.2
7.13.3
Write Pulse Glitch Protection
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a logical one.
7.13.4
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising
edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
48
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D a t a S h e e t
8. Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation
handshake, which allows specific vendor-specified software algorithms to be used for entire families of
devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address
55h, any time the device is ready to read array data. The system can read CFI information at the addresses
given in Table 8.1 to Table 8.4 on page 51. To terminate reading CFI data, the system must write the reset
command.
The system can also write the CFI query command when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read CFI data at the addresses given in Table 8.1 to
Table 8.4 on page 51. The system must write the reset command to return the device to reading array data.
For further information, please refer to the CFI Specification and CFI Publication 100. Alternatively, contact
your sales representative for copies of these documents.
Table 8.1 CFI Query Identification String
Addresses (x16)
Addresses (x8)
Data
Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
Table 8.2 System Interface String
Addresses (x16) Addresses (x8)
Data
Description
V
Min. (write/erase)
CC
1Bh
1Ch
36h
38h
0027h
0036h
D7–D4: volt, D3–D0: 100 millivolt
V
Max. (write/erase)
CC
D7–D4: volt, D3–D0: 100 millivolt
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
0000h
0000h
0007h
0007h
000Ah
0000h
0001h
0005h
0004h
0000h
V
V
Min. voltage (00h = no V pin present)
PP
PP
PP
Max. voltage (00h = no V pin present)
PP
Reserved for future use
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Reserved for future use
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
Note
CFI data related to V and time-outs may differ from actual V and time-outs of the product. Please consult the Ordering Information
CC
CC
tables to obtain the V range for particular part numbers. Please consult the Erase and Programming Performance table for typical timeout
CC
specifications.
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D a t a S h e e t
Table 8.3 Device Geometry Definition
Addresses (x16) Addresses (x8)
Data
Description
Device Size = 2N byte
27h
4Eh
00xxh
0017h = 64 Mb, 0016h = 32Mb, 0015h = 16Mb
Flash Device Interface description (refer to CFI publication 100)
28h
29h
50h
52h
000xh
0000h
0000h = x8-only bus devices
0001h = x16-only bus devices
0002h = x8/x16 bus devices
2Ah
2Bh
54h
56h
0005h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
Number of Erase Block Regions within device (01h = uniform device, 02h =
boot device)
2Ch
58h
00xxh
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
0000h, 0020h, 0000h, 0007h = 16 Mb (-R1, -R2)
003Fh, 0000h, 0000h, 0001h = 32 Mb (-R1, -R2)
0007h, 0000h, 0020h, 0000h = 32 Mb (-R3, R4)
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
00xxh
000xh
00x0h
000xh
007Fh, 0000h, 0000h, 0001h = 64 Mb (-R1, -R2, -R8, -R9)
0007h, 0000h, 0020h, 0000h = 64 Mb (-R3, -R4, -R5, -R6, -R7)
Erase Block Region 2 Information (refer to CFI publication 100)
0001h, 0000h, 0000h, 001Eh = 16 Mb (-R1, -R2)
0000h, 0000h, 0000h, 0000h = all others
31h
32h
33h
34h
60h
64h
66h
68h
00xxh
0000h
0000h
000xh
007Eh, 0000h, 0000h, 0001h = 64 Mb (-R3, -R4)
003Eh, 0000h, 0000h, 0001h = 32 Mb (-R3, R4)
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
Erase Block Region 3 Information (refer to CFI publication 100)
Erase Block Region 4 Information (refer to CFI publication 100)
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
50
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Table 8.4 Primary Vendor-Specific Extended Query
Addresses (x16) Addresses (x8)
Data
Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
86h
88h
0031h
0033h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
8Ah
000xh
Process Technology (Bits 7-2) 0010b = 200 nm MirrorBit
0009h = x8-only bus devices
0008h = all other devices
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
46h
47h
48h
49h
4Ah
4Bh
4Ch
8Ch
8Eh
90h
92h
94h
96h
98h
0002h
0001h
0001h
0004h
0000h
0000h
0001h
Sector Protect
0 = Not Supported, X = Number of sectors in smallest sector group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
0004h = Standard Mode (Refer to Text)
Simultaneous Operation
00 = Not Supported, X = Number of Sectors in Bank
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
4Dh
4Eh
9Ah
9Ch
00B5h
00C5h
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
4Fh
50h
9Eh
A0h
00xxh
0001h
02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Uniform sectors
bottom WP# protect, 05h = Uniform sectors top WP# protect
Program Suspend
00h = Not Supported, 01h = Supported
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D a t a S h e e t
9. Command Definitions
Writing specific address and data commands or sequences into the command register initiates device
operations. Table 10.2 on page 61 and Table 10.1 on page 62 define the valid register command sequences.
Writing incorrect address and data values or writing them in the improper sequence may place the device in
an unknown state. A reset command is then required to return the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens first. Refer to AC Characteristics on page 72 for timing
diagrams.
9.1
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to
retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded
Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after
which the system can read data from any non-erase-suspended sector. After completing a programming
operation in the Erase Suspend mode, the system may once again read array data with the same exception.
See Erase Suspend/Erase Resume Commands on page 60 for more information.
The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if
DQ5 goes high during an active program or erase operation, or if the device is in the autoselect mode. See
Reset Command on page 52 for more information.
See also Requirements for Reading Array Data in Device Bus Operations on page 22 for more information.
The Read-Only Operations–AC Characteristics on page 72 provide the read parameters, and Figure 16.2
on page 74 shows the timing diagram.
9.2
Reset Command
Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t
cares for this command.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ignores
reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program command sequence before
programming begins. This resets the device to the read mode. If the program command sequence is written
while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-
suspend-read mode. Once programming begins, however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must be written to return to the read mode. If the device
entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device
to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the
read mode (or erase-suspend-read mode if the device was in Erase Suspend).
Note that if DQ1 goes high during a Write Buffer Programming operation, the system must write the Write-to-
Buffer-Abort Reset command sequence to reset the device for the next operation.
52
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9.3
Autoselect Command Sequence
The autoselect command sequence allows the host system to read several identifier codes at specific
addresses:
Identifier Code
Manufacturer ID
A7:A0 (x16)
00h
A6:A-1 (x8)
00h
Device ID, Cycle 1
01h
02h
Device ID, Cycle 2
0Eh
1Ch
Device ID, Cycle 3
0Fh
1Eh
Secured Silicon Sector Factory Protect
Sector Protect Verify
03h
06h
(SA)02h
(SA)04h
Note
The device ID is read over three cycles. SA = Sector Address
The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third
write cycle that contains the autoselect command. The device then enters the autoselect mode. The system
may read at any address any number of times without initiating another autoselect command sequence:
The system must write the reset command to return to the read mode (or erase-suspend-read mode if the
device was previously in Erase Suspend).
9.4
Enter/Exit Secured Silicon Sector Command Sequence
The Secured Silicon Sector region provides a secured data area containing an 8-word/16-byte random
Electronic Serial Number (ESN). The system can access the Secured Silicon Sector region by issuing the
three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured
Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence.
The Exit Secured Silicon Sector command sequence returns the device to normal operation. Table 10.2
on page 61 and Table 10.1 on page 62 show the address and data requirements for both command
sequences. See also Secured Silicon Sector Flash Memory Region on page 47 for further information. Note
that the ACC function and unlock bypass modes are not available when the Secured Silicon Sector is
enabled.
9.4.1
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two
unlock write cycles, followed by the program set-up command. The program address and data are written
next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further
controls or timings. The device automatically provides internally generated program pulses and verifies the
programmed cell margin. Table 10.2 on page 61 and Table 10.1 on page 62 show the address and data
requirements for the word program command sequence, respectively.
When the Embedded Program algorithm is complete, the device then returns to the read mode and
addresses are no longer latched. The system can determine the status of the program operation by using
DQ7 or DQ6. Refer to Write Operation Status on page 63 for information on these status bits. Any commands
written to the device during the Embedded Program Algorithm are ignored. Note that the Secured Silicon
Sector, autoselect, and CFI functions are unavailable when a program operation is in progress. Note that a
hardware reset immediately terminates the program operation. The program command sequence should be
reinitiated once the device returns to the read mode, to ensure data integrity.
Programming is allowed in any sequence of address locations and across sector boundaries. Programming
to the same word address multiple times without intervening erases (incremental bit programming) requires a
modified programming method. For such application requirements, please contact your local Spansion
representative. Word programming is supported for backward compatibility with existing Flash driver software
and for occasional writing of individual words. Use of write buffer programming (see below) is strongly
recommended for general programming use when more than a few words are to be programmed. The
effective word programming time using write buffer programming is approximately four times shorter than the
single word programming time.
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Any bit in a word cannot be programmed from 0 back to a 1. Attempting to do so may cause the device to
set DQ5=1, or cause DQ7 and DQ6 status bits to indicate the operation was successful. However, a
succeeding read shows that the data is still 0. Only erase operations can convert a 0 to a 1.
9.4.2
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program words to the device faster than using the standard
program command sequence. The unlock bypass command sequence is initiated by first writing two unlock
cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then
enters the unlock bypass mode. A two-cycle unlock bypass mode command sequence is all that is required to
program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h;
the second cycle contains the program address and data. Additional data is programmed in the same
manner. This mode dispenses with the initial two unlock cycles required in the standard program command
sequence, resulting in faster total programming time. Table 10.2 on page 61 and Table 10.1 on page 62
show the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are
valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command
sequence. The first cycle must contain the data 90h. The second cycle must contain the data 00h. The device
then returns to the read mode.
9.4.3
Write Buffer Programming
Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming
operation. This results in faster effective programming time than the standard programming algorithms. The
Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed
by a third write cycle containing the Write Buffer Load command written at the Sector Address in which
programming occurs. The fourth cycle writes the sector address and the number of word locations, minus
one, to be programmed. For example, if the system programs six unique address locations, then 05h should
be written to the device. This tells the device how many write buffer addresses are loaded with data and
therefore when to expect the Program Buffer to Flash command. The number of locations to program cannot
exceed the size of the write buffer or the operation aborts.
The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is selected
by address bits AMAX–A4. All subsequent address/data pairs must fall within the selected-write-buffer-page.
The system then writes the remaining address/data pairs into the write buffer. Write buffer locations may be
loaded in any order.
The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This
means Write Buffer Programming cannot be performed across multiple write-buffer pages.) This also means
that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load
programming data outside of the selected write-buffer page, the operation aborts.
Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter is
decremented for every data load operation. The host system must therefore account for loading a write-buffer
location more than once. The counter decrements for each data load operation, not for each unique write-
buffer-address location. Note also that if an address location is loaded more than once into the buffer, the
final data loaded for that address is programmed.
Once the specified number of write buffer locations are loaded, the system must then write the Program
Buffer to Flash command at the sector address. Any other address and data combination aborts the Write
Buffer Programming operation. The device then begins programming. Data polling should be used while
monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be
monitored to determine the device status during Write Buffer Programming.
The write-buffer programming operation can be suspended using the standard program suspend/resume
commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to
execute the next command.
The Write Buffer Programming Sequence can be aborted in the following ways:
Load a value that is greater than the page buffer size during the Number of Locations to Program step.
Write to an address in a sector different than the one specified during the Write-Buffer-Load command.
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Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address
during the write buffer data loading stage of the operation.
Write data other than the Confirm Command after the specified number of data load cycles.
The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded), DQ6 =
toggle, and DQ5= 0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the device
for the next operation.
Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when a program
operation is in progress. This flash device is capable of handling multiple write buffer programming operations
on the same write buffer address range without intervening erases. For applications requiring incremental bit
programming, a modified programming method is required; please contact your local Spansion
representative. Any bit in a write buffer address range cannot be programmed from 0 back to a 1.
Attempting to do so may cause the device to set DQ5=1, of cause the DQ7 and DQ6 status bits to indicate
the operation was successful. However, a succeeding read shows that the data is still 0. Only erase
operations can convert a 0 to a 1.
9.4.4
Accelerated Program
The device offers accelerated program operations through the WP#/ACC or ACC pin depending on the
particular product. When the system asserts VHH on the WP#/ACC or ACC pin. The device uses the higher
voltage on the WP#/ACC or ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at
VHH for operations other than accelerated programming, or device damage may result. WP# contains an
internal pull-up; when unconnected, WP# is at VIH.
Figure 9.1 on page 56 illustrates the algorithm for the program operation. Refer to the Erase and Program
Operations–AC Characteristics on page 72 for parameters, and Figure 16.3 on page 74 for timing diagrams.
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Figure 9.1 Write Buffer Programming Operation
Write “Write to Buffer”
command and
Sector Address
Part of “Write to Buffer”
Command Sequence
Write number of addresses
to program minus 1(WC)
and Sector Address
Write first address/data
Yes
WC = 0 ?
No
Write to a different
sector address
Abort Write to
Buffer Operation?
Yes
Write to buffer ABORTED.
Must write “Write-to-buffer
Abort Reset” command
sequence to return
No
Write next address/data pair
(Note 1)
to read mode.
WC = WC - 1
Write program buffer to
flash sector address
Read DQ7 - DQ0 at
Last Loaded Address
Yes
DQ7 = Data?
No
No
No
DQ1 = 1?
DQ5 = 1?
Yes
Yes
Read DQ7 - DQ0 with
address = Last Loaded
Address
Yes
(Note 2)
DQ7 = Data?
No
FAIL or ABORT
PASS
(Note 3)
Notes
1. When Sector Address is specified, any address in the selected sector is acceptable. However, when loading Write-Buffer address
locations with data, all addresses must fall within the selected Write-Buffer Page.
2. DQ7 may change simultaneously with DQ5. Therefore, DQ7 should be verified.
3. If this flowchart location was reached because DQ5= 1, then the device FAILED. If this flowchart location was reached because DQ1= 1,
then the Write to Buffer operation was ABORTED. In either case, the proper reset command must be written before the device can begin
another operation. If DQ1= 1, write the Write-Buffer-Programming-Abort-Reset command. if DQ5= 1, write the Reset command.
4. See Table 10.2 on page 61 and Table 10.1 on page 62 for command sequences required for write buffer programming.
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Figure 9.2 Program Operation
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
Yes
No
No
Increment Address
Last Address?
Yes
Programming
Completed
Note
See Table 10.2 on page 61 and Table 10.1 on page 62 for program command sequence.
9.5
Program Suspend/Program Resume Command Sequence
The Program Suspend command allows the system to interrupt a programming operation or a Write to Buffer
programming operation so that data can be read from any non-suspended sector. When the Program
Suspend command is written during a programming process, the device halts the program operation within
15 μs maximum (5μs typical) and updates the status bits. Addresses are not required when writing the
Program Suspend command.
After the programming operation is suspended, the system can read array data from any non-suspended
sector. The Program Suspend command may also be issued during a programming operation while an erase
is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend.
If a read is needed from the Secured Silicon Sector area (One-time Program area), then user must use the
proper command sequences to enter and exit this region. Note that the Secured Silicon Sector, autoselect,
and CFI functions are unavailable when a program operation is in progress.
The system may also write the autoselect command sequence when the device is in the Program Suspend
mode. The system can read as many autoselect codes as required. When the device exits the autoselect
mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See
Autoselect Command Sequence on page 53 for more information.
After the Program Resume command is written, the device reverts to programming. The system can
determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard
program operation. See Write Operation Status on page 63 for more information.
The system must write the Program Resume command (address bits are don’t care) to exit the Program
Suspend mode and continue the programming operation. Further writes of the Resume command are
ignored. Another Program Suspend command can be written after the device resumes programming.
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Figure 9.3 Program Suspend/Program Resume
Program Operation
or Write-to-Buffer
Sequence in Progress
Write Program Suspend
Command Sequence
Write address/data
XXXh/B0h
Command is also valid for
Erase-suspended-program
operations
Wait 15 μs
Autoselect and SecSi Sector
read operations are also allowed
Read data as
required
Data cannot be read from erase- or
program-suspended sectors
Done
No
reading?
Yes
Write Program Resume
Command Sequence
Write address/data
XXXh/30h
Device reverts to
operation prior to
Program Suspend
9.6
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical erase. The system is not required to provide any
controls or timings during these operations. Table 10.2 on page 61 and Table 10.1 on page 62 show the
address and data requirements for the chip erase command sequence.
When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no
longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2.
Refer to Write Operation Status on page 63 for information on these status bits.
Any commands written during the chip erase operation are ignored. However, note that a hardware reset
immediately terminates the erase operation. If this occurs, the chip erase command sequence should be
reinitiated once the device returns to reading array data, to ensure data integrity.
Figure 10.1 on page 59 illustrates the algorithm for the erase operation. Refer to Table 16.5 on page 76 for
parameters, and Figure 16.7 on page 80 for timing diagrams.
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10. Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed
by the address of the sector to be erased, and the sector erase command. Table 10.2 on page 61 and
Table 10.1 on page 62 shows the address and data requirements for the sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase.
The system is not required to provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may
be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between
these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase address and
command following the exceeded time-out may or may not be accepted. It is recommended that processor
interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be
re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or
Erase Suspend during the time-out period resets the device to the read mode. Note that the Secured
Silicon Sector, autoselect, and CFI functions are unavailable when an erase operation is in progress.
The system must rewrite the command sequence and any additional addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See DQ3: Sector Erase
Timer on page 67). The time-out begins from the rising edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses
are no longer latched. The system can determine the status of the erase operation by reading DQ7, DQ6, or
DQ2 in the erasing sector. Refer to Write Operation Status on page 63 for information on these status bits.
Once the sector erase operation begins, only the Erase Suspend command is valid. All other commands are
ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the
sector erase command sequence should be reinitiated once the device returns to reading array data, to
ensure data integrity.
Figure 10.1 illustrates the algorithm for the erase operation. Refer to Table 16.5 on page 76 for parameters,
and Figure 16.7 on page 80 for timing diagrams.
Figure 10.1 Erase Operation
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes
1. See Table 10.2 on page 61 and Table 10.1 on page 62 for program command sequence.
2. See DQ3: Sector Erase Timer on page 67 for information on the sector erase timer.
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10.1 Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected for erasure. This command is valid only during the
sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The
Erase Suspend command is ignored if written during the chip erase operation or Embedded Program
algorithm.
When the Erase Suspend command is written during the sector erase operation, the device requires a typical
of 5 μs (maximum of 20 μs) to suspend the erase operation. However, when the Erase Suspend command is
written during the sector erase time-out, the device immediately terminates the time-out period and suspends
the erase operation.
After the erase operation is suspended, the device enters the erase-suspend-read mode. The system can
read data from or program data to any sector not selected for erasure. (The device erase suspends all
sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status
information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is
actively erasing or is erase-suspended. Refer to Write Operation Status on page 63 for information on these
status bits.
After an erase-suspended program operation is complete, the device returns to the erase-suspend-read
mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just
as in the standard word program operation. Refer to Write Operation Status on page 63 for more information.
In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to
Autoselect Mode on page 40 and Autoselect Command Sequence on page 53 sections for details.
To resume the sector erase operation, the system must write the Erase Resume command. Further writes of
the Resume command are ignored. Another Erase Suspend command can be written after the chip resumes
erasing.
Note
During an erase operation, this flash device performs multiple internal operations which are invisible to the
system. When an erase operation is suspended, any of the internal operations that were not fully completed
must be restarted. As such, if this flash device is continually issued suspend/resume commands in rapid
succession, erase progress is impeded as a function of the number of suspends. The result is a longer
cumulative erase time than without suspends. Note that the additional suspends do not affect device reliability
or future performance. In most systems rapid erase/suspend activity occurs only briefly. In such cases, erase
performance is not significantly impacted.
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10.2 Command Definitions
Figure 10.2 Command Definitions (x16 Mode, BYTE# = VIH)
Command
Sequence
(Note 1)
Bus Cycles (Notes 2–5)
First
RA
Second
Third
Fourth
Fifth
Sixth
Read (Note 5)
Reset (Note 6)
1
1
4
6
4
4
RD
F0
XXX
555
555
555
555
Manufacturer ID
AA
AA
AA
AA
2AA
55
55
55
55
555
90
90
90
90
X00
X01
X01
X03
0001
Device ID (Note 8)
2AA
2AA
2AA
555
555
555
227E
X0E (Note 19) X0F (Note 19)
Device ID (Note 9)
(Note 18)
(Note 10)
Secured Silicon Sector Factory Protect
Sector Group Protect Verify
(Note 11)
4
555
AA
2AA
55
555
90
(SA)X02
00/01
Enter Secured Silicon Sector Region
Exit Secured Silicon Sector Region
Program
3
4
4
3
1
3
3
2
2
6
6
1
1
1
555
555
555
555
SA
AA
AA
AA
AA
29
2AA
2AA
2AA
2AA
55
55
55
55
555
555
555
SA
88
90
A0
25
XXX
PA
00
PD
WC
Write to Buffer (Note 12)
Program Buffer to Flash
Write to Buffer Abort Reset (Note 13)
Unlock Bypass
SA
PA
PD
WBL
PD
555
555
XXX
XXX
555
555
XXX
XXX
55
AA
AA
A0
90
2AA
2AA
PA
55
55
PD
00
55
55
555
555
F0
20
Unlock Bypass Program (Note 14)
Unlock Bypass Reset (Note 15)
Chip Erase
XXX
2AA
2AA
AA
AA
B0
30
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Program/Erase Suspend (Note 16)
Program/Erase Resume (Note 17)
CFI Query (Note 18)
98
Legend
X = Don’t care
SA = Sector Address of sector to be verified (in autoselect mode) or erased.
Address bits A21–A15 uniquely select any sector.
RA = Read Address of memory location to be read.
RD = Read Data read from location RA during read operation.
WBL = Write Buffer Location. Address must be within same write buffer page as
PA.
PA = Program Address. Addresses latch on falling edge of WE# or CE# pulse,
whichever happens later.
WC = Word Count. Number of write buffer locations to load minus 1.
PD = Program Data for location PA. Data latches on rising edge of WE# or CE#
pulse, whichever happens first.
Notes
10. Refer to Table 7.12 on page 40 for data indicating Secured Silicon Sector
factory protect status.
1. See Table 7.1 on page 22 for description of bus operations.
2. All values are in hexadecimal.
11. Data is 00h for an unprotected sector group and 01h for a protected sector
group.
3. Shaded cells indicate read cycles. All others are write cycles.
12. Total number of cycles in command sequence is determined by number of
words written to write buffer. Maximum number of cycles in command
sequence is 21, including Program Buffer to Flash command.
4. During unlock and command cycles, when lower address bits are 555 or
2AA as shown in table, address bits above A11 and data bits above DQ7 are
don’t care.
13. Command sequence resets device for next command after aborted write-to-
buffer operation.
5. No unlock or command cycles required when device is in read mode.
6. Reset command is required to return to read mode (or to erase-suspend-
read mode if previously in Erase Suspend) when device is in autoselect
mode, or if DQ5 goes high while device is providing status information.
14. Unlock Bypass command is required prior to Unlock Bypass Program
command.
15. Unlock Bypass Reset command is required to return to read mode when
device is in unlock bypass mode.
7. Fourth cycle of the autoselect command sequence is a read cycle. Data bits
DQ15–DQ8 are don’t care. Except for RD, PD and WC. See Autoselect
Command Sequence on page 53 for more information.
16. System may read and program in non-erasing sectors, or enter autoselect
mode, when in Erase Suspend mode. Erase Suspend command is valid only
during a sector erase operation.
8. For S29GL064A and S29GL032A, Device ID must be read in three cycles.
9. For S29GL016A, Device ID must be read in one cycle.
17. Erase Resume command is valid only during Erase Suspend mode.
18. Command is valid when device is ready to read array data or when device is
in autoselect mode.
19. Refer to Table 7.12 on page 40, for individual Device IDs per device density
and model number.
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Table 10.1 Command Definitions (x8 Mode, BYTE# = VIL)
Bus Cycles (Notes 2–5)
First
Second
Third
Fourth
Data
Fifth
Data
Sixth
Data
Command Sequence
(Note 1)
Addr Data Addr Data Addr Data
Addr
Addr
Addr
Read (Note 6)
Reset (Note 7)
Manufacturer ID
1
1
4
6
4
4
RA
RD
F0
XXX
AAA
AAA
AAA
AAA
AA
AA
AA
AA
555
555
555
555
55
55
55
55
AAA
AAA
AAA
AAA
90
90
90
90
X00
X02
X02
X06
01
Device ID (Note 9)
7E
X1C
(Note 9)
X1E
(Note 9)
Device ID (Note 1)
(Note 2)
(Note 1)
Secured Silicon Sector Factory Protect
Sector Group Protect Verify
(Note 3)
4
AAA
AA
555
55
AAA
90
(SA)X04
00/01
Enter Secured Silicon Sector Region
Exit Secured Silicon Sector Region
Write to Buffer (Note 4)
3
4
3
1
3
6
6
1
1
1
AAA
AAA
AAA
SA
AA
AA
AA
29
555
555
555
55
55
55
AAA
AAA
SA
88
90
25
XXX
SA
00
BC
PA
PD
WBL
PD
Program Buffer to Flash
Write to Buffer Abort Reset (Note 5)
Chip Erase
AAA
AAA
AAA
XXX
XXX
AA
AA
AA
AA
B0
30
555
555
555
55
55
55
AAA
AAA
AAA
F0
80
80
AAA
AAA
AA
AA
555
555
55
55
AAA
SA
10
30
Sector Erase
Program/Erase Suspend (Note 6)
Program/Erase Resume (Note 7)
CFI Query (Note 8)
98
Legend
X = Don’t care
SA = Sector Address of sector to be verified (in autoselect mode) or erased.
Address bits A21–A15 uniquely select any sector.
RA = Read Address of memory location to be read.
RD = Read Data read from location RA during read operation.
WBL = Write Buffer Location. Address must be within same write buffer page as
PA.
PA = Program Address. Addresses latch on falling edge of WE# or CE# pulse,
whichever happens later.
BC = Byte Count. Number of write buffer locations to load minus 1.
PD = Program Data for location PA. Data latches on rising edge of WE# or CE#
pulse, whichever happens first.
Notes
1. See Table 7.1 on page 22 for description of bus operations.
1. For S29GL016A, Device ID must be read in one cycle.
2. All values are in hexadecimal.
2. Refer to Table 7.12 on page 40, for data indicating Secured Silicon Sector
factory protect status.
3. Shaded cells indicate read cycles. All others are write cycles.
3. Data is 00h for an unprotected sector group and 01h for a protected sector
group.
4. During unlock and command cycles, when lower address bits are 555 or
AAA as shown in table, address bits above A11 are don’t care.
4. Total number of cycles in command sequence is determined by number of
bytes written to write buffer. Maximum number of cycles in command
sequence is 37, including Program Buffer to Flash command.
5. Unless otherwise noted, address bits A21–A11 are don’t cares.
6. No unlock or command cycles required when device is in read mode.
7. Reset command is required to return to read mode (or to erase-suspend-
read mode if previously in Erase Suspend) when device is in autoselect
mode, or if DQ5 goes high while device is providing status information.
5. Command sequence resets device for next command after aborted write-to-
buffer operation.
6. System may read and program in non-erasing sectors, or enter autoselect
mode, when in Erase Suspend mode. Erase Suspend command is valid only
during a sector erase operation.
8. Fourth cycle of autoselect command sequence is a read cycle. Data bits
DQ15–DQ8 are don’t care. See Autoselect Command Sequence on page 53
or more information.
7. Erase Resume command is valid only during Erase Suspend mode.
9. For S29GL064A and S29GL032A Device ID must be read in three cycles.
8. Command is valid when device is ready to read array data or when device is
in autoselect mode.
9. Refer to Table 7.12 on page 40, for individual Device IDs per device density
and model number.
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10.3 Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5,
DQ6, and DQ7. Table 10.2 on page 68 and the following subsections describe the function of these bits. DQ7
and DQ6 each offer a method for determining whether a program or erase operation is complete or in
progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an
Embedded Program or Erase operation is in progress or is completed.
10.4 DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm
is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising
edge of the final WE# pulse in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum
programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system
must provide the program address to read valid status information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to the read
mode.
During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7.
The system must provide an address within any of the sectors selected for erasure to read valid status
information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the device returns to the read mode. If not all selected
sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected. However, if the system reads DQ7 at an address within a protected
sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted low. That is, the device may change from providing
status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read
the status or valid data. Even if the device completed the program or erase operation and DQ7 has valid data,
the data outputs on DQ0–DQ6 may be still invalid. Valid data on DQ0–DQ7 appears on successive read
cycles.
Table 10.2 on page 68 shows the outputs for Data# Polling on DQ7. Figure 10.3 on page 64 shows the Data#
Polling algorithm. Figure 16.8 on page 80 shows the Data# Polling timing diagram.
September 10, 2007 S29GL-A_00_A11
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D a t a S h e e t
Figure 10.3 Data# Polling Algorithm
START
Read DQ15–DQ0
Addr = VA
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read DQ15–DQ0
Addr = VA
Yes
DQ7 = Data?
No
PASS
FAIL
Notes
1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being
erased. During chip erase, a valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5.
10.5 RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC
.
If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or in
the erase-suspend-read mode. Table 10.2 on page 68 shows the outputs for RY/BY#.
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10.6 DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete,
or whether the device entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for
approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use
DQ7 (see DQ7: Data# Polling on page 63).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program
algorithm is complete.
Table 10.2 on page 68 shows the outputs for Toggle Bit I on DQ6. Figure 10.4 on page 66 shows the toggle
bit algorithm. Figure 16.9 on page 81 shows the toggle bit timing diagrams. Figure 16.10 on page 81 shows
the differences between DQ2 and DQ6 in graphical form. See DQ2: Toggle Bit II on page 66.
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Figure 10.4 Toggle Bit Algorithm
START
Read DQ7–DQ0
Read DQ7–DQ0
No
Toggle Bit
= Toggle?
Yes
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Note
The system should recheck the toggle bit even if DQ5 = 1 because the toggle bit may stop toggling as DQ5 changes to 1. See DQ6: Toggle
Bit I on page 65 and DQ2: Toggle Bit II on page 66 for more information.
10.7 DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that
is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is
valid after the rising edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that were selected for erasure. (The
system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the
sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is
actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus,
both status bits are required for sector and mode information. Refer to Table 10.2 on page 68 to compare
outputs for DQ2 and DQ6.
Figure 10.4 on page 66 shows the toggle bit algorithm in flowchart form, and DQ2: Toggle Bit II on page 66
explains the algorithm. See also RY/BY#: Ready/Busy# on page 64. Figure 16.9 on page 81 shows the
toggle bit timing diagram. Figure 16.10 on page 81 shows the differences between DQ2 and DQ6 in graphical
form.
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10.8 Reading Toggle Bits DQ6/DQ2
Refer to Figure 10.4 on page 66 for the following discussion. Whenever the system initially begins reading
toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling.
Typically, the system would note and store the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling,
the device completed the program or erase operation. The system can read array data on DQ7–DQ0 on the
following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is high (see DQ5: Exceeded Timing Limits on page 67). If
it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have
stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device successfully
completed the program or erase operation. If it is still toggling, the device did not completed the operation
successfully, and the system must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 10.4 on page 66).
10.9 DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or write-to-buffer time exceeded a specified internal pulse count
limit. Under these conditions DQ5 produces a 1. indicating that the program or erase cycle was not
successfully completed.
The device may output a 1 on DQ5 if the system tries to program a 1 to a location that was previously
programmed to 0. Only an erase operation can change a 0 back to a 1. Under this condition, the device
halts the operation, and when the timing limit is exceeded, DQ5 produces a 1.
In all these cases, the system must write the reset command to return the device to the reading the array (or
to erase-suspend-read if the device was previously in the erase-suspend-program mode).
10.10 DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not
erasure began. (The sector erase timer does not apply to the chip erase command.) If additional sectors are
selected for erasure, the entire time-out also applies after each additional sector erase command. When the
time-out period is complete, DQ3 switches from a 0 to a 1. If the time between additional sector erase
commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See
Sector Erase Command Sequence on page 59.
After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device accepted the command sequence, and then read DQ3. If DQ3 is 1, the
Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the
erase operation is complete. If DQ3 is 0, the device accepts additional sector erase commands. To ensure
the command is accepted, the system software should check the status of DQ3 prior to and following each
subsequent sector erase command. If DQ3 is high on the second status check, the last command might not
have been accepted.
Table 10.2 on page 68 shows the status of DQ3 relative to the other status bits.
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10.11 DQ1: Write-to-Buffer Abort
DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a 1.
The system must issue the Write-to-Buffer-Abort-Reset command sequence to return the device to reading
array data. See Write Buffer on page 24 for more details.
Table 10.2 Write Operation Status
DQ7
DQ5
DQ2
Status
(Note 2)
DQ6
(Note 1) DQ3 (Note 2) DQ1 RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
Program-Suspended
DQ7#
0
Toggle
Toggle
0
0
N/A No toggle
0
0
0
Standard Mode
1
Toggle
N/A
Invalid (not allowed)
Data
1
Program-
Sector
Program Suspend Mode Suspend
Read
Non-Program
Suspended Sector
1
1
1
Erase-Suspended Sector
1
No toggle
0
N/A
Toggle
N/A
N/A
N/A
Erase-
Suspend
Read
Non-Erase Suspended
Sector
Data
Erase Suspend Mode
Erase-Suspend-Program
(Embedded Program)
DQ7#
Toggle
0
N/A
0
Busy (Note 3)
DQ7#
DQ7#
Toggle
Toggle
0
0
N/A
N/A
N/A
N/A
0
1
0
0
Write-to-
Buffer
Abort (Note 4)
Notes
1. DQ5 switches to 1 when an Embedded Program, Embedded Erase, or Write-to-Buffer operation exceeded the maximum timing limits.
Refer to DQ5: Exceeded Timing Limits on page 67 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
4. DQ1 switches to 1 when the device aborts the write-to-buffer operation.
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11. Absolute Maximum Ratings
Description
Rating
Storage Temperature, Plastic Packages
Ambient Temperature with Power Applied
–65°C to +150°C
–65°C to +125°C
–0.5 V to +4.0 V
–0.5 V to +12.5 V
V
(Note 1)
CC
Voltage with Respect to Ground
A9, OE#, ACC and RESET# (Note 2)
All other pins (Note 1)
–0.5 V to V +0.5 V
CC
Output Short Circuit Current (Note 3)
200 mA
Notes
1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or I/Os may overshoot V to –2.0 V for periods of up to
SS
20 ns. See Figure 11.1 on page 69. Maximum DC voltage on input or I/Os is V + 0.5 V. During voltage transitions, input or I/O pins may
CC
overshoot to V + 2.0 V for periods up to 20 ns. See Figure 11.2 on page 69.
CC
2. Minimum DC input voltage on pins A9, OE#, ACC, and RESET# is –0.5 V. During voltage transitions, A9, OE#, ACC, and RESET# may
overshoot V to –2.0 V for periods of up to 20 ns. See Figure 11.1 on page 69. Maximum DC input voltage on pin A9, OE#, ACC, and
SS
RESET# is +12.5 V which may overshoot to +14.0V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
4. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not
implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 11.1 Maximum Negative Overshoot Waveform
20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
20 ns
Figure 11.2 Maximum Positive Overshoot Waveform
20 ns
VCC
+2.0 V
VCC
+0.5 V
2.0 V
20 ns
20 ns
12. Operating Ranges
Description
Range
Ambient Temperature (T ), Industrial (I) Devices
–40°C to +85°C
+2.7 V to +3.6 V
+3.0 V to +3.6 V
A
V
for full voltage range
CC
CC
Supply Voltages
V
for regulated voltage range
V
V
CC
IO
Note
Operating ranges define those limits between which the functionality of the device is guaranteed.
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13. DC Characteristics
13.1 CMOS Compatible
Parameter
Symbol
Parameter Description (Notes)
Test Conditions
Min
Typ
Max
Unit
V
V
= V to V
,
CC
IN
SS
I
Input Load Current (Note 1)
A9, ACC Input Load Current
1.0
µA
LI
= V
CC
CC max
-40°C to 0°C
0°C to 85°C
250
35
V
= V
; A9
CC
CC max
I
µA
LIT
= 12.5 V
I
Reset Leakage Current
Output Leakage Current
V
= V
; RESET# = 12.5 V
35
µA
µA
LR
CC
CC max
V
V
= V to V
= V
,
CC
OUT
SS
I
1.0
LO
CC
CC max
1 MHz
5 MHz
10 MHz
10 MHz
5
18
35
5
20
25
50
20
CE# = V OE# =
IL,
I
V
V
Initial Read Current (Notes 2, 3)
Intra-Page Read Current
mA
mA
CC1
CC2
CC
V
,
IH
CC
CE# = V OE# =
IL,
(Notes 2, 3)
I
V
IH
40 MHz
10
50
1
40
60
5
I
I
I
I
V
V
V
Active Write Current (Note 3)
Standby Current (Note 3)
Reset Current (Note 3)
CE# = V OE# = V
mA
µA
µA
µA
CC3
CC4
CC5
CC6
CC
CC
CC
IL,
IH
CE#, RESET# = V
0.3 V,
CC
WP# = V
IH
RESET# = V
0.3 V, WP# = V
1
5
SS
IH
V
= V
0.3 V;
IH
CC
IL
Automatic Sleep Mode (Notes 3, 5)
1
5
-0.1< V ≤ 0.3 V, WP# = V
IH
V
Input Low Voltage 1 (Note 6)
Input High Voltage 1 (Note 6)
–0.5
0.8
V
V
IL
V
0.7 V
V
+ 0.5
CC
IH
CC
Voltage for ACC Program
Acceleration
V
V
V
= 2.7 –3.6 V
= 2.7 –3.6 V
11.5
11.5
12.0
12.0
12.5
V
V
HH
CC
Voltage for Autoselect and Temporary
Sector Unprotect
V
12.5
0.45
ID
CC
V
Output Low Voltage (Note 6)
I
I
I
= 4.0 mA, V = V
V
V
V
V
OL
OL
OH
OH
CC
CC min
V
V
= –2.0 mA, V = V
0.85 V
CC
OH1
CC
CC min
CC min
Output High Voltage
= –100 µA, V = V
V
–0.4
OH2
CC
CC
V
Low V Lock-Out Voltage (Note 7)
2.3
2.5
LKO
CC
Notes
1. On the WP#/ACC pin only, the maximum input load current when WP# = V is 5.0 µA.
IL
2. The I current listed is typically less than 3.5 mA/MHz, with OE# at V
.
CC
IH
3. Maximum I specifications are tested with V = V max.
CC
CC
CC
4.
I
active while Embedded Erase or Embedded Program is in progress.
CC
5. Automatic sleep mode enables the low power mode when addresses remain stable for t
+ 30 ns.
ACC
6.
V
voltage requirements.
CC
7. Not 100% tested.
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14. Test Conditions
Figure 14.1 Test Setup
3.3 V
2.7 kΩ
Device
Under
Test
C
6.2 kΩ
L
Note
Diodes are IN3064 or equivalent.
Table 14.1 Test Specifications
Test Condition
All Speeds
1 TTL gate
Unit
Output Load
Output Load Capacitance, C
(including jig capacitance)
L
30
pF
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
0.0 or V
CC
Input timing measurement reference levels
Output timing measurement reference levels
0.5 V
0.5 V
V
CC
CC
V
15. Key to Switching Waveforms
Waveform
Inputs
Outputs
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
Figure 15.1 Input Waveforms and Measurement Levels
V
CC
0.5 V
Input
0.5 V
Measurement Level
Output
CC
CC
0.0 V
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16. AC Characteristics
Table 16.1 Read-Only Operations-S29GL064A Only
Parameter
Speed Options
JEDEC
Std.
Description
Read Cycle Time (Note 1)
Test Setup
90
10
100
100
100
30
11
110
110
110
30
Unit
ns
t
t
Min
Max
Max
Max
Max
Max
Max
90
90
90
25
25
AVAV
RC
t
t
Address to Output Delay
CE#, OE# = V
IL
ns
AVQV
ACC
t
t
Chip Enable to Output Delay
Page Access Time
OE# = V
IL
ns
ELQV
CE
t
ns
PACC
t
t
t
Output Enable to Output Delay
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
30
30
ns
GLQV
EHQZ
GHQZ
OE
t
t
16
ns
DF
t
16
0
ns
DF
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
t
t
Min
Min
Min
ns
ns
ns
AXQX
OH
Read
0
Output Enable Hold
Time
t
OEH
Toggle and
10
(Note 1)
Data# Polling
Notes
1. Not 100% tested.
2. See Figure 14.1 on page 71 and Table 14.1 on page 71 for test specifications
Table 16.2 Read-Only Operations-S29GL032A Only
Parameter
Speed Options
JEDEC Std.
Description
Read Cycle Time (Note 1)
Test Setup
90
10
100
100
100
30
11
Unit
ns
t
t
Min
Max
Max
Max
Max
Max
Max
90
90
90
25
25
110
110
110
30
AVAV
RC
t
t
Address to Output Delay
CE#, OE# = V
IL
ns
AVQV
ACC
t
t
Chip Enable to Output Delay
Page Access Time
OE# = V
IL
ns
ELQV
CE
t
ns
PACC
t
t
t
Output Enable to Output Delay
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
30
30
ns
GLQV
EHQZ
GHQZ
OE
t
t
16
ns
DF
DF
t
16
ns
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
t
t
Min
Min
Min
0
0
ns
ns
ns
AXQX
OH
Read
t
Output Enable Hold Time (Note 1)
Toggle and
OEH
10
Data# Polling
Notes
1. Not 100% tested.
2. See Figure 14.1 on page 71 and Table 14.1 on page 71 for test specifications.
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Table 16.3 Read-Only Operation-S29GL016A Only
Parameter
JEDEC Std.
Speed Options
Description
Read Cycle Time (Note 1)
Test Setup
90
90
90
90
25
25
10
100
100
100
30
Unit
ns
t
t
Min
Max
Max
Max
Max
Max
Max
AVAV
RC
t
t
Address to Output Delay
CE#, OE# = V
IL
ns
AVQV
ACC
t
t
Chip Enable to Output Delay
Page Access Time
OE# = V
IL
ns
ELQV
CE
t
ns
PACC
t
t
t
Output Enable to Output Delay
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
30
ns
GLQV
EHQZ
GHQZ
OE
t
t
16
16
ns
DF
t
ns
DF
Output Hold Time From Addresses, CE# or OE#, Whichever
Occurs First
t
t
Min
0
ns
AXQX
OH
Read
Output Enable Hold Time (Note 1)
Toggle and Data# Polling
Min
Min
0
ns
ns
t
OEH
10
Notes
1. Not 100% tested.
2. See Figure 14.1 on page 71 and Table 14.1 on page 71 for test specifications.
Figure 16.1 VCC Power-up Diagram
tVCS
VCC
VCC
min
VIH
RESET#
t
RH
CE#
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Figure 16.2 Read Operation Timings
tRC
Addresses Stable
tACC
Addresses
CE#
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 16.3 Page Read Timings
Same Page
A23-A2
A1-A0*
Aa
tACC
Ad
Ab
tPACC
Ac
tPACC
tPACC
Data Bus
Qa
Qb
Qc
Qd
CE#
OE#
Note
* Figure shows device in word mode. Addresses are A1–A-1 for byte mode.
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Table 16.4 Hardware Reset (RESET#)
Parameter
JEDEC Std.
All Speed
Options
Description
RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note)
RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode(See Note)
RESET# Pulse Width
Unit
μs
t
Max
Max
Min
Min
Min
Min
20
500
500
50
Ready
Ready
t
ns
t
ns
RP
t
Reset High Time Before Read (See Note)
ns
RH
t
RESET# Input Low to Standby Mode (See Note)
RY/BY# Output High to CE#, OE# pin Low
20
µs
RPD
t
0
ns
RB
Note
Not 100% tested.
Figure 16.4 Reset Timings
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRH
tRP
Notes
1. Not 100% tested.
2. See the Erase And Programming Performance on page 87 for more information.
3. For 1–16 words/1–32 bytes programmed.
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Table 16.5 Erase and Program Operations-S29GL064A
Parameter
JEDEC Std.
Speed Options
Description
90
10
100
0
11
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
Write Cycle Time (Note 1)
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Min
Min
Min
Max
90
110
AVAV
WC
t
t
Address Setup Time
AVWL
AS
t
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
15
45
0
ASO
t
t
AH
WLAX
t
Address Hold Time From CE# or OE# high during toggle bit polling
Data Setup Time
AHT
t
t
35
0
DVWH
DS
t
t
Data Hold Time
WHDX
DH
t
CE# High during toggle bit polling
OE# High during toggle bit polling
Read Recovery Time Before Write (OE# High to WE# Low)
CE# Setup Time
20
20
0
CEPH
OEPH
GHWL
t
t
t
GHWL
t
t
0
ELWL
WHEH
WLWH
CS
CH
WP
t
t
t
CE# Hold Time
0
t
Write Pulse Width
35
30
240
60
54
0.5
250
50
100
4
t
t
Write Pulse Width High
WHDL
WPH
Write Buffer Program Operation (Note 2, 3)
Single Word Program Operation (Note 2)
Accelerated Single Word Program Operation (Note 2)
Sector Erase Operation (Note 2)
t
t
t
t
µs
WHWH1
WHWH2
WHWH1
sec
ns
µs
ns
µs
WHWH2
t
V
V
Rise and Fall Time (Note 1)
Setup Time (Note 1)
VHH
HH
CC
t
VCS
t
WE# High to RY/BY# Low
90
110
BUSY
t
Program Valid before Status Polling
POLL
Notes
1. Not 100% tested.
2. See the Erase And Programming Performance on page 87 for more information.
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within t
, the device requires t
before reading status data, once programming resumes
POLL
POLL
(that is, the program resume command is written). If the suspend command was issued after t
after programming resumes. See Figure 16.5 on page 79.
, status data is available immediately
POLL
76
S29GL-A
S29GL-A_00_A11 September 10, 2007
D a t a S h e e t
Table 16.6 Erase and Program Operations-S29GL032A Only
Parameter
JEDEC Std.
Speed Options
Description
90
90
10
100
0
11
110
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
Write Cycle Time (Note 1)
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Min
Min
Min
Max
AVAV
WC
t
t
Address Setup Time
AVWL
AS
t
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
15
45
0
ASO
t
t
AH
WLAX
t
Address Hold Time From CE# or OE# high during toggle bit polling
Data Setup Time
AHT
t
t
35
0
DVWH
DS
t
t
Data Hold Time
WHDX
DH
t
CE# High during toggle bit polling
OE# High during toggle bit polling
Read Recovery Time Before Write (OE# High to WE# Low)
CE# Setup Time
20
20
0
CEPH
OEPH
GHWL
t
t
t
GHWL
t
t
0
ELWL
WHEH
WLWH
CS
CH
WP
t
t
CE# Hold Time
0
t
t
Write Pulse Width
35
30
240
60
54
0.5
250
50
100
4
t
t
Write Pulse Width High
WHDL
WPH
Write Buffer Program Operation (Note 2, 3)
Single Word Program Operation (Note 2)
Accelerated Single Word Program Operation (Note 2)
Sector Erase Operation (Note 2)
t
t
t
t
µs
WHWH1
WHWH1
WHWH2
sec
ns
µs
ns
µs
WHWH2
t
V
V
Rise and Fall Time (Note 1)
Setup Time (Note 1)
VHH
HH
CC
t
VCS
t
WE# High to RY/BY# Low
90
110
BUSY
t
Program Valid before Status Polling
POLL
Notes
1. Not 100% tested.
2. See Erase And Programming Performance on page 87 for more information
3. For 1–16 words/1–32 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. If a program suspend command is issued within t
, the device requires t
before reading status data, once programming resumes
POLL
POLL
(that is, the program resume command is written). If the suspend command was issued after t
after programming resumes. See Figure 16.5 on page 79.
, status data is available immediately
POLL
September 10, 2007 S29GL-A_00_A11
S29GL-A
77
D a t a S h e e t
Table 16.7 Erase and Program Operations-S29GL016A Only
Parameter
JEDEC Std.
Speed Options
90 10
90 100
Description
Unit
ns
t
t
Write Cycle Time (Note 1)
Address Setup Time
Min
Min
Min
Min
AVAV
WC
t
t
0
ns
AVWL
AS
t
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
15
45
ns
ASO
t
t
ns
WLAX
AH
Address Hold Time From CE# or OE# high during toggle bit
polling
t
Min
0
ns
AHT
t
t
Data Setup Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Min
Min
Max
Max
35
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
DVWH
DS
t
t
Data Hold Time
WHDX
DH
t
CE# High during toggle bit polling
OE# High during toggle bit polling
Read Recovery Time Before Write (OE# High to WE# Low)
CE# Setup Time
20
20
0
CEPH
OEPH
GHWL
t
t
t
GHWL
t
t
0
ELWL
WHEH
WLWH
CS
CH
WP
t
t
CE# Hold Time
0
t
t
Write Pulse Width
35
30
240
60
54
0.5
250
50
t
t
Write Pulse Width High
WHDL
WPH
Write Buffer Program Operation (Note 2, 3)
Single Word Program Operation (Note 2)
Accelerated Single Word Program Operation (Note 2)
Sector Erase Operation (Note 2)
t
t
t
t
µs
WHWH1
WHWH2
WHWH1
WHWH2
sec
ns
µs
ns
µs
t
V
V
Rise and Fall Time (Note 1)
Setup Time (Note 1)
VHH
HH
CC
t
VCS
t
WE# High to RY/BY# Low
90
100
BUSY
t
Program Valid before Status Polling
4
POLL
Notes
1. Not 100% tested.
2. See Erase And Programming Performance on page 87 for more information
3. For 1–16 words/1–32 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. If a program suspend command is issued within t
, the device requires t
before reading status data, once programming resumes
POLL
POLL
(that is, the program resume command is written). If the suspend command was issued after t
after programming resumes. See Figure 16.5 on page 79
, status data is available immediately
POLL
78
S29GL-A
S29GL-A_00_A11 September 10, 2007
D a t a S h e e t
Figure 16.5 Program Operation Timings
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#
OE#
tCH
tPOLL
tWP
WE#
Data
tWPH
tCS
tWHWH1
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes
1. PA = program address, PD = program data, D
is the true data at the program address.
OUT
2. Illustration shows device in word mode.
Figure 16.6 Accelerated Program Timing Diagram
VHH
VIL or VIH
VIL or VIH
ACC
tVHH
tVHH
September 10, 2007 S29GL-A_00_A11
S29GL-A
79
D a t a S h e e t
Figure 16.7 Chip/Sector Erase Operation Timings
Erase Command Sequence (last two cycles)
Read Status Data
tAS
SA
tWC
VA
Addresses
CE#
2AAh
VA
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 63.)
2. Illustration shows device in word mode.
Figure 16.8 Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
tPOLL
tCH
tOE
OE#
WE#
tDF
tOH
tOEH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ0–DQ6
Status Data
True
Valid Data
Status Data
tBUSY
RY/BY#
Note
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
80
S29GL-A
S29GL-A_00_A11 September 10, 2007
D a t a S h e e t
Figure 16.9 Toggle Bit Timings (During Embedded Algorithms)
tAHT
tAS
Addresses
CE#
tAHT
tASO
tCEPH
tOEH
WE#
OE#
tOEPH
tDH
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
DQ6 / DQ2
Valid Data
(first read)
(second read)
(stops toggling)
RY/BY#
Note
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array
data read cycle.
Figure 16.10 DQ2 vs. DQ6
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note
DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.
September 10, 2007 S29GL-A_00_A11
S29GL-A
81
D a t a S h e e t
Table 16.8 Temporary Sector Unprotect
Parameter
JEDEC Std
Description
All Speed Options
Unit
ns
t
V
Rise and Fall Time (See Note)
ID
Min
Min
500
4
VIDR
t
RESET# Setup Time for Temporary Sector Unprotect
µs
RSP
Note
Not 100% tested.
Figure 16.11 Temporary Sector Group Unprotect Timing Diagram
VID
VID
RESET#
VSS, VIL,
or VIH
VSS, VIL,
or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRRB
tRSP
RY/BY#
Figure 16.12 Sector Group Protect and Unprotect Timing Diagram
VID
VIH
RESET#
SA, A6,
A3, A2,
A1, A0
Valid*
Valid*
Valid*
Status
Sector Group Protect or Unprotect
Verify
40h
Data
60h
60h
Sector Group Protect: 150 µs,
Sector Group Unprotect: 15 ms
1 µs
CE#
WE#
OE#
Note
For sector group protect, A6:A0 = 0xx0010. For sector group unprotect, A6:A0 = 1xx0010.
82
S29GL-A
S29GL-A_00_A11 September 10, 2007
D a t a S h e e t
Table 16.9 Alternate CE# Controlled Erase and Program Operations-S29GL064A
Parameter
JEDEC Std.
Speed Options
Description
90
10
100
0
11
Unit
ns
t
t
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
90
110
AVAV
WC
t
t
t
ns
AVWL
AS
AH
DS
DH
t
t
45
35
0
ns
ELAX
DVEH
EHDX
t
ns
t
t
Data Hold Time
ns
Read Recovery Time Before Write (OE# High to WE#
Low)
t
t
t
Min
0
ns
GHEL
WLEL
GHEL
t
WE# Setup Time
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Min
Max
0
0
ns
ns
ns
ns
WS
t
t
WE# Hold Time
EHWH
WH
t
t
CE# Pulse Width
35
25
240
60
54
0.5
50
4
ELEH
EHEL
CP
t
t
CE# Pulse Width High
CPH
Write Buffer Program Operation (Notes 2, 3)
Single Word Program Operation (Note 2)
Accelerated Single Word Program Operation (Note 2)
Sector Erase Operation (Note 2)
RESET# High Time Before Write
Program Valid before Status Polling (Note 4)
t
t
t
t
µs
WHWH1
WHWH1
WHWH2
sec
ns
WHWH2
t
RH
t
µs
POLL
Notes
1. Not 100% tested.
2. See Erase And Programming Performance on page 87 for more information.
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within t
, the device requires t
before reading status data, once programming resumes
POLL
POLL
(that is, the program resume command is written). If the suspend command was issued after t
after programming resumes. See Figure 16.13 on page 86.
, status data is available immediately
POLL
September 10, 2007 S29GL-A_00_A11
S29GL-A
83
D a t a S h e e t
Table 16.10 Alternate CE# Controlled Erase and Program Operations-S29GL032A
Parameter
JEDEC Std.
Speed Options
Description
90
10
100
0
11
Unit
ns
t
t
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
90
110
AVAV
WC
t
t
t
ns
AVWL
AS
AH
DS
DH
t
t
45
35
0
ns
ELAX
DVEH
EHDX
t
ns
t
t
Data Hold Time
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
t
Min
0
ns
GHEL
WLEL
GHEL
t
WE# Setup Time
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Min
Max
0
0
ns
ns
ns
ns
WS
t
t
WE# Hold Time
EHWH
WH
t
t
CE# Pulse Width
35
25
240
60
54
0.5
50
4
ELEH
EHEL
CP
t
t
CE# Pulse Width High
CPH
Write Buffer Program Operation (Notes 2, 3)
Single Word Program Operation (Note 2)
Accelerated Single Word Program Operation (Note 2)
Sector Erase Operation (Note 2)
RESET# High Time Before Write
Program Valid before Status Polling (Note 4)
t
t
t
t
µs
WHWH1
WHWH1
WHWH2
sec
ns
WHWH2
t
RH
t
µs
POLL
Notes
1. Not 100% tested.
2. See Erase And Programming Performance on page 87 for more information
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within t
, the device requires t
before reading status data, once programming resumes
POLL
POLL
(that is, the program resume command is written). If the suspend command was issued after t
after programming resumes. See Figure 16.13 on page 86.
, status data is available immediately
POLL
84
S29GL-A
S29GL-A_00_A11 September 10, 2007
D a t a S h e e t
Table 16.11 Alternate CE# Controlled Erase and Program Operations-S29GL016A
Parameter
JEDEC Std.
Speed Options
Description
90
10
Unit
ns
t
t
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
90
100
AVAV
WC
t
t
t
0
45
35
0
ns
AVWL
AS
AH
DS
DH
t
t
ns
ELAX
DVEH
EHDX
t
ns
t
t
Data Hold Time
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
t
Min
0
ns
GHEL
GHEL
t
WE# Setup Time
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Min
Max
0
0
ns
ns
ns
ns
WLEL
WS
t
t
WE# Hold Time
EHWH
WH
t
t
CE# Pulse Width
35
25
240
60
54
0.5
50
4
ELEH
CP
t
t
CE# Pulse Width High
EHEL
CPH
Write Buffer Program Operation (Notes 2, 3)
Single Word Program Operation (Note 2)
Accelerated Single Word Program Operation (Note 2)
Sector Erase Operation (Note 2)
RESET# High Time Before Write
Program Valid before Status Polling (Note 4)
t
t
t
t
µs
WHWH1
WHWH2
WHWH1
sec
ns
WHWH2
t
RH
t
µs
POLL
Notes
1. Not 100% tested.
2. See Erase And Programming Performance on page 87 for more information
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within t
, the device requires t
before reading status data, once programming resumes
POLL
POLL
(that is, the program resume command is written). If the suspend command was issued after t
after programming resumes. See Figure 16.13 on page 86
, status data is available immediately
POLL
September 10, 2007 S29GL-A_00_A11
S29GL-A
85
D a t a S h e e t
Figure 16.13 Alternate CE# Controlled Write (Erase/Program) Operation Timings
PBA for program
2AA for erase
SA for program buffer to flash
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tPOLL
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
tRH
PBD for program 29 for program buffer to flash
55 for erase
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. D
4. Illustration shows device in word mode
is the data written to the device.
OUT
86
S29GL-A
S29GL-A_00_A11 September 10, 2007
D a t a S h e e t
17. Erase And Programming Performance
Max
Parameter
Sector Erase Time
Typ (Note 1)
(Note 2)
Unit
Comments
0.5
17.5
32
3.5
35
Excludes 00h
programming prior
to erasure
S29GL016A
sec
Chip Erase Time
S29GL032A
S29GL064A
64
(Note 6)
64
128
Total Write Buffer Program Time (Notes 3, 5)
240
200
16
µs
Total Accelerated Effective Write Buffer Program Time (Notes 4, 5)
S29GL016A
Excludes system
level overhead
(Note 7)
Chip Program Time
S29GL032A
S29GL064A
31.5
63
sec
Notes
1. Typical program and erase times assume the following conditions: 25°C, V = 3.0V, 10,000 cycles; checkerboard data pattern.
CC
2. Under worst case conditions of 90°C; Worst case V , 100,000 cycles.
CC
3. Effective programming time (typ) is 15 μs (per word), 7.5 μs (per byte).
4. Effective accelerated programming time (typ) is 12.5 μs (per word), 6.3 μs (per byte).
5. Effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer operation.
6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
7. System-level overhead is the time required to execute the command sequence(s) for the program command. See Table 10.2 on page 61
and Table 10.1 on page 62 for further information on command definitions.
Table 17.1 TSOP Pin and BGA Package Capacitance
Parameter Symbol
Parameter Description
Test Setup
Typ
6
Max
7.5
5.0
12
Unit
pF
pF
pF
pF
pF
pF
TSOP
BGA
C
Input Capacitance
V
= 0
IN
IN
4.2
8.5
5.4
7.5
3.9
TSOP
BGA
C
Output Capacitance
V
= 0
OUT
OUT
6.5
9
TSOP
BGA
C
Control Pin Capacitance
V
= 0
IN
IN2
4.7
Notes
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
September 10, 2007 S29GL-A_00_A11
S29GL-A
87
D a t a S h e e t
18. Physical Dimensions
18.1 TS048—48-Pin Standard Thin Small Outline Package (TSOP)
STANDARD PIN OUT (TOP VIEW)
A2
2
0.10 C
1
N
SEE DETAIL B
-A-
-B-
5
E
e
9
N
2
N
2
+1
5
A1
D1
4
C
D
SEATING
PLANE
B
A
0.08MM (0.0031")
M
C
A-B
6
S
B
b
7
SEE DETAAIILL A
WITH PLATING
c1
(c)
7
b1
BASE METAL
R
SECTION B-B
e/2
c
GAGE LINE
0.25MM (0.0098") BSC
0˚
-X-
X = A OR B
PARALLEL TO
SEATING PLANE
L
DETAIL A
DETAIL B
NOTES:
Package
TS 048
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (MM).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)
MO-142 (B) EC
Jedec
1
2
3
4
MIN
NOM MAX
1.20
Symbol
PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
NOT APPLICABLE.
A
A1
A2
b1
b
c1
c
D
0.15
0.05
0.95
0.17
0.17
0.10
0.10
1.00
0.20
0.22
1.05
0.23
0.27
0.16
0.21
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF
CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT
HORIZONTAL SURFACE.
5
6
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS
0.15MM (.0059") PER SIDE.
19.80 20.00 20.20
18.30 18.40 18.50
11.90 12.00 12.10
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE
0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE
BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").
D1
E
e
7
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND
0.25MM (0.0098") FROM THE LEAD TIP.
0.50 BASIC
L
0
R
N
0.50
0˚
0.60
3˚
0.70
5˚
8
9
LEAD COPLANARITY SHALL BE WITHIN 0.10MM (0.004") AS MEASURED FROM THE SEATING PLANE.
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
0.08
0.20
48
3325 \ 16-038.10a
88
S29GL-A
S29GL-A_00_A11 September 10, 2007
D a t a S h e e t
18.2 TS056—56-Pin Standard Thin Small Outline Package (TSOP)
2X
0.10
STANDARD PIN OUT (TOP VIEW)
2X (N/2 TIPS)
2X
0.10
2
0.10
A2
1
N
REVERSE PIN OUT (TOP VIEW)
3
SEE DETAIL B
A
B
1
N
5
E
N
2
N
2
+1
e
9
5
D1
A1
N
+1
N
2
4
2
D
0.25
2X (N/2 TIPS)
C
B
SEATING
PLANE
A
B
SEE DETAIL A
0.08MM (0.0031")
M
C
A - B S
b
6
7
WITH PLATING
c1
(c)
7
b1
BASE METAL
SECTION B-B
R
(c)
e/2
GAUGE PLANE
0.25MM (0.0098") BSC
θ°
PARALLEL TO
SEATING PLANE
X
C
L
X = A OR B
DETAIL A
DETAIL B
NOTES:
Package
Jedec
TS 056
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)
MO-142 (D) EC
1
2
3
4
MIN
NOM MAX
1.20
Symbol
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP).
A
A1
A2
b1
b
c1
c
D
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.
0.15
0.05
0.95
0.17
0.17
0.10
0.10
1.00
0.20
1.05
0.23
0.27
0.16
0.21
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF
CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT
HORIZONTAL SURFACE.
0.22
5
6
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS
0.15mm (.0059") PER SIDE.
19.80 20.00 20.20
18.30 18.40 18.50
13.90 14.00 14.10
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE
0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE
BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").
D1
E
e
7
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND
0.25MM (0.0098") FROM THE LEAD TIP.
0.50 BASIC
L
0
R
N
0.50
0˚
0.08
0.60
0.70
8˚
0.20
8
9
LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE.
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
56
3356 \ 16-038.10c
September 10, 2007 S29GL-A_00_A11
S29GL-A
89
D a t a S h e e t
18.3 LAA064—64-Ball Fortified Ball Grid Array (BGA)
90
S29GL-A
S29GL-A_00_A11 September 10, 2007
D a t a S h e e t
18.4 VBN048—48-Ball Fine-pitch Ball Grid Array (BGA) 10x 6 mm Package
D1
A
D
e
6
5
4
3
2
1
e
7
SE
E1
E
Ø0.50
H
G
F
E
D
C
B
A
B
A1 CORNER
+0.20
-0.50
7
6
SD
1.00
A1 ID.
Øb
Ø0.08
Ø0.15
M
C
M
C A B
0.10
C
A2
A
SEATING PLANE
0.08 C
C
A1
NOTES:
PACKAGE
JEDEC
VBN 048
N/A
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
10.00 mm x 6.00 mm NOM
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
SYMBOL
MIN
---
NOM
MAX
1.00
---
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
A2
D
---
---
OVERALL THICKNESS
BALL HEIGHT
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
0.17
0.62
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
---
0.73
BODY THICKNESS
BODY SIZE
10.00 BSC.
6.00 BSC.
5.60 BSC.
4.00 BSC.
8
N IS THE TOTAL NUMBER OF SOLDER BALLS.
E
BODY SIZE
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
D1
E1
MD
ME
N
BALL FOOTPRINT
BALL FOOTPRINT
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
ROW MATRIX SIZE D DIRECTION
ROW MATRIX SIZE E DIRECTION
TOTAL BALL COUNT
6
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
48
φb
0.35
---
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
e
0.80 BSC.
0.40 BSC.
NONE
BALL PITCH
SD / SE
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
8. NOT USED.
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3425\ 16-038.25
September 10, 2007 S29GL-A_00_A11
S29GL-A
91
D a t a S h e e t
18.5 VBK048—Ball Fine-pitch Ball Grid Array (BGA) 8.15x 6.15 mm Package
0.10 (4X)
D1
A
D
6
5
4
3
2
1
7
e
SE
E1
E
H
G
F
E
D
C
B
A
INDEX MARK
10
6
B
A1 CORNER
PIN A1
CORNER
7
φb
φ 0.08
φ 0.15
SD
M
M
C
TOP VIEW
C A B
BOTTOM VIEW
0.10
C
A2
A
SEATING PLANE
SIDE VIEW
0.08
C
C
A1
NOTES:
PACKAGE
JEDEC
VBK 048
N/A
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
8.15 mm x 6.15 mm NOM
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
SYMBOL
MIN
---
NOM
MAX
1.00
---
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
A2
D
---
OVERALL THICKNESS
BALL HEIGHT
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
0.18
0.62
---
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
---
8.15 BSC.
6.15 BSC.
5.60 BSC.
4.00 BSC.
8
0.76
BODY THICKNESS
BODY SIZE
N IS THE TOTAL NUMBER OF SOLDER BALLS.
E
BODY SIZE
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
D1
E1
MD
ME
N
BALL FOOTPRINT
BALL FOOTPRINT
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
ROW MATRIX SIZE D DIRECTION
ROW MATRIX SIZE E DIRECTION
TOTAL BALL COUNT
6
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
48
φb
0.35
---
0.43
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
e
0.80 BSC.
0.40 BSC.
---
BALL PITCH
SD / SE
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
8. NOT USED.
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3338 \ 16-038.25 \ 10.05.04
92
S29GL-A
S29GL-A_00_A11 September 10, 2007
D a t a S h e e t
18.6 VBU056—Ball Fine-pitch Ball Grid Array (BGA) 9 x 7 mm Package
D1
A
D
e
0.05
(2X)
C
8
7
6
SE
7
5
4
E
B
E1
3
e
2
1
H
G
F
E
D
C
B
A
A1 CORNER
A1 CORNER
INDEX MARK
6
10
NXφb
SD
7
φ 0.08
φ 0.15
M
C
C
0.05
(2X)
C
TOP VIEW
M
A B
BOTTOM VIEW
0.10
C
C
A2
A
0.08
C
SEATING PLANE
A1
SIDE VIEW
NOTES:
PACKAGE
JEDEC
VBU 056
N/A
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
9.00 mm x 7.00 mm NOM
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
SYMBOL
MIN
---
NOM
---
MAX
NOTE
OVERALL THICKNESS
BALL HEIGHT
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
A2
D
1.00
---
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
0.17
0.62
---
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
---
0.76
BODY THICKNESS
BODY SIZE
9.00 BSC.
7.00 BSC.
5.60 BSC.
5.60 BSC.
8
N IS THE TOTAL NUMBER OF SOLDER BALLS.
E
BODY SIZE
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
D1
E1
MD
ME
N
BALL FOOTPRINT
BALL FOOTPRINT
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
ROW MATRIX SIZE D DIRECTION
ROW MATRIX SIZE E DIRECTION
TOTAL BALL COUNT
8
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
56
φb
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
e
0.80 BSC.
0.40 BSC.
BALL PITCH
SD / SE
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
8. NOT USED.
A1,A8,D4,D5,E4,E5,H1,H8
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3440\ 16-038.25 \ 01.13.05
September 10, 2007 S29GL-A_00_A11
S29GL-A
93
D a t a S h e e t
19. Revision History
Section
Revision A (October 13, 2004)
Global
Description
Initial Release.
Revision A1 (December 17, 2004)
Secured Silicon Sector Flash Memory Region
DC Characteristics (CMOS Compatible)
Revision A2 (January 28, 2005)
Global
Updated Secured Silicon Sector address table with addresses in x8-mode.
Re-specified ILIT over temperature. Corrected WP#/ACC input load current footnote.
Added S29GL032A information.
Revision A3 (April 22, 2005)
Global
Added S29GL016A information.
Table 7.12
Corrected Secured Silicon Sector Indicator Bit.
Revision A4 (July 29, 2005)
Corrected S29GL032A fine-pitch BGA package description from VBN048 to VBK048.
Corrected S29GL016A information in Tables 15 and 17.
Global
Updated Ordering Information and Valid Combinations for S29GL016A, S29GL032A,
and S29GL064A. Added requirements for MCP Cellular Handsets.
Added VBU056 Connection Diagram and VBU056 Package Dimension drawings
Revision A5 (January 11, 2006)
Added model numbers 01 and 02 to ordering information section and autoselect codes
table.
Corrected sector address bit range in S29GL064A table for models R3, W3 and table
for models R4 and W4.
Global
Replaced model numbers W1, W2 with W3, W4 in DQ7 to DQ0 section of sector
address table.
Revision A6 (June 5, 2006)
Removed the 64 Mb MCP-compatible devices.
Global
Removed the 32 Mb single-bank products in the MCP-compatible package.
Revision A7 (January 22, 2007)
AC Characteristics
Erase and Program Operations table: Changed tBUSY to a maximum specification.
Revision A8 (January 29, 2007)
Global
Deleted Preliminary designation from document.
Revision A9 (March 23, 2007)
Connection Diagrams
Clarified notes for LAA064 package.
Corrected page breaks in tables.
Sector Address Tables
Revision A10 (August 6, 2007)
Device Geometry Definition Table
Revision A11 (September 10, 2007)
Cover page and first page
Device Geometry Definition Table
Corrected CFI values in Erase Block Region 1 & 2
GL032A is now included as EOD, in addition to GL064A.
Corrected CFI values in Erase Block Region 2
94
S29GL-A
S29GL-A_00_A11 September 10, 2007
D a t a S h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2004–2007 Spansion Inc. All rights reserved. Spansion®, the Spansion Logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, HD-
SIM™ and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names used are for informational
purposes only and may be trademarks of their respective owners.
September 10, 2007 S29GL-A_00_A11
S29GL-A
95
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