MB9BF129SA [SPANSION]
This document states the current technical specifications regarding;
| 型号： | MB9BF129SA |
| 厂家： | 
SPANSION |
| 描述： | This document states the current technical specifications regarding |
| 文件： | 总137页 (文件大小：3461K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The following document contains information on Cypress products.
MB9B120TA Series
32-bit ARM® Cortex®-M3 based Microcontroller
MB9BF129SA/TA, MB9BF128SA/TA
Data Sheet (Full Production)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may occur.
Publication Number MB9B120TA_DS706-00063
Revision 2.0
Issue Date January 30, 2015
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers
of product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to
verify that they have the latest information before finalizing their design. The following descriptions of
Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue.
Spansion Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion
Inc. The information is intended to help you evaluate this product. Do not design in this product
without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on
this proposed product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the product life
cycle, including product qualification, initial production, and the subsequent phases in the manufacturing
process that occur before full production is achieved. Changes to the technical specifications presented
in a Preliminary document should be expected while keeping these aspects of production under
consideration. Spansion places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification
has been completed, and that initial production has begun. Due to the phases of the
manufacturing process that require maintaining efficiency and quality, this document may be
revised by subsequent versions or modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their
designations wherever necessary, typically on the first page, the ordering information page, and pages
with the DC Characteristics table and the AC Erase and Program table (in the table notes). The
disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes
may include those affecting the number of ordering part numbers available, such as the addition or
deletion of a speed option, temperature range, package type, or VIO range. Changes may also include
those needed to clarify a description or to correct a typographical error or incorrect specification.
Spansion Inc. applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may
occur.”
Questions regarding these document designations may be directed to your local sales office.
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
MB9B120TA Series
32-bit ARM® Cortex®-M3 based Microcontroller
MB9BF129SA/TA, MB9BF128SA/TA
Data Sheet (Full Production)
Description
The MB9B120TA Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers
with low-power consumption mode and competitive cost.
These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have
peripheral functions such as various timers, ADCs, DACs and Communication Interfaces ( UART, CSIO,
I2C, LIN).
The products which are described in this data sheet are placed into TYPE12 product categories in "FM3
Family PERIPHERAL MANUAL".
Note: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
Publication Number MB9B120TA_DS706-00063
Revision 2.0
Issue Date January 30, 2015
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the
valid combinations offered may occur.
D a t a S h e e t
Features
32-bit ARM Cortex-M3 Core
Processor version: r2p1
Up to 60 MHz Frequency Operation
Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and
48 peripheral interrupts and 16 priority levels
24-bit System timer (Sys Tick): System timer for OS task management
On-chip Memories
[Flash memory]
Dual operation Flash memory
Main area:
Up to 1.5Mbytes(1008Kbytes(ROM0) + 512Kbytes(ROM1) of Upper bank and 16Kbytes(ROM0)
of Lower bank.)
Work area
64 Kbytes(ROM1) of Lower bank
Read cycle: 0 wait-cycle
Security function for code protection
[SRAM]
This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is
connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.
SRAM0: Up to 96 Kbytes
SRAM1: Up to 96 Kbytes
External Bus Interface
Supports SRAM, NOR NAND Flash memory device
Up to 8 chip selects
8/16-bit Data width
Up to 25-bit Address bit
Maximum area size : Up to 256 Mbytes
Supports Address/Data multiplex
Supports external RDY function
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MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Multi-function Serial Interface (Max 16channels)
16 channels with 16steps×9-bit FIFO
Operation mode is selectable from the followings for each channel.
UART
CSIO
LIN
I2C
[UART]
Full duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control: Automatically control the transmission/reception by CTS/RTS (only ch.4)
Various error detection functions available (parity errors, framing errors, and overrun errors)
[CSIO]
Full duplex double buffer
Built-in dedicated baud rate generator
Overrun error detection function available
[LIN]
LIN protocol Rev.2.1 supported
Full duplex double buffer
Master/Slave mode supported
LIN break field generation (can be changed to 13 to 16-bit length)
LIN break delimiter generation (can be changed to 1 to 4-bit length)
Various error detection functions available (parity errors, framing errors, and overrun errors)
[I2C]
Standard - mode (Max 100kbps) / Fast - mode (Max 400kbps) supported
DMA Controller (8channels)
The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process
simultaneously.
8 independently configured and operated channels
Transfer can be started by software or request from the built-in peripherals
Transfer address area: 32-bit (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand transfer
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
A/D Converter (Max 24channels)
[12-bit A/D Converter]
Successive Approximation type
Built-in 2units
Conversion time: 1.0μs @ 2.7V to 5.5V
Priority conversion available (priority at 2levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion: 4steps)
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
3
D a t a S h e e t
D/A Converter (Max 2channels)
R-2R type
10-bit resolution
Base Timer (Max 16channels)
Operation mode is selectable from the followings for each channel.
16-bit PWM timer
16-bit PPG timer
16/32-bit reload timer
16/32-bit PWC timer
General-Purpose I/O Port
This series can use its pins as general-purpose I/O ports when they are not used for external bus or
peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function
can be allocated to.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up to 154 high-speed general-purpose I/O Ports@176pin Package
Some ports are 5V tolerant.
See "List of Pin Functions" and "I/O Circuit Type" to confirm the corresponding pins.
Dual Timer (32/16-bit Down Counter)
The Dual Timer consists of two programmable 32/16-bit down counters.
Operation mode is selectable from the followings for each channel.
Free-running
Periodic (=Reload)
One-shot
Quadrature Position/Revolution Counter (QPRC) (Max 2channels)
The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position
encoder. Moreover, it is possible to use as the up/down counter.
The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
HDMI-CEC/Remote Control Reception (Up to 2channels)
HDMI-CEC transmission
Header block automatic transmission by judging Signal free
Generating status interrupt by detecting Arbitration lost
Generating START, EOM, ACK automatically to output CEC transmission by setting 1 byte data
Generating transmission status interrupt when transmitting 1 block (1 byte data and EOM/ACK)
HDMI-CEC reception
Automatic ACK reply function available
Line error detection function available
Remote control reception
4 bytes reception buffer
Repeat code detection function available
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MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Multi-function Timer
The Multi-function timer is composed of the following blocks.
16-bit free-run timer × 3ch./unit
Input capture × 4ch./unit
Output compare × 6ch./unit
A/D activation compare × 2ch./unit
Waveform generator × 3ch./unit
16-bit PPG timer × 3ch./unit
The following function can be used to achieve the motor control.
PWM signal output function
DC chopper waveform output function
Dead time function
Input capture function
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
Real-time clock (RTC)
The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 01 to 99.
The interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of the
week.) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute.
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
Watch Counter
The Watch counter is used for wake up from sleep and timer mode.
Interval timer: up to 64s (Max) @ Sub Clock : 32.768 kHz
External Interrupt Controller Unit
Up to 32 external interrupt input pins @ 176pin Package
Include one non-maskable interrupt (NMI) input pin
Watchdog Timer (2channels)
A watchdog timer can generate interrupts or a reset when a time-out value is reached.
This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog.
The "Hardware" watchdog timer is clocked by the built-in low-speed CR oscillator. Therefore, the
"Hardware" watchdog is active in any low-power consumption modes except RTC, STOP, Deep standby
RTC, Deep standby STOP modes.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator calculates the CRC which has a heavy software processing load, and achieves a
reduction of the integrity check processing load for reception data and storage.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
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D a t a S h e e t
Clock and Reset
[Clocks]
Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL).
Main Clock
Sub Clock
Built-in high-speed CR Clock
Built-in low-speed CR Clock
Main PLL Clock
: 4 MHz to 48 MHz
: 32.768 kHz
: 4 MHz
: 100 kHz
[Resets]
Reset requests from INITX pin
Power-on reset
Software reset
Watchdog timers reset
Low-voltage detection reset
Clock Super Visor reset
Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks.
If external clock failure (clock stop) is detected, reset is asserted.
If external frequency anomaly is detected, interrupt or reset is asserted.
Low-Voltage Detector (LVD)
This Series includes 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the
voltage that has been set, Low-Voltage Detector generates an interrupt or reset.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Low-Power Consumption Mode
Six low-power consumption modes supported.
SLEEP
TIMER
RTC
STOP
Deep standby RTC (selectable between keeping the value of RAM and not)
Deep standby STOP (selectable between keeping the value of RAM and not)
Debug
・Serial Wire JTAG Debug Port (SWJ-DP)
・Embedded Trace Macrocell (ETM)
Unique ID
Unique value of the device (41-bit) is set.
Power Supply
Wide range voltage : VCC
= 2.7V to 5.5V
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MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Product Lineup
Memory size
Product name
MB9BF128SA/TA
MB9BF129SA/TA
On-chip
Flash
memory
Main area
1 Mbytes
1.5 Mbytes
Work area
64 Kbytes
64 Kbytes
SRAM0
SRAM1
Total
80 Kbytes
80 Kbytes
160 Kbytes
96 Kbytes
96 Kbytes
192 Kbytes
On-chip
SRAM
Function
MB9BF128SA
MB9BF129SA
144
MB9BF128TA
MB9BF129TA
176/192
Product name
Pin count
CPU
Cortex-M3
60 MHz
Freq.
Power supply voltage range
DMAC
2.7V to 5.5V
8ch.
Addr: 25 bit (Max)
R/Wdata : 8/16 bit (Max)
External Bus Interface
CS: 8 (Max)
SRAM , NOR Flash memory , NAND Flash memory
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
Base Timer
(PWC/Reload timer/PWM/PPG)
A/D activation
16ch. (Max) with 16steps×9-bit FIFO
16ch. (Max)
2ch.
compare
Input capture
Free-run timer
Output compare
4ch.
3ch.
6ch.
MF-
Timer
1 unit
Waveform generator 3ch.
PPG 3ch.
QPRC
1ch.(Max)
2ch. (Max)
Dual Timer
1 unit
HDMI-CEC/ Remote Control
Reception
2ch. (Max)
Real-Time Clock
Watch Counter
1 unit
1 unit
CRC Accelerator
Watchdog timer
External Interrupts
I/O ports
Yes
1ch. (SW) + 1ch. (HW)
32pins (Max) + NMI × 1
122pins (Max)
154pins (Max)
12-bit A/D converter
10-bit D/A converter
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
24ch. (2 units)
2ch. (Max)
Yes
2ch.
High-speed
Low-speed
4 MHz (± 2%)
100 kHz (Typ)
SWJ-DP / ETM
Yes
Built-in CR
Debug Function
Unique ID
Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the I/O port according to your function use.
See "Electrical Characteristics 4.AC Characteristics (3)Built-in CR Oscillation Characteristics" for
accuracy of built-in CR.
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
7
D a t a S h e e t
Packages
Product name
MB9BF128SA
MB9BF129SA
MB9BF128TA
MB9BF129TA
Package
LQFP: FPT-144P-M08 (0.5mm pitch)
LQFP: FPT-176P-M07 (0.5mm pitch)
BGA: BGA-192P-M06 (0.8mm pitch)
-
-
-
: Supported
Note: See "Package Dimensions" for detailed information on each package.
8
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Pin Assignment
FPT-176P-M07
(TOP VIEW)
VCC
PA0/SIN8_0/TIOA08_0/MAD21_0
PA1/SOT8_0/TIOA09_0/MAD22_0
PA2/SCK8_0/TIOA10_0/MAD23_0
PA3/SIN9_0/TIOA11_0/MAD24_0
PA4/SOT9_0/TIOA12_0/INT03_0
PA5/SCK9_0/TIOA13_0/INT10_2
P05/TRACED0/SIN4_2/TIOA05_2/INT00_1
P06/TRACED1/SOT4_2/TIOB05_2/INT01_1
1
2
3
4
5
6
7
8
9
132 VSS
131 VCC
130 P83/MCSX6_0
129 P82/MCSX7_0
128 PF6/NMIX/WKUP0
127 P20/AIN1_1/INT05_0/CROUT_0
126 P21/SIN0_0/BIN1_1/INT06_1
125 P22/AN23/SOT0_0/ZIN1_1/TIOB07_1
124 P23/AN22/SCK0_0/RTO00_1/TIOA07_1
123 P24/AN21/SIN2_1/RTO01_1/INT01_2
122 P25/AN20/SOT2_1/RTO02_1
121 P26/AN19/SCK2_1/RTO03_1
120 P27/AN18/SCK12_0/RTO04_1/INT02_2
119 P28/AN17/ADTG_4/SOT12_0/RTO05_1/INT09_0
118 P29/AN16/SIN12_0
P07/TRACED2/ADTG_0/SCK4_2
P08/TRACED3/CTS4_2/TIOA00_2
P09/TRACECLK/RTS4_2/TIOB00_2
P50/SIN3_1/AIN0_2/INT00_0/MOEX_0
P51/SOT3_1/BIN0_2/INT01_0/MWEX_0
P52/SCK3_1/ZIN0_2/INT02_0/MDQM0_0
P53/SIN6_0/TIOA01_2/INT07_2/MDQM1_0
P54/SOT6_0/TIOB01_2/MALE_0
P55/ADTG_1/SCK6_0/MRDY_0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
117 AVRH
116 AVRL
115 AVSS
P56/SIN1_0/TIOA09_2/INT08_2/CEC1_1/MNALE_0
P57/SOT1_0/TIOB09_2/INT16_1/MNCLE_0
P58/SCK1_0/TIOA11_2/INT17_1/MNWEX_0
P59/SIN7_0/TIOB11_2/INT09_2/MNREX_0
P5A/SOT7_0/TIOA13_1/INT18_1/MCSX0_0
P5B/SCK7_0/TIOB13_1/INT19_1/MCSX1_0
P5C/TIOA06_2/INT28_0
114 AVCC
113 PB7/TIOB12_1/INT23_0
112 PB6/SCK0_2/TIOA12_1/INT22_0
111 PB5/SOT0_2/TIOB11_1/INT21_0
110 PB4/SIN0_2/TIOA11_1/INT20_0
109 PB3/TIOB10_1/INT19_0
LQFP - 176
108 PB2/SCK7_2/TIOA10_1/INT18_0
107 PB1/SOT7_2/TIOB09_1/INT17_0
106 PB0/SIN7_2/TIOA09_1/INT16_0
105 P1F/AN15/ADTG_5/FRCK0_1/TIOB15_2/INT29_1
104 P1E/AN14/RTS4_1/DTTI0X_1/TIOA15_2/INT28_1
103 P1D/AN13/CTS4_1/IC03_1/TIOB14_2/INT27_1
102 P1C/AN12/SCK4_1/IC02_1/TIOA14_2/INT26_1
101 P1B/AN11/SOT4_1/IC01_1/TIOB13_2/INT25_1
100 P1A/AN10/SIN4_1/IC00_1/TIOA13_2/INT05_1
P5D/TIOB06_2/INT29_0
VSS
P30/AIN0_0/TIOB00_1/INT03_2/WKUP4
P31/SCK6_1/BIN0_0/TIOB01_1/INT04_2
P32/SOT6_1/ZIN0_0/TIOB02_1/INT05_2
P33/ADTG_6/SIN6_1/TIOB03_1/INT04_0
P34/FRCK0_0/TIOB04_1
P35/IC03_0/TIOB05_1/INT08_1
P36/SIN5_2/IC02_0/TIOA12_2/INT09_1
P37/SOT5_2/IC01_0/TIOB12_2/INT10_1
P38/SCK5_2/IC00_0/INT11_1
99
98
97
96
95
94
93
92
91
90
89
P19/AN09/SCK2_2/INT22_1
P18/AN08/SOT2_2/INT21_1
P17/AN07/SIN2_2/INT04_1
P16/AN06/SCK0_1/INT20_1
P15/AN05/SOT0_1/IC03_2
P14/AN04/SIN0_1/IC02_2/INT03_1
P13/AN03/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1
P12/AN02/SOT1_1/IC00_2
P11/AN01/SIN1_1/FRCK0_2/INT02_1/WKUP1
P10/AN00
P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2
P3A/RTO00_0/TIOA00_1
P3B/RTO01_0/TIOA01_1
P3C/RTO02_0/TIOA02_1
P3D/RTO03_0/TIOA03_1
P3E/RTO04_0/TIOA04_1
P3F/RTO05_0/TIOA05_1
VSS
VCC
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
9
D a t a S h e e t
FPT-144P-M08
(TOP VIEW)
VCC
1
108 VSS
PA0/SIN8_0/TIOA08_0/MAD21_0
PA1/SOT8_0/TIOA09_0/MAD22_0
PA2/SCK8_0/TIOA10_0/MAD23_0
PA3/SIN9_0/TIOA11_0/MAD24_0
PA4/SOT9_0/TIOA12_0/INT03_0
PA5/SCK9_0/TIOA13_0/INT10_2
P05/TRACED0/SIN4_2/TIOA05_2/INT00_1
P06/TRACED1/SOT4_2/TIOB05_2/INT01_1
P07/TRACED2/ADTG_0/SCK4_2
2
107 VCC
3
106 P83/MCSX6_0
4
105 P82/MCSX7_0
5
104 PF6/NMIX/WKUP0
6
103 P20/AIN1_1/INT05_0/CROUT_0
102 P21/SIN0_0/BIN1_1/INT06_1
101 P22/AN23/SOT0_0/ZIN1_1/TIOB07_1
100 P23/AN22/SCK0_0/RTO00_1/TIOA07_1
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
P24/AN21/SIN2_1/RTO01_1/INT01_2
P25/AN20/SOT2_1/RTO02_1
P26/AN19/SCK2_1/RTO03_1
P27/AN18/SCK12_0/RTO04_1/INT02_2
P28/AN17/ADTG_4/SOT12_0/RTO05_1/INT09_0
P29/AN16/SIN12_0
P08/TRACED3/CTS4_2/TIOA00_2
P09/TRACECLK/RTS4_2/TIOB00_2
P50/SIN3_1/AIN0_2/INT00_0/MOEX_0
P51/SOT3_1/BIN0_2/INT01_0/MWEX_0
P52/SCK3_1/ZIN0_2/INT02_0/MDQM0_0
P53/SIN6_0/TIOA01_2/INT07_2/MDQM1_0
P54/SOT6_0/TIOB01_2/MALE_0
P55/ADTG_1/SCK6_0/MRDY_0
AVRH
AVRL
AVSS
LQFP - 144
P56/SIN1_0/TIOA09_2/INT08_2/CEC1_1/MNALE_0
P57/SOT1_0/TIOB09_2/INT16_1/MNCLE_0
P58/SCK1_0/TIOA11_2/INT17_1/MNWEX_0
P59/SIN7_0/TIOB11_2/INT09_2/MNREX_0
P5A/SOT7_0/TIOA13_1/INT18_1/MCSX0_0
P5B/SCK7_0/TIOB13_1/INT19_1/MCSX1_0
VSS
AVCC
P1F/AN15/ADTG_5/FRCK0_1/TIOB15_2/INT29_1
P1E/AN14/RTS4_1/DTTI0X_1/TIOA15_2/INT28_1
P1D/AN13/CTS4_1/IC03_1/TIOB14_2/INT27_1
P1C/AN12/SCK4_1/IC02_1/TIOA14_2/INT26_1
P1B/AN11/SOT4_1/IC01_1/TIOB13_2/INT25_1
P1A/AN10/SIN4_1/IC00_1/TIOA13_2/INT05_1
P19/AN09/SCK2_2/INT22_1
P18/AN08/SOT2_2/INT21_1
P17/AN07/SIN2_2/INT04_1
P16/AN06/SCK0_1/INT20_1
P15/AN05/SOT0_1/IC03_2
P36/SIN5_2/IC02_0/TIOA12_2/INT09_1
P37/SOT5_2/IC01_0/TIOB12_2/INT10_1
P38/SCK5_2/IC00_0/INT11_1
P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2
P3A/RTO00_0/TIOA00_1
P3B/RTO01_0/TIOA01_1
P14/AN04/SIN0_1/IC02_2/INT03_1
P13/AN03/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1
P12/AN02/SOT1_1/IC00_2
P3C/RTO02_0/TIOA02_1
P3D/RTO03_0/TIOA03_1
P3E/RTO04_0/TIOA04_1
P11/AN01/SIN1_1/FRCK0_2/INT02_1/WKUP1
P10/AN00
P3F/RTO05_0/TIOA05_1
VSS
VCC
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
10
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
BGA-192P-M06
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P81
P80
PF5
PA2
P05
P08
P53
P58
P30
P36
P3A
P3E
P42
P41
VSS
VCC
PF3
PF4
P06
P09
P54
P59
P31
P35
P3B
P43
P44
P45
VCC
VSS
P61
P60
PA3
P50
P55
P5A
P32
P34
P4A
P49
P48
INITX
X0A
PCD
PD1
PD2
PD3
P62
P56
P5B
P33
P70
P4E
P4D
P4C
P4B
X1A
PCB
PCA
PCC
PCE
PCF
PD0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PC1
PC5
PC6
PC7
PC9
VSS
VSS
P76
P74
P73
P72
P71
P75
VCC
P95
PC0
PC2
PC3
PC4
PB7
P1F
P1D
P7B
P7A
P79
P78
P77
PC8
P92
P93
P94
P25
P29
PB6
P1E
P1C
P7F
P7E
PF0
P7D
P7C
VSS
TDO
P90
P91
P24
P28
PB5
PB2
P1B
P18
P14
PF2
PF1
VSS
TCK
VCC
A
VSS
VCC
PA5
VSS
P51
PA0
PA1
PA4
P07
P52
P57
P5D
P37
P39
P3D
P3F
P40
C
TMS TRSTX VSS
B
C
D
E
F
TDI
P21
P23
P27
PB4
PB1
P1A
P16
P13
P11
MD0
X0
PF6
P20
P22
P26
PB3
PB0
P19
P15
P12
P10
MD1
X1
VCC
P83
P82
AVRH
AVRL
AVSS
AVCC
P17
VSS
P5C
VSS
P38
G
H
J
K
L
P3C
VSS
VCC
VSS
VCC
VSS
M
N
P
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
11
D a t a S h e e t
List of Pin Functions
List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No
LQFP-144
1
I/O circuit
type
Pin state
type
Pin Name
LQFP-176
BGA-192
1
C1
VCC
PA0
-
SIN8_0
TIOA08_0
MAD21_0
PA1
SOT8_0
TIOA09_0
MAD22_0
PA2
SCK8_0
TIOA10_0
MAD23_0
PA3
SIN9_0
TIOA11_0
MAD24_0
PA4
SOT9_0
TIOA12_0
INT03_0
PA5
SCK9_0
TIOA13_0
INT10_2
P05
2
3
4
5
6
7
2
3
4
5
6
7
B2
C2
C3
D5
D2
D1
I*
I*
I*
I*
I*
I*
J
J
J
J
K
K
TRACED0
SIN4_2
TIOA05_2
8
9
8
9
D3
D4
E
E
Q
Q
INT00_1
P06
TRACED1
SOT4_2
TIOB05_2
INT01_1
12
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Pin No
LQFP-144
I/O circuit
type
Pin state
type
Pin Name
LQFP-176
BGA-192
P07
TRACED2
ADTG_0
SCK4_2
P08
TRACED3
CTS4_2
TIOA00_2
P09
TRACECLK
RTS4_2
TIOB00_2
P50
10
10
11
12
E2
E
E
E
P
P
P
11
12
E3
E4
SIN3_1
AIN0_2
INT00_0
MOEX_0
P51
SOT3_1
BIN0_2
INT01_0
MWEX_0
P52
13
14
15
13
14
15
E5
F1
F2
E
E
E
K
K
K
SCK3_1
ZIN0_2
INT02_0
MDQM0_0
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
13
D a t a S h e e t
Pin Name
Pin No
LQFP-144
I/O circuit
type
Pin state
type
LQFP-176
BGA-192
P53
SIN6_0
16
16
F3
TIOA01_2
INT07_2
MDQM1_0
P54
E
K
SOT6_0
TIOB01_2
MALE_0
P55
ADTG_1
SCK6_0
MRDY_0
P56
17
18
17
18
F4
F5
E
E
J
J
SIN1_0
TIOA09_2
INT08_2
CEC1_1
MNALE_0
P57
19
19
F6
I*
S
SOT1_0
TIOB09_2
INT16_1
MNCLE_0
P58
SCK1_0
TIOA11_2
INT17_1
MNWEX_0
P59
20
21
22
20
21
22
G2
G3
G4
I*
I*
E
K
K
K
SIN7_0
TIOB11_2
INT09_2
MNREX_0
14
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Pin No
LQFP-144
I/O circuit
type
Pin state
type
Pin name
LQFP-176
BGA-192
P5A
SOT7_0
TIOA13_1
INT18_1
MCSX0_0
P5B
SCK7_0
TIOB13_1
INT19_1
MCSX1_0
P5C
TIOA06_2
INT28_0
P5D
TIOB06_2
INT29_0
VSS
23
23
G5
E
E
K
K
24
25
24
-
G6
H1
E
E
K
K
26
27
-
H2
A5
25
-
P30
AIN0_0
TIOB00_1
INT03_2
WKUP4
P31
SCK6_1
BIN0_0
TIOB01_1
INT04_2
P32
SOT6_1
ZIN0_0
TIOB02_1
INT05_2
P33
ADTG_6
SIN6_1
TIOB03_1
INT04_0
28
29
30
31
-
-
-
-
H3
H4
H5
H6
E
E
E
E
U
K
K
K
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
15
D a t a S h e e t
Pin name
Pin No
LQFP-144
I/O circuit
type
Pin state
type
LQFP-176
BGA-192
P34
FRCK0_0
TIOB04_1
P35
32
-
-
J5
E
J
IC03_0
33
34
J4
J3
E
K
TIOB05_1
INT08_1
P36
SIN5_2
IC02_0
26
E
K
TIOA12_2
INT09_1
P37
SOT5_2
IC01_0
TIOB12_2
INT10_1
P38
SCK5_2
IC00_0
INT11_1
P39
ADTG_2
DTTI0X_0
RTCCO_2
SUBOUT_2
P3A
35
36
37
27
28
29
J2
K1
K2
E
E
E
K
K
J
38
39
40
30
31
32
K3
K4
L1
RTO00_0
TIOA00_1
P3B
RTO01_0
TIOA01_1
P3C
F
F
F
J
J
J
RTO02_0
TIOA02_1
16
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Pin No
LQFP-144
I/O circuit
type
Pin state
type
Pin name
LQFP-176
BGA-192
P3D
RTO03_0
TIOA03_1
P3E
RTO04_0
TIOA04_1
P3F
RTO05_0
TIOA05_1
VSS
41
33
34
35
L2
F
F
F
J
J
J
42
43
L3
M2
44
45
36
37
A8
N1
-
-
VCC
P40
SIN10_0
TIOA00_0
INT12_1
MCSX2_0
P41
SOT10_0
TIOA01_0
INT13_1
MCSX3_0
P42
46
47
38
39
N2
N3
E
E
K
K
SCK10_0
TIOA02_0
MCLKOUT_0
P43
ADTG_7
SIN11_0
TIOA03_0
P44
48
49
40
41
M3
L4
E
J
J
I*
50
51
42
43
M4
N4
SOT11_0
TIOA04_0
P45
SCK11_0
TIOA05_0
C
I*
I*
J
J
52
53
54
44
45
46
P2
A11
P4
-
-
-
VSS
VCC
P46
X0A
55
47
P5
D
F
P47
X1A
INITX
56
57
48
49
P6
D
B
G
C
N5
P48
58
50
M5
SIN3_2
INT14_1
E
K
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
17
D a t a S h e e t
Pin name
Pin No
LQFP-144
I/O circuit
type
Pin state
type
LQFP-176
BGA-192
P49
SOT3_2
AIN0_1
TIOB00_0
P4A
SCK3_2
59
51
52
L5
E
J
60
61
62
63
K5
N6
M6
L6
BIN0_1
E
J
TIOB01_0
MADATA00_0
P4B
IGTRG0_0
ZIN0_1
TIOB02_0
MADATA01_0
P4C
SCK7_1
AIN1_2
TIOB03_0
MADATA02_0
P4D
53
54
55
E
E
E
J
J
J
SOT7_1
BIN1_2
TIOB04_0
MADATA03_0
P4E
SIN7_1
ZIN1_2
64
56
K6
E
K
TIOB05_0
INT06_2
MADATA04_0
P70
65
66
57
58
J6
TIOA04_2
MADATA05_0
P71
TIOB04_2
INT13_2
MADATA06_0
E
E
J
N8
K
18
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Pin No
LQFP-144
I/O circuit
type
Pin state
type
Pin name
LQFP-176
BGA-192
P72
SIN2_0
67
59
M8
INT14_2
WKUP2
MADATA07_0
P73
E
U
SOT2_0
INT15_2
MADATA08_0
P74
SCK2_0
MADATA09_0
P75
68
69
60
61
L8
E
E
K
J
K8
ADTG_8
SIN3_0
INT07_1
MADATA10_0
P76
SOT3_0
TIOA07_2
INT11_2
MADATA11_0
P77
70
71
62
63
P8
J8
E
E
K
K
SCK3_0
TIOB07_2
INT12_2
MADATA12_0
P78
72
73
74
64
65
66
P9
N9
M9
E
E
E
K
J
AIN1_0
TIOA15_0
MADATA13_0
P79
BIN1_0
TIOB15_0
INT23_1
MADATA14_0
VSS
K
-
-
-
-
M1
P3
-
-
VSS
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
19
D a t a S h e e t
Pin name
Pin No
LQFP-144
I/O circuit
type
Pin state
type
LQFP-176
BGA-192
P7A
ZIN1_0
INT24_1
MADATA15_0
P7B
75
67
L9
E
K
76
77
78
79
80
-
-
-
-
-
K9
P10
N10
L10
K10
TIOB07_0
INT10_0
P7C
TIOA07_0
INT11_0
P7D
TIOA14_1
INT12_0
P7E
TIOB14_1
INT24_0
P7F
E
E
E
E
E
K
K
K
K
K
TIOA15_1
INT25_0
PF0
SIN1_2
TIOB15_1
INT13_0
CEC0_0
PF1
81
-
M10
I*
S
SOT1_2
TIOA08_1
INT14_0
PF2
SCK1_2
TIOB08_1
INT15_0
PE0
82
83
-
-
N11
M11
I*
I*
K
K
84
85
86
68
69
70
N13
N12
P12
C
J
E
D
A
MD1
MD0
PE2
X0
A
PE3
X1
87
71
P13
A
B
88
89
-
72
73
-
E1
M14
P7
VSS
VCC
VSS
VSS
-
-
-
-
-
-
N7
20
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Pin No
LQFP-144
I/O circuit
type
Pin state
type
Pin name
LQFP-176
BGA-192
P10
AN00
90
74
M13
G
L
P11
AN01
SIN1_1
FRCK0_2
INT02_1
WKUP1
P12
91
92
93
75
M12
L13
L12
G
N
AN02
76
77
G
G
L
L
SOT1_1
IC00_2
P13
AN03
SCK1_1
IC01_2
RTCCO_1
SUBOUT_1
P14
AN04
94
78
L11
SIN0_1
IC02_2
INT03_1
P15
G
M
AN05
95
96
97
79
80
81
K13
K12
K14
G
G
G
L
SOT0_1
IC03_2
P16
AN06
M
M
SCK0_1
INT20_1
P17
AN07
SIN2_2
INT04_1
VSS
VSS
VSS
-
-
-
-
-
-
M7
L7
K7
-
-
-
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
21
D a t a S h e e t
Pin name
Pin No
LQFP-144
I/O circuit
type
Pin state
type
LQFP-176
BGA-192
P18
AN08
SOT2_2
INT21_1
P19
98
82
83
K11
G
G
M
M
AN09
99
J13
J12
SCK2_2
INT22_1
P1A
AN10
SIN4_1
IC00_1
TIOA13_2
INT05_1
P1B
100
84
85
86
87
G
G
G
G
M
M
M
M
AN11
SOT4_1
IC01_1
TIOB13_2
INT25_1
P1C
101
102
103
J11
J10
J9
AN12
SCK4_1
IC02_1
TIOA14_2
INT26_1
P1D
AN13
CTS4_1
IC03_1
TIOB14_2
INT27_1
P1E
AN14
RTS4_1
DTTI0X_1
TIOA15_2
INT28_1
104
88
H10
G
M
22
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Pin No
LQFP-144
I/O circuit
type
Pin state
type
Pin name
LQFP-176
BGA-192
P1F
AN15
ADTG_5
FRCK0_1
TIOB15_2
INT29_1
PB0
105
89
H9
G
M
SIN7_2
TIOA09_1
INT16_0
PB1
SOT7_2
TIOB09_1
INT17_0
PB2
106
107
-
-
H13
H12
E
E
K
K
SCK7_2
TIOA10_1
INT18_0
PB3
TIOB10_1
INT19_0
PB4
SIN0_2
TIOA11_1
INT20_0
PB5
108
109
110
-
-
-
H11
G13
G12
E
E
E
K
K
K
SOT0_2
TIOB11_1
INT21_0
PB6
111
-
G11
E
K
SCK0_2
TIOA12_1
INT22_0
PB7
TIOB12_1
INT23_0
AVCC
AVSS
VSS
VSS
112
113
-
-
G10
G9
E
E
K
K
114
115
-
90
91
-
J14
H14
J7
-
-
-
-
-
-
P11
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
23
D a t a S h e e t
Pin name
Pin No
LQFP-144
92
I/O circuit
type
Pin state
type
LQFP-176
116
BGA-192
G14
AVRL
AVRH
P29
-
-
117
93
F14
118
94
F10
AN16
SIN12_0
P28
G
G
L
AN17
ADTG_4
SOT12_0
RTO05_1
INT09_0
P27
119
95
F11
M
AN18
120
96
F12
SCK12_0
RTO04_1
INT02_2
P26
G
M
AN19
121
122
97
98
F13
E10
G
G
L
L
SCK2_1
RTO03_1
P25
AN20
SOT2_1
RTO02_1
P24
AN21
123
99
E11
SIN2_1
RTO01_1
INT01_2
G
M
24
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Pin No
LQFP-144
I/O circuit
type
Pin state
type
Pin name
LQFP-176
BGA-192
P23
AN22
124
100
E12
SCK0_0
RTO00_1
TIOA07_1
P22
G
L
AN23
125
126
101
102
E13
D12
SOT0_0
ZIN1_1
TIOB07_1
P21
SIN0_0
BIN1_1
INT06_1
P20
G
E
L
K
AIN1_1
INT05_0
CROUT_0
PF6
NMIX
WKUP0
P82
MCSX7_0
P83
MCSX6_0
VCC
127
128
103
104
D13
C13
E
K
H
I*
129
130
105
106
E14
D14
E
E
J
J
131
132
133
107
108
109
C14
G7
A13
-
-
-
VSS
VCC
P00
TRSTX
P01
TCK
SWCLK
P02
TDI
P03
TMS
134
135
136
137
110
111
112
113
B13
A12
C12
B12
E
E
E
E
I
I
I
I
SWDIO
P04
138
114
B11
TDO
SWO
P90
E
E
I
139
-
-
-
C11
N14
TIOB08_0
INT30_0
VSS
K
-
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
25
D a t a S h e e t
Pin name
Pin No
LQFP-144
I/O circuit
type
Pin state
type
LQFP-176
BGA-192
P91
140
-
-
-
D11
TIOB09_0
INT31_0
P92
SIN5_1
TIOB10_0
P93
SOT5_1
TIOB11_0
P94
E
E
E
K
J
141
142
B10
C10
J
SCK5_1
TIOB12_0
INT26_0
P95
TIOB13_0
INT27_0
PC0
143
144
145
-
-
D10
B9
E
E
H
K
K
O
DA0_0
115
C9
SIN13_0
MCSX5_0
PC1
DA1_0
146
116
B8
H
O
SOT13_0
MCSX4_0
PC2
147
148
117
118
D9
E9
SCK13_0
MAD00_0
PC3
TIOA06_1
MAD01_0
PC4
E
E
J
J
SIN14_0
TIOA08_2
CEC0_1
MAD02_0
PC5
SOT14_0
TIOA10_2
MAD03_0
VSS
149
119
F9
I*
I*
R
J
150
-
120
-
C8
L14
-
26
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Pin No
LQFP-144
I/O circuit
type
Pin state
type
Pin name
LQFP-176
BGA-192
PC6
SCK14_0
TIOA14_0
MAD04_0
PC7
CROUT_1
RTCCO_0
SUBOUT_0
MAD05_0
PC8
151
121
122
D8
I*
J
152
E8
E
J
153
154
155
123
124
125
A10
F8
SIN15_0
MAD06_0
PC9
SOT15_0
MAD07_0
PCA
SCK15_0
MAD08_0
VCC
E
E
E
J
J
J
B7
156
157
126
127
A9
G8
-
-
VSS
PCB
MAD09_0
PCC
MAD10_0
PCD
MAD11_0
PCE
158
159
160
128
129
130
A7
C7
A6
E
E
E
J
J
J
RTS4_0
TIOB06_1
MAD12_0
PCF
CTS4_0
TIOB08_2
MAD13_0
PD0
161
162
131
132
D7
E7
E
E
J
J
SCK4_0
TIOB10_2
INT30_1
MAD14_0
PD1
SOT4_0
TIOB14_0
INT31_1
MAD15_0
VSS
163
164
133
134
F7
E
E
K
K
B6
-
-
-
-
-
-
-
-
B14
H7
B1
-
-
-
-
VSS
VSS
VSS
G1
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
27
D a t a S h e e t
Pin name
Pin No
LQFP-144
I/O circuit
type
Pin state
type
LQFP-176
BGA-192
PD2
SIN4_0
TIOA03_2
INT00_2
MAD16_0
PD3
165
135
C6
E
K
166
167
136
137
D6
E6
TIOB03_2
MAD17_0
P62
ADTG_3
SCK5_0
MAD18_0
P61
E
E
J
J
SOT5_0
TIOB02_2
MAD19_0
P60
SIN5_0
TIOA02_2
INT15_1
WKUP5
MAD20_0
PF3
168
169
138
139
B5
C5
E
E
J
U
SIN6_2
TIOA06_0
INT06_0
PF4
SOT6_2
TIOB06_0
INT07_0
PF5
170
171
-
-
B4
C4
I*
I*
K
K
IGTRG0_1
INT08_0
WKUP3
CEC1_0
SCK6_2
VCC
140
172
B3
I*
T
-
173
174
175
176
141
142
143
144
-
A4
A3
A2
H8
J1
-
P80
P81
VSS
VSS
K
K
V
V
-
-
-
*: 5V tolerant I/O
28
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
List of pin functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port
number. For these pins, there are multiple pins that provide the same function for the same channel. Use the
extended port function register (EPFR) to select the pin.
Pin No
LQFP-144BGA-192
Pin
function
ADC
Pin name
Function description
LQFP-176
10
ADTG_0
ADTG_1
ADTG_2
ADTG_3
ADTG_4
ADTG_5
ADTG_6
ADTG_7
ADTG_8
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
10
18
29
137
95
89
-
E2
F5
K2
E6
F11
H9
H6
L4
P8
M13
M12
L13
L12
L11
K13
K12
K14
K11
J13
J12
J11
J10
J9
18
37
167
119
105
31
49
70
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
118
119
120
121
122
123
124
125
A/D converter external trigger input
pin
41
62
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
94
95
96
97
98
99
100
101
A/D converter analog input pin.
ANxx describes ADC ch.xx.
H10
H9
F10
F11
F12
F13
E10
E11
E12
E13
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
29
D a t a S h e e t
Pin No
LQFP-144BGA-192
Pin
function
Base Timer
0
Pin name
Function description
LQFP-176
46
TIOA00_0
TIOA00_1
TIOA00_2
TIOB00_0
TIOB00_1
TIOB00_2
TIOA01_0
TIOA01_1
TIOA01_2
TIOB01_0
TIOB01_1
TIOB01_2
TIOA02_0
TIOA02_1
TIOA02_2
TIOB02_0
TIOB02_1
TIOB02_2
TIOA03_0
TIOA03_1
TIOA03_2
TIOB03_0
TIOB03_1
TIOB03_2
TIOA04_0
TIOA04_1
TIOA04_2
TIOB04_0
TIOB04_1
TIOB04_2
TIOA05_0
TIOA05_1
TIOA05_2
TIOB05_0
TIOB05_1
TIOB05_2
TIOA06_0
TIOA06_1
TIOA06_2
TIOB06_0
38
30
11
51
-
12
39
31
16
52
-
17
40
32
139
53
-
138
41
33
135
54
-
136
42
34
57
55
-
58
43
35
8
N2
K3
E3
L5
H3
E4
N3
K4
F3
Base timer ch.0 TIOA pin
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
Base timer ch.3 TIOA pin
Base timer ch.3 TIOB pin
Base timer ch.4 TIOA pin
Base timer ch.4 TIOB pin
Base timer ch.5 TIOA pin
Base timer ch.5 TIOB pin
Base timer ch.6 TIOA pin
38
11
59
28
12
47
39
16
60
29
17
48
40
169
61
30
168
49
41
165
62
31
166
50
42
65
63
32
66
51
43
8
64
33
9
Base Timer
1
K5
H4
F4
Base Timer
2
M3
L1
C5
N6
H5
B5
L4
L2
C6
M6
H6
D6
M4
L3
J6
Base Timer
3
Base Timer
4
L6
J5
N8
N4
M2
D3
K6
J4
D4
B4
E9
H1
C4
Base Timer
5
56
-
9
Base Timer
6
170
148
25
-
118
-
-
171
TIOB06_1
TIOB06_2
Base timer ch.6 TIOB pin
161
26
131
-
D7
H2
30
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Pin No
LQFP-144BGA-192
Pin
function
Base Timer
7
Pin name
Function description
LQFP-176
77
TIOA07_0
TIOA07_1
TIOA07_2
TIOB07_0
TIOB07_1
TIOB07_2
TIOA08_0
TIOA08_1
TIOA08_2
TIOB08_0
TIOB08_1
TIOB08_2
TIOA09_0
TIOA09_1
TIOA09_2
TIOB09_0
TIOB09_1
TIOB09_2
TIOA10_0
TIOA10_1
TIOA10_2
TIOB10_0
TIOB10_1
TIOB10_2
TIOA11_0
TIOA11_1
TIOA11_2
TIOB11_0
TIOB11_1
TIOB11_2
TIOA12_0
TIOA12_1
TIOA12_2
TIOB12_0
TIOB12_1
TIOB12_2
TIOA13_0
TIOA13_1
TIOA13_2
TIOB13_0
TIOB13_1
TIOB13_2
-
100
63
-
101
64
2
P10
E12
J8
K9
E13
P9
B2
N11
F9
C11
M11
E7
C2
H13
F6
D11
H12
G2
C3
H11
C8
B10
G13
F7
D5
G12
G3
C10
G11
G4
D2
G10
J3
D10
G9
J2
D1
G5
J12
B9
G6
Base timer ch.7 TIOA pin
Base timer ch.7 TIOB pin
Base timer ch.8 TIOA pin
Base timer ch.8 TIOB pin
Base timer ch.9 TIOA pin
Base timer ch.9 TIOB pin
Base timer ch.10 TIOA pin
Base timer ch.10 TIOB pin
Base timer ch.11 TIOA pin
Base timer ch.11 TIOB pin
Base timer ch.12 TIOA pin
Base timer ch.12 TIOB pin
Base timer ch.13 TIOA pin
Base timer ch.13 TIOB pin
124
71
76
125
72
2
Base Timer
8
82
-
149
139
83
162
3
106
19
140
107
20
119
-
-
132
3
-
19
-
-
20
4
-
120
-
-
133
5
-
21
-
-
22
6
-
Base Timer
9
Base Timer
10
4
108
150
141
109
163
5
110
21
142
111
22
6
112
34
143
113
35
Base Timer
11
Base Timer
12
26
-
-
27
7
23
84
-
Base Timer
13
7
23
100
144
24
24
85
101
J11
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
31
D a t a S h e e t
Pin No
LQFP-144BGA-192
Pin
function
Base Timer
14
Pin name
Function description
LQFP-176
151
78
TIOA14_0
TIOA14_1
TIOA14_2
TIOB14_0
TIOB14_1
TIOB14_2
TIOA15_0
TIOA15_1
TIOA15_2
TIOB15_0
TIOB15_1
TIOB15_2
SWCLK
121
-
86
134
-
87
65
-
88
66
-
D8
N10
J10
B6
L10
J9
Base timer ch.14 TIOA pin
102
164
79
103
73
80
104
74
Base timer ch.14 TIOB pin
Base timer ch.15 TIOA pin
Base timer ch.15 TIOB pin
Base Timer
15
N9
K10
H10
M9
M10
H9
81
105
135
89
111
Debugger
Serial wire debug interface clock input
Serial wire debug interface data input /
output
A12
SWDIO
137
113
B12
SWO
TCK
TDI
TDO
TMS
Serial wire viewer output
J-TAG test clock input
J-TAG test data input
J-TAG debug data output
J-TAG test mode state input/output
Trace CLK output of ETM
138
135
136
138
137
12
8
9
10
11
114
111
112
114
113
12
8
9
10
11
B11
A12
C12
B11
B12
E4
D3
D4
E2
E3
TRACECLK
TRACED0
TRACED1
TRACED2
TRACED3
TRSTX
Trace data output of ETM
J-TAG test reset Input
134
110
B13
32
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Pin No
Pin
function
External
Bus
Pin name
Function description
LQFP-176 LQFP-144 BGA-192
MAD00_0
MAD01_0
MAD02_0
MAD03_0
MAD04_0
MAD05_0
MAD06_0
MAD07_0
MAD08_0
MAD09_0
MAD10_0
MAD11_0
MAD12_0
MAD13_0
MAD14_0
MAD15_0
MAD16_0
MAD17_0
MAD18_0
MAD19_0
MAD20_0
MAD21_0
MAD22_0
MAD23_0
MAD24_0
MCSX0_0
MCSX1_0
MCSX2_0
MCSX3_0
MCSX4_0
MCSX5_0
MCSX6_0
MCSX7_0
MDQM0_0
MDQM1_0
147
148
149
150
151
152
153
154
155
158
159
160
161
162
163
164
165
166
167
168
169
2
3
4
5
23
24
46
47
146
145
130
129
15
117
118
119
120
121
122
123
124
125
128
129
130
131
132
133
134
135
136
137
138
139
2
3
4
5
23
24
38
39
116
115
106
105
15
D9
E9
F9
C8
D8
E8
A10
F8
B7
A7
C7
A6
D7
E7
F7
B6
C6
D6
E6
B5
C5
B2
C2
C3
D5
G5
G6
N2
N3
B8
C9
D14
E14
F2
External bus interface address bus
External bus interface chip select
output pin
External bus interface byte mask
signal output
16
16
F3
External bus interface read enable
signal for SRAM
External bus interface write enable
signal for SRAM
MOEX_0
MWEX_0
13
14
13
14
E5
F1
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
33
D a t a S h e e t
Pin No
Pin
function
External
Bus
Pin name
MNALE_0
MNCLE_0
MNREX_0
MNWEX_0
Function description
LQFP-176 LQFP-144 BGA-192
External bus interface ALE signal to
control NAND Flash output pin
External bus interface CLE signal to
control NAND Flash output pin
External bus interface read enable
signal to control NAND Flash
19
20
22
21
19
20
22
21
F6
G2
G4
G3
External bus interface write enable
signal to control NAND Flash
MADATA00_0
MADATA01_0
MADATA02_0
MADATA03_0
MADATA04_0
MADATA05_0
MADATA06_0
MADATA07_0
MADATA08_0
MADATA09_0
MADATA10_0
MADATA11_0
MADATA12_0
MADATA13_0
MADATA14_0
MADATA15_0
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
K5
N6
M6
L6
K6
J6
N8
M8
L8
K8
P8
J8
P9
N9
M9
L9
External bus interface data bus
(Address / data multiplex bus)
External bus interface Address Latch
enable output signal for multiplex
External bus interface external RDY
input signal
External bus interface external clock
output
MALE_0
MRDY_0
17
18
48
17
18
40
F4
F5
MCLKOUT_0
M3
34
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Pin No
Pin
Pin name
Function description
LQFP-176 LQFP-144 BGA-192
function
External
Interrupt
INT00_0
INT00_1
INT00_2
INT01_0
INT01_1
INT01_2
INT02_0
INT02_1
INT02_2
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
INT06_0
INT06_1
INT06_2
INT07_0
INT07_1
INT07_2
INT08_0
INT08_1
INT08_2
INT09_0
INT09_1
INT09_2
INT10_0
INT10_1
INT10_2
INT11_0
INT11_1
INT11_2
INT12_0
INT12_1
INT12_2
INT13_0
INT13_1
INT13_2
INT14_0
INT14_1
INT14_2
13
8
165
14
9
123
15
91
120
6
13
8
135
14
9
99
15
75
96
6
78
-
-
81
-
103
84
-
E5
D3
C6
External interrupt request 00 input
pin
F1
External interrupt request 01 input
pin
D4
E11
F2
External interrupt request 02 input
pin
M12
F12
D2
L11
H3
H6
K14
H4
D13
J12
H5
B4
D12
K6
C4
P8
F3
External interrupt request 03 input
pin
94
28
31
97
29
127
100
30
170
126
64
171
70
16
172
33
19
119
34
22
76
35
7
77
36
71
78
46
72
81
47
66
82
58
67
External interrupt request 04 input
pin
External interrupt request 05 input
pin
-
External interrupt request 06 input
pin
102
56
-
62
16
140
-
19
95
26
22
-
27
7
-
28
63
-
38
64
-
External interrupt request 07 input
pin
B3
J4
F6
F11
J3
External interrupt request 08 input
pin
External interrupt request 09 input
pin
G4
K9
J2
D1
P10
K1
J8
N10
N2
P9
M10
N3
N8
N11
M5
M8
External interrupt request 10 input
pin
External interrupt request 11 input
pin
External interrupt request 12 input
pin
External interrupt request 13 input
pin
39
58
-
50
59
External interrupt request 14 input
pin
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
35
D a t a S h e e t
Pin No
Pin
Pin name
Function description
LQFP-176 LQFP-144 BGA-192
function
External
Interrupt
INT15_0
INT15_1
INT15_2
INT16_0
INT16_1
INT17_0
INT17_1
INT18_0
INT18_1
INT19_0
INT19_1
INT20_0
INT20_1
INT21_0
INT21_1
INT22_0
INT22_1
INT23_0
INT23_1
INT24_0
INT24_1
INT25_0
INT25_1
INT26_0
INT26_1
INT27_0
INT27_1
INT28_0
INT28_1
INT29_0
INT29_1
INT30_0
INT30_1
INT31_0
INT31_1
NMIX
83
169
68
106
20
107
21
108
23
109
24
110
96
111
98
112
99
113
74
79
75
80
101
143
102
144
103
25
-
139
60
-
20
-
21
-
23
-
24
-
80
-
82
-
83
-
66
-
67
-
85
-
86
-
87
-
88
-
89
-
133
-
M11
C5
L8
H13
G2
H12
G3
H11
G5
G13
G6
G12
K12
G11
K11
G10
J13
G9
M9
L10
L9
K10
J11
D10
J10
B9
External interrupt request 15 input
pin
External interrupt request 16 input
pin
External interrupt request 17 input
pin
External interrupt request 18 input
pin
External interrupt request 19 input
pin
External interrupt request 20 input
pin
External interrupt request 21 input
pin
External interrupt request 22 input
pin
External interrupt request 23 input
pin
External interrupt request 24 input
pin
External interrupt request 25 input
pin
External interrupt request 26 input
pin
External interrupt request 27 input
pin
J9
H1
H10
H2
H9
C11
F7
D11
B6
External interrupt request 28 input
pin
104
26
External interrupt request 29 input
pin
105
139
163
140
164
128
External interrupt request 30 input
pin
External interrupt request 31 input
pin
Non-Maskable Interrupt input
134
104
C13
36
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Pin No
Pin
function
GPIO
Pin name
Function description
LQFP-176 LQFP-144 BGA-192
P00
P01
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P1A
P1B
P1C
P1D
P1E
P1F
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
134
135
136
137
138
8
9
10
11
12
90
91
92
93
94
95
96
97
110
111
112
113
114
8
9
10
11
B13
A12
C12
B12
B11
D3
D4
E2
E3
E4
M13
M12
L13
L12
L11
K13
K12
K14
K11
J13
J12
J11
General-purpose I/O port 0
General-purpose I/O port 1
General-purpose I/O port 2
12
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
103
102
101
100
99
98
97
96
95
94
98
99
100
101
102
103
104
105
127
126
125
124
123
122
121
120
119
118
J10
J9
H10
H9
D13
D12
E13
E12
E11
E10
F13
F12
F11
F10
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
37
D a t a S h e e t
Pin No
Pin
function
GPIO
Pin name
Function description
LQFP-176 LQFP-144 BGA-192
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P3A
P3B
P3C
P3D
P3E
P3F
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P4A
P4B
P4C
P4D
P4E
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P5A
P5B
P5C
P5D
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
46
47
48
49
50
51
55
56
58
59
60
61
62
63
64
13
14
15
16
17
18
19
20
21
22
23
24
25
26
-
-
-
-
-
-
H3
H4
H5
H6
J5
J4
J3
J2
26
27
28
29
30
31
32
33
34
35
38
39
40
41
42
43
47
48
50
51
52
53
54
55
56
13
14
15
16
17
18
19
20
21
22
23
24
-
General-purpose I/O port 3
K1
K2
K3
K4
L1
L2
L3
M2
N2
N3
M3
L4
M4
N4
P5
P6
M5
L5
K5
N6
M6
L6
K6
E5
F1
General-purpose I/O port 4
F2
F3
F4
F5
F6
General-purpose I/O port 5
G2
G3
G4
G5
G6
H1
H2
-
38
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Pin No
Pin
function
GPIO
Pin name
Function description
LQFP-176 LQFP-144 BGA-192
P60
P61
P62
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P7A
P7B
P7C
P7D
P7E
P7F
P80
P81
P82
P83
P90
P91
P92
P93
P94
P95
PA0
PA1
PA2
PA3
PA4
PA5
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
169
168
167
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
139
138
137
57
58
59
60
61
62
63
64
65
66
67
-
C5
B5
E6
J6
N8
M8
L8
K8
P8
J8
P9
N9
M9
L9
K9
P10
N10
L10
K10
A3
General-purpose I/O port 6
General-purpose I/O port 7
-
-
-
-
80
174
175
129
130
139
140
141
142
143
144
2
142
143
105
106
-
-
-
-
-
-
2
3
4
5
6
7
-
-
-
-
-
-
-
-
A2
General-purpose I/O port 8
General-purpose I/O port 9
E14
D14
C11
D11
B10
C10
D10
B9
B2
C2
C3
D5
3
4
5
6
General-purpose I/O port A
General-purpose I/O port B
D2
D1
7
106
107
108
109
110
111
112
113
H13
H12
H11
G13
G12
G11
G10
G9
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
39
D a t a S h e e t
Pin No
Pin
function
GPIO
Pin name
Function description
LQFP-176 LQFP-144 BGA-192
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PCA
PCB
PCC
PCD
PCE
PCF
PD0
PD1
PD2
PD3
PE0
PE2
PE3
PF0
PF1
PF2
PF3
PF4
PF5
PF6
145
146
147
148
149
150
151
152
153
154
155
158
159
160
161
162
163
164
165
166
84
115
116
117
118
119
120
121
122
123
124
125
128
129
130
131
132
133
134
135
136
68
C9
B8
D9
E9
F9
C8
D8
E8
A10
F8
B7
A7
C7
General-purpose I/O port C
A6
D7
E7
F7
B6
General-purpose I/O port D
General-purpose I/O port E
C6
D6
N13
P12
P13
M10
N11
M11
B4
86
87
81
82
70
71
-
-
-
-
-
83
General-purpose I/O port F*
170
171
172
128
C4
B3
C13
140
104
40
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Pin No.
Pin
function
Multi
Function
Serial
0
Pin name
Function description
LQFP-176 LQFP-144 BGA-192
SIN0_0
SIN0_1
SIN0_2
SOT0_0
(SDA0_0)
SOT0_1
(SDA0_1)
126
94
110
102
78
-
D12
L11
G12
Multifunction serial interface ch.0
input pin
Multifunction serial interface ch.0
output pin.
125
95
101
79
E13
K13
This pin operates as SOT0 when it is
used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA0 when it is used in an I2C
(operation mode 4).
SOT0_2
(SDA0_2)
111
-
G11
SCK0_0
(SCL0_0)
SCK0_1
(SCL0_1)
SCK0_2
(SCL0_2)
SIN1_0
SIN1_1
SIN1_2
SOT1_0
(SDA1_0)
SOT1_1
(SDA1_1)
Multifunction serial interface ch.0
clock I/O pin.
This pin operates as SCK0 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL0 when it is
used in an I2C (operation mode 4).
124
96
100
80
-
E12
K12
G10
112
Multi
Function
Serial
1
19
91
81
19
75
-
F6
M12
M10
Multifunction serial interface ch.1
input pin
Multifunction serial interface ch.1
output pin.
20
92
20
76
G2
This pin operates as SOT1 when it is
used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA1 when it is used in an I2C
(operation mode 4).
L13
SOT1_2
(SDA1_2)
82
-
N11
SCK1_0
(SCL1_0)
SCK1_1
(SCL1_1)
SCK1_2
(SCL1_2)
Multifunction serial interface ch.1
clock I/O pin.
This pin operates as SCK1 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL1 when it is
used in an I2C (operation mode 4).
21
93
83
21
77
-
G3
L12
M11
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
41
D a t a S h e e t
Pin No.
Pin
function
Multi
Function
Serial
2
Pin name
Function description
LQFP-176 LQFP-144 BGA-192
SIN2_0
SIN2_1
SIN2_2
SOT2_0
(SDA2_0)
SOT2_1
(SDA2_1)
67
123
97
59
99
81
M8
E11
K14
Multifunction serial interface ch.2
input pin
Multifunction serial interface ch.2
output pin.
68
60
98
L8
This pin operates as SOT2 when it is
used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA2 when it is used in an I2C
(operation mode 4).
122
E10
SOT2_2
(SDA2_2)
98
82
K11
SCK2_0
(SCL2_0)
SCK2_1
(SCL2_1)
SCK2_2
(SCL2_2)
Multifunction serial interface ch.2
clock I/O pin.
This pin operates as SCK2 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL2 when it is
used in an I2C (operation mode 4).
69
121
99
61
97
83
K8
F13
J13
Multi
Function
Serial
3
SIN3_0
SIN3_1
SIN3_2
70
13
58
62
13
50
P8
E5
Multifunction serial interface ch.3
input pin
M5
SOT3_0
(SDA3_0)
SOT3_1
Multifunction serial interface ch.3
output pin.
71
14
63
14
J8
This pin operates as SOT3 when it is
used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA3 when it is used in an I2C
(operation mode 4).
F1
(SDA3_1)
SOT3_2
(SDA3_2)
59
51
L5
SCK3_0
(SCL3_0)
SCK3_1
(SCL3_1)
SCK3_2
(SCL3_2)
Multifunction serial interface ch.3
clock I/O pin.
This pin operates as SCK3 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL3 when it is
used in an I2C (operation mode 4).
72
15
60
64
15
52
P9
F2
K5
42
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Pin No.
Pin
function
Multi
Function
Serial
4
Pin name
Function description
LQFP-176 LQFP-144 BGA-192
SIN4_0
SIN4_1
SIN4_2
SOT4_0
(SDA4_0)
SOT4_1
(SDA4_1)
165
100
8
135
84
8
C6
J12
D3
Multifunction serial interface ch.4
input pin
Multifunction serial interface ch.4
output pin.
164
101
134
85
B6
This pin operates as SOT4 when it is
used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA4 when it is used in an I2C
(operation mode 4).
J11
SOT4_2
(SDA4_2)
9
9
D4
SCK4_0
(SCL4_0)
SCK4_1
(SCL4_1)
SCK4_2
(SCL4_2)
RTS4_0
RTS4_1
RTS4_2
CTS4_0
CTS4_1
CTS4_2
SIN5_0
Multifunction serial interface ch.4
clock I/O pin.
This pin operates as SCK4 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL4 when it is
used in an I2C (operation mode 4).
163
102
10
133
86
F7
J10
E2
10
161
104
12
162
103
11
169
141
34
131
88
12
132
87
11
139
-
26
D7
H10
E4
E7
J9
Multifunction serial interface ch.4
RTS output pin
Multifunction serial interface ch.4
CTS input pin
E3
Multi
Function
Serial
5
C5
B10
J3
Multifunction serial interface ch.5
input pin
SIN5_1
SIN5_2
Multifunction serial interface ch.5
output pin.
SOT5_0
(SDA5_0)
168
142
138
-
B5
This pin operates as SOT5 when it is
used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA5 when it is used in an I2C
(operation mode 4).
SOT5_1
(SDA5_1)
C10
SOT5_2
(SDA5_2)
35
27
J2
SCK5_0
(SCL5_0)
Multifunction serial interface ch.5
clock I/O pin.
This pin operates as SCK5 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL5 when it is
used in an I2C (operation mode 4).
167
143
36
137
-
E6
D10
K1
SCK5_1
(SCL5_1)
SCK5_2
(SCL5_2)
28
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
43
D a t a S h e e t
Pin No.
Pin
function
Multi
Function
Serial
6
Pin name
Function description
LQFP-176 LQFP-144 BGA-192
SIN6_0
SIN6_1
SIN6_2
SOT6_0
(SDA6_0)
SOT6_1
(SDA6_1)
16
31
170
16
-
-
F3
H6
B4
Multifunction serial interface ch.6
input pin
Multifunction serial interface ch.6
output pin.
17
30
17
-
F4
This pin operates as SOT6 when it is
used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA6 when it is used in an I2C
(operation mode 4).
H5
SOT6_2
(SDA6_2)
171
-
C4
SCK6_0
(SCL6_0)
SCK6_1
(SCL6_1)
SCK6_2
(SCL6_2)
SIN7_0
SIN7_1
SIN7_2
SOT7_0
(SDA7_0)
Multifunction serial interface ch.6
clock I/O pin.
This pin operates as SCK6 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL6 when it is
used in an I2C (operation mode 4).
18
29
18
-
F5
H4
B3
172
-
Multi
Function
Serial
7
22
64
106
22
56
-
G4
K6
H13
Multifunction serial interface ch.7
input pin
Multifunction serial interface ch.7
output pin.
23
63
23
55
G5
L6
This pin operates as SOT7 when it is
used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA7 when it is used in an I2C
(operation mode 4).
SOT7_1
(SDA7_1)
SOT7_2
(SDA7_2)
107
-
H12
SCK7_0
(SCL7_0)
Multifunction serial interface ch.7
clock I/O pin.
This pin operates as SCK7 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL7 when it is
used in an I2C (operation mode 4).
24
62
24
54
-
G6
M6
H11
SCK7_1
(SCL7_1)
SCK7_2
(SCL7_2)
108
44
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Pin No.
Pin
function
Multi
Function
Serial
8
Pin name
Function description
LQFP-176 LQFP-144 BGA-192
Multifunction serial interface ch.8
input pin
Multifunction serial interface ch.6
output pin.
SIN8_0
2
2
B2
This pin operates as SOT8 when it is
used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA8 when it is used in an I2C
(operation mode 4).
SOT8_0
(SDA8_0)
3
3
C2
Multifunction serial interface ch.7
clock I/O pin.
SCK8_0
(SCL8_0)
This pin operates as SCK8 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL8 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.9
input pin
4
5
4
5
C3
D5
Multi
Function
Serial
9
SIN9_0
Multifunction serial interface ch.9
output pin.
This pin operates as SOT9 when it is
used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA9 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.9
clock I/O pin.
This pin operates as SCK9 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL9 when it is
used in an I2C (operation mode 4).
SOT9_0
(SDA9_0)
6
7
6
7
D2
D1
SCK9_0
(SCL9_0)
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
45
D a t a S h e e t
Pin No.
Pin
function
Multi
Function
Serial
Pin name
Function description
LQFP-176 LQFP-144 BGA-192
Multifunction serial interface ch.10
input pin
Multifunction serial interface ch.10
output pin.
SIN10_0
46
38
N2
10
This pin operates as SOT10 when it
is used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA10 when it is used in an I2C
(operation mode 4).
SOT10_0
(SDA10_0)
47
39
N3
Multifunction serial interface ch.10
clock I/O pin.
SCK10_0
(SCL10_0)
This pin operates as SCK10 when it
is used in a UART/CSIO (operation
modes 0 to 2) and as SCL10 when it
is used in an I2C (operation mode 4).
Multifunction serial interface ch.11
input pin
48
49
40
41
M3
L4
Multi
Function
Serial
11
SIN11_0
Multifunction serial interface ch.11
output pin.
This pin operates as SOT11 when it
is used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA11 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.11
clock I/O pin.
This pin operates as SCK11 when it
is used in a UART/CSIO (operation
modes 0 to 2) and as SCL11 when it
is used in an I2C (operation mode 4).
SOT11_0
(SDA11_0)
50
51
42
43
M4
N4
SCK11_0
(SCL11_0)
46
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Pin No.
Pin
function
Multi
Function
Serial
Pin name
Function description
LQFP-176 LQFP-144 BGA-192
Multifunction serial interface ch.12
input pin
Multifunction serial interface ch.12
output pin.
SIN12_0
118
94
F10
12
This pin operates as SOT12 when it
is used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA12 when it is used in an I2C
(operation mode 4).
SOT12_0
(SDA12_0)
119
95
F11
Multifunction serial interface ch.12
clock I/O pin.
SCK12_0
(SCL12_0)
This pin operates as SCK12 when it
is used in a UART/CSIO (operation
modes 0 to 2) and as SCL12 when it
is used in an I2C (operation mode 4).
Multifunction serial interface ch.13
input pin
120
145
96
F12
C9
Multi
Function
Serial
13
SIN13_0
115
Multifunction serial interface ch.13
output pin.
This pin operates as SOT13 when it
is used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA13 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.13
clock I/O pin.
This pin operates as SCK13 when it
is used in a UART/CSIO (operation
modes 0 to 2) and as SCL13 when it
is used in an I2C (operation mode 4).
SOT13_0
(SDA13_0)
146
147
116
117
B8
D9
SCK13_0
(SCL13_0)
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
47
D a t a S h e e t
Pin No.
Pin
function
Multi
Function
Serial
Pin name
Function description
LQFP-176 LQFP-144 BGA-192
Multifunction serial interface ch.14
input pin
Multifunction serial interface ch.14
output pin.
SIN14_0
149
119
F9
14
This pin operates as SOT14 when it
is used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA14 when it is used in an I2C
(operation mode 4).
SOT14_0
(SDA14_0)
150
120
C8
Multifunction serial interface ch.14
clock I/O pin.
SCK14_0
(SCL14_0)
This pin operates as SCK14 when it
is used in a UART/CSIO (operation
modes 0 to 2) and as SCL14 when it
is used in an I2C (operation mode 4).
Multifunction serial interface ch.15
input pin
151
153
121
123
D8
Multi
Function
Serial
15
SIN15_0
A10
Multifunction serial interface ch.15
output pin.
This pin operates as SOT15 when it
is used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA15 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.15
clock I/O pin.
This pin operates as SCK15 when it
is used in a UART/CSIO (operation
modes 0 to 2) and as SCL15 when it
is used in an I2C (operation mode 4).
SOT15_0
(SDA15_0)
154
155
124
125
F8
SCK15_0
(SCL15_0)
B7
48
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Pin No
Pin
function
Multi
Function
Timer
0
Pin name
Function description
LQFP-176 LQFP-144 BGA-192
Input signal controlling wave form
generator outputs RTO00 to RTO05
of multi-function timer 0.
DTTI0X_0
DTTI0X_1
37
29
88
K2
104
H10
FRCK0_0
FRCK0_1
FRCK0_2
IC00_0
IC00_1
IC00_2
IC01_0
IC01_1
IC01_2
IC02_0
32
105
91
36
100
92
35
101
93
34
102
94
-
J5
H9
M12
K1
J12
L13
J2
J11
L12
J3
16-bit free-run timer ch.0 external
clock input pin
89
75
28
84
76
27
85
77
26
86
78
-
16-bit input capture ch.0 input pin of
multi-function timer 0.
ICxx describes channel number.
IC02_1
IC02_2
IC03_0
J10
L11
J4
33
IC03_1
IC03_2
103
95
87
79
J9
K13
RTO00_0
(PPG00_0)
RTO00_1
(PPG00_1)
RTO01_0
(PPG00_0)
RTO01_1
(PPG00_1)
RTO02_0
(PPG02_0)
RTO02_1
(PPG02_1)
RTO03_0
(PPG02_0)
RTO03_1
(PPG02_1)
RTO04_0
(PPG04_0)
RTO04_1
(PPG04_1)
RTO05_0
(PPG04_0)
RTO05_1
(PPG04_1)
IGTRG0_0
IGTRG0_1
Wave form generator output of
multi-function timer 0.
This pin operates as PPG00 when it
is used in PPG0 output modes.
Wave form generator output of
multi-function timer 0.
This pin operates as PPG00 when it
is used in PPG0 output modes.
Wave form generator output of
multi-function timer 0.
This pin operates as PPG02 when it
is used in PPG0 output modes.
Wave form generator output of
multi-function timer 0.
This pin operates as PPG02 when it
is used in PPG0 output modes.
Wave form generator output of
multi-function timer 0.
This pin operates as PPG04 when it
is used in PPG0 output modes.
Wave form generator output of
multi-function timer 0.
This pin operates as PPG04 when it
is used in PPG0 output modes.
PPG IGBT mode external trigger
input pin
38
124
39
30
100
31
99
32
98
33
97
34
96
35
95
K3
E12
K4
123
40
E11
L1
122
41
E10
L2
121
42
F13
L3
120
43
F12
M2
F11
119
61
172
53
140
N6
B3
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
49
D a t a S h e e t
Pin No
LQFP-144BGA-192
Pin
function
Quadrature
Position/
Revolution
Counter
0
Pin name
Function description
LQFP-176
AIN0_0
AIN0_1
28
-
H3
L5
QPRC ch.0 AIN input pin
QPRC ch.0 BIN input pin
QPRC ch.0 ZIN input pin
QPRC ch.1 AIN input pin
QPRC ch.1 BIN input pin
QPRC ch.1 ZIN input pin
59
13
51
13
-
AIN0_2
E5
BIN0_0
29
H4
K5
F1
BIN0_1
60
52
14
-
BIN0_2
14
ZIN0_0
30
H5
N6
F2
ZIN0_1
61
53
15
65
103
54
66
102
55
67
101
56
122
77
29
122
77
29
ZIN0_2
15
Quadrature
Position/
Revolution
Counter
1
AIN1_0
73
N9
D13
M6
M9
D12
L6
AIN1_1
127
62
AIN1_2
BIN1_0
74
BIN1_1
126
63
BIN1_2
ZIN1_0
75
L9
ZIN1_1
125
64
E13
K6
E8
ZIN1_2
Real-time
clock
RTCCO_0
RTCCO_1
RTCCO_2
SUBOUT_0
SUBOUT_1
SUBOUT_2
152
93
0.5 seconds pulse output pin of Real-
time clock
L12
K2
E8
37
152
93
Sub clock output pin
L12
K2
37
50
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Pin No
Pin
function
RESET
Pin name
Function description
LQFP-176 LQFP-144 BGA-192
External Reset Input. A reset is valid
when INITX="L".
INITX
57
49
N5
Mode
Mode 0 Pin.
During normal operation, MD0="L"
must be input. During serial
programming to Flash memory,
MD0="H" must be input.
Mode 1 Pin.
MD0
MD1
85
69
N12
During serial programming to Flash
memory, MD1="L" must be input.
84
68
N13
POWER
1
1
C1
N1
P4
45
54
89
37
46
73
M14
VCC
Power supply Pin
131
107
109
126
C14
A13
A9
133
156
Low-Power
Consumption
Mode
Deep standby mode return signal
input pin 0
Deep standby mode return signal
input pin 1
Deep standby mode return signal
input pin 2
Deep standby mode return signal
input pin 3
Deep standby mode return signal
input pin 4
Deep standby mode return signal
input pin 5
WKUP0
WKUP1
WKUP2
WKUP3
WKUP4
WKUP5
128
91
104
75
C13
M12
M8
B3
67
59
172
28
140
-
H3
169
139
C5
HDMI-
CEC/
Remote
Control
Reception
DAC
CEC0_0
CEC0_1
CEC1_0
CEC1_1
81
149
172
19
-
M10
F9
HDMI-CEC/Remote Control
Reception ch.0 input/output pin
119
140
19
B3
HDMI-CEC/Remote Control
Reception ch.1 input/output pin
F6
DA0_0
DA1_0
D/A converter ch.0 analog output pin
D/A converter ch.1 analog output pin
145
146
115
116
C9
B8
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
51
D a t a S h e e t
Pin No
Pin
function
GND
Pin name
Function description
LQFP-176 LQFP-144 BGA-192
27
44
25
36
45
A5
A8
A11
53
72
E1
G7
G8
H8
M1
P3
88
108
132
127
157
144
176
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P7
N7
M7
L7
VSS
GND Pin
K7
J7
P11
N14
L14
B14
H7
B1
G1
J1
P12
P5
CLOCK
X0
X0A
X1
Main clock (oscillation) input pin
Sub clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) I/O pin
Built-in high-speed CR-osc clock
output port
86
55
70
47
87
56
71
48
P13
P6
X1A
CROUT_0
CROUT_1
127
152
103
122
D13
E8
Analog
POWER
A/D converter, D/A converter analog
power pin
A/D converter analog reference
voltage input pin
A/D converter, D/A converter GND
pin
A/D converter analog reference
voltage input pin
AVCC
AVRH
AVSS
AVRL
C
114
117
115
116
52
90
93
91
92
44
J14
F14
H14
G14
P2
Analog
GND
C pin
Power supply stabilization capacity
pin
* : 5V tolerant I/O
52
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
I/O Circuit Type
Type
Circuit
Remarks
A
It is possible to select the main
oscillation / GPIO function
Pull-up
resistor
When the main oscillation is
selected.
Oscillation feedback resistor
: Approximately 1 MΩ
With Standby mode control
Digital output
Digital output
P-ch
P-ch
X1
When the GPIO is selected.
CMOS level output.
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
N-ch
R
: Approximately 50 kΩ
IOH= -4 mA, IOL= 4 mA
Pull-up resistor control
Digital input
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
Digital output
P-ch
N-ch
P-ch
X0
Digital output
Pull-up resistor control
B
CMOS level hysteresis input
Pull-up resistor
: Approximately 50 kΩ
Pull-up resistor
Digital input
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
53
D a t a S h e e t
Type
Circuit
Remarks
C
Open drain output
CMOS level hysteresis input
Digital input
Digital output
N-ch
D
It is possible to select the sub
oscillation / GPIO function
Pull-up
resistor
When the sub oscillation is
selected.
Oscillation feedback resistor
: Approximately 5 MΩ
With Standby mode control
P-ch
P-ch
Digital output
Digital output
X1A
When the GPIO is selected.
CMOS level output.
N-ch
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
IOH= -4 mA, IOL= 4 mA
R
Pull-up resistor control
Digital input
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
Digital output
P-ch
N-ch
P-ch
X0A
Digital output
Pull-up resistor control
54
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Type
Circuit
Remarks
E
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
P-ch
P-ch
: Approximately 50 kΩ
Digital output
Digital output
IOH= -4 mA, IOL= 4 mA
When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
+B input available
N-ch
R
Pull-up resistor control
Digital input
Standby mode control
F
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
P-ch
P-ch
IOH= -12 mA, IOL= 12 mA
+B input available
Digital output
Digital output
N-ch
R
Pull-up resistor control
Digital input
Standby mode control
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
55
D a t a S h e e t
Type
Circuit
Remarks
G
CMOS level output
CMOS level hysteresis input
With input control
Analog input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
IOH= -4 mA, IOL= 4 mA
When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
+B input available
Digital output
Digital output
P-ch
P-ch
N-ch
Pull-up resistor control
Digital input
R
Standby mode control
Analog input
Input control
H
CMOS level output
CMOS level hysteresis input
With input control
Analog output
P-ch
P-ch
Digital output
Digital output
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
IOH = -4 mA, IOL = 4 mA
N-ch
Pull-up resistor control
Digital input
R
Standby mode Control
Analog output
56
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Type
Circuit
Remarks
CMOS level output
CMOS level hysteresis input
5 V tolerant
I
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
IOH= -4 mA, IOL= 4 mA
Available to control PZR
registers.
When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
P-ch
P-ch
Digital output
Digital output
N-ch
R
Pull-up resistor control
Digital input
Standby mode control
J
CMOS level hysteresis input
Mode input
K
CMOS level output
CMOS level hysteresis input
With standby mode control
IOH= -18.0 mA, IOL= 16.5 mA
P-ch
Digital output
Digital output
N-ch
R
Digital input
Standby mode Control
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
57
D a t a S h e e t
Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your Spansion semiconductor devices.
1. Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to
prevent such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can
cause large current flows. Such conditions if present for extended periods of time can damage the
device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation.
Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may
be formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Code: DS00-00004-3E
58
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and equipment
such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.
Precautions Related to Usage of Devices
Spansion semiconductor devices are intended for use in standard applications (computers, office automation
and other office equipment, industrial, communications, and measurement equipment, personal or
household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or
abnormal operation may directly affect human lives or cause physical injury or property damage, or where
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea
floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult
with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
2. Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance
during soldering, you should only mount under Spansion's recommended conditions. For detailed
information about mount conditions, contact your sales representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the
board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the
soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for
storage temperature. Mounting processes should conform to Spansion recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are
more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in
increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and has
established a ranking of mounting conditions for each product. Users are advised to mount packages in
accordance with Spansion ranking of recommended conditions.
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
59
D a t a S h e e t
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent,
do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Spansion packages semiconductor devices in highly moisture-resistant aluminum
laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags
for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion
recommended conditions for baking.
Condition: 125°C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus
for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high
resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to
minimize shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board
assemblies.
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MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
3. Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will
adversely affect the device. If you use devices in such conditions, consider ways to prevent such
exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation.
Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible
substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Spansion products in other special environmental conditions should
consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
61
D a t a S h e e t
Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected
within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be
connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels,
to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the
total output current rating.
Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low
impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass
capacitor between each Power supply pin and GND pin near this device.
Stabilizing power supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is
within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage
stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at
the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended
operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary
fluctuation on switching the power supply.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit
board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as
close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins
are surrounded by ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Sub crystal oscillator
This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to
fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.
・ Surface mount type
Size : More than 3.2mm × 1.5mm
Load capacitance : Approximately 6 pF to 7 pF
・ Lead type
Load capacitance : Approximately 6 pF to 7 pF
62
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Using an external clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input
the clock to X0. X1(PE3) can be used as a general-purpose I/O port.
Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock
input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port.
• Example of Using an External Clock
Device
X0(X0A)
Set as
Can be used as
general-purpose
I/O ports.
External clock
input
X1(PE3),
X1A (P47)
Handling when using Multi-function serial pin as I2C pin
If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled.
However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external
I2C bus system with power OFF.
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between
the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency
characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to
thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the
specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7μF would be recommended for this series.
C
Device
CS
VSS
GND
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the
pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins
is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for
switching the pin level and rewriting the Flash memory data. It is because of preventing the device
erroneously switching to test mode due to noise.
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
63
D a t a S h e e t
Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS.
Turning on : VCC → AVCC → AVRH
Turning off : AVRH → AVCC → VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a
checksum of data at the end. If an error is detected, retransmit the data.
Differences in features among the products with different memory sizes and between
Flash memory products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and
oscillation characteristics among the products with different memory sizes and between Flash memory
products and MASK products are different because chip layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric
characteristics.
Pull-Up function of 5V tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5V tolerant I/O.
Adjoining wiring on circuit board
If wiring of the crystal oscillation circuit (X0/X1 and X0A/X1A) adjoins and also runs in parallel with the
wiring of GPIO, there is a possibility that the oscillation erroneously counts because oscillation wave has
noise with the change of GPIO. Keep as much distance as possible between both wirings and insert the
ground pattern between them in order to avoid this possibility.
64
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Block Diagram
TRSTX,TCK,
TDI,TMS
SWJ-DP
ETM
SRAM0
80/96 Kbytes
TDO
ROM
Table
TRACEDx,
TRACECLK
TPIU
I
SRAM1
80/96 Kbytes
D
NVIC
Sys
Flash I/F
Security
On-Chip Flash
1 Mbytes+64 Kbytes/
1.5 Mbytes+64 Kbytes
Dual-Timer
WatchDog Timer
(Software)
Clock Reset
Generator
INITX
WatchDog Timer
(Hardware)
DMAC
8ch.
CSV
CLK
X0
X1
Main
Source Clock
CR
PLL
CR
Osc
Sub
Osc
X0A
X1A
4 MHz 100 kHz
CROUT
MADx
AVCC,
AVSS,
AVRH
MADATAx
External Bus I/F
12-bit A/D Converter
Unit 0
MCSXx,MDQMx,
MOEX,MWEX,
MALE,MRDY,
MNALE,MNCLE,
MNWEX,MNREX,
MCLKOUT
ANxx
Unit 1
ADTGx
10-bit D/Aconverter
2 Units
DAx
Power-On
Reset
Base Timer
16-bit 16ch./
32-bit 8ch.
LVD
TIOAx
TIOBx
LVD Ctrl
Regulator
C
IRQ-Monitor
CRC Accelerator
Watch Counter
AINx
BINx
ZINx
QPRC
2ch.
WKUPx
Deep Standby Ctrl
A/D Activation Compare
2ch.
CEC0_x,
CEC1_x
HDMI-CEC/
Remote Reciver Control
16-bit Input Capture
4ch.
IC0x
RTCCO,
SUBOUT
Real-Time Clock
External Interrupt
Controller
32pin + NMI
16-bit Free-run Timer
3ch.
FRCK0
INTx
NMIX
16-bit Output Compare
6ch.
MD0,
MD1
P0x,
P1x,
DTTI0X
RTO0x
MODE-Ctrl
GPIO
Waveform Generator
3ch.
.
.
.
PIN-Function-Ctrl
PFx
SCKx
SINx
SOTx
CTS4
RTS4
16-bit PPG
3ch.
IGTRGx
Multi-function Serial I/F
16ch.
HW flow control(ch.4)
Multi-function Timer × 1
Memory Size
See " Memory size" in "Product Lineup" to confirm the memory size.
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
65
D a t a S h e e t
Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0xFFFF_FFFF
Reserved
0xE010_0000
0xE000_0000
Cortex-M3 Private
Peripherals
0x4006_1000
0x4006_0000
DMAC
Reserved
Reserved
0x4004_0000
0x4003_F000
0x4003_C000
0x4003_B000
0x4003_A000
0x4003_9000
0x4003_8000
EXT-bus I/F
Reserved
RTC
0x7000_0000
0x6000_0000
External Device
Area
Watch Counter
CRC
MFS
Reserved
Reserved
0x4400_0000
0x4003_6000
0x4003_5000
LVD/DS mode
HDMI-CEC/
0x4003_4000 Remote Control Receiver
32Mbytes
Bit band alias
0x4200_0000
0x4000_0000
0x2400_0000
0x2200_0000
GPIO
Reserved
Int-Req.Read
EXTI
0x4003_3000
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
0x4002_9000
0x4002_8000
0x4002_7000
0x4002_6000
0x4002_5000
0x4002_4000
Peripherals
Reserved
32Mbytes
Bit band alias
Reserved
CR Trim
Reserved
D/AC
Reserved
0x2001_8000
0x2000_0000
0x1FFE_8000
SRAM1
SRAM0
A/DC
QPRC
Base Timer
PPG
Reserved
0x0051_8000
0x0050_8000
0x0040_4000
0x0040_0000
Flash(Work area)
Reserved
Reserved
See "Memory map(2)" for
the memory size details.
Security/CR Trim
0x4002_1000
0x4002_0000
MFT unit0
Reserved
0x4001_6000
0x4001_5000
Flash(Main area)
Dual Timer
Reserved
0x0000_0000
0x4001_3000
0x4001_2000
SW WDT
HW WDT
0x4001_1000
0x4001_0000
Clock/Reset
Reserved
Flash I/F
0x4000_1000
0x4000_0000
66
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Memory Map (2)
MB9BF129SA/TA
MB9BF128SA/TA
0x2008_0000
0x2008_0000
0x2001_4000
Reserved
Reserved
0x2001_8000
SRAM1
80Kbytes
SRAM1
64Kbytes
0x2000_4000
0x2000_0000
0x1FFF_C000
0x2000_4000
0x2000_0000
0x1FFF_C000
SRAM1ꢀ16Kbytes*
SRAM0ꢀ16Kbytes*
SRAM1ꢀ16Kbytes*
SRAM0ꢀ16Kbytes*
SRAM0
64Kbytes
SRAM0
80Kbytes
0x1FFE_C000
0x1FFE_8000
Reserved
Reserved
ROM1_SA0-7(8KBx8)
Reserved
0x0051_8000
0x0050_8000
0x0051_8000
0x0050_8000
ROM1_SA0-7(8KBx8)
Reserved
0x0040_4000
0x0040_2000
0x0040_0000
0x0040_4000
0x0040_2000
0x0040_0000
CR trimming
Security
CR trimming
Security
Reserved
Reserved
0x0018_0000
0x0010_0000
ROM1_SA8-15(8KBx8)
0x0010_0000
ROM0_SA9-23(64KBx15)
ROM0_SA9-23(64KBx15)
ROM0_SA8(48KB)
ROM0_SA8(48KB)
ROM0_SA2-3(8KBx2)
ROM0_SA2-3(8KBx2)
0x0000_0000
0x0000_0000
* : The content of SRAM can be retained at the deep standby modes by the setting of Deep Standby RAM
Retention Register (DSRAMR).
See "MB9B520T/420T/320T/120T Series Flash programming Manual" for sector structure of Flash.
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
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D a t a S h e e t
Peripheral Address Map
Start address
End address
Bus
Peripherals
0x4000_0000
0x4000_1000
0x4001_0000
0x4001_1000
0x4001_2000
0x4001_3000
0x4001_5000
0x4001_6000
0x4002_0000
0x4002_1000
0x4002_4000
0x4002_5000
0x4002_6000
0x4002_7000
0x4002_8000
0x4002_9000
0x4002_E000
0x4002_F000
0x4003_0000
0x4003_1000
0x4003_2000
0x4003_3000
0x4003_4000
0x4003_5000
0x4003_5800
0x4003_6000
0x4003_8000
0x4003_9000
0x4003_A000
0x4003_B000
0x4003_C000
0x4003_F000
0x4004_0000
0x4006_0000
0x4006_1000
0x4000_0FFF
0x4000_FFFF
0x4001_0FFF
0x4001_1FFF
0x4001_2FFF
0x4001_4FFF
0x4001_5FFF
0x4001_FFFF
0x4002_0FFF
0x4002_3FFF
0x4002_4FFF
0x4002_5FFF
0x4002_6FFF
0x4002_7FFF
0x4002_8FFF
0x4002_DFFF
0x4002_EFFF
0x4002_FFFF
0x4003_0FFF
0x4003_1FFF
0x4003_2FFF
0x4003_3FFF
0x4003_4FFF
0x4003_57FF
0x4003_5FFF
0x4003_7FFF
0x4003_8FFF
0x4003_9FFF
0x4003_AFFF
0x4003_BFFF
0x4003_EFFF
0x4003_FFFF
0x4005_FFFF
0x4006_0FFF
0x41FF_FFFF
Flash Memory I/F register
Reserved
AHB
Clock/Reset Control
Hardware Watchdog timer
Software Watchdog timer
Reserved
APB0
Dual-Timer
Reserved
Multi-function timer unit0
Reserved
PPG
Base Timer
Quadrature Position/Revolution Counter (QPRC)
A/D Converter
APB1
D/A Converter
Reserved
Built-in CR trimming
Reserved
External Interrupt
Interrupt Source Check Resister
Reserved
GPIO
HDMI-CEC/Remote control Reception
Low-Voltage Detector
Deep standby mode Controller
Reserved
APB2
Multi-function serial Interface
CRC
Watch Counter
Real-time clock
Reserved
External bus interface
Reserved
AHB
DMAC register
Reserved
68
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the "L" level.
INITX=1
This is the period when the INITX pin is the "H" level.
SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register
(STB_CTL) is set to "0".
SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register
(STB_CTL) is set to "1".
Input enabled
Indicates that the input function can be used.
Internal input fixed at "0"
This is the status that the input function cannot be used. Internal input is fixed at "L".
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Trace output
Indicates that the trace function can be used.
GPIO selected
In Deep standby mode, pins switch to the general-purpose I/O port.
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
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D a t a S h e e t
List of Pin Status
Power-on
Deep standby
RTC mode or Deep
standby STOP mode
state
Return from
Deep
standby
reset or
low-voltage
detection
state
Device Run mode
internal or SLEEP
reset state mode state STOP mode state
Timer mode,
RTC mode, or
INITX
input state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
INITX = 1
-
Power supply stable
Power supply stable Power supply stable
INITX = 1 INITX = 1
-
-
INITX = 0 INITX = 1 INITX = 1
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Maintain
previous
state
GPIO
Setting
Setting
Setting
GPIO
selected
disabled
disabled
disabled
selected
A
Main crystal
oscillator input
pin/
Input
Input
Input
Input
Input
Input
Input
Input
Input
External main
clock input
selected
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Maintain
previous
state
GPIO
Setting
Setting
Setting
GPIO
selected
disabled
disabled
disabled
selected
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
External main
clock input
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Setting
Setting
Setting
disabled
disabled
disabled
B
Maintain
previous
Maintain
previous
Maintain
previous
Maintain
previous
Maintain
previous
Maintain
previous
Hi-Z /
Internal
input
state/When state/When state/When state/When state/When state/When
oscillation oscillation oscillation oscillation oscillation oscillation
Hi-Z /
Hi-Z /
Main crystal
oscillator output
pin
Internal
Internal
fixed at
"0"/
stops*1,
stops*1,
stops*1,
stops*1,
stops*1,
stops*1,
input fixed input fixed
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
at "0"
at "0"
or Input
enable
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed
at "0"
at "0"
at "0"
at "0"
at "0"
at "0"
Pull-up /
Input
Pull-up /
Input
Pull-up /
Input
Pull-up /
Input
Pull-up /
Input
Pull-up /
Input
Pull-up /
Input
Pull-up /
Input
Pull-up /
Input
INITX
C
D
input pin
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Mode
Input
Input
Input
Input
Input
Input
Input
Input
Input
input pin
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Mode
Input
Input
Input
Input
Input
Input
Input
Input
Input
input pin
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
E
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Input
Hi-Z /
Input
GPIO
Setting
Setting
Setting
GPIO
GPIO
selected
disabled
disabled
disabled
selected
selected
enabled
enabled
70
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Power-on
reset or
low-voltage
detection
state
Deep standby
RTC mode or Deep
standby STOP mode
state
Return from
Deep
standby
Device Run mode
internal or SLEEP
reset state mode state STOP mode state
Timer mode,
RTC mode, or
INITX
input state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
INITX = 1
-
Power supply stable
Power supply stable Power supply stable
INITX = 1 INITX = 1
-
-
INITX = 0 INITX = 1 INITX = 1
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Maintain
previous
state
GPIO
Setting
Setting
Setting
GPIO
selected
disabled
disabled
disabled
selected
F
Sub crystal
oscillator input
pin /
Input
Input
Input
Input
Input
Input
Input
Input
Input
External sub
clock input
selected
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Maintain
previous
state
GPIO
Setting
Setting
Setting
GPIO
selected
disabled
disabled
disabled
selected
Hi-Z /
Internal
input fixed
at "0"
Hi-Z/
Internal
input fixed
at "0"
External sub
clock input
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Setting
Setting
Setting
disabled
disabled
disabled
G
Maintain
previous
Maintain
previous
Maintain
previous
Maintain
previous
Maintain
previous
Hi-Z /
Internal
input
state/When state/When state/When state/When state/When
Maintain oscillation oscillation oscillation oscillation oscillation
Hi-Z /
Hi-Z /
Sub crystal
oscillator output
pin
Internal
Internal
fixed at
"0"/
previous
state
stops*2,
stops*2,
stops*2,
stops*2,
stops*2,
input fixed input fixed
Hi-Z /
Hi-Z /
Hi-Z/
Hi-Z/
Hi-Z/
at "0"
at "0"
or Input
enable
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed
at "0"
at "0"
at "0"
at "0"
at "0"
Maintain
previous
state
Setting
Setting
Setting
NMIX selected
disabled
disabled
disabled
Hi-Z /
WKUP
input
Maintain
previous
state
Maintain
previous
state
WKUP
input
GPIO
H
Hi-Z /
selected
Hi-Z /
Input
Hi-Z /
Input
enabled
GPIO
Internal
input fixed
at "0"
enabled
Hi-Z
Hi-Z
selected
enabled
enabled
Pull-up /
Input
Pull-up /
Input
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
JTAG
selected
enabled
enabled
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Internal
input fixed
at "0"
I
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
GPIO
Setting
Setting
Setting
GPIO
selected
disabled
disabled
disabled
selected
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
71
D a t a S h e e t
Power-on
reset or
low-voltage
detection
state
Deep standby
RTC mode or Deep
standby STOP mode
state
Return from
Deep
standby
Device Run mode
internal or SLEEP
reset state mode state STOP mode state
Timer mode,
RTC mode, or
INITX
input state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
INITX = 1
-
Power supply stable
Power supply stable Power supply stable
INITX = 1 INITX = 1
-
-
INITX = 0 INITX = 1 INITX = 1
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Resource selected
Hi-Z /
Input
Hi-Z /
Input
Maintain
previous
state
Maintain
previous
state
GPIO
J
Hi-Z
selected
GPIO
enabled
enabled
selected
Maintain
previous
state
External interrupt
enabled selected
Setting
Setting
Setting
disabled
disabled
disabled
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Maintain
previous
state
Resource other
than above
selected
GPIO
K
Hi-Z /
Internal
input fixed
at "0"
selected
Hi-Z /
Input
Hi-Z /
Input
Hi-Z
Hi-Z
enabled
enabled
GPIO
selected
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed input fixed
Analog input
selected
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
L
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Resource other
than above
selected
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Maintain
previous
state
Setting
Setting
Setting
GPIO
disabled
disabled
disabled
selected
GPIO
selected
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed input fixed
Analog input
selected
Hi-Z
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
M
Maintain
previous
state
External interrupt
enabled selected
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Maintain
previous
state
Resource other
than above
selected
Setting
Setting
Setting
GPIO
disabled
disabled
disabled
selected
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
72
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Power-on
reset or
low-voltage
detection
state
Deep standby
RTC mode or Deep
standby STOP mode
state
Return from
Deep
standby
Device Run mode
internal or SLEEP
reset state mode state STOP mode state
Timer mode,
RTC mode, or
INITX
input state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
INITX = 1
-
Power supply stable
Power supply stable Power supply stable
INITX = 1 INITX = 1
-
-
INITX = 0 INITX = 1 INITX = 1
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed input fixed
Analog input
selected
Hi-Z
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Hi-Z /
WKUP
input
WKUP
input
WKUP
enabled
enabled
Maintain
previous
state
enabled
N
External interrupt
enabled selected
Maintain
previous
state
Maintain
previous
state
Setting
Setting
Setting
GPIO
disabled
disabled
disabled
selected
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Resource other
than above
selected
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
Analog output
selected
Setting
Setting
Setting
*3
*4
disabled
disabled
disabled
GPIO
Hi-Z /
Internal
input fixed
at "0"
Resource other
than above
selected
Maintain
previous
state
selected
Internal
GPIO
O
Hi-Z /
Hi-Z /
Input
Hi-Z /
Input
Maintain
previous
state
selected
Internal input fixed
Hi-Z
input fixed
at "0"
at "0"
enabled
enabled
GPIO
selected
Setting
Setting
Setting
Trace
Trace selected
disabled
disabled
disabled
output
GPIO
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Maintain
previous
state
selected
Internal
Resource other
than above
selected
GPIO
P
Hi-Z /
Hi-Z /
Input
Hi-Z /
Input
selected
Internal input fixed
Hi-Z
input fixed
at "0"
at "0"
enabled
enabled
GPIO
selected
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
73
D a t a S h e e t
Power-on
reset or
low-voltage
detection
state
Deep standby
RTC mode or Deep
standby STOP mode
state
Return from
Deep
standby
Device Run mode
internal or SLEEP
reset state mode state STOP mode state
Timer mode,
RTC mode, or
INITX
input state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
INITX = 1
-
Power supply stable
Power supply stable Power supply stable
INITX = 1 INITX = 1
-
-
INITX = 0 INITX = 1 INITX = 1
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Trace
Trace selected
output
Setting
Setting
Setting
Maintain
previous
state
disabled
disabled
disabled
GPIO
selected
Internal
input fixed
at "0"
External interrupt
enabled selected
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Maintain
previous
state
GPIO
Q
R
S
selected
Resource other
than above
selected
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Input
Hi-Z /
Input
Hi-Z
enabled
enabled
GPIO
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
CEC
Setting
Setting
Setting
enabled
disabled
disabled
disabled
Maintain
previous
state
Maintain
previous
state
Resource other
than above
selected
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Input
Hi-Z /
Input
GPIO
Hi-Z
selected
enabled
enabled
GPIO
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
CEC
enabled
Maintain
previous
state
Setting
Setting
Setting
disabled
disabled
disabled
External interrupt
enabled selected
Maintain
previous
state
Maintain
previous
state
GPIO
Hi-Z /
Internal
input fixed
at "0"
selected
Internal
Resource other
than above
selected
GPIO
Hi-Z /
Hi-Z /
Input
Hi-Z /
Input
selected
Internal input fixed
Hi-Z
input fixed
at "0"
at "0"
enabled
enabled
GPIO
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
CEC
enabled
Hi-Z /
WKUP
input
Maintain
previous
state
WKUP
input
Setting
Setting
Setting
WKUP
enabled
disabled
disabled
disabled
enabled
Maintain
previous
state
Maintain
previous
state
enabled
T
External interrupt
enabled selected
GPIO
GPIO
selected
Internal
input fixed
at "0"
selected
Hi-Z /
Internal
input fixed
at "0"
Resource other
than above
selected
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Input
Hi-Z /
Input
Hi-Z
enabled
enabled
GPIO
selected
74
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Power-on
reset or
low-voltage
detection
state
Deep standby
RTC mode or Deep
standby STOP mode
state
Return from
Deep
standby
Device Run mode
internal or SLEEP
reset state mode state STOP mode state
Timer mode,
RTC mode, or
INITX
input state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
INITX = 1
-
Power supply stable
Power supply stable Power supply stable
INITX = 1 INITX = 1
-
-
INITX = 0 INITX = 1 INITX = 1
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Hi-Z /
WKUP
input
WKUP
input
WKUP
enabled
Maintain
previous
state
Setting
Setting
Setting
enabled
enabled
disabled
disabled
disabled
External interrupt
enabled selected
Maintain
previous
state
Maintain
previous
state
GPIO
U
GPIO
selected
Hi-Z /
Internal
input fixed
at "0"
selected
Internal
Resource other
than above
selected
Hi-Z /
Hi-Z /
Input
Hi-Z /
Input
Internal input fixed
Hi-Z
Hi-Z
input fixed
at "0"
at "0"
enabled
enabled
GPIO
selected
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Input
Hi-Z /
Input
Maintain
previous
state
Maintain
previous
state
GPIO
GPIO
V
selected
selected
enabled
enabled
*1 : Oscillation is stopped at Sub timer mode, Low-speed CR timer mode, RTC mode, STOP mode, Deep
standby RTC mode, and Deep standby STOP mode.
*2 : Oscillation is stopped at STOP mode and Deep standby STOP mode.
*3 : Maintain previous state at timer mode. GPIO selected Internal input fixed at "0" at RTC mode, STOP mode.
*4 : Maintain previous state at timer mode. Hi-Z/Internal input fixed at "0" at RTC mode, STOP mode.
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
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Electrical Characteristics
1. Absolute Maximum Ratings
Parameter
Rating
Symbol
Unit
Remarks
Min
Max
Power supply voltage*1, *2
VCC
AVCC
AVRH
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS + 6.5
VSS + 6.5
VSS + 6.5
V
V
V
Analog power supply voltage*1, *3
Analog reference voltage*1, *3
VCC + 0.5
(≤ 6.5V)
VSS - 0.5
V
Input voltage*1
VI
VSS - 0.5
VSS - 0.5
VSS + 6.5
VSS + 3.63
AVCC + 0.5
(≤ 6.5V)
VCC + 0.5
(≤ 6.5V)
+2
V
V
5V tolerant
5V tolerant*8
Analog pin input voltage*1
Output voltage*1
VIA
VSS - 0.5
V
V
VO
VSS - 0.5
-2
Clamp maximum current
ICLAMP
mA *8
Clamp total maximum current
Σ[ICLAMP
]
+20
mA *8
10
20
39
4
12
16.5
100
50
mA 4mA type
mA 12mA type
mA P80/P81
mA 4mA type
mA 12mA type
mA P80/P81
mA
"L" level maximum output current*4
IOL
-
-
"L" level average output current*5
IOLAV
"L" level total maximum output current
"L" level total average output current*6
∑IOL
∑IOLAV
-
-
mA
- 10
- 20
- 39
- 4
- 12
- 18
mA 4mA type
mA 12mA type
mA P80/P81
mA 4mA type
mA 12mA type
mA P80/P81
"H" level maximum output current*4
IOH
-
"H" level average output current*5
IOHAV
-
-
"H" level total maximum output
current
∑IOH
- 100
mA
"H" level total average output current*6 ∑IOHAV
-
-
- 50
390
+ 150
mA
mW
°C
Power consumption
Storage temperature
PD
TSTG
- 55
*1 : These parameters are based on the condition that VSS = AVSS = 0V.
*2 : VCC must not drop below VSS - 0.5V.
*3 : Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on.
*4 : The maximum output current is defined as the value of the peak current flowing through any one of the
corresponding pins.
*5 : The average output current is defined as the average current value flowing through any one of the
corresponding pins for a 100 ms period.
*6 : The total average output current is defined as the average current value flowing through all of
corresponding pins for a 100ms.
*7: VCC = AVCC = AVRH = VSS = AVSS = AVRL = 0.0V
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MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
*8 :
・See "List of Pin Functions" and "I/O Circuit Type" about +B input available pin.
・Use within recommended operating conditions.
・Use at DC voltage (current) the +B input.
・The +B signal should always be applied a limiting resistance placed between the +B signal
and the device.
・The value of the limiting resistance should be set so that when the +B signal is applied the
input current to the device pin does not exceed rated values, either instantaneously or for
prolonged periods.
・Note that when the device drive current is low, such as in the low-power consumpsion modes,
the +B input potential may pass through the protective diode and increase the potential at
the VCC and AVCC pin, and this may affect other devices.
・Note that if a +B signal is input when the device power supply is off (not fixed at 0V), the
power supply is provided from the pins, so that incomplete operation may result.
・The following is a recommended circuit example (I/O equivalent circuit).
Protection Diode
VCC
VCC
P-ch
Limiting
resistor
Digital output
Digital input
+B input (0V to 16V)
N-ch
R
AVCC
Analog input
<WARNING>
Semiconductor devices may be permanently damaged by application of stress (including, without limitation,
voltage, current or temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
77
D a t a S h e e t
2. Recommended Operating Conditions
(VSS = AVSS = 0.0V)
Value
Parameter
Symbol Conditions
Unit
Remarks
Min
2.7*2
2.7
Max
5.5
Power supply voltage
Analog power supply voltage
VCC
-
-
-
-
V
V
V
V
AVCC
5.5
AVCC = VCC
AVRH
AVRL
2.7
AVCC
AVSS
Analog reference voltage
AVSS
For built-in
Regulator*1
Smoothing capacitor
Operating temperature
CS
-
1
10
μF
Ta
-
- 40
+ 105
°C
*1 : See " C Pin" in "Handling Devices" for the connection of the smoothing capacitor.
*2 : In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage
or more, instruction execution and low voltage detection function by built-in High-speed CR(including
Main PLL is used) or built-in Low-speed CR is possible to operate only.
<WARNING>
The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of device and
could result in device failure.
No warranty is made with respect to any use, operating conditions or combinations not represented on this
data sheet. If you are considering application under any conditions other than listed herein, please contact
sales representatives beforehand.
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MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
3. DC Characteristics
(1) Current Rating
Symbol
Value
Parameter (Pin
name)
Conditions
Unit Remarks
Typ*1 Max*2
CPU : 60 MHz,
Peripheral : 30 MHz
29
19
37
26
mA
mA
*3,*5
PLL
RUN mode
CPU:60 MHz,
Peripheral clock stops
*3,*5
High-speed CR
RUN mode
CPU/ Peripheral : 4 MHz
*4,*3
ICC
3.1
6.4
mA
µA
Sub
RUN mode
CPU/ Peripheral : 32 kHz
*3,*6
170
2300
Low-speed CR
RUN mode
CPU/ Peripheral : 100 kHz
*
210
2300
µA
3
PLL
Peripheral : 30 MHz
*3,*5
19
2.1
160
190
20
-
26
5.1
2200
2200
75
mA
mA
µA
µA
μA
SLEEP mode
High-speed CR
SLEEP mode
Sub
SLEEP mode
Low-speed CR
SLEEP mode
Peripheral : 4 MHz*4
3
*
ICCS
ICCH
ICCT
ICCR
Power
supply
current
Peripheral : 32 kHz
*3,*6
Peripheral : 100 kHz
3
*
Ta = + 25°C
3
*
STOP mode
Ta = + 105°C
1.3
5.5
6.5
95
mA
mA
mA
μA
3
*
Ta = + 25°C
2.8
-
*3,*6
Main
TIMER mode
Ta = + 105°C
*3,*6
Ta = + 25°C
24
-
*3,*6
Sub
TIMER mode
Ta = + 105°C
*3,*6
1.7
89
mA
μA
Ta = + 25°C
21
-
*3,*6
RTC mode
Ta = + 105°C
*3,*6
1.7
mA
*1 : Ta=+25℃,VCC= 3.3V
*2 : Ta=+105℃,VCC=5.5V
*3 : When all ports are fixed.
*4 : When setting it to 4MHz by trimming.
*5 : When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*6 : When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
79
D a t a S h e e t
Symbol
Parameter (Pin
name)
Value
Typ*1 Max*2
Conditions
Unit Remarks
Ta = + 25°C,
When RAM is off
*
Ta = + 25°C,
1.9
4.8
5.5
13
17
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
3
When RAM is on(16 KB)
*4,*3
Ta = + 25°C,
When RAM is on(32 KB)
20
*4,*3
Deep Standby
STOP mode
ICCHD
Ta = + 105°C,
When RAM is off
300
320
330
14
3
*
Ta = + 105°C,
When RAM is on(16 KB)
*4,*3
Ta = + 105°C,
When RAM is on(32 KB)
*4,*3
-
Power
supply
current
Ta = + 25°C,
When RAM is off
2.5
5.4
6.1
*3,*5
Ta = + 25°C,
When RAM is on(16 KB)
18
*4,*3,*5
Ta = + 25°C,
When RAM is on(32 KB)
21
*4,*3,*5
Deep Standby
RTC mode
ICCRD
Ta = + 105°C,
When RAM is off
*3,*5
Ta = + 105°C,
When RAM is on(16 KB)
*4,*3,*5
Ta = + 105°C,
When RAM is on(32 KB)
*4,*3,*5
305
325
335
-
*1 : VCC=3.3V
*2 : VCC=5.5V
*3 : When all ports are fixed and LVD off.
*4 : For more information about RAM retention area, see "Memory Map (2)" in "Memory Map".
*5 : When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
80
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Low-Voltage Detection Current
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Typ
Symbol
Parameter
Conditions
Unit
Remarks
(Pin name)
Min
Max
For occurrence of
reset
-
0.13
0.3
μA
Low-Voltage
detection circuit
(LVD) power
supply current
ICCLVD
(VCC)
At operation
For occurrence of
interrupt
-
0.13
0.3
μA
Flash Memory Current
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Typ
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
At ROM0
Write/Erase
-
9.9
11.8
mA *1
Flash memory
write/erase
current
ICCFLASH
(VCC)
VCC
At ROM1
Write/Erase
-
9.5
11.2
mA *1
*1 : When programming or erase in flash memory, Flash Memory Write/Erase current (ICCFLASH) is added to
the Power supply current (ICC).
In addition, When programming or erase in flash memory ROM0 and ROM1 at the same time, Flash
Memory Write/Erase current (ICCFLASH) of both ROM0 and ROM1 are added to the Power supply current
(ICC).
A/D Converter Current
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, Ta = - 40°C to + 105°C)
Value
Typ
Pin
name
Parameter
Symbol
Conditions
Unit
mA
μA
Remarks
Min
Max
At 1unit
operation
-
0.69
0.9
Power supply
current
ICCAD
(VCC)
AVCC
AVRH
At stop
-
-
-
0.6
35
1.97
3.4
At 1unit
operation
AVRH=5.5V
Reference
power supply
current
1.1
0.2
mA
ICCAVRH
(VCC)
(AVRH)
At stop
μA
D/A Converter Current
(VCC = AVCC = 2.7V to 5.5V, VSS = AV SS = 0V, Ta = - 40°C to + 105°C)
Value
Typ
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
At 1unit
operation
AVCC=3.3V
At 1unit
operation
AVCC=5.0V
250
315
380
μA
IDDA*2
(VCC)
Power supply
current*1
AVCC
380
-
475
-
580
30
μA
μA
IDSA
(VCC)
At stop
*1 : No-load
*2 : Generates the max current by the CODE about 0x200
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
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D a t a S h e e t
(2) Pin Characteristics
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, Ta = - 40°C to + 105°C)
Value
Typ
Parameter Symbol Pin name
Conditions
Unit Remarks
Min
Max
CMOS
"H" level
hysteresis
input
-
-
-
-
VCC × 0.8
-
VCC + 0.3
V
V
V
V
input pin,
voltage
(hysteresis
input)
VIHS
MD0, MD1
5V tolerant
input pin
VCC × 0.8
VSS - 0.3
VSS - 0.3
-
-
-
VSS + 5.5
VCC × 0.2
VCC × 0.2
CMOS
"L" level
input
voltage
(hysteresis
input)
hysteresis
input pin,
MD0, MD1
5V tolerant
input pin
VILS
VCC ≥ 4.5 V,
IOH = - 4 mA
4mA type
12mA type
P80/P81
VCC - 0.5
VCC - 0.5
VCC - 0.4
VSS
-
-
-
-
-
-
VCC
VCC
VCC
0.4
V
V
V
V
V
V
VCC < 4.5 V,
IOH = - 2 mA
VCC ≥ 4.5 V,
IOH = - 12 mA
VCC < 4.5 V,
IOH = - 8 mA
VCC ≥ 4.5 V,
IOH = - 18.0 mA
VCC < 4.5 V,
IOH = - 12.0 mA
VCC ≥ 4.5 V,
IOL = 4 mA
"H" level
output
VOH
voltage
4mA type
12mA type
P80/P81
VCC < 4.5 V,
IOL = 2 mA
VCC ≥ 4.5 V,
IOL = 12 mA
VCC < 4.5 V,
IOL = 8 mA
VCC ≥ 4.5 V,
IOL = 16.5 mA
VCC < 4.5 V,
IOL = 10.5 mA
"L" level
output
VOL
VSS
0.4
voltage
VSS
0.4
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MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Value
Typ
Parameter Symbol Pin name
Conditions
Unit Remarks
Min
Max
-
-
- 5
-
+ 5
μA
CEC0_0,
CEC0_1,
CEC1_0,
CEC1_1
VCC = AVCC
AVRH = VSS
AVSS = AVRL =
0.0V
=
=
Input leak
current
IIL
-
-
+1.8
μA
kΩ
Pull-up
resistance
value
VCC ≥ 4.5 V
33
-
50
-
90
RPU
Pull-up pin
VCC < 4.5 V
180
Other than
VCC,
VSS,
Input
capacitance
CIN
AVCC,
AVSS,
AVRH,
AVRL
-
-
5
15
pF
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
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4. AC Characteristics
(1) Main Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Pin
name
Parameter
Input frequency
Input clock cycle
Symbol
Conditions
Unit
MHz
MHz
ns
Remarks
Min
4
Max
48
VCC ≥ 4.5V
VCC < 4.5V
When crystal oscillator
is connected
When using external
clock
When using external
clock
When using external
clock
4
20
FCH
-
-
4
48
250
55
X0,
X1
tCYLH
-
20.83
45
Input clock pulse
width
PWH/tCYLH,
PWL/tCYLH
%
Input clock rising
time and falling
time
When using external
clock
tCF,
tCR
-
-
5
ns
FCM
FCC
-
-
-
-
-
-
60
60
MHz Master clock
Base clock
(HCLK/FCLK)
MHz
Internal operating
clock*1 frequency
FCP0
FCP1
FCP2
-
-
-
-
-
-
-
-
-
32
32
32
MHz APB0 bus clock*2
MHz APB1 bus clock*2
MHz APB2 bus clock*2
Base clock
tCYCC
-
-
16.7
-
ns
(HCLK/FCLK)
Internal operating
clock*1 cycle time
tCYCP0
tCYCP1
tCYCP2
-
-
-
-
-
-
31.25
31.25
31.25
-
-
-
ns
ns
ns
APB0 bus clock*2
APB1 bus clock*2
APB2 bus clock*2
*1 : For more information about each internal operating clock, see "CHAPTER 2-1: Clock" in "FM3 Family
PERIPHERAL MANUAL".
*2 : For about each APB bus which each peripheral is connected to, see "Block Diagram" in this data sheet.
X0
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(2) Sub Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Typ
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
When crystal
-
-
32.768
-
kHz oscillator is
connected*
Input frequency
1/ tCYLL
When using
external clock
When using
external clock
When using
external clock
-
-
32
10
45
-
-
-
100
31.25
55
kHz
X0A,
X1A
Input clock cycle
tCYLL
-
μs
Input clock pulse
width
PWH/tCYLL,
PWL/tCYLL
%
* : For more information about crystal oscillator, see "Sub crystal oscillator" in "Handling Devices".
X0A
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(3) Built-in CR Oscillation Characteristics
・ Built-in High-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Min Typ Max
Parameter
Symbol
Conditions
Unit
MHz
μs
Remarks
Ta = + 25°C,
3.6V < VCC ≤ 5.5V
Ta = 0°C to + 85°C,
3.6V < VCC ≤ 5.5V
Ta = -40°C to + 105°C,
3.6V < VCC ≤ 5.5V
Ta = + 25°C,
2.7V ≤ VCC ≤ 3.6V
Ta = - 20°C to + 85°C,
2.7V ≤ VCC ≤ 3.6V
Ta = - 20°C to + 105°C,
2.7V ≤ VCC ≤ 3.6V
Ta = -40°C to + 105°C,
2.7V ≤ VCC ≤ 3.6V
3.92
4
4
4
4
4
4
4
4
-
4.08
3.9
4.1
3.88
3.94
3.92
3.9
4.12
4.06
4.08
4.1
When trimming*1
Clock frequency
FCRH
3.88
2.8
4.12
5.2
Ta = - 40°C to + 105°C
-
When not trimming
Frequency
stability time
2
tCRWT
-
30
*
*1 : In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature
trimming.
*2 : Frequency stable time is time to stable of the frequency of the High-speed CR.
clock after the trim value is set. After setting the trim value, the period when the frequency stability
time passes can use the High-speed CR clock as a source clock.
・ Built-in Low-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Typ Max
Parameter
Symbol
Conditions
Unit
Remarks
Min
Clock frequency
FCRL
-
50
100
150
kHz
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(4-1) Operating Conditions of Main PLL (In the case of using main clock for input of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
Remarks
Min Typ Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiplication rate
FPLLI
-
FPLLO
FCLKPLL
4
5
75
-
-
-
-
-
16
MHz
37 multiplier
150
60
PLL macro oscillation clock frequency
MHz
MHz
Main PLL clock frequency*2
*1 : Time from when the PLL starts operating until the oscillation stabilizes.
*2 : For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family
PERIPHERAL MANUAL".
(4-2) Operating Conditions of Main PLL (In the case of using built-in high-speed CR for input clock
of main PLL)
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
Remarks
Min Typ Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiplication rate
FPLLI
-
FPLLO
FCLKPLL
3.8
19
72
-
4
-
-
4.2
MHz
35 multiplier
150
60
PLL macro oscillation clock frequency
MHz
MHz
Main PLL clock frequency*2
-
*1 : Time from when the PLL starts operating until the oscillation stabilizes.
*2 : For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family
PERIPHERAL MANUAL".
Note: Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the
frequency/temperature has been trimmed.
Main PLL connection
Main PLL
clock
(CLKPLL)
PLL input
clock
PLL macro
oscillation clock
Main clock (CLKMO)
K
M
divider
Main
PLL
divider
High-speed CR clock (CLKHC)
N
divider
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(5) Reset Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit Remarks
Min
Max
Reset input time
tINITX
INITX
-
500
-
ns
(6) Power-on Reset Timing
Parameter
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Pin
name
Symbol
Unit
Remarks
Min
0
Max
Power supply rising time
Tr
-
-
ms
ms
Power supply shut down time
Toff
1
VCC
Time until releasing
Power-on reset
Tprt
1.34
18.6
ms
VCC_minimum
VDH_minimum
VCC
0.2V
0.2V
0.2V
Tr
Tprt
Toff
Internal RST
RST Active
Release
start
CPU Operation
Glossary
・VCC_minimum : Minimum VCC of recommended operating conditions
・VDH_minimum : Minimum release voltage (when SVHR=00000) of Low-Voltage detection reset.
See "7. Low-Voltage Detection Characteristics"
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(7) External Bus Timing
External bus clock output characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Max
50
VCC ≥ 4.5V
VCC < 4.5V
-
-
MHz
MHz
Output frequency
tCYCLE
MCLKOUT*
32
* : The external bus clock (MCLKOUT) is a divided clock of HCLK.
For more information about setting of clock divider, see "CHAPTER 12: External Bus Interface" in "FM3
Family PERIPHERAL MANUAL".
When external bus clock is not output, this characteristics does not give any effect on external bus operation.
MCLKOUT
External bus signal input/output characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol Conditions
Value
Unit
Remarks
VIH
0.8 × VCC
0.2 × VCC
0.8 × VCC
0.2 × VCC
V
V
V
V
Signal input characteristics
VIL
-
VOH
Signal output characteristics
VOL
VIH
VIL
VIH
VIL
Input signal
VOH
VOL
VOH
VOL
Output signal
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D a t a S h e e t
Separate Bus Access Asynchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
tOEW
Pin name
Conditions
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
Max
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
MOEX
MOEX
MCLK×n-3
-
Min pulse width
MCSX ↓ → Address
output delay time
MOEX ↑ →
Address hold time
MCSX ↓ →
MOEX ↓ delay time
MOEX ↑ →
MCSX ↑ time
MCSX[7:0],
MAD[24:0]
MOEX,
-9
-12
+9
+12
tCSL – AV
tOEH - AX
tCSL - OEL
tOEH - CSH
tCSL - RDQML
tDS - OE
MCLK×m+9
MCLK×m+12
MCLK×m-9 MCLK×m+9
0
MAD[24:0]
VCC < 4.5V MCLK×m-12 MCLK×m+12
MOEX,
MCSX[7:0]
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
MCLK×m+9
MCLK×m+12
MCLK×m-9 MCLK×m+9
0
MCSX ↓ →
MCSX,
MDQM[1:0]
MOEX,
MADATA[15:0]
MOEX,
MDQM ↓ delay time
Data set up →
MOEX ↑ time
MOEX ↑ →
Data hold time
MWEX
Min pulse width
MWEX ↑ → Address
output delay time
MCSX ↓ →
MWEX ↓ delay time
MWEX ↑ →
MCSX ↑ delay time
MCSX ↓→
MDQM ↓ delay time
MCSX ↓→
Data output time
MWEX ↑ →
VCC < 4.5V MCLK×m-12 MCLK×m+12
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
20
38
-
-
tDH - OE
0
-
-
MADATA[15:0]
tWEW
MWEX
MCLK×n-3
MWEX,
MAD[24:0]
MCLK×m+9
MCLK×m+12
MCLK×n+9
tWEH - AX
tCSL - WEL
tWEH - CSH
tCSL-WDQML
tCSL-DV
0
MCLK×n-9
MWEX,
MCSX[7:0]
MCLK×n-12 MCLK×n+12
MCLK×m+9
MCLK×m+12
0
MCSX,
MDQM[1:0]
MCSX,
MADATA[15:0]
MWEX,
MADATA[15:0]
MCLK×n-9
MCLK×n+9
MCLK×n-12 MCLK×n+12
MCLK-9
MCLK+9
MCLK-12
MCLK+12
tWEH - DX
0
MCLK×m+12 ns
Data hold time
Note: When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16).
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MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
tCYCLE
MCLK
tOEH-CSH
tWEH-CSH
tWEH-AX
MCSX[7:0]
MAD[24:0]
MOEX
tCSL-AV
tOEH-AX
tCSL-AV
Address
Address
tCSL-OEL
tOEW
tCSL-WDQML
tCSL-RDQML
MDQM[1:0]
tCSL-WEL
tWEW
MWEX
tDS-OE
tDH-OE
tWEH-DX
Invalid
RD
WD
MADATA[15:0]
tCSL-DV
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D a t a S h e e t
Separate Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
tAV
Pin name
Conditions
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
Max
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
MCLK,
MAD[24:0]
Address delay time
1
12
9
12
9
12
9
12
9
12
tCSL
1
1
1
1
MCLK,
MCSX[7:0]
MCSX delay time
MOEX delay time
tCSH
tREL
MCLK,
MOEX
tREH
tDS
19
37
Data set up →
MCLK ↑ time
MCLK ↑ →
MCLK,
MADATA[15:0]
MCLK,
-
tDH
0
-
Data hold time
MADATA[15:0]
9
12
9
12
9
12
9
12
tWEL
tWEH
tDQML
tDQMH
tODS
tOD
1
MCLK,
MWEX
MWEX delay time
1
1
MDQM[1:0]
delay time
MCLK,
MDQM[1:0]
1
MCLK+1
1
MCLK+18
MCLK+24
18
MCLK ↑ →
Data output time
MCLK ↑ →
MCLK,
MADATA[15:0]
MCLK,
Data hold time
MADATA[15:0]
24
Note: When the external load capacitance CL = 30 pF.
tCYCLE
MCLK
tCSL
tCSH
MCSX[7:0]
tAV
tAV
Address
Address
MAD[24:0]
MOEX
tREL
tREH
tDQML
tDQMH
tDQML
tDQMH
tWEH
tOD
MDQM[1:0]
tWEL
MWEX
tDS
tDH
RD
Invalid
WD
MADATA[15:0]
tODS
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MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Multiplexed Bus Access Asynchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
tALE-CHMADV
tCHMADH
Pin name
Conditions
Unit
ns
Min
Max
+10
+20
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
Multiplexed
address delay time
Multiplexed
0
MALE,
MADATA[15:0]
MCLK×n+0 MCLK×n+12
MCLK×n+0 MCLK×n+20
ns
address hold time
Note: When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16).
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
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Multiplexed Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
tCHAL
Pin name
Conditions
Unit Remarks
Min
Max
9
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
ns
ns
ns
ns
1
12
9
12
MCLK,
ALE
MALE delay time
tCHAH
1
1
MCLK ↑ →
Multiplexed
Address delay time
MCLK ↑ →
Multiplexed
Data output time
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
tCHMADV
tOD
ns
ns
MCLK,
MADATA[15:0]
tCHMADX
1
tOD
Note: When the external load capacitance CL = 30 pF.
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
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D a t a S h e e t
NAND Flash Memory Mode
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
tNREW
Pin name
Conditions
Unit
ns
Min
Max
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
MNREX
Min pulse width
Data setup →
MNREX↑time
MNREX↑→
Data hold time
MNREX
MCLK×n-3
-
MNREX,
MADATA[15:0]
MNREX,
20
38
-
-
tDS – NRE
ns
tDH – NRE
0
-
ns
MADATA[15:0]
VCC ≥ 4.5V MCLK×m-9
MCLK×m+9
MNALE↑→
MNWEX delay time
MNALE↓→
MNWEX delay time
MNCLE↑→
MNWEX delay time
MNWEX↑→
MNCLE delay time
MNWEX
Min pulse width
MNWEX↓→
Data output time
MNALE,
MNWEX
MNALE,
MNWEX
MNCLE,
MNWEX
MNCLE,
MNWEX
tALEH - NWEL
tALEL - NWEL
tCLEH - NWEL
tNWEH - CLEL
tNWEW
ns
VCC < 4.5V MCLK×m-12 MCLK×m+12
VCC ≥ 4.5V MCLK×m-9
MCLK×m+9
VCC < 4.5V MCLK×m-12 MCLK×m+12
VCC ≥ 4.5V MCLK×m-9
MCLK×m+9
VCC < 4.5V MCLK×m-12 MCLK×m+12
ns
ns
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
MCLK×m+9
MCLK×m+12
0
ns
MNWEX
MCLK×n-3
-
ns
MNWEX,
MADATA[15:0]
MNWEX,
- 9
-12
+ 9
+12
MCLK×m+11
MCLK×m+12
tNWEL – DV
tNWEH – DX
ns
MNWEX↑→
Data hold time
0
ns
MADATA[15:0]
Note: When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16).
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D a t a S h e e t
NAND Flash Memory Read
MCLK
MNREX
MADATA[15:0]
Read
NAND Flash Memory Address Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Write
96
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
NAND Flash Memory Command Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Write
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D a t a S h e e t
External Ready Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol Pin name Conditions
Unit Remarks
Min
Max
MCLK ↑
MRDY input
setup time
VCC ≥ 4.5V
19
MCLK,
MRDY
tRDYI
-
ns
VCC < 4.5V
37
When RDY is input
···
MCLK
Over 2cycles
Original
MOEX
MWEX
tRDYI
MRDY
When RDY is released
·· · ·· ·
MCLK
2 cycles
Extended
MOEX
MWEX
tRDYI
0.5×VCC
MRDY
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D a t a S h e e t
(8) Base Timer Input Timing
・ Timer input timing
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit Remarks
Min
Max
TIOAn/TIOBn
(when using as
ECK, TIN)
tTIWH
tTIWL
,
Input pulse width
-
2tCYCP
-
ns
tTIWH
tTIWL
ECK
TIN
VIHS
VIHS
VILS
VILS
・ Trigger input timing
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol Pin name Conditions
Unit Remarks
Min
Max
TIOAn/TIOBn
(when using as
TGIN)
tTRGH
tTRGL
,
Input pulse width
-
2tCYCP
-
ns
tTRGH
tTRGL
VIHS
VIHS
TGIN
VILS
VILS
Note: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see "Block Diagram" in this data
sheet.
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(9) CSIO/UART Timing
・ CSIO (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
VCC < 4.5V
Pin
VCC ≥ 4.5V
Parameter
Serial clock cycle time
SCK ↓ → SOT delay time
Symbol
Conditions
Unit
ns
name
SCKx
SCKx,
SOTx
SCKx,
SINx
Min
Max
Min
Max
tSCYC
4tCYCP
-
4tCYCP
-
tSLOVI
- 30
50
0
+ 30
- 20
30
0
+ 20
ns
Master mode
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tIVSHI
tSHIXI
tSLSH
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
SCKx,
SINx
2tCYCP
10
-
2tCYCP
10
-
SCKx
SCKx
-
-
tCYCP
10
+
tCYCP
10
+
tSHSL
-
-
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
33
-
Slave mode
10
20
10
20
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
・The above characteristics apply to CLK synchronous mode.
・tCYCP indicates the APB bus clock cycle time.
・About the APB bus number which Multi-function Serial is connected to, see "Block Diagram"
in this data sheet.
・These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
・When the external load capacitance CL = 30 pF.
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MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
SOT
SIN
VOH
VOL
tIVSHI
VIH
VIL
tSHIXI
VIH
VIL
Master mode
tSLSH
tSHSL
VIH
VIH
tR
VIH
SCK
VIL
VIL
F
t
tSLOVE
VOH
VOL
SOT
SIN
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
Slave mode
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
101
D a t a S h e e t
・ CSIO (SPI = 0, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
VCC < 4.5V
Pin
VCC ≥ 4.5V
Parameter
Serial clock cycle time
SCK ↑ → SOT delay time
Symbol
Conditions
Unit
ns
name
SCKx
SCKx,
SOTx
SCKx,
SINx
Min
Max
Min
Max
tSCYC
4tCYCP
-
4tCYCP
-
tSHOVI
- 30
50
0
+ 30
- 20
30
0
+ 20
ns
Master mode
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
tIVSLI
tSLIXI
tSLSH
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
SCKx,
SINx
2tCYCP
10
-
2tCYCP
10
-
SCKx
SCKx
-
-
tCYCP
10
+
tCYCP
10
+
tSHSL
-
-
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
33
-
Slave mode
10
20
10
20
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
・The above characteristics apply to CLK synchronous mode.
・tCYCP indicates the APB bus clock cycle time.
・About the APB bus number which Multi-function Serial is connected to, see "Block Diagram"
in this data sheet.
・These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
・When the external load capacitance CL = 30 pF.
102
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
tSCYC
VOH
VOH
SCK
VOL
tSHOVI
SOT
SIN
VOH
VOL
tIVSLI
VIH
VIL
tSLIXI
VIH
VIL
Master mode
tSHSL
tSLSH
VIH
VIH
tF
SCK
VIL
VIL
tR
VIL
tSHOVE
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
103
D a t a S h e e t
・ CSIO (SPI = 1, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
VCC < 4.5V
Pin
VCC ≥ 4.5V
Parameter
Serial clock cycle time
SCK ↑ → SOT delay time
Symbol
Conditions
Unit
ns
name
SCKx
SCKx,
SOTx
SCKx,
SINx Master mode
SCKx,
SINx
Min
Max
Min
Max
tSCYC
4tCYCP
-
4tCYCP
-
tSHOVI
- 30
50
0
+ 30
- 20
30
0
+ 20
ns
SIN → SCK ↓ setup time
SCK ↓→ SIN hold time
SOT → SCK ↓ delay time
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓→ SIN hold time
tIVSLI
tSLIXI
tSOVLI
tSLSH
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
SCKx,
SOTx
2tCYCP
30
-
2tCYCP
30
-
-
-
2tCYCP
10
-
2tCYCP
10
-
SCKx
-
-
tCYCP
10
+
tCYCP
10
+
tSHSL
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
-
-
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
33
-
Slave mode
10
20
10
20
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
・The above characteristics apply to CLK synchronous mode.
・tCYCP indicates the APB bus clock cycle time.
・About the APB bus number which Multi-function Serial is connected to, see "Block Diagram"
in this data sheet.
・These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
・When the external load capacitance CL = 30 pF.
104
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
tSCYC
VOH
VOL
VOL
SCK
tSHOVI
tSOVLI
VOH
VOL
VOH
VOL
SOT
SIN
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
Master mode
tSLSH
tSHSL
SCK
VIH
tF
VIH
VIL
VIH
VIL
tSHOVE
tR
*
VOH
VOL
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
* : Changes when writing to TDR register
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
105
D a t a S h e e t
・ CSIO (SPI = 1, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
VCC < 4.5V
Pin
name
SCKx
VCC ≥ 4.5V
Parameter
Symbol
Conditions
Unit
Min
Max
Min
Max
Serial clock cycle time
tSCYC
4tCYCP
-
4tCYCP
-
ns
SCKx,
SOTx
SCK ↓ → SOT delay time
tSLOVI
- 30
+ 30
- 20
+ 20
ns
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
SOT → SCK ↑ delay time
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tIVSHI
tSHIXI
tSOVHI
tSLSH
50
0
-
-
30
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
Master mode
2tCYCP
30
2tCYCP
10
tCYCP
10
-
2tCYCP
30
2tCYCP
10
tCYCP
10
-
-
-
-
-
SCKx
SCKx
-
-
+
+
tSHSL
-
-
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
33
-
Slave mode
10
20
10
20
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
・The above characteristics apply to CLK synchronous mode.
・tCYCP indicates the APB bus clock cycle time.
・About the APB bus number which Multi-function Serial is connected to, see "Block Diagram"
in this data sheet.
・These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
・When the external load capacitance CL = 30 pF.
106
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
tSCYC
VOL
VOH
VOH
SCK
tSOVHI
tSLOVI
VOH
VOL
VOH
VOL
SOT
SIN
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
Master mode
tSLSH
tSHSL
tR
V
SCK
V
V
IH
V
IH
IH
V
V
IL
IL
IL
tF
tSLOVE
VOH
VOL
VOH
VOL
SOT
SIN
tSHIXE
tIVSHE
V
IL
V
IL
IH
V
IH
V
Slave mode
・ UART external clock input (EXT = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol Conditions
Unit Remarks
Min
Max
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK falling time
tSLSH
tSHSL
tF
tCYCP + 10
tCYCP + 10
-
-
5
5
ns
ns
ns
ns
CL = 30pF
-
-
SCK rising time
tR
tF
tR
t
t
SLSH
SHSL
SCK
V
V
V
IH
IH
IH
VIL
VIL
V
IL
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
107
D a t a S h e e t
(10) External Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Min
Parameter Symbol Pin name Conditions
Unit
Remarks
Max
A/D converter
trigger input
ns Free-run timer input
clock
ADTG
1
-
2tCYCP
*
-
FRCKx
ICxx
DTTIxX
Input capture
ns Waveform generator
tINH,
tINL
Input pulse width
1
-
*2
*3
2tCYCP
*
-
-
-
2tCYCP + 100*1
500
ns
ns
External interrupt,
NMI
INTxx
Deep standby wake
up
WKUPx
*4
500
-
ns
*1 : tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected
to, see "Block Diagram" in this data sheet.
*2 : When in RUN mode, in SLEEP mode.
*3 : When in STOP mode, in TIMER mode.
*4 : When in Deep standby RTC mode, in Deep standby STOP mode.
108
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
(11) Quadrature Position/Revolution Counter timing
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Conditions
Unit
Min
Max
AIN pin "H" width
AIN pin "L" width
BIN pin "H" width
BIN pin "L" width
Time from AIN pin "H"
level to BIN rise
Time from BIN pin "H"
level to AIN fall
Time from AIN pin "L"
level to BIN fall
Time from BIN pin "L"
level to AIN rise
Time from BIN pin "H"
level to AIN rise
Time from AIN pin "H"
level to BIN fall
Time from BIN pin "L"
level to AIN fall
tAHL
tALL
tBHL
tBLL
-
-
-
-
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
QCR:CGSC="0"
QCR:CGSC="0"
tAUBU
tBUAD
tADBD
tBDAU
tBUAU
tAUBD
tBDAD
tADBU
2tCYCP
*
-
ns
Time from AIN pin "L"
level to BIN rise
ZIN pin "H" width
ZIN pin "L" width
Time from determined ZIN
level to AIN/BIN rise and
fall
Time from AIN/BIN rise
and fall time to determined
ZIN level
tZHL
tZLL
tZABE
QCR:CGSC="1"
QCR:CGSC="1"
tABEZ
* : tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Quadrature Position/Revolution Counter is connected to, see "Block
Diagram" in this data sheet.
tALL
tAHL
AIN
BIN
tADBD
tAUBU
tBUAD
tBDAU
tBHL
tBLL
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
109
D a t a S h e e t
tBLL
tBHL
BIN
AIN
tBDAD
tBUAU
tAUBD
tADBU
tAHL
tALL
ZIN
ZIN
AIN/BIN
110
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
(12) I2C Timing
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Standard-mode Fast-mode
Parameter
Symbol Conditions
Unit Remarks
Min
Max
Min Max
SCL clock frequency
(Repeated) START condition
hold time
FSCL
0
100
0
400 kHz
tHDSTA
4.0
-
0.6
-
μs
SDA ↓ → SCL ↓
SCLclock "L" width
SCLclock "H" width
(Repeated) START condition
setup time
tLOW
tHIGH
4.7
4.0
-
-
1.3
0.6
-
-
μs
μs
tSUSTA
4.7
-
0.6
-
μs
SCL ↑ → SDA ↓
Data hold time
CL = 30 pF,
R = (Vp/IOL)*1
tHDDAT
0
3.45*2
0
0.9*3 μs
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
tSUDAT
tSUSTO
250
4.0
-
-
100
0.6
-
-
ns
μs
Bus free time between
"STOP condition" and
"START condition"
Noise filter
tBUF
4.7
-
-
1.3
-
-
μs
4
4
tSP
-
2 tCYCP
*
2 tCYCP
*
ns
*1 : R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current.
*2 : The maximum tHDDAT must satisfy that it does not extend at least "L" period (tLOW) of device's SCL signal.
*3 : Fast-mode I2C bus device can be used on Standard-mode I2C bus system as long as the device
satisfies the requirement of "tSUDAT ≥ 250 ns".
*4 : tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see "Block Diagram" in this data sheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
111
D a t a S h e e t
(13) ETM Timing
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Min Max
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
2
10
TRACECLK,
TRACED[3:0]
Data hold
tETMH
ns
2
15
-
40 MHz
20 MHz
TRACECLK
frequency
1/ tTRACE
-
TRACECLK
25
50
-
-
ns
ns
TRACECLK
clock cycle
tTRACE
Note: When the external load capacitance CL = 30 pF.
HCLK
TRACECLK
TRACED[3:0]
112
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
(14) JTAG Timing
Parameter
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Symbol Pin name Conditions
Unit
ns
Remarks
Min
Max
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
TMS, TDI setup
time
TCK,
TMS, TDI
tJTAGS
15
-
TCK,
TMS, TDI
TMS, TDI hold time tJTAGH
TDO delay time tJTAGD
15
-
ns
-
-
25
45
TCK,
TDO
ns
VCC < 4.5V
Note: When the external load capacitance CL = 30 pF.
TCK
TMS/TDI
TDO
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
113
D a t a S h e e t
5. 12-bit A/D Converter
・Electrical characteristics for the A/D converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, Ta = - 40°C to + 105°C)
Value
Typ
-
± 1.5
± 2.2
± 6
Pin
name
Parameter
Symbol
Unit
Remarks
Min
Max
12
± 4.5
± 2.5
± 15
Resolution
-
-
-
-
-
-
-
-
-
-
bit
Integral Nonlinearity
Differential Nonlinearity
Zero transition voltage
Full-scale transition
voltage
LSB
LSB
mV
AVRH = 2.7V
to 5.5V
VZT
ANxx
VFST
-
ANxx
-
1.0*1
0.3
50
AVRH ± 5 AVRH ± 15 mV
Conversion time
-
-
-
-
-
-
-
-
-
μs
μs
ns
μs
Sampling time*2
Ts
10
Compare clock cycle*3
State transition time to
operation permission
Tcck
Tstt
1000
1.0
-
Analog input capacity
Analog input resistor
CAIN
RAIN
-
-
-
-
-
-
9.5
pF
1.62
2.35
4
AVCC ≥ 4.5V
AVCC < 4.5V
kΩ
Interchannel disparity
Analog port input current
Analog input voltage
-
-
-
-
-
-
-
-
-
-
-
-
-
LSB
μA
V
V
V
ANxx
ANxx
AVRH
AVRL
5
AVRL
2.7
AVSS
AVRH
AVCC
AVSS
Reference voltage
*1 : The conversion time is the value of sampling time (Ts) + compare time (Tc).
The condition of the minimum conversion time is when the value of sampling time: 300ns, the value of
compare time:700ns (AVCC ≥ 4.5V).
Ensure that it satisfies the value of the sampling time (Ts) and compare clock cycle (Tcck).
For setting of the sampling time and compare clock cycle, see "CHAPTER 1-1: A/D Converter" in "FM3
Family PERIPHERAL MANUAL Analog Macro Part".
The register setting of the A/D Converter are reflected in the operation according to the APB bus clock
timing.
The sampling clock and compare clock is generated from the Base clock (HCLK).
About the APB bus number which the A/D Converter is connected to, see "Block Diagram" in this data
sheet.
*2 : A necessary sampling time changes by external impedance.
Ensure that it sets the sampling time to satisfy (Equation 1).
*3 : The compare time (Tc) is the value of (Equation 2).
114
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
Comparator
ANxx
Analog input pin
Rext
RAIN
Analog
signal source
CAIN
(Equation 1) Ts ≥ ( RAIN + Rext ) × CAIN × 9
Ts : Sampling time
RAIN : input resistor of A/D = 1.62 kΩ ch.0 to ch.7
input resistor of A/D = 1.58 kΩ ch.8 to ch.15
at 4.5V < AVCC < 5.5V
at 4.5V < AVCC < 5.5V
input resistor of A/D = 1.56 kΩ ch.16 to ch.23 at 4.5V < AVCC < 5.5V
input resistor of A/D = 2.35 kΩ ch.0 to ch.7
input resistor of A/D = 2.3 kΩ ch.8 to ch.15
at 2.7V < AVCC < 4.5V
at 2.7V < AVCC < 4.5V
input resistor of A/D = 2.25 kΩ ch.16 to ch.23 at 2.7V < AVCC < 4.5V
CAIN : input capacity of A/D = 9.5pF at 2.7V < AVCC < 5.5V
Rext : Output impedance of external circuit
(Equation 2) Tc = Tcck × 14
Tc : Compare time
Tcck : Compare clock cycle
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
115
D a t a S h e e t
・Definition of 12-bit A/D Converter Terms
・Resolution
・Integral Nonlinearity
: Analog variation that is recognized by an A/D converter.
: Deviation of the line between the zero-transition point
(0b000000000000 ←→ 0b000000000001) and the full-scale transition point
(0b111111111110 ←→ 0b111111111111) from the actual conversion
characteristics.
・Differential Nonlinearity : Deviation from the ideal value of the input voltage that is required to change
the output code by 1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
Actual conversion
characteristics
characteristics
0xFFE
0xFFD
0x(N+1)
0xN
{1 LSB(N-1) + VZT}
VFST
Ideal characteristics
(Actually-
measured
value)
VNT
0x004
(Actually-measured
value)
V(N+1)T
(Actually-measured
value)
0x(N-1)
0x(N-2)
0x003
0x002
Actual conversion
characteristics
VNT
(Actually-measured
value)
Ideal characteristics
0x001
(Actually-measured value)
Analog input
VZT
Actual conversion characteristics
AVRL
AVRH
AVRL
AVRH
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
[LSB]
V(N + 1) T - VNT
- 1 [LSB]
1LSB
VFST – VZT
1LSB =
4094
N
VZT
: A/D converter digital output value.
: Voltage at which the digital output changes from 0x000 to 0x001.
VFST : Voltage at which the digital output changes from 0xFFE to 0xFFF.
VNT : Voltage at which the digital output changes from 0x(N − 1) to 0xN.
116
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
6. 10-bit D/A Converter
Electrical Characteristics for the D/A Converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, Ta = - 40°C to + 105°C)
Value
Typ Max
Parameter
Symbol Pin name
Unit
Remarks
Min
-
0.47
2.37
- 4.0
Resolution
-
-
10
0.69
3.43
bit
μs
μs
tc20
tc100
INL
0.58
2.90
-
Load 20 pF
Load 100 pF
Conversion time
Integral Nonlinearity*1
Differential
+ 4.0 LSB
DNL
DAx
- 0.9
-
+ 0.9 LSB
Nonlinearity*1,*2
-
- 20.0
3.10
2.0
-
-
10.0
mV Code is 0x000
Output Voltage offset
VOFF
+ 5.4 mV Code is 0x3FF
4.50
-
3.80
-
-
kΩ D/A operation
MΩ D/A stop
ns
Analog output
impedance
Output undefined period
RO
tR
-
70
*1 : No-load
*2 : Generates the max current by the CODE about 0x200
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
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7. Low-Voltage Detection Characteristics
(1) Low-Voltage Detection Reset
(Ta = - 40°C to + 105°C)
Value
Unit
Remarks
Parameter
Symbol
Conditions
Min
2.25
2.30
2.39
Typ
2.45
2.50
2.60
Max
2.65
2.70
2.81
When voltage
drops
When voltage rises
When voltage
drops
When voltage rises
When voltage
drops
When voltage rises
When voltage
drops
When voltage rises
When voltage
drops
When voltage rises
When voltage
drops
When voltage rises
When voltage
drops
When voltage rises
When voltage
drops
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SVHR*1 = 00000
SVHR*1 = 00001
SVHR*1 = 00010
SVHR*1 = 00011
SVHR*1 = 00100
SVHR*1 = 00101
SVHR*1 = 00110
SVHR*1 = 00111
SVHR*1 = 01000
SVHR*1 = 01001
SVHR*1 = 01010
Same as SVHR = 0000 value
2.48 2.70 2.92
Same as SVHR = 0000 value
2.58 2.80 3.02
Same as SVHR = 0000 value
2.76 3.00 3.24
Same as SVHR = 0000 value
2.94 3.20 3.46
Same as SVHR = 0000 value
3.31 3.60 3.89
Same as SVHR = 0000 value
3.40 3.70 4.00
Same as SVHR = 0000 value
3.68 4.00 4.32
Same as SVHR = 0000 value
3.77 4.10 4.43
Same as SVHR = 0000 value
3.86 4.20 4.54
When voltage rises
When voltage
drops
When voltage rises
When voltage
drops
When voltage rises
When voltage
drops
Released voltage
LVD
stabilization wait
time
LVD detection
delay time
Same as SVHR = 0000 value
6432 ×
When voltage rises
TLVDW
-
-
-
-
μs
*2
tCYCP
TLVDDL
-
-
200
μs
*1 : The SVHR bit of Low-voltage Detection Voltage Control Register (LVD_CTL) is initialized to “0000” by
low-voltage detection reset.
*2 : tCYCP indicates the APB2 bus clock cycle time.
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(2) Interrupt of Low-Voltage Detection
(Ta = - 40°C to + 105°C)
Value
Typ
2.80
2.90
3.00
3.10
3.20
3.30
3.60
3.70
3.70
3.80
4.00
4.10
4.10
4.20
4.20
4.30
Parameter
Symbol Conditions
Unit
Remarks
Min
2.58
2.67
2.76
2.85
2.94
3.04
3.31
3.40
3.40
3.50
3.68
3.77
3.77
3.86
3.86
3.96
Max
3.02
3.13
3.24
3.35
3.46
3.56
3.89
4.00
4.00
4.10
4.32
4.43
4.43
4.54
4.54
4.64
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
SVHI = 00011
SVHI = 00100
SVHI = 00101
SVHI = 00110
SVHI = 00111
SVHI = 01000
SVHI = 01001
SVHI = 01010
LVD stabilization
wait time
6432 ×
tCYCP
TLVDW
-
-
-
-
-
-
μs
μs
*
LVD detection
delay time
TLVDDL
200
* : tCYCP indicates the APB2 bus clock cycle time.
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
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8. Flash Memory Write/Erase Characteristics
(1) Write / Erase time
(VCC = 2.7V to 5.5V, Ta = - 40°C to + 105°C)
Value
Parameter
Unit
Remarks
Typ
Max
Large Sector
Small Sector
1.1
2.7
Sector erase
time
Includes write time prior to internal
erase
s
0.3
20
0.9
Not including system-level overhead
time
Includes write time prior to internal
erase
Half word (16-bit) write time
Chip erase time
317
μs
31
79
s
* : The typical value is immediately after shipment, the maximam value is guarantee value under 10,000 cycle
of erase/write.
(2)Write cycles and data hold time
Erase/write cycles (cycle) Data hold time (year)
Remarks
1,000
10,000
20*
10*
* : At average + 85C
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D a t a S h e e t
9. Return Time from Low-Power Consumption Mode
(1) Return Factor: Interrupt/WKUP
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the
return factor to starting the program operation.
・Return Count Time
(VCC = 2.7V to 5.5V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
Remarks
Typ
Max*
SLEEP mode
tCYCC
ns
High-speed CR TIMER mode,
Main TIMER mode,
43
83
μs
PLL TIMER mode
Low-speed CR TIMER mode
Sub TIMER mode
310
534
620
724
μs
μs
Ticnt
RTC mode,
STOP mode
278
479
μs
298
288
543
523
μs
μs
When RAM is off
When RAM is on
Deep Standby RTC mode,
Deep Standby STOP mode
* : The maximum value depends on the accuracy of built-in CR.
・Operation example of return from Low-Power consumption mode (by external interrupt*)
Ext.INT
Interrupt factor
Active
accept
Ticnt
Interrupt factor
clear by CPU
CPU
Operation
Start
* : External interrupt is set to detecting fall edge.
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
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D a t a S h e e t
・Operation example of return from Low-Power consumption mode (by internal resource interrupt*)
Internal
Resource INT
Interrupt factor
Active
accept
Ticnt
Interrupt factor
clear by CPU
CPU
Operation
Start
* : Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
・The return factor is different in each Low-Power consumption modes.
See "CHAPTER 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3
Family PERIPHERAL MANUAL about the return factor from Low-Power consumption mode.
・When interrupt recoveries, the operation mode that CPU recoveries depends on the state before
the Low-Power consumption mode transition. See "CHAPTER 6: Low Power Consumption
Mode" in "FM3 Family PERIPHERAL MANUAL".
122
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D a t a S h e e t
(2) Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to
starting the program operation.
・Return Count Time
(VCC = 2.7V to 5.5V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
Remarks
Typ
Max*
SLEEP mode
149
264
μs
High-speed CR TIMER mode,
Main TIMER mode,
149
264
μs
PLL TIMER mode
Low-speed CR TIMER mode
Sub TIMER mode
318
308
248
298
288
603
583
443
543
523
μs
μs
μs
μs
μs
Trcnt
RTC/STOP mode
When RAM is off
When RAM is on
Deep Standby RTC mode,
Deep Standby STOP mode
* : The maximum value depends on the accuracy of built-in CR.
・Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
123
D a t a S h e e t
・Operation example of return from low power consumption mode (by internal resource reset*)
Internal
Resource RST
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
* : Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
・The return factor is different in each Low-Power consumption modes.
See "CHAPTER 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3
Family PERIPHERAL MANUAL.
・When interrupt recoveries, the operation mode that CPU recoveries depends on the state before
the Low-Power consumption mode transition. See "CHAPTER 6: Low Power Consumption
Mode" in "FM3 Family PERIPHERAL MANUAL".
・The time during the power-on reset/low-voltage detection reset is excluded. See "(6) Power-on
Reset Timing in 4. AC Characteristics in ■Electrical Characteristics" for the detail on the time
during the power-on reset/low -voltage detection reset.
・When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main
clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or
the main PLL clock stabilization wait time.
・The internal resource reset means the watchdog reset and the CSV reset.
124
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t ( P r e l i m i n a r y )
Ordering Information
On-chip
Flash
memory
On-chip
SRAM
Part number
Package
Packing
Main: 1 Mbyte
Work: 64 Kbyte
MB9BF128SAPMC-GE1
MB9BF129SAPMC-GE1
MB9BF128TAPMC-GE1
MB9BF129TAPMC-GE1
MB9BF128TABGL-GE1
MB9BF129TABGL-GE1
160 Kbyte
192 Kbyte
160 Kbyte
192 Kbyte
160 Kbyte
192 Kbyte
Plastic・LQFP,
144-pin (0.5 mm pitch)
(FPT-144P-M08)
Main: 1.5 Mbyte
Work: 64 Kbyte
Main: 1 Mbyte
Work: 64 Kbyte
Plastic・LQFP,
176-pin (0.5 mm pitch)
(FPT-176P-M07)
Tray
Main: 1.5 Mbyte
Work: 64 Kbyte
Main: 1 Mbyte
Work: 64 Kbyte
Plastic・FBGA,
192-pin (0.8 mm pitch)
(BGA-192P-M06)
Main: 1.5 Mbyte
Work: 64 Kbyte
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
125
D a t a S h e e t
Package Dimensions
176-pin plastic LQFP
Lead pitch
0.50 mm
24.0 × 24.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Plastic mold
1.70 mm MAX
P-LQFP-0176-2424-0.50
Code
(Reference)
(FPT-176P-M07)
176-pin plastic LQFP
(FPT-176P-M07)
Note 1) * : Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness
Note 3) Pins width do not include tie bar cutting remainder.
26.00±0.20(1.024±.008)SQ
*24.00±0.10(.945±.004)SQ
0.145±0.055
(.006±.002)
132
89
133
88
0.08(.003)
Details of "A" part
1.50+–00.210
(Mounting height)
.059+–..000084
0.10±0.10
(.004±.004)
(Stand off)
0°~8°
INDEX
0.25(.010)
0.50±0.20
176
45
(.020±.008)
0.60±0.15
"A"
(.024±.006)
1
44
LEAD No.
0.50(.020)
0.22±0.05
(.009±.002)
M
0.08(.003)
Dimensions in mm (inches).
C
Note: The values in parentheses are reference values.
2004-2010 FUJITSU SEMICONDUCTOR LIMITED F176013S-c-1-3
126
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
D a t a S h e e t
144-pin plastic LQFP
Lead pitch
0.50 mm
20.0 × 20.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm MAX
1.20 g
Code
(Reference)
(FPT-144P-M08)
P-LFQFP144-20×20-0.50
144-pin plastic LQFP
(FPT-144P-M08)
Note 1) *:Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
22.00±0.20(.866±.008)SQ
20.00±0.10(.787±.004)SQ
*
0.145±0.055
(.006±.002)
108
73
109
72
0.08(.003)
Details of "A" part
1.50+–00.210
(Mounting height)
.059–+..000048
0.10±0.10
(.004±.004)
(Stand off)
0°~8°
INDEX
144
37
0.25(.010)
0.50±0.20
(.020±.008)
"A"
0.60±0.15
(.024±.006)
1
36
LEAD No.
0.50(.020)
0.22±0.05
(.009±.002)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F144019S-c-4-8
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
127
D a t a S h e e t
192-ball plastic FBGA
Ball pitch
0.80 mm
12.00 mm × 12.00 mm
Ball
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.45 mm Max.
0.34 g
(BGA-192P-M06)
192-ball plastic FBGA
(BGA-192P-M06)
10.40(.409)REF
12.00±0.10(.472±.004)
0.20(.008) S
B
B
0.80(.031)
REF
14
13
12
11
10
9
0.80(.031)
REF
A
8
7
6
12.00±0.10
(.472±.004)
10.40(.409)
REF
5
4
3
2
1
P
N M L
K
J
H G F
E
D C B A
INDEX
(INDEX AREA)
0.20(.008) S
A
192-ø0.45±0.10
(192-ø.018±.004)
M
ø0.08(.003)
S A B
1.25±0.20
(.049±.008)
(Seated height)
0.35±0.10
(.014±.004)
(Stand off)
S
0.10(.004) S
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2008-2010 FUJITSU SEMICONDUCTOR LIMITED B192006S-c-1-3
128
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D a t a S h e e t
Major Changes
Page
Section
Change Results
Revision 0.1
-
-
Initial release
Revision 0.2
-
-
-
Company name and layout design change
Revision 1.0
-
Preliminary → Full Production
FEATURES
External Bus Interface
Added the descriptions as follows
Maximum area size : Up to 256 Mbytes
2
FEATURES
A/D Converter
FEATURES
Multi-function Timer
PRODUCT LINEUP
Function
3
5
7
Corrected conversion time
Corrected the channel count of "A/D activation compare"
Added the footnote
HANDLING DEVICES
Power supply pins
BLOCK DIAGRAM
MEMORY MAP
63
65
66
Added the description
Corrected the figure
Corrected the Address of “External Device Area”
Memory Map(1)
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
2. Recommended Operating Conditions
76
78
Added the Item of “Input Voltage”
Added the footnote
Corrected the Condition
3.DC Characteristics
(1) Current Rating
Corrected the Value
Corrected the Remarks
79 - 81
Added the footnote
83
88
(2) Pin Characteristics
Added the Item of “Inputleak current”
Revised the values of “Time until releasing Power-on reset”
Corrected the figure
4. AC Characteristics
(6) Power-on Reset Timing
Corrected the Glossary
(9) CSIO Timing
Synchronous serial (SPI=1, SCINV=1)
Corrected the figure of “MS bit=1”
107
114
External clock (EXT=1):asynchronous only Corrected the figure
Corrected the Pins name
AN00 - AN23 → ANxx
Corrected the Min Vale of “Conversion time”
5.12-bit A/D Converter
・Electrical characteristics for the A/D converter
Corrected the Min Vale of “Sampling time”
Corrected the Min Value of “Compare clock cycle”
Corrected the “State Transitontime to operation permission”
Corrected the footnote
9. Electrical characteristics for the A/D
converter
(1) Write / Erase time
10. Return Time from Low-Power
Consumption Mode
(1) Return Factor: Interrupt/WKUP
Return Count Time
119
120
Revised the values of “TBD”
Revised the values of “TBD”
Revised the values of “TBD”
(2) Return Factor: Reset
Return Count Time
122
Revision 2.0
-
Changed the series name.
MB9B120T Series -> MB9B120TA Series
Changed the product name as follows.
MB9BF128SA, MB9BF129SA, MB9BF128TA, MB9BF129TA
-
-
-
List of Pin Functions
· List of pin functions
I/O Circuit Type
Memory Map
· Memory map(2)
41 to 48
55, 56
67
Added LIN to the description of SOTxx
Added about +B input
Added the summary of Flash memory sector
Electrical Characteristics
1. Absolute Maximum Ratings
Electrical Characteristics
3. DC Characteristics
(1) Current rating
· Added the Clamp maximum current
· Added about +B input
76, 77
79, 80
· Changed the expression of condition
· Added Main TIMER mode current
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
129
D a t a S h e e t
Page
Section
Change Results
Electrical Characteristics
4. AC Characteristics
(4-1) Operating Conditions of Main PLL
(4-2) Operating Conditions of Main PLL
Electrical Characteristics
4. AC Characteristics
(7) CSIO/UART Timing
Electrical Characteristics
5. 12bit A/D Converter
87
· Added the figure of Main PLL connection
· Modified from UART Timing to CSIO/UART Timing
· Changed from Internal shift clock operation to Master mode
· Changed from External shift clock operation to Slave mode
· Added the typical value of Integral Nonlinearity, Differential
Nonlinearity, Zero transition voltage and Full-scale transition voltage
Change to full part number
100 to 107
114
125
Ordering Information
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D a t a S h e e t
January 30, 2015, MB9B120TA_DS706-00063-2v0-E
131
D a t a S h e e t
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January 30, 2015, MB9B120TA_DS706-00063-2v0-E
133
D a t a S h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use
where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not
be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the
products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in
this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and
Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a
Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any
product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to
its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party
rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind
arising out of the use of the information in this document.
Copyright © 2013-2015 Spansion All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM
ORNANDTM, Easy DesignSimTM, TraveoTM and combinations thereof, are trademarks and registered trademarks of
,
Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be
trademarks of their respective owners.
134
MB9B120TA_DS706-00063-2v0-E, January 30, 2015
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