MB9AF114MA [SPANSION]
This document states the current technical specifications regarding;
| 型号： | MB9AF114MA |
| 厂家： | 
SPANSION |
| 描述： | This document states the current technical specifications regarding |
| 文件： | 总121页 (文件大小：3165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The following document contains information on Cypress products.
MB9A110A Series
32-bit ARM® Cortex®-M3 based Microcontroller
MB9AF111LA/MA/NA, MB9AF112LA/MA/NA,
MB9AF114LA/MA/NA, MB9AF115MA/NA, MB9AF116MA/NA
Data Sheet (Full Production)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may occur.
Publication Number MB9A110A-DS706-00011
Revision 3.0
Issue Date December 16, 2014
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers
of product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to
verify that they have the latest information before finalizing their design. The following descriptions of
Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue.
Spansion Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion
Inc. The information is intended to help you evaluate this product. Do not design in this product
without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on
this proposed product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the product life
cycle, including product qualification, initial production, and the subsequent phases in the manufacturing
process that occur before full production is achieved. Changes to the technical specifications presented
in a Preliminary document should be expected while keeping these aspects of production under
consideration. Spansion places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification
has been completed, and that initial production has begun. Due to the phases of the
manufacturing process that require maintaining efficiency and quality, this document may be
revised by subsequent versions or modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their
designations wherever necessary, typically on the first page, the ordering information page, and pages
with the DC Characteristics table and the AC Erase and Program table (in the table notes). The
disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes
may include those affecting the number of ordering part numbers available, such as the addition or
deletion of a speed option, temperature range, package type, or VIO range. Changes may also include
those needed to clarify a description or to correct a typographical error or incorrect specification.
Spansion Inc. applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may
occur.”
Questions regarding these document designations may be directed to your local sales office.
MB9A110A-DS706-00011-3v0-E, December 16, 2014
MB9A110A Series
32-bit ARM® Cortex®-M3 based Microcontroller
MB9AF111LA/MA/NA, MB9AF112LA/MA/NA,
MB9AF114LA/MA/NA, MB9AF115MA/NA, MB9AF116MA/NA
Data Sheet (Full Production)
DESCRIPTION
The MB9A110A Series are a highly integrated 32-bit microcontroller that target for high-performance and
cost-sensitive embedded control applications.
The MB9A110A Series are based on the ARM Cortex-M3 Processor and on-chip Flash memory and SRAM,
and peripheral functions, including Motor Control Timers, ADCs and Communication Interfaces (UART,
CSIO, I2C, LIN).
The products which are described in this data sheet are placed into TYPE1 product categories in " FM3
Family PERIPHERAL MANUAL ".
Note: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
Publication Number MB9A110A-DS706-00011
Revision 3.0
Issue Date December 16, 2014
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the
valid combinations offered may occur.
D a t a S h e e t
FEATURES
32-bit ARM Cortex-M3 Core
Processor version: r2p1
Up to 40MHz Frequency Operation
Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and
48 peripheral interrupts and 16 priority levels
24-bit System timer (Sys Tick): System timer for OS task management
On-chip Memories
[Flash memory]
Up to 512 Kbyte
Read cycle: 0wait-cycle
Security function for code protection
[SRAM]
This Series contain a total of up to 32Kbyte on-chip SRAM. On-chip SRAM is composed of two
independent SRAM (SRAM0,SRAM1) . SRAM0 is connected to I-code bus and D-code bus of Cortex-M3
core. SRAM1 is connected to System bus.
SRAM0: Up to 16 Kbytes
SRAM1: Up to 16 Kbytes
Multi-function Serial Interface (Max 8channels)
4 channels with 16steps × 9bit FIFO (ch.4-ch.7), 4 channels without FIFO (ch.0-ch.3)
Operation mode is selectable from the followings for each channel.
UART
CSIO
LIN
I2C
[UART]
Full-duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)*
Various error detection functions available (parity errors, framing errors, and overrun errors)
* : MB9AF111LA, F312LA and F314LA do not support Hardware Flow control
[CSIO]
Full-duplex double buffer
Built-in dedicated baud rate generator
Overrun error detection function available
[LIN]
LIN protocol Rev.2.1 supported
Full-duplex double buffer
Master/Slave mode supported
LIN break field generation (can be changed 13-16bit length)
LIN break delimiter generation (can be changed 1-4bit length)
Various error detection functions available (parity errors, framing errors, and overrun errors)
[I2C]
Standard-mode (Max 100kbps) / Fast-mode (Max 400Kbps) supported
2
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
External Bus Interface*
Supports SRAM, NOR Flash device
Up to 8 chip selects
8/16-bit Data width
Up to 25-bit Address bit
Maximum area size : Up to 256 Mbytes
Supports Address/Data multiplex
Supports external RDY function
* : MB9AF111LA, F312LA and F314LA do not support External Bus Interface
DMA Controller (8channels)
The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process
simultaneously.
8 independently configured and operated channels
Transfer can be started by software or request from the built-in peripherals
Transfer address area: 32bit(4Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand transfer
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
A/D Converter (Max 16channels)
[12-bit A/D Converter]
Successive Approximation type
Built-in 3units*
Conversion time: 1.0μs@5V
Priority conversion available (priority at 2levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion:
4steps)
* : MB9AF111LA, F112LA , F114LA built-in 2units
Base Timer (Max 8channels)
Operation mode is selectable from the followings for each channel.
16-bit PWM timer
16-bit PPG timer
16/32-bit reload timer
16/32-bit PWC timer
December 16, 2014, MB9A110A-DS706-00011-3v0-E
3
D a t a S h e e t
Multi-function Timer (Max 2units)
The Multi-function timer is composed of the following blocks.
16-bit free-run timer × 3ch/unit
Input capture × 4ch/unit
Output compare × 6ch/unit
A/D activation compare × 3ch/unit
Waveform generator × 3ch/unit
16-bit PPG timer × 3ch/unit
The following function can be used to achieve the motor control.
PWM signal output function
DC chopper waveform output function
Dead timer function
Input capture function
A/D converter activate function
DTIF (Motor emergency stop) interrupt function
Quadrature Position/Revolution Counter (QPRC) (Max 2units)
The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position
encoder. Moreover, it is possible to use up/down counter.
The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
Dual Timer (32/16bit Down Counter)
The Dual Timer consists of two programmable 32/16-bit down counters.
Operation mode is selectable from the followings for each timer channel.
Free-running
Periodic (=Reload)
One-shot
Watch Counter
The Watch counter is used for wake up from Low-Power Consumption mode.
Interval timer: up to 64s(Max)@ Sub Clock : 32.768kHz
Watch dog Timer (2channels)
A watchdog timer can generate interrupts or a reset when a time-out value is reached.
This series consists of two different watchdogs, a "Hardware" watchdog and a, "Software" watchdog.
The "Hardware" watchdog timer is clocked by the built-in low speed CR oscillator. Therefore, the
"Hardware" watchdog is active in any low-power consumption modes except STOP mode.
4
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
External Interrupt Controller Unit
Up to 16 external interrupt input pins.
Include one non-maskable interrupt (NMI) input pin.
General-Purpose I/O Port
This series can use its pins as general-purpose I/O ports when they are not used for external bus or
peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function
can be allocated to.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up to 83 fast General Purpose I/O Ports @ 100pin Package
Some ports are 5V tolerant I/O (MB9AF115MA/NA, MB9AF116MA/NA only)
Please see "PIN DESCRIPTION" to confirm the corresponding pins.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator calculates the CRC which has a heavy software processing load, and achieves a
reduction of the integrity check processing load for reception data and storage.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Clock and Reset
[Clocks]
Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL).
Main Clock
Sub Clock
: 4MHz to 48MHz
: 32.768kHz
Built-in high-speed CR Clock: 4MHz
Built-in low-speed CR Clock : 100kHz
Main PLL Clock
[Resets]
Reset requests from INITX pins
Power-on reset
Software reset
Watchdog timers reset
Low-voltage detector reset
Clock supervisor reset
Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks.
External clock failure (clock stop) is detected, reset is asserted.
External frequency anomaly is detected, interrupt or reset is asserted.
December 16, 2014, MB9A110A-DS706-00011-3v0-E
5
D a t a S h e e t
Low-Voltage Detector (LVD)
This Series include 2-stage monitoring of voltage on the VCC. When the voltage falls below the voltage
that has been set, Low-Voltage Detector generates an interrupt or reset.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Low-Power Consumption Mode
Three Low-Power Consumption modes supported.
SLEEP
TIMER
STOP
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Embedded Trace Macrocells (ETM).*
*: MB9AF111LA/MA, F312LA/MA, F314LA/MA, F315MA and F316MA support only SWJ-DP.
Power Supply
VCC
= 2.7V to 5.5V: Correspond to the wide range voltage.
6
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
PRODUCT LINEUP
Memory size
Product name
MB9AF111LA/MA/NA MB9AF112LA/MA/NA MB9AF114LA/MA/NA
On-chip Flash memory
On-chip SRAM
64Kbytes
16Kbytes
128Kbytes
16Kbytes
256Kbytes
32Kbytes
Product name
On-chip Flash memory
On-chip SRAM
MB9AF115MA/NA
384Kbytes
MB9AF116MA/NA
512Kbytes
32Kbytes
32Kbytes
Function
Product name
Pin count
MB9AF111MA
MB9AF112MA
MB9AF114MA
MB9AF115MA
MB9AF116MA
MB9AF111NA
MB9AF112NA
MB9AF114NA
MB9AF115NA
MB9AF116NA
100
MB9AF111LA
MB9AF112LA
MB9AF114LA
64
80
Cortex-M3
40MHz
CPU
Freq.
Power supply voltage range
DMAC
2.7V to 5.5V
8ch.
Addr:21-bit (Max)
Data:8-bit
CS:4 (Max)
Addr:25-bit (Max)
Data:8/16-bit
CS:8 (Max)
-
External Bus Interface
Support: SRAM, NOR Support: SRAM, NOR
Flash
Flash
8ch. (Max)
ch.4 to ch.7: FIFO (16steps × 9-bit)
ch.0 to ch.3: No FIFO
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
Base Timer
(PWC/ Reload timer/PWM/PPG)
8ch. (Max)
A/D
activation
compare
Input
capture
Free-run
timer
3ch.
4ch.
3ch.
6ch.
MF-
Timer
1 unit
2 units (Max)
Output
compare
Waveform
generator
PPG
3ch.
3ch.
QPRC
2ch. (Max)
Dual Timer
1 unit
Watch Counter
CRC Accelerator
Watchdog timer
External Interrupts
I/O ports
1 unit
Yes
1ch. (SW) + 1ch. (HW)
8pins (Max)+ NMI × 1 11pins (Max)+ NMI × 1 16pins (Max)+ NMI × 1
51pins (Max)
9ch. (2 units)
66pins (Max)
12ch. (3 units)
Yes
83pins (Max)
16ch. (3 units)
12-bit A/D converter
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
2ch.
Built-in
High-speed
4MHz
December 16, 2014, MB9A110A-DS706-00011-3v0-E
7
D a t a S h e e t
MB9AF111MA
MB9AF111NA
MB9AF112NA
MB9AF114NA
MB9AF115NA
MB9AF116NA
MB9AF111LA
MB9AF112LA
MB9AF114LA
MB9AF112MA
MB9AF114MA
MB9AF115MA
MB9AF116MA
100kHz
Product name
CR
Low-speed
Debug Function
SWJ-DP
SWJ-DP/ETM
Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the I/O port according to your function use.
See " ELECTRICAL CHARACTERISTICS 4.AC Characteristics (3)Built-in CR Oscillation
Characteristics" for accuracy of built-in CR.
8
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
PACKAGES
MB9AF111MA MB9AF111NA
MB9AF111LA MB9AF112MA MB9AF112NA
MB9AF112LA MB9AF114MA MB9AF114NA
MB9AF114LA MB9AF115MA MB9AF115NA
MB9AF116MA MB9AF116NA
Product name
Package
LQFP:FPT-64P-M38 (0.5mm pitch)
LQFP:FPT-64P-M39 (0.65mm pitch)
QFN:LCC-64P-M24 (0.5mm pitch)
LQFP:FPT-80P-M37 (0.5mm pitch)
LQFP:FPT-100P-M23 (0.5mm pitch)
QFP:FPT-100P-M06 (0.65mm pitch)
BGA:BGA-112P-M04 (0.8mm pitch)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
*
: Supported
*
: MB9AF115NA, MB9AF116NA are planning
Note: Refer to "PACKAGE DIMENSIONS" for detailed information on each package.
December 16, 2014, MB9A110A-DS706-00011-3v0-E
9
D a t a S h e e t
PIN ASSIGNMENT
FPT-100P-M23
(TOP VIEW)
VCC
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_1
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_1
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_1
P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_1
P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_1
P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_1
P56/INT08_2/DTTI1X_0/MADATA06_1
1
2
3
4
5
6
7
8
9
75 VSS
74 P20/INT05_0/CROUT_0/AIN1_1/MAD24_1
73 P21/SIN0_0/INT06_1/BIN1_1
72 P22/SOT0_0/TIOB7_1/ZIN1_1
71 P23/SCK0_0/TIOA7_1/RTO00_1
70 P1F/AN15/ADTG_5/FRCK0_1/MAD23_1
69 P1E/AN14/RTS4_1/DTTI0X_1/MAD22_1
68 P1D/AN13/CTS4_1/IC03_1/MAD21_1
67 P1C/AN12/SCK4_1/IC02_1/MAD20_1
66 P1B/AN11/SOT4_1/IC01_1/MAD19_1
65 P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_1
64 P19/AN09/SCK2_2/MAD17_1
63 P18/AN08/SOT2_2/MAD16_1
62 AVSS
P30/AIN0_0/TIOB0_1/INT03_2/MADATA07_1
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA08_1 10
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA09_1 11
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1 12
P34/FRCK0_0/TIOB4_1/MADATA11_1 13
P35/IC03_0/TIOB5_1/INT08_1/MADATA12_1 14
P36/IC02_0/SIN5_2/INT09_1/MADATA13_1 15
P37/IC01_0/SOT5_2/INT10_1/MADATA14_1 16
P38/IC00_0/SCK5_2/INT11_1/MADATA15_1 17
P39/DTTI0X_0/ADTG_2 18
LQFP - 100
61 AVRH
60 AVCC
59 P17/AN07/SIN2_2/INT04_1/MAD15_1
58 P16/AN06/SCK0_1/MAD14_1
57 P15/AN05/SOT0_1/IC03_2/MAD13_1
56 P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_1
55 P13/AN03/SCK1_1/IC01_2/MAD11_1
54 P12/AN02/SOT1_1/IC00_2/MAD10_1
53 P11/AN01/SIN1_1/INT02_1/FRCK0_2/MAD09_1
52 P10/AN00
P3A/RTO00_0/TIOA0_1 19
P3B/RTO01_0/TIOA1_1 20
P3C/RTO02_0/TIOA2_1 21
P3D/RTO03_0/TIOA3_1 22
P3E/RTO04_0/TIOA4_1 23
P3F/RTO05_0/TIOA5_1 24
VSS 25
51 VCC
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
10
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
FPT-100P-M06
(TOP VIEW)
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_1 81
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_1 82
P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_1 83
P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_1 84
P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_1 85
P56/INT08_2/DTTI1X_0/MADATA06_1 86
P30/AIN0_0/TIOB0_1/INT03_2/MADATA07_1 87
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA08_1 88
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA09_1 89
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1 90
P34/FRCK0_0/TIOB4_1/MADATA11_1 91
P35/IC03_0/TIOB5_1/INT08_1/MADATA12_1 92
P36/IC02_0/SIN5_2/INT09_1/MADATA13_1 93
P37/IC01_0/SOT5_2/INT10_1/MADATA14_1 94
P38/IC00_0/SCK5_2/INT11_1/MADATA15_1 95
P39/DTTI0X_0/ADTG_2 96
50 P22/SOT0_0/TIOB7_1/ZIN1_1
49 P23/SCK0_0/TIOA7_1/RTO00_1
48 P1F/AN15/ADTG_5/FRCK0_1/MAD23_1
47 P1E/AN14/RTS4_1/DTTI0X_1/MAD22_1
46 P1D/AN13/CTS4_1/IC03_1/MAD21_1
45 P1C/AN12/SCK4_1/IC02_1/MAD20_1
44 P1B/AN11/SOT4_1/IC01_1/MAD19_1
43 P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_1
42 P19/AN09/SCK2_2/MAD17_1
41 P18/AN08/SOT2_2/MAD16_1
40 AVSS
QFP - 100
39 AVRH
38 AVCC
37 P17/AN07/SIN2_2/INT04_1/MAD15_1
36 P16/AN06/SCK0_1/MAD14_1
35 P15/AN05/SOT0_1/IC03_2/MAD13_1
34 P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_1
33 P13/AN03/SCK1_1/IC01_2/MAD11_1
32 P12/AN02/SOT1_1/IC00_2/MAD10_1
31 P11/AN01/SIN1_1/INT02_1/FRCK0_2/MAD09_1
P3A/RTO00_0/TIOA0_1 97
P3B/RTO01_0/TIOA1_1 98
P3C/RTO02_0/TIOA2_1 99
P3D/RTO03_0/TIOA3_1 100
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
December 16, 2014, MB9A110A-DS706-00011-3v0-E
11
D a t a S h e e t
FPT-80P-M37
(TOP VIEW)
VCC
1
2
60 P20/INT05_0/CROUT_0/AIN1_1/MAD24_1
59 P21/SIN0_0/INT06_1/BIN1_1
58 P22/SOT0_0/TIOB7_1/ZIN1_1
57 P23/SCK0_0/TIOA7_1
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_1
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_1
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_1
P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_1
P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_1
P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_1
P56/INT08_2/DTTI1X_0/MADATA06_1
P30/AIN0_0/TIOB0_1/INT03_2/MADATA07_1
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA08_1
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA09_1
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1
P39/DTTI0X_0/ADTG_2
3
4
5
56 P1B/AN11/SOT4_1/IC01_1/MAD19_1
55 P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_1
54 P19/AN09/SCK2_2/MAD17_1
53 P18/AN08/SOT2_2/MAD16_1
52 AVSS
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
51 AVRH
LQFP - 80
50 AVCC
49 P17/AN07/SIN2_2/INT04_1/MAD15_1
48 P16/AN06/SCK0_1/MAD14_1
47 P15/AN05/SOT0_1/IC03_2/MAD13_1
46 P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_1
45 P13/AN03/SCK1_1/IC01_2/MAD11_1
44 P12/AN02/SOT1_1/IC00_2/MAD10_1
43 P11/AN01/SIN1_1/INT02_1/FRCK0_2/MAD09_1
42 P10/AN00
P3A/RTO00_0/TIOA0_1
P3B/RTO01_0/TIOA1_1
P3C/RTO02_0/TIOA2_1
P3D/RTO03_0/TIOA3_1
P3E/RTO04_0/TIOA4_1
P3F/RTO05_0/TIOA5_1
VSS
41 VCC
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
12
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
FPT-64P-M38/M39
(TOP VIEW)
VCC
1
2
3
4
5
6
7
8
9
48 P21/SIN0_0/INT06_1
47 P22/SOT0_0/TIOB7_1
46 P23/SCK0_0/TIOA7_1
45 P19/AN09/SCK2_2
44 P18/AN08/SOT2_2
43 AVSS
P50/INT00_0/AIN0_2/SIN3_1
P51/INT01_0/BIN0_2/SOT3_1
P52/INT02_0/ZIN0_2/SCK3_1
P30/AIN0_0/TIOB0_1/INT03_2
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6
P39/DTTI0X_0/ADTG_2
42 AVRH
LQFP - 64
41 AVCC
40 P17/AN07/SIN2_2/INT04_1
39 P15/AN05/IC03_2
38 P14/AN04/INT03_1/IC02_2
37 P13/AN03/SCK1_1/IC01_2
36 P12/AN02/SOT1_1/IC00_2
35 P11/AN01/SIN1_1/INT02_1/FRCK0_2
34 P10/AN00
P3A/RTO00_0/TIOA0_1 10
P3B/RTO01_0/TIOA1_1 11
P3C/RTO02_0/TIOA2_1 12
P3D/RTO03_0/TIOA3_1 13
P3E/RTO04_0/TIOA4_1 14
P3F/RTO05_0/TIOA5_1 15
VSS 16
33 VCC
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
December 16, 2014, MB9A110A-DS706-00011-3v0-E
13
D a t a S h e e t
BGA-112P-M04
1
2
3
4
5
6
7
8
9
10
11
TMS/
SWDIO
A
B
C
D
E
F
TRSTX
VSS
VCC
P50
P53
P30
P34
P37
P3B
VCC
VCC
VSS
P81
VSS
P51
P54
P31
P35
P38
P3C
P3F
VSS
C
P80
P52
VSS
P55
P32
P36
P3A
P3E
VSS
X1A
X0A
VCC
P61
P60
VSS
P33
P39
P3D
VSS
P40
INITX
VSS
P0E
P0F
P62
P0B
P0C
P0D
P63
P07
P08
P09
P0A
VCC
VSS
P20
VSS
TDI
TDO/
SWO
TCK/
SWCLK
P05
VSS
P22
VSS
P06
P21
P56
P23
AN15
AN11
Index
AN14
AN10
AN07
AN04
VSS
MD1
X0
AN12
AN13
AN08
VSS
AN02
P4E
AN09 AVRH
AN06 AVSS
AN03 AVCC
G
H
J
P44
P43
P42
P41
P4C
P49
P48
P45
AN05
P4D
P4B
P4A
AN01
VSS
X1
AN00
VCC
VSS
K
L
MD0
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
14
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
LCC-64P-M24
(TOP VIEW)
VCC
1
2
3
4
5
6
7
8
9
48 P21/SIN0_0/INT06_1
47 P22/SOT0_0/TIOB7_1
46 P23/SCK0_0/TIOA7_1
45 P19/AN09/SCK2_2
44 P18/AN08/SOT2_2
43 AVSS
P50/INT00_0/AIN0_2/SIN3_1
P51/INT01_0/BIN0_2/SOT3_1
P52/INT02_0/ZIN0_2/SCK3_1
P30/AIN0_0/TIOB0_1/INT03_2
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6
P39/DTTI0X_0/ADTG_2
42 AVRH
QFN - 64
41 AVCC
40 P17/AN07/SIN2_2/INT04_1
39 P15/AN05/IC03_2
38 P14/AN04/INT03_1/IC02_2
37 P13/AN03/SCK1_1/IC01_2
36 P12/AN02/SOT1_1/IC00_2
35 P11/AN01/SIN1_1/INT02_1/FRCK0_2
34 P10/AN00
P3A/RTO00_0/TIOA0_1 10
P3B/RTO01_0/TIOA1_1 11
P3C/RTO02_0/TIOA2_1 12
P3D/RTO03_0/TIOA3_1 13
P3E/RTO04_0/TIOA4_1 14
P3F/RTO05_0/TIOA5_1 15
VSS 16
33 VCC
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
December 16, 2014, MB9A110A-DS706-00011-3v0-E
15
D a t a S h e e t
LIST OF PIN FUNCTIONS
List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin
Pin No
I/O circuit Pin state
Pin name
LQFP-64
QFN-64
1
type
type
LQFP-100 QFP-100 BGA-112 LQFP-80
1
79
B1
1
VCC
P50
-
INT00_0
AIN0_2
SIN3_1
2
-
2
80
C1
2
E
H
RTO10_0
(PPG10_0)
MADATA00_1
P51
INT01_0
BIN0_2
3
-
SOT3_1
(SDA3_1)
3
81
C2
3
E
H
RTO11_0
(PPG10_0)
MADATA01_1
P52
INT02_0
ZIN0_2
4
-
SCK3_1
(SCL3_1)
4
82
B3
4
E
H
RTO12_0
(PPG12_0)
MADATA02_1
P53
SIN6_0
TIOA1_2
INT07_2
5
6
83
84
D1
D2
5
6
-
-
E
E
H
RTO13_0
(PPG12_0)
MADATA03_1
P54
SOT6_0
(SDA6_0)
TIOB1_2
I
RTO14_0
(PPG14_0)
MADATA04_1
16
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80
I/O circuit Pin state
Pin name
LQFP-64
QFN-64
type
type
P55
SCK6_0
(SCL6_0)
7
85
D3
7
-
ADTG_1
E
I
RTO15_0
(PPG14_0)
MADATA05_1
P56
INT08_2
DTTI1X_0
MADATA06_1
P30
8
9
86
87
D5
E1
8
9
-
E
E
H
H
AIN0_0
5
-
TIOB0_1
INT03_2
MADATA07_1
P31
BIN0_0
TIOB1_1
6
-
10
88
E2
10
E
E
H
H
SCK6_1
(SCL6_1)
INT04_2
MADATA08_1
P32
ZIN0_0
TIOB2_1
7
11
89
E3
11
SOT6_1
(SDA6_1)
INT05_2
MADATA09_1
P33
-
INT04_0
8
TIOB3_1
SIN6_1
12
13
90
91
E4
F1
12
E
E
H
ADTG_6
MADATA10_1
P34
-
-
FRCK0_0
TIOB4_1
MADATA11_1
-
I
December 16, 2014, MB9A110A-DS706-00011-3v0-E
17
D a t a S h e e t
Pin No
I/O circuit Pin state
Pin name
LQFP-64
QFN-64
type
type
LQFP-100 QFP-100 BGA-112 LQFP-80
P35
IC03_0
14
15
92
93
F2
F3
-
-
-
TIOB5_1
INT08_1
MADATA12_1
P36
E
H
IC02_0
-
SIN5_2
E
E
H
H
INT09_1
MADATA13_1
P37
IC01_0
SOT5_2
(SDA5_2)
16
17
94
95
G1
G2
-
-
-
-
INT10_1
MADATA14_1
P38
IC00_0
SCK5_2
(SCL5_2)
E
H
INT11_1
MADATA15_1
P39
18
19
96
97
F4
13
14
9
DTTI0X_0
ADTG_2
P3A
E
I
I
RTO00_0
(PPG00_0)
G3
10
G
TIOA0_1
P3B
RTO01_0
(PPG00_0)
20
21
98
99
H1
H2
15
16
11
12
G
G
G
I
I
I
TIOA1_1
P3C
RTO02_0
(PPG02_0)
TIOA2_1
P3D
RTO03_0
(PPG02_0)
22
-
100
-
G4
B2
17
-
13
-
TIOA3_1
VSS
-
18
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80
I/O circuit Pin state
Pin name
LQFP-64
QFN-64
type
type
P3E
RTO04_0
(PPG04_0)
23
24
1
2
H3
J2
18
19
14
G
I
TIOA4_1
P3F
RTO05_0
(PPG04_0)
15
G
G
I
TIOA5_1
VSS
25
26
3
4
L1
J1
20
-
16
-
-
-
VCC
P40
TIOA0_0
27
5
J4
-
-
H
RTO10_1
(PPG10_1)
INT12_1
P41
TIOA1_0
28
29
30
6
7
8
L5
K5
J5
-
-
-
-
-
-
G
G
G
H
I
RTO11_1
(PPG10_1)
INT13_1
P42
TIOA2_0
RTO12_1
(PPG12_1)
P43
TIOA3_0
I
RTO13_1
(PPG12_1)
ADTG_7
P44
21
-
TIOA4_0
MAD00_1
31
32
9
H5
L6
-
-
G
G
I
I
RTO14_1
(PPG14_1)
P45
22
-
TIOA5_0
MAD01_1
10
RTO15_1
(PPG14_1)
-
-
-
-
-
-
K2
J3
-
-
-
-
-
-
VSS
VSS
VSS
-
-
-
H4
December 16, 2014, MB9A110A-DS706-00011-3v0-E
19
D a t a S h e e t
Pin No
I/O circuit Pin state
Pin name
LQFP-64
QFN-64
17
type
type
LQFP-100 QFP-100 BGA-112 LQFP-80
33
34
35
11
12
13
L2
L4
K1
23
24
25
C
VSS
-
-
-
-
18
VCC
P46
36
14
L3
26
19
D
M
X0A
P47
37
38
15
16
K3
K4
27
28
20
21
D
B
N
C
X1A
INITX
P48
DTTI1X_1
INT14_1
SIN3_2
MAD02_1
P49
39
17
K6
29
-
E
H
22
-
TIOB0_0
AIN0_1
IC10_1
40
18
J6
30
E
I
SOT3_2
(SDA3_2)
MAD03_1
P4A
23
-
TIOB1_0
BIN0_1
IC11_1
41
42
43
19
20
21
L7
K7
H6
31
32
33
E
E
I
I
I
SCK3_2
(SCL3_2)
MAD04_1
P4B
24
-
TIOB2_0
ZIN0_1
IC12_1
MAD05_1
P4C
TIOB3_0
25
-
SCK7_1
(SCL7_1)
E / I*
AIN1_2
IC13_1
MAD06_1
20
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80
I/O circuit Pin state
Pin name
LQFP-64
QFN-64
type
type
P4D
TIOB4_0
26
SOT7_1
(SDA7_1)
44
45
22
23
J7
34
35
E / I*
I
BIN1_2
FRCK1_1
MAD07_1
P4E
-
TIOB5_0
INT06_2
SIN7_1
ZIN1_2
MAD08_1
MD1
27
K8
E / I*
I
-
46
47
48
24
25
26
K9
L8
L9
36
37
38
28
29
30
C
J
P
D
A
PE0
MD0
X0
A
PE2
X1
49
27
L10
39
31
A
F
F
B
K
L
PE3
50
51
28
29
L11
K11
40
41
32
33
VSS
-
-
VCC
P10
52
53
30
31
J11
J10
42
43
34
AN00
P11
AN01
SIN1_1
INT02_1
FRCK0_2
MAD09_1
P12
35
-
AN02
36
SOT1_1
(SDA1_1)
54
32
J8
44
F
K
IC00_2
MAD10_1
VSS
-
-
-
-
-
-
-
K10
J9
-
-
-
-
VSS
December 16, 2014, MB9A110A-DS706-00011-3v0-E
21
D a t a S h e e t
Pin No
I/O circuit Pin state
Pin name
LQFP-64
QFN-64
type
type
LQFP-100 QFP-100 BGA-112 LQFP-80
P13
AN03
37
SCK1_1
(SCL1_1)
55
56
57
33
34
35
H10
45
46
47
F
K
IC01_2
MAD11_1
P14
-
AN04
38
INT03_1
IC02_2
SIN0_1
MAD12_1
P15
H9
F
F
L
-
39
AN05
IC03_2
H7
K
SOT0_1
(SDA0_1)
-
-
MAD13_1
P16
AN06
58
59
36
37
G10
G9
48
49
F
F
K
L
SCK0_1
(SCL0_1)
MAD14_1
P17
AN07
40
SIN2_2
INT04_1
MAD15_1
AVCC
AVRH
AVSS
-
60
61
62
38
39
40
H11
F11
G11
50
51
52
41
42
43
-
-
-
P18
AN08
44
-
63
41
G8
53
F
F
K
K
SOT2_2
(SDA2_2)
MAD16_1
P19
AN09
45
64
-
42
-
F10
H8
54
-
SCK2_2
(SCL2_2)
-
-
MAD17_1
VSS
-
22
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80
I/O circuit Pin state
Pin name
LQFP-64
QFN-64
type
type
P1A
AN10
SIN4_1
INT05_1
IC00_1
MAD18_1
P1B
65
66
67
43
44
45
F9
55
56
-
-
F
L
AN11
SOT4_1
(SDA4_1)
E11
E10
-
-
F
F
K
K
IC01_1
MAD19_1
P1C
AN12
SCK4_1
(SCL4_1)
IC02_1
MAD20_1
P1D
AN13
68
69
70
46
47
48
F8
E9
-
-
-
-
-
-
CTS4_1
IC03_1
MAD21_1
P1E
F
F
F
K
K
K
AN14
RTS4_1
DTTI0X_1
MAD22_1
P1F
AN15
D11
ADTG_5
FRCK0_1
MAD23_1
VSS
-
-
-
-
B10
C9
-
-
-
-
-
-
VSS
December 16, 2014, MB9A110A-DS706-00011-3v0-E
23
D a t a S h e e t
Pin No
I/O circuit Pin state
Pin name
LQFP-64
QFN-64
type
type
LQFP-100 QFP-100 BGA-112 LQFP-80
P23
SCK0_0
(SCL0_0)
57
46
-
71
49
D10
E
I
TIOA7_1
RTO00_1
(PPG00_1)
-
P22
SOT0_0
(SDA0_0)
47
72
73
74
50
51
52
E8
58
E
E
E
I
TIOB7_1
ZIN1_1
P21
-
48
-
SIN0_0
INT06_1
BIN1_1
P20
C11
C10
59
60
H
H
INT05_0
CROUT_0
AIN1_1
MAD24_1
VSS
-
75
76
53
54
A11
A10
-
-
-
-
-
-
VCC
P00
49
-
77
78
79
80
81
55
56
57
58
59
A9
B9
61
62
63
64
65
TRSTX
MCSX7_1
P01
E
E
E
E
E
E
E
E
E
E
50
TCK
SWCLK
P02
51
-
B11
A8
B8
TDI
MCSX6_1
P03
52
53
TMS
SWDIO
P04
TDO
SWO
P05
TRACED0
TIOA5_2
SIN4_2
INT00_1
MCSX5_1
VSS
82
-
60
-
C8
D8
-
-
-
-
E
F
-
24
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80
I/O circuit Pin state
Pin name
LQFP-64
QFN-64
type
type
P06
TRACED1
TIOB5_2
83
84
61
62
D9
A7
-
-
E
F
SOT4_2
(SDA4_2)
INT01_1
MCSX4_1
P07
66
-
ADTG_0
MCLKOUT_1
TRACED2
-
E
G
SCK4_2
(SCL4_2)
P08
TRACED3
TIOA0_2
CTS4_2
MCSX3_1
P09
85
86
87
63
64
65
B7
C7
D7
-
-
-
-
E
E
G
G
H
TRACECLK
TIOB0_2
RTS4_2
MCSX2_1
P0A
54
-
SIN4_0
67
INT00_2
FRCK1_0
MCSX1_1
P0B
E / I*
SOT4_0
(SDA4_0)
55
-
88
89
66
67
A6
B6
68
69
E / I*
I
I
TIOB6_1
IC10_0
MCSX0_1
P0C
SCK4_0
(SCL4_0)
56
E / I*
TIOA6_1
IC11_0
MALE_1
VSS
-
-
-
-
-
D4
C3
-
-
-
-
-
-
VSS
December 16, 2014, MB9A110A-DS706-00011-3v0-E
25
D a t a S h e e t
Pin No
I/O circuit Pin state
Pin name
LQFP-64
QFN-64
type
type
LQFP-100 QFP-100 BGA-112 LQFP-80
P0D
RTS4_0
TIOA3_2
IC12_0
MDQM0_1
P0E
90
91
68
69
C6
A5
70
71
-
E
I
CTS4_0
TIOB3_2
IC13_0
MDQM1_1
P0F
-
E
I
92
93
70
71
B5
D6
72
73
57
-
NMIX
E
E
J
CROUT_1
P63
INT03_0
MWEX_1
P62
H
SCK5_0
(SCL5_0)
58
-
94
95
96
72
73
74
C5
B4
C4
74
75
76
E
E
I
I
ADTG_3
MOEX_1
P61
SOT5_0
(SDA5_0)
59
TIOB2_2
P60
SIN5_0
TIOA2_2
INT15_1
MRDY_1
VCC
60
E / I*
H
-
97
98
75
76
77
78
A4
A3
A2
A1
77
78
79
80
61
62
63
64
-
-
P80
H
H
O
O
99
P81
100
VSS
* : 5V tolerant I/O on MB9AF115MA/NA and MB9AF116MA/NA
26
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
List of pin functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No
LQFP- QFP- BGA- LQFP-LQFP-
Module
Pin name
Function
100 100 112
80
64
QFN-
64
ADC
ADTG_0
ADTG_1
ADTG_2
ADTG_3
ADTG_4
ADTG_5
ADTG_6
ADTG_7
ADTG_8
AN00
84
7
62
85
96
72
-
A7
D3
F4
66
7
-
-
9
18
94
-
13
74
-
C5
-
58
-
A/D converter external trigger input
pin
70
12
30
-
48
90
8
D11
E4
J5
-
-
12
-
8
-
-
-
-
-
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
27
19
85
40
9
30
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
5
J11
J10
J8
42
43
44
45
46
47
48
49
53
54
55
56
-
34
35
36
37
38
39
-
AN01
AN02
AN03
H10
H9
H7
G10
G9
G8
F10
F9
AN04
AN05
AN06
AN07
40
44
45
-
A/D converter analog input pin.
ANxx describes ADC ch.xx.
AN08
AN09
AN10
AN11
E11
E10
F8
-
AN12
-
AN13
-
-
AN14
E9
D11
J4
-
-
AN15
-
-
Base Timer
0
TIOA0_0
TIOA0_1
TIOA0_2
TIOB0_0
TIOB0_1
TIOB0_2
TIOA1_0
TIOA1_1
TIOA1_2
TIOB1_0
TIOB1_1
TIOB1_2
-
-
Base timer ch.0 TIOA pin
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
97
63
18
87
64
6
G3
B7
J6
14
-
10
-
30
9
22
5
E1
C7
L5
H1
D1
L7
E2
D2
86
28
20
5
-
-
Base Timer
1
-
-
98
83
19
88
84
15
5
11
-
41
10
6
31
10
6
23
6
-
December 16, 2014, MB9A110A-DS706-00011-3v0-E
27
D a t a S h e e t
Pin No
LQFP- QFP- BGA- LQFP-LQFP-
Module
Pin name
Function
100 100 112
80
64
QFN-
64
Base Timer
2
TIOA2_0
TIOA2_1
TIOA2_2
TIOB2_0
TIOB2_1
TIOB2_2
TIOA3_0
TIOA3_1
TIOA3_2
TIOB3_0
TIOB3_1
TIOB3_2
TIOA4_0
TIOA4_1
TIOA4_2
TIOB4_0
TIOB4_1
TIOB4_2
TIOA5_0
TIOA5_1
TIOA5_2
TIOB5_0
TIOB5_1
TIOB5_2
TIOA6_1
TIOB6_1
TIOA7_0
TIOA7_1
TIOA7_2
TIOB7_0
TIOB7_1
TIOB7_2
29
21
96
42
11
95
30
22
90
43
12
91
31
23
-
7
99
74
20
89
73
8
K5
H2
C4
K7
E3
B4
J5
-
-
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
Base timer ch.3 TIOA pin
Base timer ch.3 TIOB pin
Base timer ch.4 TIOA pin
Base timer ch.4 TIOB pin
Base timer ch.5 TIOA pin
Base timer ch.5 TIOB pin
16
76
32
11
75
-
12
60
24
7
59
-
Base Timer
3
100
68
21
90
69
9
G4
C6
H6
E4
A5
H5
H3
-
17
70
33
12
71
21
18
-
13
-
25
8
-
Base Timer
4
-
1
14
-
-
44
13
-
22
91
-
J7
34
-
26
-
F1
-
-
-
Base Timer
5
32
24
82
45
14
83
89
88
-
10
2
L6
J2
22
19
-
-
15
-
60
23
92
61
67
66
-
C8
K8
F2
D9
B6
A6
-
35
-
27
-
-
-
Base Timer
6
Base timer ch.6 TIOA pin
Base timer ch.6 TIOB pin
69
68
-
56
55
-
Base Timer
7
Base timer ch.7 TIOA pin
Base timer ch.7 TIOB pin
71
-
49
-
D10
-
57
-
46
-
-
-
-
-
-
72
-
50
-
E8
-
58
-
47
-
28
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
Pin No
LQFP- QFP- BGA- LQFP-LQFP-
Module
Pin name
Function
100 100 112
80
64
QFN-
64
Debugger
SWCLK
SWDIO
Serial wire debug interface clock input
Serial wire debug interface data input /
output
78
80
56
58
B9
A8
62
64
50
52
SWO
TCK
TDI
Serial wire viewer output
J-TAG test clock input
81
78
79
81
80
86
82
83
84
85
77
31
32
39
40
41
42
43
44
45
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
74
59
56
57
59
58
64
60
61
62
63
55
9
B8
B9
B11
B8
A8
C7
C8
D9
A7
B7
A9
H5
L6
65
62
63
65
64
-
53
50
51
53
52
-
J-TAG test data input
TDO
TMS
J-TAG debug data output
J-TAG test mode state input/output
TRACECLK Trace CLK output of ETM
TRACED0
-
-
TRACED1
-
-
Trace data output of ETM
TRACED2
-
-
TRACED3
-
-
TRSTX
J-TAG test reset input
61
21
22
29
30
31
32
33
34
35
43
44
45
46
47
48
49
53
54
55
56
-
49
-
External
Bus
MAD00_1
MAD01_1
MAD02_1
MAD03_1
MAD04_1
MAD05_1
MAD06_1
MAD07_1
MAD08_1
MAD09_1
MAD10_1
MAD11_1
10
17
18
19
20
21
22
23
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
52
-
K6
J6
-
-
L7
-
K7
H6
J7
-
-
-
K8
J10
J8
-
-
-
H10
H9
H7
G10
G9
G8
F10
F9
-
MAD12_1 External bus interface address bus
-
MAD13_1
MAD14_1
MAD15_1
MAD16_1
MAD17_1
MAD18_1
MAD19_1
MAD20_1
MAD21_1
MAD22_1
MAD23_1
MAD24_1
-
-
-
-
-
-
E11
E10
F8
-
-
-
-
E9
-
-
D11
C10
-
-
60
-
December 16, 2014, MB9A110A-DS706-00011-3v0-E
29
D a t a S h e e t
Pin No
LQFP- QFP- BGA- LQFP-LQFP-
Module
Pin name
Function
100 100 112
80
64
QFN-
64
External
Bus
MCSX0_1
MCSX1_1
MCSX2_1
MCSX3_1
MCSX4_1
MCSX5_1
MCSX6_1
MCSX7_1
MDQM0_1
MDQM1_1
88
87
86
85
83
82
79
77
90
91
66
65
64
63
61
60
57
55
68
69
A6
D7
C7
B7
D9
C8
B11
A9
C6
A5
68
67
-
-
-
-
-
-
-
-
-
-
-
-
External bus interface chip select
output pin
-
-
63
61
70
71
External bus interface byte mask signal
output
External bus interface read enable
signal for SRAM
External bus interface write enable
signal for SRAM
MOEX_1
MWEX_1
94
93
72
71
C5
D6
74
73
-
-
2
3
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
C1
C2
B3
D1
D2
D3
D5
E1
E2
E3
E4
F1
F2
F3
G1
G2
2
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MADATA00_1
MADATA01_1
MADATA02_1
MADATA03_1
MADATA04_1
MADATA05_1
MADATA06_1
MADATA07_1
MADATA08_1
MADATA09_1
MADATA10_1
MADATA11_1
MADATA12_1
MADATA13_1
MADATA14_1
MADATA15_1
4
4
5
5
6
6
7
7
8
8
9
9
External bus interface data bus
10
11
12
13
14
15
16
17
10
11
12
-
-
-
-
-
Address Latch enable signal for
multiplex
89
67
B6
69
-
MALE_1
External RDY input signal
External bus clock output
96
84
74
62
C4
A7
76
66
-
-
MRDY_1
MCLKOUT_1
30
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
Pin No
LQFP- QFP- BGA- LQFP-LQFP-
Module
Pin name
Function
100 100 112
80
64
QFN-
64
External
Interrupt
INT00_0
INT00_1
INT00_2
INT01_0
INT01_1
INT02_0
INT02_1
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
INT06_1
INT06_2
2
80
60
65
81
61
82
31
71
34
87
90
37
88
52
43
89
51
23
C1
C8
D7
C2
D9
B3
J10
D6
H9
E1
2
2
External interrupt request 00
input pin
82
87
3
-
-
54
3
67
3
External interrupt request 01
input pin
83
4
-
-
4
4
External interrupt request 02
input pin
53
93
56
9
43
73
46
9
35
-
External interrupt request 03
input pin
38
5
12
59
10
74
65
11
73
45
E4
12
49
10
60
55
11
59
35
8
External interrupt request 04
input pin
G9
E2
40
6
C10
F9
-
External interrupt request 05
input pin
-
E3
7
C11
K8
48
27
External interrupt request 06
input pin
External interrupt request 07
input pin
INT07_2
5
83
D1
5
-
INT08_1
INT08_2
14
8
92
86
F2
-
-
-
External interrupt request 08
input pin
D5
8
External interrupt request 09
input pin
External interrupt request 10
input pin
External interrupt request 11
input pin
External interrupt request 12
input pin
External interrupt request 13
input pin
External interrupt request 14
input pin
INT09_1
INT10_1
INT11_1
INT12_1
INT13_1
INT14_1
15
16
17
27
28
39
93
94
95
5
F3
G1
G2
J4
-
-
-
-
-
-
-
-
-
-
6
L5
K6
-
17
29
External interrupt request 15
input pin
Non-Maskable Interrupt input
INT15_1
NMIX
96
92
74
70
C4
B5
76
72
60
57
December 16, 2014, MB9A110A-DS706-00011-3v0-E
31
D a t a S h e e t
Pin No
LQFP- QFP- BGA- LQFP-LQFP-
Module
Pin name
Function
100 100 112
80
64
QFN-
64
49
50
51
52
53
-
-
-
-
-
54
55
56
-
GPIO
P00
P01
P02
P03
P04
P05
P06
P07
P08
P09
P0A
P0B
P0C
P0D
P0E
P0F
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P1A
P1B
P1C
P1D
P1E
P1F
P20
P21
P22
P23
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
74
73
72
71
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
30
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
52
51
50
49
A9
B9
B11
A8
B8
61
62
63
64
65
-
-
66
-
C8
D9
A7
B7
General-purpose I/O port 0
C7
-
D7
A6
B6
C6
A5
B5
J11
J10
J8
H10
H9
H7
G10
G9
G8
F10
F9
67
68
69
70
71
72
42
43
44
45
46
47
48
49
53
54
55
56
-
-
57
34
35
36
37
38
39
-
40
44
45
-
-
-
-
-
-
-
48
47
46
General-purpose I/O port 1
E11
E10
F8
-
-
-
60
59
58
57
E9
D11
C10
C11
E8
General-purpose I/O port 2
D10
32
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
Pin No
LQFP- QFP- BGA- LQFP-LQFP-
Module
Pin name
Function
100 100 112
80
64
QFN-
64
5
GPIO
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P3A
P3B
P3C
P3D
P3E
P3F
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P4A
P4B
P4C
P4D
P4E
P50
P51
P52
P53
P54
P55
P56
P60
P61
P62
P63
P80
P81
PE0
PE2
PE3
9
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
E1
E2
E3
E4
F1
F2
F3
G1
G2
F4
G3
H1
H2
G4
H3
J2
9
10
11
12
-
-
-
-
-
13
14
15
16
17
18
19
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
27
28
29
30
31
32
36
37
39
40
41
42
43
44
45
2
6
7
8
-
-
-
-
-
General-purpose I/O port 3
9
10
11
12
13
14
15
-
-
-
-
-
2
5
6
7
8
9
J4
L5
K5
J5
H5
L6
L3
K3
K6
J6
L7
K7
H6
J7
K8
C1
C2
B3
D1
D2
D3
D5
C4
B4
C5
D6
A3
A2
K9
L9
L10
-
-
-
21
22
26
27
29
30
31
32
33
34
35
2
3
4
5
6
7
8
76
75
74
73
78
79
36
38
39
10
14
15
17
18
19
20
21
22
23
80
81
82
83
84
85
86
74
73
72
71
76
77
24
26
27
-
19
20
-
22
23
24
25
26
27
2
3
4
-
-
-
-
60
59
58
-
62
63
28
30
31
General-purpose I/O port 4
3
4
5
6
7
8
96
95
94
93
98
99
46
48
49
General-purpose I/O port 5
General-purpose I/O port 6
General-purpose I/O port 8
General-purpose I/O port E
December 16, 2014, MB9A110A-DS706-00011-3v0-E
33
D a t a S h e e t
Pin No
LQFP- QFP- BGA- LQFP-LQFP-
Module
Pin name
Function
100 100 112
80
64
QFN-
64
Multi
Function
Serial
0
SIN0_0
SIN0_1
73
56
51
34
C11
H9
59
46
48
Multifunction serial interface ch.0
input pin
-
Multifunction serial interface ch.0
output pin.
SOT0_0
(SDA0_0)
72
57
71
50
35
49
E8
58
47
57
47
This pin operates as SOT0 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA0 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.0
clock I/O pin.
SOT0_1
(SDA0_1)
H7
-
SCK0_0
(SCL0_0)
D10
46
This pin operates as SCK0 when it is
used in a CSIO (operation mode 2)
and as SCL0 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.1
input pin
SCK0_1
(SCL0_1)
58
53
36
31
G10
J10
48
43
-
Multi
Function
Serial
1
SIN1_1
35
Multifunction serial interface ch.1
output pin.
SOT1_1
This pin operates as SOT1 when it is
54
55
32
33
J8
44
45
36
37
(SDA1_1) used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA1 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.1
clock I/O pin.
SCK1_1
(SCL1_1)
This pin operates as SCK1 when it is
used in a CSIO (operation mode 2)
and as SCL1 when it is used in an I2C
(operation mode 4).
H10
34
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
Pin No
LQFP- QFP- BGA- LQFP-LQFP-
Module
Pin name
Function
100 100 112
80
64
QFN-
64
Multi
Function
Serial
2
Multifunction serial interface ch.2
input pin
Multifunction serial interface ch.2
output pin.
SIN2_2
59
63
37
41
G9
G8
49
40
SOT2_2
This pin operates as SOT2 when it is
53
54
44
(SDA2_2) used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA2 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.2
clock I/O pin.
SCK2_2
(SCL2_2)
This pin operates as SCK2 when it is
used in a CSIO (operation mode 2)
and as SCL2 when it is used in an I2C
(operation mode 4).
64
42
F10
45
Multi
Function
Serial
3
SIN3_1
SIN3_2
2
80
17
C1
K6
2
2
-
Multifunction serial interface ch.3
input pin
39
29
Multifunction serial interface ch.3
output pin.
SOT3_1
(SDA3_1)
3
40
4
81
18
82
19
C2
J6
3
30
4
3
-
This pin operates as SOT3 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA3 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.3
clock I/O pin.
This pin operates as SCK3 when it is
used in a CSIO (operation mode 2)
and as SCL3 when it is used in an I2C
(operation mode 4).
SOT3_2
(SDA3_2)
SCK3_1
(SCL3_1)
B3
L7
4
-
SCK3_2
(SCL3_2)
41
31
December 16, 2014, MB9A110A-DS706-00011-3v0-E
35
D a t a S h e e t
Pin No
LQFP- QFP- BGA- LQFP-LQFP-
Module
Pin name
Function
100 100 112
80
64
QFN-
64
Multi
Function
Serial
4
SIN4_0
SIN4_1
SIN4_2
87
65
82
65
43
60
D7
F9
C8
67
55
-
54
Multifunction serial interface ch.4
input pin
-
-
SOT4_0
(SDA4_0)
88
66
83
89
67
84
66
44
61
67
45
62
A6
E11
D9
68
56
-
55
-
Multifunction serial interface ch.4
output pin.
This pin operates as SOT4 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA4 when it is
used in an I2C (operation mode 4).
SOT4_1
(SDA4_1)
SOT4_2
(SDA4_2)
-
SCK4_0
(SCL4_0)
Multifunction serial interface ch.4
clock I/O pin.
This pin operates as SCK4 when it is
used in a CSIO (operation mode 2)
and as SCL4 when it is used in an I2C
(operation mode 4).
B6
69
-
56
-
SCK4_1
(SCL4_1)
E10
A7
SCK4_2
(SCL4_2)
-
-
RTS4_0
RTS4_1
RTS4_2
CTS4_0
CTS4_1
CTS4_2
SIN5_0
SIN5_2
90
69
86
91
68
85
96
15
68
47
64
69
46
63
74
93
C6
E9
C7
A5
F8
B7
C4
F3
70
-
-
-
Multifunction serial interface ch.4
RTS output pin
-
-
71
-
-
Multifunction serial interface ch.4
CTS input pin
-
-
-
Multi
Function
Serial
5
76
-
60
-
Multifunction serial interface ch.5
input pin
Multifunction serial interface ch.5
output pin.
SOT5_0
(SDA5_0)
95
16
94
17
73
94
72
95
B4
G1
C5
G2
75
59
This pin operates as SOT5 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA5 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.5
clock I/O pin.
This pin operates as SCK5 when it is
used in a CSIO (operation mode 2)
and as SCL5 when it is used in an I2C
(operation mode 4).
SOT5_2
(SDA5_2)
-
-
SCK5_0
(SCL5_0)
74
-
58
-
SCK5_2
(SCL5_2)
36
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
Pin No
LQFP- QFP- BGA- LQFP-LQFP-
Module
Pin name
Function
100 100 112
80
64
QFN-
64
Multi
Function
Serial
6
SIN6_0
SIN6_1
5
83
90
D1
E4
5
-
Multifunction serial interface ch.6
input pin
12
12
8
Multifunction serial interface ch.6
output pin.
SOT6_0
(SDA6_0)
6
11
7
84
89
85
D2
E3
D3
6
11
7
-
This pin operates as SOT6 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA6 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.6
clock I/O pin.
SOT6_1
(SDA6_1)
7
-
SCK6_0
(SCL6_0)
This pin operates as SCK6 when it is
used in a CSIO (operation mode 2)
and as SCL6 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.7
input pin
SCK6_1
(SCL6_1)
10
45
88
23
E2
K8
10
35
6
Multi
Function
Serial
7
SIN7_1
27
Multifunction serial interface ch.7
output pin.
SOT7_1
This pin operates as SOT7 when it is
44
43
22
21
J7
34
33
26
25
(SDA7_1) used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA7 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.7
clock I/O pin.
SCK7_1
(SCL7_1)
This pin operates as SCK7 when it is
used in a CSIO (operation mode 2)
and as SCL7 when it is used in an I2C
(operation mode 4).
H6
December 16, 2014, MB9A110A-DS706-00011-3v0-E
37
D a t a S h e e t
Pin No
LQFP- QFP- BGA- LQFP- LQFP-
Module
Pin name
Function
100 100 112
80
64
QFN-
64
Multi
Function
Timer
0
Input signal of waveform generator to
control outputs RTO00 to RTO05 of
multi-function timer 0
DTTI0X_0
DTTI0X_1
18
69
96
47
F4
E9
13
-
9
-
FRCK0_0
FRCK0_1
FRCK0_2
IC00_0
IC00_1
IC00_2
IC01_0
IC01_1
IC01_2
IC02_0
IC02_1
IC02_2
IC03_0
IC03_1
IC03_2
13
70
53
17
65
54
16
66
55
15
67
56
14
68
57
91
48
31
95
43
32
94
44
33
93
45
34
92
46
35
F1
D11
J10
G2
F9
-
-
-
-
16-bit free-run timer external clock
input pin
43
-
35
-
55
44
-
-
J8
36
-
G1
E11
H10
F3
56
45
-
-
16-bit input capture input pin of
multi-function timer 0.
ICxx describes channel number.
37
-
E10
H9
F2
-
-
46
-
38
-
F8
-
-
H7
47
39
RTO00_0
(PPG00_0)
Waveform generator output of
multi-function timer 0.
This pin operates as PPG00 when it is
used in PPG 0 output mode.
19
71
97
49
G3
14
-
10
-
RTO00_1
(PPG00_1)
D10
Waveform generator output of
multi-function timer 0.
(PPG00_0) This pin operates as PPG00 when it is
used in PPG 0 output mode.
Waveform generator output of
multi-function timer 0.
(PPG02_0) This pin operates as PPG02 when it is
used in PPG 0 output mode.
Waveform generator output of
multi-function timer 0.
(PPG02_0) This pin operates as PPG02 when it is
used in PPG 0 output mode.
Waveform generator output of
multi-function timer 0.
(PPG04_0) This pin operates as PPG04 when it is
used in PPG 0 output mode.
RTO01_0
20
21
22
23
24
98
99
100
1
H1
H2
G4
H3
J2
15
16
17
18
19
11
12
13
14
15
RTO02_0
RTO03_0
RTO04_0
Waveform generator output of
multi-function timer 0.
(PPG04_0) This pin operates as PPG04 when it is
used in PPG 0 output mode.
RTO05_0
2
38
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
Pin No
LQFP- QFP- BGA- LQFP-LQFP-
Module
Pin name
Function
100 100 112
80
64
QFN-
64
Multi
Function
Timer
1
Input signal of waveform generator to
control outputs RTO10 to RTO15 of
multi-function timer 1
DTTI1X_0
DTTI1X_1
8
86
17
D5
K6
8
-
39
29
-
FRCK1_0
FRCK1_1
IC10_0
IC10_1
IC11_0
IC11_1
IC12_0
IC12_1
IC13_0
IC13_1
87
44
88
40
89
41
90
42
91
43
65
22
66
18
67
19
68
20
69
21
D7
J7
67
34
68
30
69
31
70
32
71
33
-
-
-
-
-
-
-
-
-
-
16-bit free-run timer ch.1 external
clock input pin
A6
J6
B6
L7
C6
K7
A5
H6
16-bit input capture input pin of
multi-function timer 1.
ICxx describes channel number.
RTO10_0
(PPG10_0)
Waveform generator output of
multi-function timer 1.
This pin operates as PPG10 when it is
used in PPG 1 output mode.
2
27
3
80
5
C1
J4
2
-
-
-
-
-
-
-
-
-
-
-
-
-
RTO10_1
(PPG10_1)
RTO11_0
(PPG10_0)
Waveform generator output of
multi-function timer 1.
This pin operates as PPG10 when it is
used in PPG 1 output mode.
81
6
C2
L5
B3
K5
D1
J5
3
-
RTO11_1
(PPG10_1)
28
4
RTO12_0
(PPG12_0)
Waveform generator output of
multi-function timer 1.
This pin operates as PPG12 when it is
used in PPG 1 output mode.
82
7
4
-
RTO12_1
(PPG12_1)
29
5
RTO13_0
(PPG12_0)
Waveform generator output of
multi-function timer 1.
This pin operates as PPG12 when it is
used in PPG 1 output mode.
83
8
5
-
RTO13_1
(PPG12_1)
30
6
RTO14_0
(PPG14_0)
Waveform generator output of
multi-function timer 1.
This pin operates as PPG14 when it is
used in PPG 1 output mode.
84
9
D2
H5
D3
L6
6
21
7
22
RTO14_1
(PPG14_1)
31
7
RTO15_0
(PPG14_0)
Waveform generator output of
multi-function timer 1.
This pin operates as PPG14 when it is
used in PPG 1 output mode.
85
10
RTO15_1
(PPG14_1)
32
December 16, 2014, MB9A110A-DS706-00011-3v0-E
39
D a t a S h e e t
Pin No
LQFP- QFP- BGA- LQFP-LQFP-
Module
Pin name
Function
100 100 112
80
64
QFN-
64
Quadrature
Position/
Revolution
Counter
0
AIN0_0
AIN0_1
AIN0_2
BIN0_0
BIN0_1
BIN0_2
ZIN0_0
ZIN0_1
ZIN0_2
AIN1_1
AIN1_2
BIN1_1
BIN1_2
ZIN1_1
ZIN1_2
9
87
18
80
88
19
81
89
20
82
52
21
51
22
50
23
E1
J6
9
5
QPRC ch.0 AIN input pin
QPRC ch.0 BIN input pin
QPRC ch.0 ZIN input pin
40
2
30
2
22
2
C1
E2
L7
C2
E3
K7
B3
C10
H6
C11
J7
10
41
3
10
31
3
6
23
3
11
42
4
11
32
4
7
24
4
Quadrature
Position/
Revolution
Counter
1
74
43
73
44
72
45
60
33
59
34
58
35
-
QPRC ch.1 AIN input pin
QPRC ch.1 BIN input pin
QPRC ch.1 ZIN input pin
25
-
26
-
E8
K8
27
40
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
Pin No
LQFP- QFP- BGA- LQFP-LQFP-
Module
Pin name
Function
100 100 112
80
28
37
64
QFN-
64
RESET
Mode
External Reset Input. A reset is valid
when INITX= "L"
Mode 0 pin.
During normal operation, MD0= "L"
must be input. During serial
programming to flash memory, MD0=
"H" must be input.
Mode 1 pin.
INITX
MD0
38
47
16
25
K4
L8
21
29
MD1
During serial programming to flash
memory, MD1= "L" must be input.
Power supply pin
Power supply pin
Power supply pin
Power supply pin
Power supply pin
Power supply pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
46
24
K9
36
28
POWER
GND
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
X0
1
26
35
51
76
97
-
25
-
-
79
4
B1
J1
1
-
25
41
-
77
-
20
-
-
-
24
40
-
-
-
-
-
-
-
-
-
1
-
18
33
-
61
-
16
-
-
-
-
32
-
-
-
-
-
-
-
-
-
13
29
54
75
-
3
-
-
-
12
28
-
-
-
-
-
53
-
-
K1
K11
A10
A4
B2
L1
K2
J3
H4
L4
L11
K10
J9
H8
B10
C9
A11
D8
D4
C3
-
34
50
-
-
-
-
-
75
-
-
GND pin
GND pin
GND pin
GND pin
Main clock (oscillation) input pin
Sub clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) I/O pin
-
-
100
48
36
49
37
74
78
26
14
27
15
52
A1
L9
L3
L10
K3
C10
80
38
26
39
27
60
64
30
19
31
20
-
CLOCK
X0A
X1
X1A
CROUT_0
Built-in high-speed CR-osc clock
output port
CROUT_1
92
70
B5
72
57
Analog
POWER
A/D converter analog power supply
pin
AVCC
60
38
H11
50
41
A/D converter analog reference
voltage input pin
AVRH
AVSS
C
61
62
33
39
40
11
F11
G11
L2
51
52
23
42
43
17
Analog
GND
C pin
A/D converter GND pin
Power supply stabilization capacity
pin
December 16, 2014, MB9A110A-DS706-00011-3v0-E
41
D a t a S h e e t
I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
It is possible to select the
main oscillation / GPIO
function
Pull-up
resistor
When the main oscillation is
selected.
Oscillation feedback resistor
: Approximately 1MΩ
With Standby mode control
P-ch
P-ch
Digital output
Digital output
X1
When the GPIO is selected.
CMOS level output.
N-ch
R
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
Pull-up resistor control
Digital input
: Approximately 50kΩ
IOH = -4mA, IOL = 4mA
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
Digital output
P-ch
N-ch
P-ch
X0
Digital output
Pull-up resistor control
B
CMOS level hysteresis input
Pull-up resistor
: Approximately 50kΩ
Pull-up resistor
Digital input
42
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
Type
Circuit
Remarks
C
Open drain output
CMOS level hysteresis input
Digital input
Digital output
N-ch
D
It is possible to select the sub
oscillation / GPIO function
Pull-up
resistor
When the sub oscillation is
selected.
Oscillation feedback resistor
: Approximately 5MΩ
With Standby mode control
P-ch
Digital output
P-ch
X1A
When the GPIO is selected.
CMOS level output.
N-ch
Digital output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
R
Pull-up resistor control
Digital input
: Approximately 50kΩ
IOH = -4mA, IOL = 4mA
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
Digital output
P-ch
N-ch
P-ch
X0A
Digital output
Pull-up resistor control
December 16, 2014, MB9A110A-DS706-00011-3v0-E
43
D a t a S h e e t
Type
Circuit
Remarks
E
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50kΩ
P-ch
P-ch
N-ch
IOH = -4mA, IOL = 4mA
When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
+B input is available
Digital output
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
F
CMOS level output
CMOS level hysteresis input
With input control
Analog input
With pull-up resistor control
With standby mode control
Pull-up resistor
P-ch
N-ch
P-ch
Digital output
Digital output
: Approximately 50kΩ
IOH = -4mA, IOL = 4mA
When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
+B input is available
R
Pull-up resistor control
Digital input
Standby mode control
Analog input
Input control
44
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
Type
Circuit
Remarks
G
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50kΩ
IOH = -12mA, IOL = 12mA
+B input is available
P-ch
P-ch
Digital output
N-ch
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
H
CMOS level output
CMOS level hysteresis input
With standby mode control
IOH = -20.5mA, IOL= 18.5mA
Digital output
Digital output
N-ch
R
Digital input
Standby mode control
December 16, 2014, MB9A110A-DS706-00011-3v0-E
45
D a t a S h e e t
Type
Circuit
Remarks
I
CMOS level output
CMOS level hysteresis input
5V tolerant
With standby mode control
IOH = -4mA, IOL = 4mA
When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
P-ch
N-ch
Digital output
Digital output
R
Digital input
Standby mode control
J
CMOS level hysteresis input
Mode Input
46
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
HANDLING PRECAUTIONS
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your Spansion semiconductor devices.
1. Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to
prevent such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can
cause large current flows. Such conditions if present for extended periods of time can damage the
device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation.
Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may
be formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Code: DS00-00004-3E
December 16, 2014, MB9A110A-DS706-00011-3v0-E
47
D a t a S h e e t
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and equipment
such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.
Precautions Related to Usage of Devices
Spansion semiconductor devices are intended for use in standard applications (computers, office
automation and other office equipment, industrial, communications, and measurement equipment, personal
or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or
abnormal operation may directly affect human lives or cause physical injury or property damage, or where
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea
floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult
with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
2. Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat
resistance during soldering, you should only mount under Spansion's recommended conditions. For detailed
information about mount conditions, contact your sales representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the
board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the
soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for
storage temperature. Mounting processes should conform to Spansion recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads
are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch
results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder
bridges.
You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and has
established a ranking of mounting conditions for each product. Users are advised to mount packages in
accordance with Spansion ranking of recommended conditions.
48
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent,
do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Spansion packages semiconductor devices in highly moisture-resistant aluminum
laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags
for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion
recommended conditions for baking.
Condition: 125°C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus
for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high
resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to
minimize shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board
assemblies.
December 16, 2014, MB9A110A-DS706-00011-3v0-E
49
D a t a S h e e t
3. Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will
adversely affect the device. If you use devices in such conditions, consider ways to prevent such
exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation.
Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible
substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Spansion products in other special environmental conditions should
consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf
50
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
HANDLING DEVICES
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected
within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be
connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels,
to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the
total output current rating.
Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low
impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass
capacitor between each Power supply pin and GND pin, between AVCC pin and AVSS pin near this device.
Stabilizing power supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the
fluctuation is within the recommended operating conditions of the VCC power supply voltage.
As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation
in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not
exceed 10% of the VCC value in the recommended operating conditions, and the transient
fluctuation rate does not exceed 0.1 V/μs when there is a momentary fluctuation on switching
the power supply.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit
board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located
as close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins
are surrounded by ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Using an external clock
When using an external clock, the clock signal should be driven to the X0,X0A pin only and the X1,X1A
pin should be kept open.
Example of Using an External Clock
Device
X0(X0A)
Open
X1(X1A)
Handling when using Multi function serial pin as I2C pin
If it is using the multi function serial pin as I2C pins, P-ch transistor of digital output is always disabled.
However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external
I2C bus system with power OFF.
December 16, 2014, MB9A110A-DS706-00011-3v0-E
51
D a t a S h e e t
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the
regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor
of equivalent frequency characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance
variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select
the capacitor that meets the specifications in the operating conditions to use by evaluating
the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7μF would be recommended for this series.
C
Device
CS
VSS
GND
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the
pull-up/down resistor stays low, as well as the distance between the mode pins and VCC pins or VSS pins is
as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for
switching the pin level and rewriting the Flash memory data. It is because of preventing the device
erroneously switching to test mode due to noise.
Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter, connect AVCC = VCC and AVSS = VSS.
Turning on : VCC → AV CC → AVRH
Turning off : AVRH → AVCC → VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a
checksum of data at the end. If an error is detected, retransmit the data.
Differences in features among the products with different memory sizes and between
Flash products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and
oscillation characteristics among the products with different memory sizes and between Flash products and
MASK products are different because chip layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric
characteristics.
52
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
BLOCK DIAGRAM
MB9AF111LA/MA/NA, F112LA/MA/NA, F114LA/MA/NA, F115MA/NA, F116MA/NA
TRSTX,TCK,
TDI,TMS
SRAM0
8/16
Kbyte
SWJ-DP
TPIU*1
ETM*1
TDO
ROM
Table
TRACED[3:0],
TRACECLK
On-Chip
Flash
64/128/256/384/512
Kbyte
Cortex-M3 Core
@40 MHz(Max)
Flash I/F
Security
I
D
NVIC
Sys
SRAM1
8/16
Kbyte
Dual-Timer
WatchDog Timer
(Software)
Clock Reset
Generator
INITX
WatchDog Timer
(Hardware)
DMAC
8ch
CSV
CLK
Main
Source Clock
X0
PLL
Osc
Sub
Osc
X1
CR
4MHz
CR
100kHz
X0A
MAD[24:0]
CROUT
External Bus I/F*2
MADATA[15:0]
AVCC,
AVSS,AVRH
12-bit A/D Converter x 3
Unit 0
MCSX[7:0],
MOEX,MWEX,
MALE,
MRDY,
MCLKOUT,
MDQM[1:0]
AN[15:0]
ADTGx
Unit 1
Unit 2*2
Power-On
Reset
TIOA[7:0]
TIOB[7:0]
Base Timer
16-bit 8ch. /
32-bit 4ch.
LVD
LVD Ctrl
Regulator
C
IRQ-Monitor
AIN[1:0]
BIN[1:0]
ZIN[1:0]
QPRC
2ch.
CRC
Accelerator
A/D Activation
Compare
3ch.
Watch Counter
External Interrupt
Controller
16-pin + NMI
INT[15:0]
NMIX
IC0[3:0]
IC1[3:0]
16-bit Input Capture
4ch.
16-bit Free-Run
Timer
FRCK[1:0]
MD[1:0]
MODE-Ctrl
GPIO
3ch.
16-bit Output
Compare
6ch.
P0[F:0],
P1[F:0],
.
.
PIN-Function-Ctrl
DTTI[1:0]X
RTO0[5:0]
RTO1[5:0]
Waveform Generator
3ch.
.
Px[x:0]
SCK[7:0]
SIN[7:0]
SOT[7:0]
CTS4
Multi-Function Serial I/F
8ch.
16-bit PPG
3ch.
(with FIFO ch.4 to 7)
& HW flow control(ch.4)*2
RTS4
Multi-Function Timer x 2
*1: For the MB9AF111LA/MA, F112LA/MA, MB9AF114LA/MA, MB9AF115MA and MB9AF116MA,
ETM is not available.
*2: For the MB9AF111LA, F112LA and MB9AF114LA, the External Bus Interface and 12-bit A/D Converter
(unit 2) are not available. And the Multi-function Serial Interface does not support hardware flow control in
these products.
December 16, 2014, MB9A110A-DS706-00011-3v0-E
53
D a t a S h e e t
MEMORY SIZE
See "Memory size" in "PRODUCT LINEUP" to confirm the memory size.
54
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
MEMORY MAP
Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0xFFFF_FFFF
Reserved
0xE010_0000
0xE000_0000
Cortex-M3 Private
Peripherals
0x4006_1000
0x4006_0000
0x4005_0000
DMAC
Reserved
EXT-bus I/F
Reserved
0x4003_F000
Reserved
0x4003_B000
0x4003_A000
0x4003_9000
0x4003_8000
0x4003_7000
Watch Counter
CRC
0x7000_0000
0x6000_0000
External Device
Area
MFS
Reserved
LVD
Reserved
0x4003_5000
0x4400_0000
0x4200_0000
0x4000_0000
Reserved
32Mbytes
Bit band alias
0x4003_4000
0x4003_3000
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
GPIO
Reserved
Int-Req.Read
EXTI
Peripherals
Reserved
Reserved
CR Trim
0x2400_0000
0x2200_0000
32Mbytes
Bit band alias
Reserved
0x4002_8000
0x4002_7000
A/DC
Reserved
QPRC
0x4002_6000
0x4002_5000
Base Timer
PPG
0x2008_0000
0x2000_0000
0x1FF8_0000
SRAM1
SRAM0
Reserved
0x4002_2000
0x4002_1000
0x4002_0000
Reserved
See the next page
"nMemory Map
(2),(3)"
MFT Unit1
MFT Unit0
0x0010_2000
0x0010_0000
Security/CR Trim
for the memory size
details.
0x4001_6000
0x4001_5000
Dual Timer
Reserved
Flash
0x4001_3000
SW WDT
HW WDT
0x0000_0000
0x4001_2000
0x4001_1000
Clock/Reset
0x4001_0000
Reserved
Flash I/F
0x4000_1000
0x4000_0000
December 16, 2014, MB9A110A-DS706-00011-3v0-E
55
D a t a S h e e t
Memory Map (2)
MB9AF116MA/NA
MB9AF115MA/NA
MB9AF114LA/MA/NA
0x2008_0000
0x2008_0000
0x2008_0000
Reserved
Reserved
Reserved
0x2000_4000
0x2000_0000
0x1FFF_C000
0x2000_4000
0x2000_0000
0x1FFF_C000
0x2000_4000
0x2000_0000
0x1FFF_C000
SRAM1
16Kbytes
SRAM1
16Kbytes
SRAM1
16Kbytes
SRAM0
16Kbytes
SRAM0
16Kbytes
SRAM0
16Kbytes
Reserved
Reserved
Reserved
0x0010_2000
0x0010_1000
0x0010_0000
0x0010_2000
0x0010_1000
0x0010_0000
0x0010_2000
0x0010_1000
0x0010_0000
CR trimming
Security
CR trimming
Security
CR trimming
Security
Reserved
0x0008_0000
Reserved
Reserved
0x0006_0000
SA10-15(64KBx6)
0x0004_0000
SA10-13(64KBx4)
SA10-11(64KBx2)
SA8-9(48KBx2)
SA4-7(8KBx4)
SA8-9(48KBx2)
SA4-7(8KBx4)
SA8-9(48KBx2)
SA4-7(8KBx4)
0x0000_0000
0x0000_0000
0x0000_0000
*: See "MB9A310A/110A Series Flash programming Manual" for sector structure of Flash.
56
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
Memory Map (3)
MB9AF112LA/MA/NA
MB9AF111LA/MA/NA
0x2008_0000
0x2008_0000
Reserved
Reserved
0x2000_2000
0x2000_0000
0x1FFF_E000
0x2000_2000
0x2000_0000
0x1FFF_E000
SRAM1
8Kbytes
SRAM1
8Kbytes
SRAM0
8Kbytes
SRAM0
8Kbytes
Reserved
Reserved
0x0010_2000
0x0010_1000
0x0010_0000
0x0010_2000
0x0010_1000
0x0010_0000
CR trimming
Security
CR trimming
Security
Reserved
Reserved
0x0002_0000
0x0000_0000
0x0001_0000
0x0000_0000
SA8-9(48KBx2)
SA4-7(8KBx4)
SA8-9(16KBx2)
SA4-7(8KBx4)
* : See "MB9A310A/110A Series Flash programming Manual" for sector structure of Flash.
December 16, 2014, MB9A110A-DS706-00011-3v0-E
57
D a t a S h e e t
Peripheral Address Map
Start address
End address
Bus
Peripherals
0x4000_0000H
0x4000_1000H
0x4001_0000H
0x4001_1000H
0x4001_2000H
0x4001_3000H
0x4001_5000H
0x4001_6000H
0x4002_0000H
0x4002_1000H
0x4002_2000H
0x4002_4000H
0x4002_5000H
0x4002_6000H
0x4002_7000H
0x4002_8000H
0x4002_E000H
0x4002_F000H
0x4003_0000H
0x4003_1000H
0x4003_2000H
0x4003_3000H
0x4003_4000H
0x4003_5000H
0x4003_6000H
0x4003_7000H
0x4003_8000H
0x4003_9000H
0x4003_A000H
0x4003_B000H
0x4003_F000H
0x4004_0000H
0x4005_0000H
0x4006_0000H
0x4006_1000H
0x4006_2000H
0x4006_3000H
0x4006_4000H
0x4000_0FFFH
0x4000_FFFFH
0x4001_0FFFH
0x4001_1FFFH
0x4001_2FFFH
0x4001_4FFFH
0x4001_5FFFH
0x4001_FFFFH
0x4002_0FFFH
0x4002_1FFFH
0x4002_3FFFH
0x4002_4FFFH
0x4002_5FFFH
0x4002_6FFFH
0x4002_7FFFH
0x4002_DFFFH
0x4002_EFFFH
0x4002_FFFFH
0x4003_0FFFH
0x4003_1FFFH
0x4003_2FFFH
0x4003_3FFFH
0x4003_4FFFH
0x4003_5FFFH
0x4003_6FFFH
0x4003_7FFFH
0x4003_8FFFH
0x4003_9FFFH
0x4003_AFFFH
0x4003_EFFFH
0x4003_FFFFH
0x4004_FFFFH
0x4005_FFFFH
0x4006_0FFFH
0x4006_1FFFH
0x4006_2FFFH
0x4006_3FFFH
0x41FF_FFFFH
Flash Memory I/F register
Reserved
AHB
Clock/Reset Control
Hardware Watchdog timer
Software Watchdog timer
Reserved
APB0
Dual-Timer
Reserved
Multi-function timer unit0
Multi-function timer unit1
Reserved
PPG
Base Timer
APB1
Quadrature Position/Revolution Counter (QPRC)
A/D Converter
Reserved
Built-in CR trimming
Reserved
External Interrupt
Interrupt Source Check Register
Reserved
GPIO
Reserved
Low-Voltage Detector
APB2 Reserved
Reserved
Multi-function serial Interface
CRC
Watch Counter
Reserved
External Bus interface
Reserved
Reserved
DMAC register
Reserved
AHB
Reserved
Reserved
Reserved
58
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
PIN STATUS IN EACH CPU STATE
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the "L" level.
INITX=1
This is the period when the INITX pin is the "H" level.
SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register
(STB_CTL) is set to "0".
SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register
(STB_CTL) is set to "1".
Input enabled
Indicates that the input function can be used.
Internal input fixed at "0"
This is the status that the input function cannot be used. Internal input is fixed at "L".
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Trace output
Indicates that the trace function can be used.
December 16, 2014, MB9A110A-DS706-00011-3v0-E
59
D a t a S h e e t
List of Pin Status
Power-on reset
or low-voltage
detection state
Run mode or
SLEEP mode
state
INITX input Device internal
Timer mode or STOP mode
state
state
Power supply stable
INITX=0 INITX=1
reset state
Power supply
unstable
Power supply
stable
Pin status type Function group
Power supply stable
INITX=1
-
-
INITX=1
-
-
-
SPL=0
SPL=1
A
Hi-Z/ Internal
input fixed at
"0"
Setting
Setting
Maintain
Maintain
GPIO selected
Setting disabled
Input enabled
disabled
disabled
previous state
previous state
Main crystal
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
oscillator input pin
B
Hi-Z/
Setting
Setting
Maintain
Maintain
GPIO selected
Setting disabled
Internal input
fixed at "0"
disabled
disabled
previous state
previous state
Maintain
Maintain
previous state/ previous state/
Hi-Z/
Main crystal
oscillator output
pin
Hi-Z/
Hi-Z/
Hi-Z at
oscillation
stop*1/
Hi-Z at
oscillation
stop*1/
Internal input
fixed at "0"/
or Input enable
Maintain
Internal input
fixed at "0"
Internal input
fixed at "0"
previous state
Internal input
fixed at "0"
Internal input
fixed at "0"
C
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Pull-up/ Input
enabled
INITX input pin
D
Mode input pin
Input enabled
Hi-Z
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
E
JTAG
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Maintain
selected
previous state
Maintain
Maintain
Hi-Z/ Internal
input fixed at
"0"
previous state
previous state
GPIO
Setting
Setting
Setting disabled
Setting disabled
selected
disabled
disabled
F
Trace selected
Trace output
Setting
Setting
External interrupt
enabled selected
Maintain
disabled
disabled
previous state
Maintain
Maintain
GPIO
previous state
previous state
Hi-Z/
selected, or
Hi-Z/
Hi-Z/
Hi-Z
Internal input
fixed at "0"
resource other than
above selected
Input enabled
Input enabled
60
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
Power-on reset
or low-voltage
detection state
Run mode or
SLEEP mode
state
INITX input Device internal
state reset state
Timer mode or STOP mode
state
Power supply
unstable
Power supply
stable
Pin status type Function group
Power supply stable
INITX=0 INITX=1
Power supply stable
INITX=1
-
-
INITX=1
-
-
-
SPL=0
SPL=1
G
Setting
Setting
Trace selected
Setting disabled
Hi-Z
Trace output
disabled
disabled
Maintain
Maintain
GPIO selected, or
resource other than
above selected
Hi-Z/
previous state
previous state
Hi-Z/
Hi-Z/
Internal input
fixed at "0"
Input enabled
Input enabled
H
External interrupt
enabled selected
Setting
Setting
Maintain
Setting disabled
Hi-Z
disabled
disabled
previous state
Maintain
Maintain
GPIO selected, or
resource other than
above selected
Hi-Z/
previous state
previous state
Hi-Z/
Hi-Z/
Internal input
fixed at "0"
Input enabled
Input enabled
I
Hi-Z/ Internal
input fixed at
"0"
GPIO selected,
Hi-Z/
Hi-Z/
Maintain
Maintain
Hi-Z
Setting disabled
Hi-Z
resource selected
Input enabled
Input enabled
previous state
previous state
J
Setting
Setting
Maintain
NMIX selected
disabled
disabled
previous state
Maintain
Maintain
GPIO selected, or
resource other than
above selected
Hi-Z/
previous state
previous state
Hi-Z/
Hi-Z/
Internal input
fixed at "0"
Input enabled
Input enabled
December 16, 2014, MB9A110A-DS706-00011-3v0-E
61
D a t a S h e e t
Power-on reset
or low-voltage
detection state
Run mode or
SLEEP mode
state
INITX input Device internal
Timer mode or STOP mode
state
state
Power supply stable
INITX=0 INITX=1
reset state
Power supply
unstable
Power supply
stable
Pin status type Function group
Power supply stable
INITX=1
-
-
INITX=1
-
-
-
SPL=0
SPL=1
K
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Internal input
fixed at "0"/
Analog input
enabled
Internal input
fixed at "0"/
Analog input
enabled
Internal input
fixed at "0"/
Analog input
enabled
Internal input
fixed at "0"/
Analog input
enabled
Analog input
selected
Hi-Z
GPIO selected, or
resource other than
above selected
Hi-Z/
Setting
Setting
Maintain
Maintain
Setting disabled
Setting disabled
Internal input
fixed at "0"
disabled
disabled
previous state
previous state
L
External interrupt
enabled selected
Setting
Setting
Maintain
Maintain
Maintain
disabled
disabled
previous state
previous state
previous state
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Internal input
fixed at "0"/
Analog input
enabled
Internal input
fixed at "0"/
Analog input
enabled
Internal input
fixed at "0"/
Analog input
enabled
Internal input
fixed at "0"/
Analog input
enabled
Analog input
selected
Hi-Z
GPIO selected, or
resource other than
above selected
Hi-Z/
Setting
Setting
Maintain
Maintain
Setting disabled
Setting disabled
Input enabled
Internal input
fixed at "0"
disabled
disabled
previous state
previous state
M
Hi-Z/ Internal
input fixed at
"0"
Setting
Setting
Maintain
Maintain
GPIO selected
disabled
disabled
previous state
previous state
Sub crystal
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
oscillator input pin
62
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
Power-on reset
or low-voltage
detection state
Run mode or
SLEEP
mode state
INITX input Device internal
state reset state
Timer mode or STOP mode state
Power supply
unstable
Power
supply stable
Pin status type Function group
Power supply stable
INITX=0 INITX=1
Power supply stable
INITX=1
-
-
INITX=1
-
-
-
SPL=0
SPL=1
N
Maintain
previous
state
Hi-Z/
Setting
Setting
Maintain
GPIO selected
Setting disabled
Internal input
fixed at "0"
disabled
disabled
previous state
Maintain
previous state/
Hi-Z at
Maintain
previous state/
Hi-Z at
Hi-Z/
Internal input
fixed at "0"/
or Input
Sub crystal
oscillator output
pin
Hi-Z/
Hi-Z/
Maintain
previous
state
Internal input
fixed at "0"
Internal input
fixed at "0"
oscillation
stop*2/
oscillation
stop*2/
enabled
Internal input
fixed at "0"
Internal input
fixed at "0"
O
Maintain
previous
state
Hi-Z/ Internal
input fixed at
"0"
Hi-Z/
Hi-Z/
Maintain
GPIO pin
Hi-Z
Input enabled
Input enabled
previous state
P
Input
Mode input pin
Input enabled
Setting disabled
Input enabled
Input enabled
Input enabled
Input enabled
enabled
Maintain
previous
state
Setting
Setting
Maintain
Hi-Z/Input
enabled
GPIO selected
disabled
disabled
previous state
*1 : Oscillation is stopped at sub timer mode, low-speed CR timer mode, and stop mode.
*2 : Oscillation is stopped at stop mode.
December 16, 2014, MB9A110A-DS706-00011-3v0-E
63
D a t a S h e e t
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Min
Parameter
Symbol
Unit
Remarks
Max
Power supply voltage*1, *2
VCC
AVCC
AVRH
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS + 6.5
VSS + 6.5
VSS + 6.5
VCC + 0.5
(≤ 6.5V)
VSS + 6.5
AVCC + 0.5
(≤ 6.5V)
VCC + 0.5
(≤ 6.5V)
+2
V
V
V
Analog power supply voltage*1, *3
Analog reference voltage*1, *3
VSS - 0.5
VSS - 0.5
VSS - 0.5
V
V
V
Input voltage*1
VI
5V tolerant
Analog pin input voltage*1
Output voltage*1
VIA
VO
VSS - 0.5
-2
V
Clamp maximum current
ICLAMP
mA
*7
Clamp total maximum current
Σ[ICLAMP
]
+20
10
20
39
4
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
°C
*7
4mA type
12mA type
P80, P81
4mA type
12mA type
P80, P81
"L" level maximum output current*4
IOL
-
-
"L" level average output current*5
IOLAV
12
18.5
100
50
- 10
- 20
- 39
- 4
- 12
- 20.5
- 100
- 50
300
+ 150
"L" level total maximum output current
"L" level total average output current*6
∑IOL
∑IOLAV
-
-
4mA type
12mA type
P80, P81
4mA type
12mA type
P80, P81
"H" level maximum output current*4
IOH
-
-
"H" level average output current*5
IOHAV
"H" level total maximum output current
"H" level total average output current*6
Power consumption
∑IOH
∑IOHAV
PD
-
-
-
Storage temperature
TSTG
- 55
*1 : These parameters are based on the condition that VSS = AVSS = 0.0V.
*2 : Vcc must not drop below VSS - 0.5V.
*3 : Be careful not to exceed VCC + 0.5 V, for example, when the power is turned on.
*4 : The maximum output current is defined as the value of the peak current flowing through any one of the
corresponding pins.
*5 : The average output current is defined as the average current value flowing through any one of the
corresponding pins for a 100 ms period.
*6 : The total average output current is defined as the average current value flowing through all of
corresponding pins for a 100ms.
64
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
*7 :
・
・
・
・
・
See "LIST OF PIN FUNCTIONS" and "I/O CIRCUIT TYPE" about +B input available pin.
Use within recommended operating conditions.
Use at DC voltage (current) the +B input.
The +B signal should always be applied a limiting resistance placed between the +B signal and the device.
The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the device pin does not exceed rated values, either instantaneously or for prolonged periods.
Note that when the device drive current is low, such as in the low-power consumpsion modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC and AVCC pin, and
this may affect other devices.
・
・
・
Note that if a +B signal is input when the device power supply is off (not fixed at 0V), the power supply is
provided from the pins, so that incomplete operation may result.
The following is a recommended circuit example (I/O equivalent circuit).
Protection Diode
VCC
VCC
P-ch
Limiting
resistor
Digital output
Digital input
+B input (0V to 16V)
N-ch
R
AVCC
Analog input
<WARNING>
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
December 16, 2014, MB9A110A-DS706-00011-3v0-E
65
D a t a S h e e t
2. Recommended Operating Conditions
(Vss = AVss = 0.0V)
Value
Parameter
Symbol Conditions
Unit
Remarks
Min
2.7*2
2.7
Max
Power supply voltage
Analog power supply voltage
Analog reference voltage
Vcc
AVcc
AVRH
-
-
-
5.5
5.5
V
V
V
AVcc = Vcc
2.7
AVcc
For built-in
regulator*1
CS
-
1
10
μF
Smoothing capacitor
FPT-100P-M23
FPT-80P-M37
FPT-64P-M38
FPT-64P-M39
LCC-64P-M24
BGA-112P-M04
Ta
-
- 40
+ 105
°C
When
mounted on
four-layer
PCB
Operating
temperature
- 40
- 40
- 40
+ 105
+ 105
+ 85
°C
FPT-100P-M06
Ta
When
°C Icc ≤ 35mA
mounted on
double-sided
single-layer
PCB
°C Icc > 35mA
*1 : See " · C Pin" in "HANDLING DEVICES" for the connection of the smoothing capacitor.
*2 : In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage
or more, instruction execution and low voltage detection function by built-in High-speed CR(including
Main PLL is used) or built-in Low-speed CR is possible to operate only.
<WARNING>
The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure. No warranty is made
with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their representatives beforehand.
66
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
3. DC Characteristics
Current rating
(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, Ta = - 40°C to + 105°C)
Value
Pin
name
Parameter Symbol
Conditions
Unit Remarks
Typ*3 Max*4
CPU : 40MHz,
Peripheral : 40MHz,
Flash 0Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
*5
CPU : 40MHz,
Peripheral : 40MHz,
Flash 3Wait
FRWTR.RWT = 00
FSYNDN.SD = 011
*5
CPU/ Peripheral : 4MHz*2
Flash 0Wait
32
21
41
28
mA *1
PLL
RUN mode
mA *1
RUN
mode
current
Icc
High-speed
CR
RUN mode
3.9
0.15
0.2
7.7
3.2
3.3
mA *1
mA *1
mA *1
FRWTR.RWT = 00
FSYNDN.SD = 000
CPU/ Peripheral : 32kHz
Flash 0Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
*6
CPU/ Peripheral : 100kHz
Flash 0Wait
VCC
Sub
RUN mode
Low-speed
CR
RUN mode
FRWTR.RWT = 00
FSYNDN.SD = 000
Peripheral : 40MHz
PLL
10
1.2
0.1
0.1
15
4.4
3.1
3.1
mA *1
mA *1
mA *1
mA *1
SLEEP mode *5
High-speed
CR
SLEEP mode
Sub
Peripheral : 4MHz*2
SLEEP
mode
Iccs
Peripheral : 32kHz
current
SLEEP mode *6
Low-speed
CR
Peripheral : 100kHz
SLEEP mode
*1 : When all ports are fixed.
*2 : When setting it to 4MHz by trimming.
*3 : Ta=+25°C, VCC=5.5V
*4 : Ta=+105°C, VCC=5.5V
*5 : When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*6 : When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
December 16, 2014, MB9A110A-DS706-00011-3v0-E
67
D a t a S h e e t
(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, Ta = - 40°C to + 105°C)
Value
Pin
name
Parameter Symbol
Conditions
Unit Remarks
Typ*2 Max*2
Ta = + 25°C,
When LVD is off
*3
Ta = + 105°C,
When LVD is off
*3
Ta = + 25°C,
When LVD is off
*4
Ta = + 105°C,
When LVD is off
*4
2.5
-
3
mA *1
Main
TIMER
mode
6
mA *1
μA *1
mA *1
TIMER
mode
ICCT
current
60
-
230
3.1
VCC
Sub
TIMER
mode
Ta = + 25°C,
When LVD is off
Ta = + 105°C,
When LVD is off
35
-
200
3
μA *1
STOP
mode
current
ICCH
STOP mode
mA *1
*1 : When all ports are fixed.
*2 : VCC=5.5V
*3 : When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*4 : When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
· Low-Voltage Detection Current
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Max
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Typ
Low-voltage
At operation
for interrupt
Vcc = 5.5V
detection circuit
(LVD) power
supply current
ICCLVD
VCC
4
7
μA
At not detect
· Flash Memory Current
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Typ
Max
Flash memory
write/erase
current
ICCFLASH
VCC
At Write/Erase
11.4
13.1
mA
· A/D Converter Current
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, Ta = - 40°C to + 105°C)
Value
Max
Pin
name
Parameter
Symbol
Conditions
Unit
mA
μA
Remarks
Typ
At 1unit
operation
0.57
0.72
Power supply
current
ICCAD
AVCC
AVRH
At stop
0.06
1.1
20
At 1unit
operation
AVRH=5.5V
1.96
4
mA
Reference power
supply current
ICCAVRH
At stop
0.06
μA
68
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
Pin Characteristics
(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, Ta = - 40°C to + 105°C)
Value
Typ
Parameter Symbol Pin name Conditions
Unit Remarks
Min
Max
CMOS
"H" level
hysteresis
-
-
-
Vcc × 0.8
-
-
-
Vcc + 0.3
V
V
V
input
input pin,
MD0,1
5V tolerant
I/O pin
voltage
(hysteresis
input)
VIHS
Vcc × 0.8
Vss - 0.3
Vss + 5.5
Vcc × 0.2
"L" level input
voltage
(hysteresis
input)
CMOS
hysteresis
input pin,
MD0,1
VILS
Vcc ≥ 4.5 V
IOH = - 4mA
4mA type
Vcc - 0.5
-
Vcc
V
Vcc < 4.5 V
IOH = - 2mA
Vcc ≥ 4.5 V
IOH = - 12mA
Vcc < 4.5 V
IOH = - 8mA
Vcc ≥ 4.5 V
IOH = - 20.5mA
Vcc < 4.5 V
IOH = - 13.0mA
"H" level
output voltage
VOH
12mA type
P80, P81
Vcc - 0.5
Vcc - 0.4
Vss
-
-
-
-
Vcc
Vcc
0.4
V
V
V
Vcc ≥ 4.5 V
IOL = 4mA
4mA type
12mA type
Vcc < 4.5 V
IOL = 2mA
Vcc ≥ 4.5 V
IOL = 12mA
Vcc < 4.5 V
IOL = 8mA
Vcc ≥ 4.5 V
IOL = 18.5mA
Vcc < 4.5 V
IOL = 10.5mA
"L" level
output voltage
VOL
Vss
0.4
V
V
P80, P81
-
Vss
- 5
-
-
0.4
+ 5
Input leak
current
Pull-up
resistor
value
IIL
-
μA
kΩ
Vcc ≥ 4.5 V
25
30
50
80
100
200
RPU Pull-up pin
Other than
Vcc < 4.5 V
Input
capacitance
Vcc, Vss,
AVcc, AVss,
CIN
-
-
5
15
pF
AVRH
December 16, 2014, MB9A110A-DS706-00011-3v0-E
69
D a t a S h e e t
4. AC Characteristics
(1) Main Clock Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Value
Pin
name
Parameter
Input frequency
Input clock cycle
Symbol
Conditions
Unit
Remarks
Min
Max
48
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
PWH/tCYLH
PWL/tCYLH
4
4
4
4
When crystal oscillator
is connected
When using external
clock
When using external
clock
When using external
clock
MHz
MHz
ns
20
48
20
250
250
FCH
20.83
50
X0
X1
tCYLH
-
Input clock pulse
width
45
55
%
Input clock rising
time and falling
time
tCF
tCR
When using external
clock
-
-
5
ns
FCM
FCC
-
-
-
-
-
-
40
40
MHz Master clock
Base clock
(HCLK/FCLK)
MHz
Internal operating
clock*1
frequency
FCP0
FCP1
FCP2
-
-
-
-
-
-
-
-
-
40
40
40
MHz APB0 bus clock*2
MHz APB1 bus clock*2
MHz APB2 bus clock*2
Base clock
tCYCC
-
-
25
-
ns
(HCLK/FCLK)
Internal operating
clock*1
cycle time
-
-
-
-
-
-
25
25
25
-
-
-
ns
ns
ns
APB0 bus clock*2
APB1 bus clock*2
APB2 bus clock*2
tCYCP0
tCYCP1
tCYCP2
*1 : For more information about each internal operating clock, see "CHAPTER 2-1: Clock" in "FM3 Family
PERIPHERAL MANUAL".
*2 : For about each APB bus which each peripheral is connected to, see "BLOCK DIAGRAM" in this data
sheet.
X0
70
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
(2) Sub Clock Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Value
Typ
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
When crystal
-
-
32.768
-
kHz oscillator is
connected
Input frequency
FCL
When using
external clock
When using
external clock
When using
external clock
-
-
32
10
45
-
-
-
100
31.25
55
kHz
X0A
X1A
Input clock cycle
tCYLL
-
μs
Input clock pulse
width
PWH/tCYLL
PWL/tCYLL
%
X0A
(3) Built-in CR Oscillation Characteristics
Built-in high-speed CR
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Value
Typ Max
Parameter
Symbol
Conditions
Unit
MHz
μs
Remarks
Min
Ta = + 25°C
3.96
4
4.04
When trimming*1
Ta =
0°C to + 70°C
3.84
4
4.16
Clock frequency
FCRH
Ta =
3.8
3
4
4
-
4.2
5
- 40°C to + 105°C
Ta =
When not trimming
- 40°C to + 105°C
Frequency
stability time
2
tCRWT
-
-
90
*
*1 : In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming.
*2 : Frequency stable time is time to stable of the frequency of the High-speed CR.
clock after the trim value is set. After setting the trim value, the period when the frequency stability
time passes can use the High-speed CR clock as a source clock.
Built-in low-speed CR
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Value
Typ Max
Parameter
Symbol
Conditions
Unit
Remarks
Min
Clock frequency
FCRL
-
50
100
150
kHz
December 16, 2014, MB9A110A-DS706-00011-3v0-E
71
D a t a S h e e t
(4-1) Operating Conditions of Main PLL (In the case of using main clock for input clock of PLL)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
Remarks
Min Typ Max
PLL oscillation stabilization wait time
(LOCK UP time)*1
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiple rate
PLL macro oscillation clock frequency
Main PLL clock frequency*2
fPLLI
-
fPLLO
FCLKPLL
4
13
200
-
-
-
-
-
16
75
300
40
MHz
multiple
MHz
MHz
*1 : Time from when the PLL starts operating until the oscillation stabilizes.
*2 : For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family
PERIPHERAL MANUAL".
(4-2) Operating Conditions of Main PLL (In the case of using the built-in high speed CR for the
input clock of the main PLL)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
Remarks
Min Typ Max
PLL oscillation stabilization wait time
(LOCK UP time)*1
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiple rate
fPLLI
-
fPLLO
FCLKPLL
3.8
50
190
-
4
-
-
4.2
71
300
40
MHz
multiple
MHz
PLL macro oscillation clock frequency
Main PLL clock frequency*2
-
MHz
*1 : Time from when the PLL starts operating until the oscillation stabilizes.
*2 : For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family
PERIPHERAL MANUAL".
When setting PLL multiple rate, please take the accuracy of the built-in high-speed CR clock into account
and prevent the master clock from exceeding the maximum frequency.
Main PLL connection
Main PLL
clock
(CLKPLL)
PLL input
clock
PLL macro
oscillation clock
Main clock (CLKMO)
K
M
divider
Main
PLL
divider
High-speed CR clock (CLKHC)
N
divider
72
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
(5) Reset Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit Remarks
Min
Max
Reset input time
tINITX
INITX
-
500
-
ns
(6) Power-on Reset Timing
Parameter
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Value
Pin
name
Symbol
Unit
Remarks
Min
0
Max
Power supply rising time
Tr
-
-
ms
ms
Power supply shut down time
Toff
1
Vcc
Time until releasing
Power-on reset
Tprt
0.446
0.744
ms
VCC_minimum
VDH_minimum
VCC
0.2V
0.2V
0.2V
Tr
Tprt
Toff
Internal RST
CPU Operation
Glossary
RST Active
Release
start
・VCC_minimum : Minimum VCC of recommended operating conditions
・VDH_minimum : Minimum release voltage of Low-Voltage detection reset.
See "8. Low-Voltage Detection Characteristics"
December 16, 2014, MB9A110A-DS706-00011-3v0-E
73
D a t a S h e e t
(7) External Bus Timing
External bus clock output Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
tCYCLE
-
Pin name
Conditions
Unit
Min
Max
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
-
-
25
40
32
-
MHz
MHz
ns
Output frequency
MCLKOUT
Minimum clock cycle
time
31.25
-
ns
Note: The external bus clock output is a divided clock of HCLK. For more information about setting of clock
divider, see "CHAPTER 12: External Bus Interface" in "FM3 Family PERIPHERAL MANUAL"
When external bus clock is not output, this characteristic does not give any effect on external bus
operation.
MCLKOUT
External bus signal input/output Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol Conditions
Value
Unit
Remarks
VIH
0.8 × VCC
0.2 × VCC
0.8 × VCC
0.2 × VCC
V
V
V
V
Signal input characteristics
VIL
-
VOH
Signal output characteristics
VOL
VIH
VIL
VIH
VIL
Input signal
VOH
VOL
VOH
VOL
Output signal
74
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
Separate Bus Access Asynchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
tOEW
Pin name
Conditions
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
Max
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
MOEX
MOEX
MCLK×n-3
-
Min pulse width
MCSX ↓→ Address
output delay time
MOEX ↑ →
Address hold time
MCSX ↓→
MOEX ↓ delay time
MOEX ↑ →
MCSX ↑ time
-9
-12
+ 9
+ 12
MCSX[7:0]
MAD[24:0]
MOEX
tCSL – AV
tOEH - AX
tCSL - OEL
tOEH - CSH
tCSL - RDQML
tDS - OE
MCLK×m+9
MCLK×m+12
MCLK×m-9 MCLK×m+9
0
MAD[24:0]
Vcc < 4.5V MCLK×m-12 MCLK×m+12
MOEX
MCSX[7:0]
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
MCLK×m+9
MCLK×m+12
MCLK×m-9 MCLK×m+9
0
MCSX ↓ →
MCSX
MDQM[1:0]
MOEX
MADATA[15:0]
MOEX
MADATA[15:0]
MDQM ↓ delay time
Data set up →
MOEX ↑ time
MOEX ↑ →
Data hold time
MWEX
Min pulse width
MWEX ↑ → Address
output delay time
MCSX ↓ →
MWEX ↓ delay time
MWEX ↑ →
MCSX ↑ delay time
MCSX ↓ →
MDQM ↓ delay time
MCSX ↓ →
Data output time
MWEX ↑ →
Vcc < 4.5V MCLK×m-12 MCLK×m+12
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
20
38
-
-
tDH - OE
0
-
-
tWEW
MWEX
MCLK×n-3
MCLK×m+9
MCLK×m+12
MCLK×n+9
MWEX
MAD[24:0]
tWEH - AX
tCSL - WEL
tWEH - CSH
tCSL-WDQML
tCSL - DV
tWEH - DX
0
MCLK×n-9
Vcc < 4.5V MCLK×n-12 MCLK×n+12
MWEX
MCSX[7:0]
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
MCLK×m+9
MCLK×m+12
MCLK×n+9
0
MCLK×n-9
MCSX
MDQM[1:0]
MCSX
MADATA[15:0]
MWEX
MADATA[15:0]
Vcc < 4.5V MCLK×n-12 MCLK×n+12
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
MCLK-9
MCLK+9
MCLK+12
MCLK-12
MCLK×m+9
MCLK×m+12
0
Data hold time
Note: When the external load capacitance CL = 30pF (m = 0 to 15, n = 1 to 16).
December 16, 2014, MB9A110A-DS706-00011-3v0-E
75
D a t a S h e e t
tCYCLE
MCLK
tOEH-CSH
tWEH-CSH
tWEH-AX
MCSX[7:0]
MAD[24:0]
MOEX
tCSL-AV
tOEH-AX
tCSL-AV
Address
Address
tCSL-OEL
tOEW
tCSL-WDQML
tCSL-RDQML
MDQM[1:0]
MWEX
tCSL-WEL
tWEW
tDS-OE
tDH-OE
tWEH-DX
Invalid
MADATA[15:0]
RD
WD
tCSL-DV
76
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
Separate Bus Access Synchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
tAV
Pin name
Conditions
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
Max
9
12
9
12
9
12
9
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
MCLK
MAD[24:0]
Address delay time
1
tCSL
1
1
1
1
MCLK
MCSX[7:0]
MCSX delay time
MOEX delay time
tCSH
tREL
12
9
12
MCLK
MOEX
tREH
tDS
19
37
Data set up →
MCLK ↑ time
MCLK ↑→
MCLK
MADATA[15:0]
MCLK
MADATA[15:0]
-
-
tDH
0
Data hold time
9
12
9
12
9
12
9
12
tWEL
tWEH
tDQML
tDQMH
tODS
tOD
1
MCLK
MWEX
MWEX delay time
1
1
1
MDQM[1:0]
delay time
MCLK
MDQM[1:0]
MCLK+18
MCLK+24
18
MCLK ↑ →
Data output time
MCLK ↑ →
MCLK,
MADATA[15:0]
MCLK
MCLK+1
1
1
Data output time
MADATA[15:0]
24
Note: When the external load capacitance CL = 30pF.
tCYCLE
MCLK
tCSL
tCSH
MCSX[7:0]
tAV
tAV
Address
Address
MAD[24:0]
tREL
tREH
MOEX
tDQML
tDQMH
tDQML
tDQMH
tWEH
tOD
MDQM[1:0]
tWEL
MWEX
tDS
tDH
RD
Invalid
WD
MADATA[15:0]
tODS
December 16, 2014, MB9A110A-DS706-00011-3v0-E
77
D a t a S h e e t
Multiplexed Bus Access Asynchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Max
10
Vcc ≥ 4.5V
Multiplexed
Address delay time
tALE-CHMADV
0
ns
Vcc < 4.5V
20
MALE
MADATA[15:0]
Vcc ≥ 4.5V
MCLK×n+0 MCLK×n+10
MCLK×n+0 MCLK×n+20
Multiplexed
Address hold time
tCHMADH
ns
Vcc < 4.5V
Note: When the external load capacitance CL = 30pF (m = 0 to 15, n = 1 to 16).
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
78
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
Multiplexed Bus Access Synchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Value
Max
Parameter
Symbol
tCHAL
Pin name
Conditions
Unit Remarks
Min
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
9
12
9
ns
ns
ns
ns
1
MCLK
ALE
MALE delay time
tCHAH
1
1
12
MCLK ↑ →
Multiplexed
Address delay time
MCLK ↑ →
Multiplexed
Data output time
Vcc ≥ 4.5V
tCHMADV
tOD
ns
ns
MCLK
MADATA[15:0]
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
tCHMADX
1
tOD
Note: When the external load capacitance CL = 30pF.
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
December 16, 2014, MB9A110A-DS706-00011-3v0-E
79
D a t a S h e e t
External Ready Input Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol Pin name Conditions
Unit Remarks
Min
19
Max
MCLK ↑
MRDY input
setup time
Vcc ≥ 4.5V
MCLK
MRDY
tRDYI
-
ns
Vcc < 4.5V
37
When RDY is input
···
MCLK
Over 2cycles
Original
MOEX
MWEX
tRDYI
MRDY
When RDY is released
··· ···
MCLK
2 cycles
Extended
MOEX
MWEX
tRDYI
0.5×VCC
MRDY
80
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
(8) Base Timer Input Timing
Timer input timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit Remarks
Min
Max
TIOAn/TIOBn
(when using as
ECK,TIN)
tTIWH
tTIWL
Input pulse width
-
2tCYCP
-
ns
tTIWH
tTIWL
ECK
TIN
VIHS
VIHS
VILS
VILS
Trigger input timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol Pin name Conditions
Unit Remarks
Min
Max
TIOAn/TIOBn
tTRGH
tTRGL
Input pulse width
(when using as
TGIN)
-
2tCYCP
-
ns
tTRGH
tTRGL
TGIN
VIHS
VIHS
VILS
VILS
Note: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see "BLOCK DIAGRAM" in this
data sheet.
December 16, 2014, MB9A110A-DS706-00011-3v0-E
81
D a t a S h e e t
(9) CSIO/UART Timing
CSIO (SPI = 0, SCINV = 0)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Vcc < 4.5V
Vcc ≥ 4.5V
Pin
name
SCKx
SCKx
SOTx
SCKx
SINx
Parameter
Serial clock cycle time
SCK ↓ → SOT delay time
Symbol
Conditions
Unit
ns
Min
Max
Min
Max
tSCYC
4tcycp
-
4tcycp
-
tSLOVI
- 30
50
0
+ 30
- 20
30
0
+ 20
ns
Master mode
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑→ SIN hold time
tIVSHI
tSHIXI
tSLSH
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
SCKx
SINx
2tcycp -
10
2tcycp -
10
SCKx
SCKx
-
-
tcycp +
10
tcycp +
10
tSHSL
-
-
SCKx
SOTx
SCKx
SINx
SCKx
SINx
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
30
-
Slave mode
10
20
10
20
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes: The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "BLOCK
DIAGRAM" in this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30pF.
82
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
SOT
SIN
VOH
VOL
tIVSHI
VIH
VIL
tSHIXI
VIH
VIL
Master mode
tSLSH
tSHSL
VIH
VIH
tR
VIH
SCK
VIL
VIL
F
t
tSLOVE
VOH
VOL
SOT
SIN
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
Slave mode
December 16, 2014, MB9A110A-DS706-00011-3v0-E
83
D a t a S h e e t
CSIO (SPI = 0, SCINV = 1)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Vcc < 4.5V
Vcc ≥ 4.5V
Pin
name
SCKx
SCKx
SOTx
SCKx
SINx
Parameter
Symbol
tSCYC
Conditions
Unit
ns
Min
4tcycp
Max
-
Min
4tcycp
Max
-
Serial clock cycle time
SCK ↑ → SOT delay time
tSHOVI
- 30
50
0
+ 30
- 20
30
0
+ 20
ns
Master mode
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
tIVSLI
tSLIXI
tSLSH
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
SCKx
SINx
2tcycp -
10
2tcycp -
10
SCKx
SCKx
-
-
tcycp +
10
tcycp +
10
tSHSL
-
-
SCKx
SOTx
SCKx
SINx
SCKx
SINx
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
30
-
Slave mode
10
20
10
20
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes: The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "BLOCK
DIAGRAM" in this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30pF.
84
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
tSCYC
VOH
VOH
SCK
VOL
tSHOVI
SOT
SIN
VOH
VOL
tIVSLI
VIH
VIL
tSLIXI
VIH
VIL
Master mode
tSHSL
tSLSH
VIH
VIH
tF
SCK
VIL
VIL
tR
VIL
tSHOVE
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
December 16, 2014, MB9A110A-DS706-00011-3v0-E
85
D a t a S h e e t
CSIO (SPI = 1, SCINV = 0)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Vcc < 4.5V
Vcc ≥ 4.5V
Pin
name
SCKx
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SOTx
Parameter
Symbol
tSCYC
Conditions
Unit
ns
Min
4tcycp
Max
-
Min
4tcycp
Max
-
Serial clock cycle time
SCK ↑→ SOT delay time
tSHOVI
- 30
50
0
+ 30
- 20
30
0
+ 20
ns
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
SOT → SCK ↓ delay time
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
tIVSLI
tSLIXI
tSOVLI
tSLSH
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
Master mode
2tcycp -
30
2tcycp -
30
-
-
2tcycp -
10
2tcycp -
10
SCKx
SCKx
-
-
tcycp +
10
tcycp +
10
tSHSL
-
-
SCKx
SOTx
SCKx
SINx
SCKx
SINx
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
30
-
Slave mode
10
20
10
20
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes: The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "BLOCK
DIAGRAM" in this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30pF.
86
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
tSCYC
VOH
VOL
VOL
SCK
tSHOVI
tSOVLI
VOH
VOL
VOH
VOL
SOT
SIN
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
Master mode
tSLSH
tSHSL
SCK
VIH
tF
VIH
VIL
VIH
VIL
tSHOVE
tR
*
VOH
VOL
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
December 16, 2014, MB9A110A-DS706-00011-3v0-E
87
D a t a S h e e t
CSIO (SPI = 1, SCINV = 1)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Vcc < 4.5V
Vcc ≥ 4.5V
Pin
name
SCKx
Parameter
Symbol
Conditions
Unit
Min
Max
-
Min
Max
-
Serial clock cycle time
tSCYC
4tcycp
4tcycp
ns
SCKx
SOTx
tSLOVI
- 30
+ 30
- 20
+ 20
ns
SCK ↓→ SOT delay time
SCKx
SINx
SCKx
SINx
SCKx
SOTx
tIVSHI
tSHIXI
tSOVHI
tSLSH
50
0
-
-
30
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
SIN → SCK ↑ setup time
SCK ↑ →SIN hold time
SOT → SCK ↑ delay time
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
Master mode
2tcycp -
30
2tcycp -
10
tcycp +
10
2tcycp -
30
2tcycp -
10
tcycp +
10
-
-
SCKx
SCKx
-
-
tSHSL
-
-
SCKx
SOTx
SCKx
SINx
SCKx
SINx
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
30
-
Slave mode
10
20
10
20
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes: The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "BLOCK
DIAGRAM" in this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30pF.
88
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
tSCYC
VOL
VOH
VOH
SCK
tSOVHI
tSLOVI
VOH
VOL
VOH
VOL
SOT
SIN
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
Master mode
tSHSL
tSLSH
tR
tF
VIH
SCK
VIH
VIH
VIL
VIL
VIL
tSLOVE
SOT
SIN
VOH
VOL
VOH
VOL
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
Slave mode
UART external clock input (EXT = 1)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol Conditions
Min
Max
Unit Remarks
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK falling time
tSLSH
tSHSL
tF
tcycp + 10
tcycp + 10
-
-
5
5
ns
ns
ns
ns
CL = 30pF
-
-
SCK rising time
tR
tR
VIL
tF
VIH
tSHSL
tSLSH
SCK
VIH
VIH
VIL
VIL
December 16, 2014, MB9A110A-DS706-00011-3v0-E
89
D a t a S h e e t
(10) External input timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Value
Min
Parameter Symbol Pin name Conditions
Unit
Remarks
Max
A/D converter
trigger input
Free-run timer input
clock
Input capture
Wave form
ADTG
-
2tCYCP
*
*
-
ns
FRCKx
ICxx
tINH
tINL
Input pulse width
DTTIxX
-
2tCYCP
-
-
-
ns
ns
ns
generator
Except
2tCYCP + 100*
500
Timer mode,
Stop mode
Timer mode,
Stop mode
INTxx,
NMIX
External interrupt
NMI
* : tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are
connected to, see "BLOCK DIAGRAM" in this data sheet.
90
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
(11) Quadrature Position/Revolution Counter timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Conditions
Unit
Min
Max
AIN pin "H" width
AIN pin "L" width
BIN pin "H" width
BIN pin "L" width
BIN rise time from
AIN pin "H" level
AIN fall time from
BIN pin "H" level
BIN fall time from
AIN pin "L" level
tAHL
tALL
tBHL
tBLL
-
-
-
-
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
QCR:CGSC = "0"
QCR:CGSC = "0"
tAUBU
tBUAD
tADBD
tBDAU
tBUAU
tAUBD
tBDAD
tADBU
AIN rise time from
BIN pin "L" level
AIN rise time from
BIN pin "H" level
BIN fall time from
AIN pin "H" level
AIN fall time from
BIN pin "L" level
2tCYCP
*
-
ns
BIN rise time from
AIN pin "L" level
ZIN pin "H" width
ZIN pin "L" width
AIN/BIN rise and fall time
from determined ZIN level
Determined ZIN level from
AIN/BIN rise and fall time
tZHL
tZLL
tZABE
tABEZ
QCR:CGSC = "1"
QCR:CGSC = "1"
* : tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Quadrature Position/Revolution Counter is connected to, see "BLOCK
DIAGRAM" in this data sheet.
tALL
tAHL
AIN
BIN
tADBD
tAUBU
tBUAD
tBDAU
tBHL
tBLL
December 16, 2014, MB9A110A-DS706-00011-3v0-E
91
D a t a S h e e t
tBLL
tBHL
BIN
AIN
tBDAD
tBUAU
tAUBD
tADBU
tAHL
tALL
ZIN
ZIN
AIN/BIN
92
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
(12) I2C timing
Parameter
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Standard-mode Fast-mode
Symbol Conditions
Unit Remarks
Min
Max
Min Max
SCL clock frequency
(Repeated) START condition
hold time
FSCL
0
100
0
400
kHz
tHDSTA
4.0
-
0.6
-
μs
SDA ↓→ SCL ↓
SCLclock "L" width
SCLclock "H" width
(Repeated) START condition
setup time
SCL ↑ → SDA ↓
Data hold time
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
tLOW
tHIGH
4.7
4.0
-
-
1.3
0.6
-
-
μs
μs
tSUSTA
4.7
-
0.6
-
μs
CL = 30pF,
R =
(Vp/IOL)*1
tHDDAT
tSUDAT
tSUSTO
0
3.45*2
0
0.9*3
μs
ns
μs
250
4.0
-
-
100
0.6
-
-
Bus free time between
"STOP condition" and
"START condition"
Noise filter
tBUF
tSP
4.7
-
-
1.3
-
-
μs
4
4
-
2 tCYCP
*
2 tCYCP
*
ns
*1 : R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2 : The maximum tHDDAT must satisfy that it doesn't extend at least "L" period (tLOW) of device's SCL signal.
*3 : Fast-mode I2C bus device can be used on Standard-mode I2C bus system as long as the device satisfies the
requirement of "tSUDAT ≥ 250 ns".
*4 : tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see "BLOCK DIAGRAM" in this data sheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
December 16, 2014, MB9A110A-DS706-00011-3v0-E
93
D a t a S h e e t
(13) ETM timing
Parameter
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Value
Symbol
Pin name
Conditions
Vcc ≥ 4.5V
Vcc < 4.5V
Unit
Remarks
Min Max
2
9
TRACECLK
TRACED[3:0]
Data hold
tETMH
ns
2
15
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
-
-
40 MHz
32 MHz
TRACECLK
frequency
1/tTRACE
TRACECLK
25
-
-
ns
ns
TRACECLK
Clock cycle time
tTRACE
31.25
Note: When the external load capacitance CL = 30pF.
HCLK
TRACECLK
TRACED[3:0]
94
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
(14) JTAG timing
Parameter
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Value
Symbol Pin name Conditions
Unit
ns
Remarks
Min
Max
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
TMS, TDI setup
time
TCK
TMS,TDI
tJTAGS
15
-
TCK
TMS,TDI
TMS, TDI hold time tJTAGH
15
-
-
ns
25
45
TCK
TDO
TDO delay time
tJTAGD
ns
Vcc < 4.5V
-
Note: When the external load capacitance CL = 30pF.
TCK
TMS/TDI
TDO
December 16, 2014, MB9A110A-DS706-00011-3v0-E
95
D a t a S h e e t
5. 12-bit A/D Converter
Electrical Characteristics for the A/D Converter
(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, Ta = - 40°C to + 105°C)
Value
Typ
-
Pin
name
-
Parameter
Symbol
Unit
bit
Remarks
Min
-
Max
12
Resolution
Integral
-
-
-
-
± 1.7
± 4.5
LSB
Nonlinearity
Differential
Nonlinearity
Zero transition voltage
Full-scale transition
voltage
-
-
-
-
-
± 1.7
± 8
± 2.5
± 15
LSB
mV
AVRH = 2.7V to 5.5V
VZT
VFST
ANxx
ANxx
AVRH±8 AVRH±15 mV
1.0*1
1.2*1
*2
-
-
AVcc ≥ 4.5V
AVcc < 4.5V
AVcc ≥ 4.5V
AVcc < 4.5V
Conversion time
Sampling time
-
-
-
-
-
-
μs
ns
ns
μs
pF
-
-
-
-
Ts
*2
Compare clock cycle*3
Tcck
Tstt
CAIN
50
-
-
-
-
2000
1.0
State transition time to
operation permission
Analog input capacity
Analog input resistor
-
12.9
2
3.8
4
AVcc ≥ 4.5V
AVcc < 4.5V
RAIN
-
-
-
-
-
-
-
-
kΩ
LSB
μA
Interchannel disparity
Analog port input
current
-
-
ANxx
5
Analog input voltage
Reference voltage
-
-
ANxx
AVRH
AVSS
2.7
-
-
AVRH
AVCC
V
V
*1 : The conversion time is the value of sampling time (Ts) + compare time (Tc).
The condition of the minimum conversion time is the following.
AVcc ≥ 4.5V, HCLK=40MHz sampling time: 300ns, compare time: 700ns
AVcc < 4.5V, HCLK=40MHz sampling time: 500ns, compare time: 700ns
Ensure that it satisfies the value of the sampling time (Ts) and compare clock cycle (Tcck).
For setting of the sampling time and compare clock cycle, see "CHAPTER 1-1: A/D Converter" in "FM3
Family PERIPHERAL MANUAL Analog Macro Part".
The A/D Converter register is set at APB bus clock timing. The sampling clock and compare clock are set at
Base clock (HCLK).
About the APB bus number which the A/D Converter is connected to, see "BLOCK DIAGRAM" in this
data sheet.
*2 : A necessary sampling time changes by external impedance.
Ensure that it set the sampling time to satisfy (Equation 1)
*3 : The compare time (Tc) is the value of (Equation 2)
96
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
Comparator
ANxx
Analog input pin
Rext
RAIN
Analog
signal source
CAIN
(Equation 1) Ts ≥ (RAIN + Rext) × CAIN × 9
Ts : Sampling time
RAIN : input resistor of A/D = 2kΩ
input resistor of A/D = 3.8kΩ
4.5 ≤ AVCC ≤ 5.5
2.7 ≤ AVCC < 4.5
CAIN : input capacity of A/D = 12.9pF 2.7 ≤ AVCC ≤ 5.5
Rext : Output impedance of external circuit
(Equation 2) Tc = Tcck × 14
Tc : Compare time
Tcck : Compare clock cycle
December 16, 2014, MB9A110A-DS706-00011-3v0-E
97
D a t a S h e e t
Definition of 12-bit A/D Converter Terms
Resolution
Integral Nonlinearity
: Analog variation that is recognized by an A/D converter.
: Deviation of the line between the zero-transition point
(0b000000000000←→0b000000000001) and the full-scale transition point
(0b111111111110←→0b111111111111) from the actual conversion
characteristics.
Differential Nonlinearity : Deviation from the ideal value of the input voltage that is required to change
the output code by 1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
Actual conversion
characteristics
characteristics
0xFFE
0xFFD
0x(N+1)
0xN
{1 LSB(N-1) + VZT}
VFST
Ideal characteristics
(Actually-
measured
value)
VNT
0x004
0x003
0x002
0x001
(Actually-measured
value)
V(N+1)T
(Actually-measured
value)
0x(N-1)
0x(N-2)
Actual conversion
characteristics
VNT
(Actually-measured
value)
Ideal characteristics
(Actually-measured value)
Analog input
VZT
Actual conversion characteristics
AVSS
AVRH
AVSS
AVRH
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
[LSB]
V(N + 1) T - VNT
- 1 [LSB]
1LSB
VFST – VZT
1LSB =
4094
N
VZT
: A/D converter digital output value.
: Voltage at which the digital output changes from 0x000 to 0x001.
VFST : Voltage at which the digital output changes from 0xFFE to 0xFFF.
VNT : Voltage at which the digital output changes from 0x(N − 1) to 0xN.
98
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
6. Low-voltage detection characteristics
Low-voltage detection reset
(Ta = - 40°C to + 105°C)
Value
Min Typ Max
Parameter
Symbol Conditions
Unit
Remarks
Detected voltage
Released voltage
VDL
VDH
-
-
2.25
2.30
2.45
2.50
2.65
2.70
V
V
When voltage drops
When voltage rises
Interrupt of low-voltage detection
(Ta = - 40°C to + 105°C)
Value
Min Typ Max
Parameter
Symbol Conditions
Unit
Remarks
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
2.58
2.67
2.76
2.85
2.94
3.04
3.31
3.40
3.40
3.50
3.68
3.77
3.77
3.86
3.86
3.96
2.8
2.9
3.0
3.1
3.2
3.3
3.6
3.7
3.7
3.8
4.0
4.1
4.1
4.2
4.2
4.3
3.02
3.13
3.24
3.34
3.45
3.56
3.88
3.99
3.99
4.10
4.32
4.42
4.42
4.53
4.53
4.64
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
SVHI = 0000
VDH
VDL
SVHI = 0001
VDH
VDL
SVHI = 0010
VDH
VDL
SVHI = 0011
VDH
VDL
SVHI = 0100
VDH
VDL
SVHI = 0111
VDH
VDL
SVHI = 1000
VDH
VDL
SVHI = 1001
VDH
LVD stabilization
wait time
2240 ×
tcycp *
TLVDW
-
-
-
μs
* : tCYCP indicates the APB2 bus clock cycle time.
December 16, 2014, MB9A110A-DS706-00011-3v0-E
99
D a t a S h e e t
7. Flash Memory Write/Erase Characteristics
(1) Write / Erase time
(Vcc = 2.7V to 5.5V, Ta = - 40°C to + 105°C)
Value
Parameter
Unit
s
Remarks
Typ*
0.7
0.3
Max*
3.7
1.1
Large Sector
Includes write time prior to
internal erase
Sector erase time
Small Sector
Half word (16 bit)
write time
Not including system-level
overhead time.
12
384
μs
64K/128K/256KByte
384K/512KByte
5.2
8
23.6
38.4
s
s
Chip
erase time
Includes write time prior to
internal erase
* : The typical value is immediately after shipment, the maximam value is guarantee value under 100,000
cycle of erase/write.
(2) Erase/write cycles and data hold time
Erase/write cycles
(cycle)
Data hold time
(year)
Remarks
1,000
10,000
100,000
20*
10*
5*
* : At average + 85C
100
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
8. Return Time from Low-Power Consumption Mode
(1) Return Factor: Interrupt
The return time from Low-Power consumption mode is indicated as follows. It is from
receiving the return factor to starting the program operation.
・Return Count Time
(VCC = 2.7V to 5.5V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
Remarks
Typ
Max*
SLEEP mode
tCYCC
ns
High-speed CR TIMER mode,
Main TIMER mode,
40
80
μs
PLL TIMER mode
Ticnt
Low-speed CR TIMER mode
Sub TIMER mode
STOP mode
453
453
453
737
737
737
μs
μs
μs
* : The maximum value depends on the accuracy of built-in CR.
・Operation example of return from Low-Power consumption mode (by external interrupt*)
Ext.INT
Interrupt factor
Active
accept
Ticnt
Interrupt factor
clear by CPU
CPU
Operation
Start
* : External interrupt is set to detecting fall edge.
December 16, 2014, MB9A110A-DS706-00011-3v0-E
101
D a t a S h e e t
・Operation example of return from Low-Power consumption mode (by internal resource interrupt*)
Internal
Resource INT
Interrupt factor
Active
accept
Ticnt
Interrupt factor
clear by CPU
CPU
Operation
Start
* : Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
・The return factor is different in each Low-Power consumption modes.
See "CHAPTER 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3
Family PERIPHERAL MANUAL about the return factor from Low-Power consumption mode.
・When interrupt recoveries, the operation mode that CPU recoveries depends on the state before
the Low-Power consumption mode transition. See "CHAPTER 6: Low Power Consumption
Mode" in "FM3 Family PERIPHERAL MANUAL".
102
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
(2) Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from
releasing reset to starting the program operation.
・Return Count Time
(VCC = 2.7V to 5.5V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
Remarks
Typ
Max*
SLEEP mode
308
444
μs
High-speed CR TIMER mode,
Main TIMER mode,
308
444
μs
PLL TIMER mode
Trcnt
Low-speed CR TIMER mode
Sub TIMER mode
STOP mode
428
428
428
684
684
684
μs
μs
μs
* : The maximum value depends on the accuracy of built-in CR.
・Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
December 16, 2014, MB9A110A-DS706-00011-3v0-E
103
D a t a S h e e t
・Operation example of return from low power consumption mode (by internal resource reset*)
Internal
Resource RST
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
・The return factor is different in each Low-Power consumption modes.
See "CHAPTER 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3
Family PERIPHERAL MANUAL.
・When interrupt recoveries, the operation mode that CPU recoveries depends on the state before
the Low-Power consumption mode transition. See "CHAPTER 6: Low Power Consumption
Mode" in "FM3 Family PERIPHERAL MANUAL".
・The time during the power-on reset/low-voltage detection reset is excluded. See "(6) Power-on
Reset Timing in 4. AC Characteristics in ■ELECTRICAL CHARACTERISTICS" for the detail
on the time during the power-on reset/low -voltage detection reset.
・When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main
clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or
the main PLL clock stabilization wait time.
・The internal resource reset means the watchdog reset and the CSV reset.
104
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
ORDERING INFORMATION
On-chip
Flash
memory
On-chip
SRAM
Part number
Package
Packing
MB9AF111LAPMC1-G-JNE2
MB9AF112LAPMC1-G-JNE2
MB9AF114LAPMC1-G-JNE2
MB9AF111LAPMC-G-JNE2
MB9AF112LAPMC-G-JNE2
MB9AF114LAPMC-G-JNE2
MB9AF111LAQN-G-AVE2
MB9AF112LAQN-G-AVE2
MB9AF114LAQN-G-AVE2
MB9AF111MAPMC-G-JNE2
MB9AF112MAPMC-G-JNE2
MB9AF114MAPMC-G-JNE2
MB9AF115MAPMC-G-JNE2
MB9AF116MAPMC-G-JNE2
MB9AF111NAPMC-G-JNE2
MB9AF112NAPMC-G-JNE2
MB9AF114NAPMC-G-JNE2
MB9AF115NAPMC-G-JNE2
MB9AF116NAPMC-G-JNE2
MB9AF111NAPF-G-JNE1
MB9AF112NAPF-G-JNE1
MB9AF114NAPF-G-JNE1
MB9AF115NAPF-G-JNE1
MB9AF116NAPF-G-JNE1
MB9AF111NABGL-GE1
64Kbyte
128Kbyte
256Kbyte
64Kbyte
16Kbyte
16Kbyte
32Kbyte
16Kbyte
16Kbyte
32Kbyte
16Kbyte
16Kbyte
32Kbyte
16Kbyte
16Kbyte
32Kbyte
32Kbyte
32Kbyte
16Kbyte
16Kbyte
32Kbyte
32Kbyte
32Kbyte
16Kbyte
16Kbyte
32Kbyte
32Kbyte
32Kbyte
16Kbyte
16Kbyte
32Kbyte
Plastic LQFP
(0.5mm pitch), 64-pin
(FPT-64P-M38)
Plastic LQFP
128Kbyte
256Kbyte
64Kbyte
(0.65mm pitch), 64-pin
(FPT-64P-M39)
Plastic QFN
128Kbyte
256Kbyte
64Kbyte
(0.5mm pitch), 64-pin
(LCC-64P-M24)
128Kbyte
256Kbyte
384Kbyte
512Kbyte
64Kbyte
Plastic LQFP
(0.5mm pitch), 80-pin
(FPT-80P-M37)
Tray
128Kbyte
256Kbyte
384Kbyte
512Kbyte
64Kbyte
Plastic LQFP
(0.5mm pitch), 100-pin
(FPT-100P-M23)
128Kbyte
256Kbyte
384Kbyte
512Kbyte
64Kbyte
Plastic QFP
(0.65mm pitch), 100-pin
(FPT-100P-M06)
Plastic PFBGA
MB9AF112NABGL-GE1
128Kbyte
256Kbyte
(0.8mm pitch), 112-pin
(BGA-112P-M04)
MB9AF114NABGL-GE1
December 16, 2014, MB9A110A-DS706-00011-3v0-E
105
D a t a S h e e t
PACKAGE DIMENSIONS
100-pin plastic LQFP
Lead pitch
0.50 mm
14.00 mm × 14.00 mm
Gullwing
Package width ×
package length
Lead shape
Lead bend
direction
Normal bend
Plastic mold
1.70 mm MAX
0.65 g
Sealing method
Mounting height
Weight
(FPT-100P-M23)
100-pin plastic LQFP
(FPT-100P-M23)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
*14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
+0.20
1.50
-0.10
+.008
(.059
)
-.004
(Mounting height)
INDEX
0°~8°
0.10±0.10
100
26
(.004±.004)
(Stand off)
0.50±0.20
(.020±.008)
"A"
0.25(.010)
0.60±0.15
1
25
(.024±.006)
0.50(.020)
0.22±0.05
(.009±.002)
0.145±0.055
(.006±.002)
M
0.08(.003)
Dimensions in mm (inches).
Note:The values in parentheses are reference values.
C
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F100034S-c-3-4
106
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
100-pin plastic QFP
Lead pitch
0.65 mm
14.00 × 20.00 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Plastic mold
3.35 mm MAX
P-QFP100-14×20-0.65
Code
(Reference)
(FPT-100P-M06)
100-pin plastic QFP
(FPT-100P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
*
20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
*14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
31
0.25(.010)
3.00–+00..3205
.118+–..001048
(Mounting height)
0~8°
1
30
0.65(.026)
0.32±0.05
(.013±.002)
0.17±0.06
(.007±.002)
M
0.13(.005)
0.25±0.20
(.010±.008)
(Stand off)
0.80±0.20
(.031±.008)
0.88±0.15
"A"
(.035±.006)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2002-2010 FUJITSU SEMICONDUCTOR LIMITED F100008S-c-5-7
December 16, 2014, MB9A110A-DS706-00011-3v0-E
107
D a t a S h e e t
80-pin plastic LQFP
Lead pitch
0.50 mm
12.00 mm × 12.00 mm
Gullwing
Package width ×
package length
Lead shape
Lead bend
direction
Normal bend
Plastic mold
1.70 mm MAX
0.47 g
Sealing method
Mounting height
Weight
(FPT-80P-M37)
80-pin plastic LQFP
(FPT-80P-M37)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00± 0.20(.551± .008)SQ
*12.00± 0.10(.472± .004)SQ
0.145± 0.055
(.006± .002)
60
41
Details of "A" part
61
40
1.50–+00..1200
(Mounting height)
.059–+..000048
0.25(.010)
0~8°
0.08(.003)
0.50± 0.20
(.020± .008)
0.60± 0.15
0.10± 0.05
(.004± .002)
(Stand off)
(.024± .006)
INDEX
80
21
"A"
1
20
0.50(.020)
0.22± 0.05
M
0.08(.003)
(.009± .002)
Dimensions in mm (inches).
C
Note: The values in parentheses are reference values.
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F80037S-c-1-2
108
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
64-pin plastic LQFP
Lead pitch
0.50 mm
10.00 mm × 10.00 mm
Gullwing
Package width ×
package length
Lead shape
Lead bend
direction
Normal bend
Plastic mold
1.70 mm MAX
0.32 g
Sealing method
Mounting height
Weight
(FPT-64P-M38)
64-pin plastic LQFP
(FPT-64P-M38)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
*10.00±0.10(.394±.004)SQ
0.145 ± 0.055
(.006 ± .002)
48
33
Details of "A" part
49
32
1.50–+00..1200
0.08(.003)
(Mounting height)
.059–+..000048
0.25(.010)
0~8°
INDEX
0.50±0.20
(.020±.008)
0.60 ± 0.15
(.024±.006)
0.10 ± 0.10
(.004±.004)
(Stand off)
64
17
"A"
1
16
0.50(.020)
0.22±0.05
M
0.08(.003)
(.009±.002)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2010 FUJITSU SEMICONDUCTOR LIMITED F64038S-c-1-2
December 16, 2014, MB9A110A-DS706-00011-3v0-E
109
D a t a S h e e t
64-pin plastic LQFP
Lead pitch
0.65 mm
12.00 mm × 12.00 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm MAX
0.47 g
(FPT-64P-M39)
64-pin plastic LQFP
(FPT-64P-M39)
Note 1) Pins width and pins thickness include plating thickness.
14.00±0.20(.551±.008)SQ
12.00±0.10(.472±.004)SQ
48
33
Details of "A" part
49
32
1.50–+00..1200
.059–+..000048
0~8˚
0.10(.004)
0.10±0.10
(.004±.004)
INDEX
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)BSC
64
17
1
16
"A"
0.65(.026)
0.32±0.05
(.013±.002)
M
0.13(.005)
C
Dimensions in mm (inches).
2010-2011 FUJITSU SEMICONDUCTOR LIMITED HMbF64-39Sc-2-2
Note: The values in parentheses are referencevalues.
110
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
112-ball plastic PFBGA
Ball pitch
0.80 mm
10.00 × 10.00 mm
Soldering ball
Plastic mold
Ф 0.45 mm
Package width ×
package length
Lead shape
Sealing method
Ball size
Mounting height
Weight
1.45 mm Max.
0.22 g
(BGA-112P-M04)
112-ball plastic PFBGA
(BGA-112P-M04)
10.00±0.10(.394±.004)
0.20(.008) S
B
0.80(.031)
REF
B
11
10
9
0.80(.031)
REF
8
A
7
10.00±0.10
(.394±.004)
6
5
4
3
2
1
L
K
J
H
G
F
E D
C
B
A
(INDEX AREA)
0.20(.008) S
1.25±0.20
(.049±.008)
(Seated height)
INDEX
0.35±0.10
(.014±.004)
(Stand off)
A
112-Ф0.45±010
(112-Ф0.18±.004)
M
Ф0.08(.003) S A B
S
0.10(.004) S
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2003-2010 FUJITSU SEMICONDUCTOR LIMITED B112004S-c-2-3
December 16, 2014, MB9A110A-DS706-00011-3v0-E
111
D a t a S h e e t
64-pin plastic QFN
Lead pitch
0.50 mm
9.00 mm × 9.00 mm
Plastic mold
0.90 mm MAX
-
Package width ×
package length
Sealing method
Mounting height
Weight
(LCC-64P-M24)
64-pin plastic QFN
(LCC-64P-M24)
9.00±0.10
(.354±.004)
6.00±0.10
(.236±.004)
0.25±0.05
(.010±.002)
6.00±0.10
(.236±.004)
9.00±0.10
(.354±.004)
INDEX AREA
0.45 (.018)
1PIN ID
(0.20R (.008R))
0.50 (.020)
(TYP)
0.40±0.05
(.016±.002)
0.85±0.05
(.033±.002)
0.05 (.002) MAX
(0.20 (.008))
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2011 FUJITSU SEMICONDUCTOR LIMITED HMbC64-24Sc-2-1
112
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
MAJOR CHANGES
Page
Section
Change Results
Revision 1.0
-
-
Initial release
Revision 2.0
• Revised series name and part number:
MB9A110 Series→MB9A110A Series
MB9AF111L → MB9AF111LA
MB9AF112L → MB9AF112LA
MB9AF114L → MB9AF114LA
MB9AF111M → MB9AF111MA
MB9AF112M → MB9AF112MA
MB9AF114M → MB9AF114MA
MB9AF115M → MB9AF115MA
MB9AF116M → MB9AF116MA
MB9AF111N → MB9AF111NA
MB9AF112N → MB9AF112NA
MB9AF114N → MB9AF114NA
MB9AF115N → MB9AF115NA
MB9AF116N → MB9AF116NA
-
-
•Added the package.
LCC-64P-M24
PRODUCT LINEUP
Added the following description.
ch.4 to ch.7: FIFO (16steps × 9-bit)
ch.0 to ch.3: No FIFO
• Function
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
8
Corrected the following description.
7pins (Max) → 8pins (Max)
• External Interrupts
SIGNAL DESCRIPTION
Multi-function Serial (ch.0 to ch.7)
Corrected the description for function.
34 to
37
•Added "LIN pin"
• Deleted "UART pin"
I/O CIRCUIT TYPE
• Corrected the following schematic for "TypeB".
CMOS level hysteresis input → Digital input
42, 43
• Corrected the following schematic for "TypeC".
Control Pin → Digital output
HANDLING DEVICES
Corrected the description.
51
54
• Power supply pins
MEMORY SIZE
Added " MEMORY SIZE".
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
Added the items FCM to the Internal operating clock frequency.
69
(1) Main Clock Input Characteristics
(4-2) Operating Conditions of Main PLL
Added the description.
71
72
(7) External Bus Timing
• External bus clock output Characteristics
(8) Base Timer Input Timing
Added the Note.
79
88
• Trigger input timing
(10) External input timing
6. 12-bit A/D Converter
Corrected the footnote.
• Corrected the value of "Full-scale transition voltage".
Min: -20 → AVRH-20
• Electrical characteristics for the A/D
converter
Max: +20 → AVRH+20
94
• Corrected the value of "Compare clock cycle".
Max: 10000 → 2000
• Corrected the value of "Reference voltage".
Min: AVSS → 2.7
Revision 2.1
-
-
Company name and layout design change
Revision 3.0
FEATURES
External Bus Interface
3
Added the description of Maximum area size
9
PACKAGES
Deleted FPT-64P-M24, FPT-64P-M23, FPT-80P-M21, FPT-100P-M20
Added the description of I2C to the type of E, F and I
Added about +B input
44, 46
44, 45
51
I/O CIRCUIT TYPE
I/O CIRCUIT TYPE
HANDLING DEVICES
Added "Stabilizing power supply voltage"
December 16, 2014, MB9A110A-DS706-00011-3v0-E
113
D a t a S h e e t
Page
Section
Change Results
HANDLING DEVICES
Crystal oscillator circuit
HANDLING DEVICES
C Pin
Added the following description
"Evaluate oscillation of your using crystal oscillator by your mount board."
51
52
53
54
Changed the description
BLOCK DIAGRAM
Modified the block diagram
Changed to the following description
See "Memory size" in "PRODUCT LINEUP" to confirm the memory size.
MEMORY SIZE
MEMORY MAP
· Memory map(1)
MEMORY MAP
· Memory map(2)(3)
55
Modified the area of "Extarnal Device Area"
56, 57
Added the summary of Flash memory sector and the note
· Added the Clamp maximum current
· Added the output current of P80 and P81
· Added about +B input
· Modified the minimum value of Analog reference voltage
· Added Smoothing capacitor
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
64, 65
66
ELECTRICAL CHARACTERISTICS
2. Recommended Operation Conditions
· Added the note about less than the minimum power supply voltage
· Changed the table format
· Added Main TIMER mode current
· Added Flash Memory Current
ELECTRICAL CHARACTERISTICS
3. DC Characteristics
(1) Current rating
67, 68
71
· Moved A/D Converter Current
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
Added Frequency stability time at Built-in high-speed CR
(3) Built-in CR Oscillation Characteristics
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(4-1)(4-2) Operating Conditions of Main
PLL
· Added Main PLL clock frequency
· Added the figure of Main PLL connection
72
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(6) Power-on Reset Timing
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(7) External Bus Timing
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
· Added Time until releasing Power-on reset
· Changed the figure of timing
73
75-77
82-89
Modified Data output time
· Modified from UART Timing to CSIO/UART Timing
· Changed from Internal shift clock operation to Master mode
· Changed from External shift clock operation to Slave mode
· Added the typical value of Integral Nonlinearity, Differential Nonlinearity,
Zero transition voltage and Full-scale transition voltage
· Modified Stage transition time to operation permission
· Modified the minimum value of Reference voltage
(8) CSIO/UART Timing
ELECTRICAL CHARACTERISTICS
5. 12bit A/D Converter
96
ELECTRICAL CHARACTERISTICS
9. Return Time from Low-Power
Consumption Mode
101
Added Return Time from Low-Power Consumption Mode
105
106
ORDERING INFORMATION
PACKAGE DIMENSIONS
Change to full part number
Deleted FPT-64P-M24, FPT-64P-M23, FPT-80P-M21, FPT-100P-M20
114
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
December 16, 2014, MB9A110A-DS706-00011-3v0-E
115
D a t a S h e e t
116
MB9A110A-DS706-00011-3v0-E, December 16, 2014
D a t a S h e e t
December 16, 2014, MB9A110A-DS706-00011-3v0-E
117
D a t a S h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use
where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not
be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the
products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in
this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and
Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a
Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any
product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to
its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party
rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind
arising out of the use of the information in this document.
Copyright © 2011-2014 Spansion All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM
ORNANDTM, Easy DesignSimTM, TraveoTM and combinations thereof, are trademarks and registered trademarks of
,
Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be
trademarks of their respective owners.
118
MB9A110A-DS706-00011-3v0-E, December 16, 2014
相关型号：
MB9AF115MPMC
RISC Microcontroller, 32-Bit, FLASH, CORTEX-M3 CPU, 40MHz, CMOS, PQFP80, 12 X 12 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-80
CYPRESS
©2020 ICPDF网 联系我们和版权申明