MB84VD21091EM-70PBS_技术文档

TM

SPANSION MCP

Data Sheet

September 2003

This document specifies SPANSION^TMmemory products that are now offered by both Advanced Micro Devices and

Fujitsu. Although the document is marked with the name of the company that originally developed the specification,

these products will be offered to customers of both AMD and Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a SPANSION^TMproduct. Future routine

revisions will occur when appropriate, and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these

products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about SPANSION^TMmemory

solutions.

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-50306-1E

Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM

CMOS

16M (×8/×16) FLASH MEMORY &

2M (×8/×16) STATIC RAM

MB84VD2108XEM^-70/MB84VD2109XEM^-70

■ FEATURES

• Power Supply Voltage of 2.7 V to 3.3 V

• High Performance

70 ns maximum access time (Flash)

70 ns maximum access time (SRAM)

• Operating Temperature

–40 °C to +85 °C

• Package 56-ball BGA

(Continued)

■ PRODUCT LINE UP

Part No.

MB84VD2108XEM/MB84VD2109XEM

+0.3 V

–0.3 V

+0.3 V

–0.3 V

Supply Voltage(V)

V^CCf= 3.0 V

V^CCs= 3.0 V

Max Address Access Time (ns)

Max CE Access Time (ns)

Max OE Access Time (ns)

70

30

70

35

Note: Both V^CCf and V^CCs must be in recommended operation range when either part is being accessed.

■ PACKAGE

56-ball plastic BGA

(BGA-56P-M02)

MB84VD2108XEM/2109XEM-70

(Continued)

• FLASH MEMORY

• Simultaneous Read/Write Operations (Dual Bank)

Miltiple devices available with different bank sizes (Please refer to ORDERING INFORMATION)

Host system can program or erase in one bank, then immediately and simultaneously read from the other bank

Zero latency between read and write operations

Read-while-erase

Read-while-program

• Minimum 100,000 Write/Erase Cycles

• Sector Erase Architecture

Eight 4 K words and thirty one 32 K words.

Any combination of sectors can be concurrently erased. Also supports full chip erase.

• Boot Code Sector Architecture

MB84VD2108XEM: Top sector

MB84VD2109XEM: Bottom sector

• Embedded Erase^TM* Algorithms

Automatically pre-programs and erases the chip or any sector

• Embedded Program^TM* Algorithms

Automatically writes and verifies data at specified address

• Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion

• Ready-Busy Output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic Sleep Mode

When addresses remain stable, automatically switch themselves to low power mode.

• Low V^CCWrite Inhibit ≤ 2.5 V

• HiddenROM Region

64K byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence

Factory serialized and protected to provide a secure electronic serial number (ESN)

• WP/ACC Input Pin

At V^IL, allows protection of boot sectors, regardless of sector protection/unprotection status

(MB84VD2108XEM:SA37,SA38 MB84VD2109XEM:SA0,SA1)

At V^IH, allows removal of boot sector protection

At V^ACC, program time will reduse by 40%.

• Erase Suspend/Resume

Suspends the erase operation to allow a read in another sector within the same device

• Please refer to “MBM29DL16XTE/BE” Datasheet in Detailed Function

* : Embedded Erase^TMand Embedded Program^TMare trademarks of Advanced Micro Devices, Inc.

• SRAM

• Power Dissipation

Operating : 40 mA Max

Standby : 7 µA Max

• Power Down Features using CE1s and CE2s

• Data Retention Supply Voltage: 1.5 V to 3.3 V

• CE1s and CE2s Chip Select

• Byte Data Control: LB (DQ⁷to DQ⁰), UB (DQ¹⁵to DQ⁸)

2

MB84VD2108XEM/2109XEM-70

■ PIN ASSIGNMENT

(Top View)

Marking side

B8

C8

D8

E8

F8

G8

A15

N.C.

A16

CIOf

Vss

A7

B7

C7

D7

E7

SA

F7

G7

H7

A11

A12

A13

A14

DQ15/A-1

DQ7

DQ14

A6

A8

B6

C6

A9

D6

E6

F6

G6

H6

A19

A10

DQ6

DQ13

DQ12

DQ5

A5

B5

C5

F5

G5

H5

WE

CE2s

N.C.

DQ4

Vccs

CIOs

INDEX

LAND*

A4

B4

C4

F4

G4

H4

WP/ACC RESET RY/BY

DQ3

Vccf

DQ11

A3

LB

B3

C3

D3

E3

F3

G3

H3

UB

A18

A17

DQ1

DQ9

DQ10

DQ2

A2

A7

B2

A6

C2

A5

D2

A4

E2

F2

G2

H2

VSS

OE

DQ0

DQ8

B1

A3

C1

A2

D1

A1

E1

A0

F1

G1

CEf

CE1s

* : There is no solder ball. This land should be open electrically.

(BGA-56P-M02)

3

MB84VD2108XEM/2109XEM-70

■ PIN DESCRIPTION

Pin Name

A¹⁶to A⁰

A¹⁹to A¹⁷, A^-1

SA

Function

Address Inputs (Common)

Address Input (Flash)

Input/Output

I

Address Input (SRAM)

Data Inputs / Outputs (Common)

Chip Enable (Flash)

I

DQ¹⁵to DQ⁰

CEf

I/O

I

CE1s

Chip Enable (SRAM)

CE2s

Chip Enable (SRAM)

OE

Output Enable (Common)

Write Enable (Common)

WE

Ready/Busy Outputs (Flash) Open Drain

Output

RY/BY

O

UB

LB

Upper Byte Control (SRAM)

Lower Byte Control (SRAM)

I

I/O Configuration (Flash)

CIOf

CIOf=V^CCf is Word mode ( ×16),

CIOf=V^SSis Byte mode ( × 8)

I

I/O Configuration (SRAM)

CIOs

CIOs=V^CCs is Word mode (×16),

CIOs=V^SSis Byte mode (× 8)

I

Hardware Reset Pin / Sector Protection Un-

lock (Flash)

RESET

WP/ACC

N.C.

Write Protect / Acceleration (Flash)

No Internal Connection

I

—

V^SS

Device Ground (Common)

Device Power Supply (Flash)

Device Power Supply (SRAM)

Power

V^CCf

V^CCs

4

MB84VD2108XEM/2109XEM-70

■ BLOCK DIAGRAM

V^CCf

V^SS

A¹⁹to A⁰

RY/BY

A¹⁹to A⁰

A^–1

WP/ACC

RESET

CEf

16 M bit

Flash Memory

DQ¹⁵/A–¹to DQ⁰

CIOf

DQ¹⁵/A–¹to DQ⁰

V^CCs

V^SS

A¹⁶to A⁰

DQ¹⁵to DQ⁰

2 M bit

SA

LB

Static RAM

UB

WE

OE

CE1s

CE2s

CIOs

5

MB84VD2108XEM/2109XEM-70

■ DEVICE BUS OPERATIONS

User Bus Operations Table (Flash = Word mode; CIOf = V^CCf, SRAM = Word mode; CIOs = V^CCs)

WP/

DQ⁷to

DQ⁰

DQ¹⁵to

DQ⁸

Operation *^1,*³

ACC

CEf CE1s CE2s OE WE SA LB UB

RESET

5

*

H

X

L

Full Standby

H

L

X

High-Z

H

X

H

X

H

X

H

X

H

High-Z

L

H

Output Disable

H

X

H

X

H

X

L

X

L

X

L

H

L

H

L

X

High-Z

D^OUT

D^IN

High-Z

D^OUT

D^IN

Read from Flash *²

Write to Flash

L

H

X

L

H

L

H

L

D^OUT

High-Z

D^OUT

D^IN

D^OUT

Read from SRAM

Write to SRAM

H

L

H

L

H

L

X

H

X

H

L

High-Z

D^IN

L

H

X

H

L

High-Z

D^IN

H

High-Z

Temporary Sector

Group Unprotection *⁴

X

High-Z

X

High-Z

X

V^ID

L

X

L

H

X

L

Flash Hardware

Reset

Boot Block Sector

Write Protection

X

Legend: L = V^IL, H = V^IH, X = V^ILor V^IH. See DC Characteristics for voltage levels.

*1 : Other operations except for indicated this column are inhibited.

*2 : WE can be V^ILif OE is V^IL, OE at V^IHinitiates the write operations.

*3 : Do not apply CEf = V^IL, CE1s = V^ILand CE2s = V^IHat a time.

*4 : It is also used for the extended sector group protections.

*5 : WP/ACC = V^IL; protection of boot sectors.

WP/ACC = V^IH; removal of boot sectors protection.

WP/ACC = V^ACC(9 V) ; Program time will reduce by 40%.

6

MB84VD2108XEM/2109XEM-70

User Bus Operations Table (Flash = Word mode; CIOf = V^CCf, SRAM = Byte mode; CIOs = V^SS)

WP/

DQ⁷to

DQ⁰

DQ¹⁵to

DQ⁸

Operation *^1,*³

ACC

CEf CE1s CE2s OE WE SA LB UB

RESET

5

*

H

X

L

Full Standby

H

L

X

High-Z

H

X

H

X

H

X

H

X

H

High-Z

L

H

Output Disable

H

X

H

X

H

X

L

X

L

H

L

H

L

X

High-Z

D^OUT

D^IN

High-Z

D^OUT

D^IN

X

L

Read from Flash *²

Write to Flash

L

H

X

L

H

Read from SRAM

Write to SRAM

H

L

H

L

SA

X

D^OUT

D^IN

High-Z

H

X

L

X

Temporary Sector

X

High-Z

X

High-Z

X

V^ID

L

X

L

Group Unprotection *⁴

H

X

L

Flash Hardware

Reset

Boot Block Sector

Write Protection

X

Legend: L = V^IL, H = V^IH, X = V^ILor V^IH. See DC Characteristics for voltage levels.

*1 : Other operations except for indicated this column are inhibited.

*2 : WE can be V^ILif OE is V^IL, OE at V^IHinitiates the write operations.

*3 : Do not apply CEf = V^IL, CE1s = V^ILand CE2s = V^IHat a time.

*4 : It is also used for the extended sector group protections.

*5 : WP/ACC = V^IL; protection of boot sectors.

WP/ACC = V^IH; removal of boot sectors protection.

WP/ACC = V^ACC(9 V); Program time will reduce by 40%.

7

MB84VD2108XEM/2109XEM-70

User Bus Operations Table (Flash = Byte mode; CIOf = V^SS, SRAM = Byte mode; CIOs = V^SS)

WP/

DQ⁷to

DQ⁰

DQ¹⁴

to DQ⁸

Operation *^1,*³

ACC

CEf CE1s CE2s DQ¹⁵/A^–1OE WE SA LB UB

RESET

5

*

H

X

L

Full Standby

H

L

X

High-Z High-Z

H

X

H

X

H

X

H

X

H

High-Z High-Z

L

H

Output Disable

H

X

H

X

H

X

L

X

L

A^–1

H

L

H

L

X

High-Z High-Z

X

L

Read from Flash *²

Write to Flash

L

D^OUT

High-Z

H

X

L

H

D^IN

Read from SRAM

Write to SRAM

H

X

L

H

L

SA

X

D^OUT

D^IN

High-Z

H

X

L

X

Temporary Sector

X

V^ID

L

X

L

Group Unprotection *⁴

H

X

L

Flash Hardware Re-

set

High-Z High-Z

Boot Block Sector

Write Protection

X

Legend: L = V^IL, H = V^IH, X = V^ILor V^IH. See DC Characteristics for voltage levels.

*1 : Other operations except for indicated this column are inhibited.

*2 : WE can be V^ILif OE is V^IL, OE at V^IHinitiates the write operations.

*3 : Do not apply CEf = V^IL, CE1s = V^ILand CE2s = V^IHat a time.

*4 : It is also used for the extended sector group protections.

*5 : WP/ACC = V^IL; protection of boot sectors.

WP/ACC = V^IH; removal of boot sectors protection.

WP/ACC = V^ACC(9 V); Program time will reduce by 40%.

8

MB84VD2108XEM/2109XEM^-70

■ ABSOLUTE MAXIMUM RATINGS

Rating

Parameter

Symbol

Unit

Min

–55

–40

Max

+125

Storage Temperature

Tstg

T^A

°C

V

Ambient Temperature with Power Applied

+85

V^CCf +0.4

V^CCs +0.4

+4.0

Voltage with Respect to Ground All pins

except RESET, WP/ACC *¹

VIN, VOUT

–0.3

V

VCCf/VCCs Supply *¹

RESET *²

VCCf, VCCs

VIN

–0.3

–0.5

V

+ 13.0

+10.5

V

WP/ACC *³

VIN

V

*1 : Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may undershoot

VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf+0.4 V or VCCs+0.4 V.

During voltage transitions, input or I/O pins may overshoot to VCCf+2.0 V or VCCs+2.0 V for periods of up to 20 ns.

*2 : Minimum DC input voltage on RESET pin is –0.5 V. During voltage transitions, RESET pins may undershoot

VSS to –2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCCf or VCCs)

does not exceed +9.0 V. Maximum DC input voltage on RESET pins is +13.0 V which may overshoot to +14.0 V

for periods of up to 20 ns.

*3 : Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may undershoot

Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may

overshoot to +12.0 V for periods of up to 20 ns, when VCCf is applied.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING CONDITIONS

Value

Parameter

Symbol

Unit

Min

–40

+2.7

Max

+85

Ambient Temperature

V^CCf/VCCs Supply Voltages

T^A

°C

V

Vccf, Vccs

+3.3

Note: Operating ranges define those limits between which the functionality of the device is guaranteed.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

9

MB84VD2108XEM/2109XEM-70

■ ELECTRICAL CHARACTERISTICS

1. DC Characteristics

Value

Typ

—

Parameter

Symbol

Test Conditions

V^IN= V^SSto V^CCf, V^CCs

Unit

Min

–1.0

Max

+1.0

Input Leakage Current

Output Leakage Current

I^LI

µA

I^LO

V^OUT= V^SSto V^CCf, V^CCs

—

RESET Inputs Leakage

Current

V^CCf= V^CCf Max, V^CCs= V^CCs Max,

RESET = 12.5 V

I^LIT

—

35

µA

t^CYCLE= 5 MHz Byte

—

13

15

7

mA

t^CYCLE= 5 MHz Word

t^CYCLE= 1 MHz Byte

t^CYCLE= 1 MHz Word

Flash V^CCActive Current

(Read) *¹

CEf = V^IL,

OE = V^IH

I^CC1f

mA

7

Flash V^CCActive Current

(Program/Erase) *²

I^CC2f

CEf = V^IL, OE = V^IH

—

35

Byte

Word

Byte

—

48

50

48

50

Flash V^CCActive Current

(Read-While-Program) *⁵

I^CC3f

Flash V^CCActive Current

(Read-While-Erase) *⁵

I^CC4f

CEf = V^IL, OE = V^IH

mA

Word

Flash V^CCActive Current

(Erase-Suspend-Program)

I^CC5f

I^LIA

—

35

20

mA

ACC Input Leakage

Current

V^CCf= V^CCf Max, V^CCs= V^CCs Max,

WP/ACC = V^ACCMax

V^CCs = V^CCs Max,

SRAM V^CCActive Current

Flash V^CCStandby Current

I^CC1s

CE1s = V^IL,

CE2s = V^IH

t^CYCLE=10 MHz

—

40

mA

t^CYCLE= 10 MHz

t^CYCLE= 1 MHz

—

40

8

mA

CE1s = 0.2 V,

CE2s = V^CCs – 0.2 V

I^CC2s

V^CCf = V^CCf Max, CEf = V^CCf ± 0.3 V

RESET = V^CCf ± 0.3 V,

WP/ACC = V^CCf± 0.3 V

I^SB1f

—

1

5

µA

Flash V^CCStandby Current

(RESET)

V^CCf = V^CCf Max, RESET = V^SS± 0.3 V,

WP/ACC = V^CCf± 0.3 V

I^SB2f

V^CCf = V^CCf Max, CEf = V^SS± 0.3 V

RESET = V^CCf ± 0.3 V,

WP/ACC = V^CCf± 0.3 V

Flash V^CCCurrent

(Automatic Sleep Mode) *³

I^SB3f

—

1

5

µA

V^IN= V^CCf± 0.3 V or V^SS± 0.3 V

(Continued)

10

MB84VD2108XEM/2109XEM^-70

(Continued)

Value

Parameter

Symbol

Test Conditions

Unit

Min

Typ

Max

CE1s > VCCs – 0.2 V, CE2s > VCCs – 0.2 V

LB = UB > VCCs–0.2 V or < 0.2 V

SRAM V^CCStandby Current

ISB1s

—

7

µA

CE1s > VCCs – 0.2 V or < 0.2 V,

SRAM V^CCStandby Current ISB2s CE2s < 0.2 V

LB = UB > VCCs–0.2 V or < 0.2V

—

7

µA

Input Low Level

Input High Level

V^IL

—

–0.3

2.4

—

0.5

V

VCC+0.3

VIH

6

*

Voltage for Sector

Protection, and Temporary

Sector Unprotection

(RESET) *⁴

VID

—

11.5

8.5

—

12.5

V

Voltage for Program

Acceleration (WP/ACC) *⁴

VACC

9.0

9.5

SRAM Output Low Level

SRAM Output High Level

Flash Output Low Level

Flash Output High Level

V^OL

V^OH

V^OL

V^OH

VCCs = VCCsMin, I^OL= 4.0 mA

VCCs = VCCsMin, I^OH= –0.5 mA

VCCf = VCCfMin, I^OL= 4.0 mA

VCCf = VCCfMin, I^OH= –0.5 mA

—

2.4

—

0.45

—

V

0.4

—

2.4

Flash Low V^CCf Lock-Out

Voltage

VLKO

—

2.3

—

2.5

V

* 1 : The ICC current listed includes both the DC operating current and the frequency dependent component.

*2 : ICC active while Embedded Algorithm (program or erase) is in progress.

*3 : Automatic sleep mode enables the low power mode when address remain stable for 150 ns.

*4 : Applicable for only V^CCf applying.

*5 : Embedded Algorithm (program or erase) is in progress. (@5 MHz)

*6 : V^CCindicates lower of VCCf or VCCs.

11

MB84VD2108XEM/2109XEM-70

2. AC Characteristics

• CE Timing

Symbol

JEDEC Standard

t^CCR

Value

Min

0

Parameter

Test Setup

Unit

CE Recover Time

—

ns

• Timing Diagram for alternating SRAM to Flash

CEf

t

CCR

tCCR

CE1s

CE2s

tCCR

• Flash Characteristics

Please refer to “■16M FLASH MEMORY CHARACTERISTICS for MCP” part.

• SRAM Characteristics,

Please refer to “■2M SRAM CHARACTERISTICS for MCP” part.

12

MB84VD2108XEM/2109XEM-70

■ 16M FLASH MEMORY CHARACTERISTICS for MCP

1. Flexible Sector-erase Architecture on Flash Memory

• Eight 4 K words, and thirty one 32 K words.

• Individual-sector, multiple-sector, or bulk-erase capability.

Word mode

Byte mode

Bank size 1

Bank size 4 Bank size 3 Bank size 2

0FFFFFh

0FF000h

0FE000h

0FD000h

0FC000h

0FB000h

0FA000h

0F9000h

0F8000h

0F0000h

0E8000h

0E0000h

0D8000h

0D0000h

0C8000h

0C0000h

0B8000h

0B0000h

0A8000h

0A0000h

098000h

090000h

088000h

080000h

078000h

070000h

068000h

060000h

058000h

050000h

048000h

040000h

038000h

030000h

028000h

020000h

018000h

010000h

008000h

000000h

1FFFFFh

1FE000h

1FC000h

1FA000h

1F8000h

1F6000h

1F4000h

1F2000h

1F0000h

1E0000h

1D0000h

1C0000h

1B0000h

1A0000h

190000h

180000h

170000h

160000h

150000h

140000h

130000h

120000h

110000h

100000h

0F0000h

0E0000h

0D0000h

0C0000h

0B0000h

0A0000h

090000h

080000h

070000h

060000h

050000h

040000h

030000h

020000h

010000h

000000h

SA38 : 8KB (4KW)

SA37 : 8KB (4KW)

SA36 : 8KB (4KW)

SA35 : 8KB (4KW)

SA34 : 8KB (4KW)

SA33 : 8KB (4KW)

SA32 : 8KB (4KW)

SA31 : 8KB (4KW)

SA30 : 64KB (32KW)

SA29 : 64KB (32KW)

SA28 : 64KB (32KW)

SA27 : 64KB (32KW)

SA26 : 64KB (32KW)

SA25 : 64KB (32KW)

SA24 : 64KB (32KW)

SA23 : 64KB (32KW)

SA22 : 64KB (32KW)

SA21 : 64KB (32KW)

SA20 : 64KB (32KW)

SA19 : 64KB (32KW)

SA18 : 64KB (32KW)

SA17 : 64KB (32KW)

SA16 : 64KB (32KW)

SA15 : 64KB (32KW)

SA14 : 64KB (32KW)

SA13 : 64KB (32KW)

SA12 : 64KB (32KW)

SA11 : 64KB (32KW)

SA10 : 64KB (32KW)

SA9 : 64KB (32KW)

SA8 : 64KB (32KW)

SA7 : 64KB (32KW)

SA6 : 64KB (32KW)

SA5 : 64KB (32KW)

SA4 : 64KB (32KW)

SA3 : 64KB (32KW)

SA2 : 64KB (32KW)

SA1 : 64KB (32KW)

SA0 : 64KB (32KW)

Bank 1

Bank 2

Sector Architecture (Top Boot Block)

13

MB84VD2108XEM/2109XEM-70

(Continued)

Word mode Byte mode

1FFFFFh

Bank size 1

Bank size 4 Bank size 3 Bank size 2

0FFFFFh

0F8000h

0F0000h

0E8000h

0E0000h

0D8000h

0D0000h

0C8000h

0C0000h

0B8000h

0B0000h

0A8000h

0A0000h

098000h

090000h

088000h

080000h

078000h

070000h

068000h

060000h

058000h

050000h

048000h

040000h

038000h

030000h

028000h

020000h

018000h

010000h

008000h

007000h

006000h

005000h

004000h

003000h

002000h

001000h

000000h

SA38 : 64KB (32KW)

SA37 : 64KB (32KW)

SA36 : 64KB (32KW)

SA35 : 64KB (32KW)

SA34 : 64KB (32KW)

SA33 : 64KB (32KW)

SA32 : 64KB (32KW)

SA31 : 64KB (32KW)

SA30 : 64KB (32KW)

SA29 : 64KB (32KW)

SA28 : 64KB (32KW)

SA27 : 64KB (32KW)

SA26 : 64KB (32KW)

SA25 : 64KB (32KW)

SA24 : 64KB (32KW)

SA23 : 64KB (32KW)

SA22 : 64KB (32KW)

SA21 : 64KB (32KW)

SA20 : 64KB (32KW)

SA19 : 64KB (32KW)

SA18 : 64KB (32KW)

SA17 : 64KB (32KW)

SA16 : 64KB (32KW)

SA15 : 64KB (32KW)

SA14 : 64KB (32KW)

SA13 : 64KB (32KW)

SA12 : 64KB (32KW)

SA11 : 64KB (32KW)

SA10 : 64KB (32KW)

SA9 : 64KB (32KW)

SA8 : 64KB (32KW)

SA7 : 8KB (4KW)

SA6 : 8KB (4KW)

SA5 : 8KB (4KW)

SA4 : 8KB (4KW)

SA3 : 8KB (4KW)

SA2 : 8KB (4KW)

SA1 : 8KB (4KW)

SA0 : 8KB (4KW)

1F0000h

1E0000h

1D0000h

1C0000h

1B0000h

1A0000h

190000h

180000h

170000h

160000h

150000h

140000h

130000h

120000h

110000h

100000h

0F0000h

0E0000h

0D0000h

0C0000h

0B0000h

0A0000h

090000h

080000h

070000h

060000h

050000h

040000h

030000h

020000h

010000h

00E000h

00C000h

00A000h

008000h

006000h

004000h

002000h

000000h

Bank 2

Bank 1

Sector Architecture (Bottom Boot Block)

14

MB84VD2108XEM/2109XEM-70

Sector Address Table (Top Boot Block, Bank Size=1)

Sector Address

Bank Address

Address Range

(Byte mode)

Address Range

(Word mode)

Bank

Sector

A¹⁹

0

1

A¹⁸

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

X

0

A¹³

X

0

A¹²

X

0

SA0

SA1

000000h to 00FFFFh 000000h to 007FFFh

010000h to 01FFFFh 008000h to 00FFFFh

020000h to 02FFFFh 010000h to 017FFFh

030000h to 03FFFFh 018000h to 01FFFFh

040000h to 04FFFFh 020000h to 027FFFh

050000h to 05FFFFh 028000h to 02FFFFh

060000h to 06FFFFh 030000h to 037FFFh

070000h to 07FFFFh 038000h to 03FFFFh

080000h to 08FFFFh 040000h to 047FFFh

090000h to 09FFFFh 048000h to 04FFFFh

0A0000h to 0AFFFFh 050000h to 057FFFh

0B0000h to 0BFFFFh 058000h to 05FFFFh

0C0000h to 0CFFFFh 060000h to 067FFFh

0D0000h to 0DFFFFh 068000h to 06FFFFh

0E0000h to 0EFFFFh 070000h to 077FFFh

0F0000h to 0FFFFFh 078000h to 07FFFFh

100000h to 10FFFFh 080000h to 087FFFh

110000h to 11FFFFh 088000h to 08FFFFh

120000h to 12FFFFh 090000h to 097FFFh

130000h to 13FFFFh 098000h to 09FFFFh

140000h to 14FFFFh 0A0000h to 0A7FFFh

150000h to 15FFFFh 0A8000h to 0AFFFFh

160000h to 16FFFFh 0B0000h to 0B7FFFh

170000h to 17FFFFh 0B8000h to 0BFFFFh

180000h to 18FFFFh 0C0000h to 0C7FFFh

190000h to 19FFFFh 0C8000h to 0CFFFFh

1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

1F0000h to 1F1FFFh 0F8000h to 0F8FFFh

1F2000h to 1F3FFFh 0F9000h to 0F9FFFh

1F4000h to 1F5FFFh 0FA000h to 0FAFFFh

1F6000h to 1F7FFFh 0FB000h to 0FBFFFh

1F8000h to 1F9FFFh 0FC000h to 0FCFFFh

1FA000h to 1FBFFFh 0FD000h to 0FDFFFh

1FC000h to 1FDFFFh 0FE000h to 0FEFFFh

1FE000h to 1FFFFFh 0FF000h to 0FFFFFh

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

Bank 2

0

1

0

1

0

1

Bank 1

1

0

1

0

1

0

1

15

MB84VD2108XEM/2109XEM-70

Sector Address Table (Bottom Boot Block, Bank Size=1)

Sector Address

Bank Address

Address Range

(BYTE mode)

Address Range

(WORD mode)

Bank

Sector

A¹⁹

0

1

A¹⁸

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

0

A¹³

0

A¹²

0

SA0

SA1

000000h to 001FFFh 000000h to 000FFFh

002000h to 003FFFh 001000h to 001FFFh

004000h to 005FFFh 002000h to 002FFFh

006000h to 007FFFh 003000h to 003FFFh

008000h to 009FFFh 004000h to 004FFFh

00A000h to 00BFFFh 005000h to 005FFFh

00C000h to 00DFFFh 006000h to 006FFFh

00E000h to 00FFFFh 007000h to 007FFFh

010000h to 01FFFFh 008000h to 00FFFFh

020000h to 02FFFFh 010000h to 017FFFh

030000h to 03FFFFh 018000h to 01FFFFh

040000h to 04FFFFh 020000h to 027FFFh

050000h to 05FFFFh 028000h to 02FFFFh

060000h to 06FFFFh 030000h to 037FFFh

070000h to 07FFFFh 038000h to 03FFFFh

080000h to 08FFFFh 040000h to 047FFFh

090000h to 09FFFFh 048000h to 04FFFFh

0A0000h to 0AFFFFh 050000h to 057FFFh

0B0000h to 0BFFFFh 058000h to 05FFFFh

0C0000h to 0CFFFFh 060000h to 067FFFh

0D0000h to 0DFFFFh 068000h to 06FFFFh

0E0000h to 0EFFFFh 070000h to 077FFFh

0F0000h to 0FFFFFh 078000h to 07FFFFh

100000h to 10FFFFh 080000h to 087FFFh

110000h to 11FFFFh 088000h to 08FFFFh

120000h to 12FFFFh 090000h to 097FFFh

130000h to 13FFFFh 098000h to 09FFFFh

140000h to 14FFFFh 0A0000h to 0A7FFFh

150000h to 15FFFFh 0A8000h to 0AFFFFh

160000h to 16FFFFh 0B0000h to 0B7FFFh

170000h to 17FFFFh 0B8000h to 0BFFFFh

180000h to 18FFFFh 0C0000h to 0C7FFFh

190000h to 19FFFFh 0C8000h to 0CFFFFh

1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

0

1

SA2

0

1

0

SA3

0

1

Bank 1

SA4

1

0

SA5

1

0

1

SA6

1

0

SA7

1

SA8

X

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

Bank 2

16

MB84VD2108XEM/2109XEM-70

Sector Address Table (Top Boot Block, Bank Size=2)

Sector Address

Bank Address

Address Range

(BYTE mode)

Address Range

(WORD mode)

Bank

Sector

A¹⁹

0

1

A¹⁸

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

X

0

A¹³

X

0

A¹²

X

0

SA0

SA1

000000h to 00FFFFh 000000h to 007FFFh

010000h to 01FFFFh 008000h to 00FFFFh

020000h to 02FFFFh 010000h to 017FFFh

030000h to 03FFFFh 018000h to 01FFFFh

040000h to 04FFFFh 020000h to 027FFFh

050000h to 05FFFFh 028000h to 02FFFFh

060000h to 06FFFFh 030000h to 037FFFh

070000h to 07FFFFh 038000h to 03FFFFh

080000h to 08FFFFh 040000h to 047FFFh

090000h to 09FFFFh 048000h to 04FFFFh

0A0000h to 0AFFFFh 050000h to 057FFFh

0B0000h to 0BFFFFh 058000h to 05FFFFh

0C0000h to 0CFFFFh 060000h to 067FFFh

0D0000h to 0DFFFFh 068000h to 06FFFFh

0E0000h to 0EFFFFh 070000h to 077FFFh

0F0000h to 0FFFFFh 078000h to 07FFFFh

100000h to 10FFFFh 080000h to 087FFFh

110000h to 11FFFFh 088000h to 08FFFFh

120000h to 12FFFFh 090000h to 097FFFh

130000h to 13FFFFh 098000h to 09FFFFh

140000h to 14FFFFh 0A0000h to 0A7FFFh

150000h to 15FFFFh 0A8000h to 0AFFFFh

160000h to 16FFFFh 0B0000h to 0B7FFFh

170000h to 17FFFFh 0B8000h to 0BFFFFh

180000h to 18FFFFh 0C0000h to 0C7FFFh

190000h to 19FFFFh 0C8000h to 0CFFFFh

1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

1F0000h to 1F1FFFh 0F8000h to 0F8FFFh

1F2000h to 1F3FFFh 0F9000h to 0F9FFFh

1F4000h to 1F5FFFh 0FA000h to 0FAFFFh

1F6000h to 1F7FFFh 0FB000h to 0FBFFFh

1F8000h to 1F9FFFh 0FC000h to 0FCFFFh

1FA000h to 1FBFFFh 0FD000h to 0FDFFFh

1FC000h to 1FDFFFh 0FE000h to 0FEFFFh

1FE000h to 1FFFFFh 0FF000h to 0FFFFFh

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

Bank 2

0

1

0

1

0

Bank 1

0

1

0

1

0

1

0

1

17

MB84VD2108XEM/2109XEM-70

Sector Address Table (Bottom Boot Block, Bank Size=2)

Sector Address

Bank Address

Address Range

(BYTE mode)

Address Range

(WORD mode)

Bank

Sector

A¹⁹

0

1

A¹⁸

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

0

A¹³

0

A¹²

0

SA0

SA1

000000h to 001FFFh 000000h to 000FFFh

002000h to 003FFFh 001000h to 001FFFh

004000h to 005FFFh 002000h to 002FFFh

006000h to 007FFFh 003000h to 003FFFh

008000h to 009FFFh 004000h to 004FFFh

00A000h to 00BFFFh 005000h to 005FFFh

00C000h to 00DFFFh 006000h to 006FFFh

00E000h to 00FFFFh 007000h to 007FFFh

010000h to 01FFFFh 008000h to 00FFFFh

020000h to 02FFFFh 010000h to 017FFFh

030000h to 03FFFFh 018000h to 01FFFFh

040000h to 04FFFFh 020000h to 027FFFh

050000h to 05FFFFh 028000h to 02FFFFh

060000h to 06FFFFh 030000h to 037FFFh

070000h to 07FFFFh 038000h to 03FFFFh

080000h to 08FFFFh 040000h to 047FFFh

090000h to 09FFFFh 048000h to 04FFFFh

0A0000h to 0AFFFFh 050000h to 057FFFh

0B0000h to 0BFFFFh 058000h to 05FFFFh

0C0000h to 0CFFFFh 060000h to 067FFFh

0D0000h to 0DFFFFh 068000h to 06FFFFh

0E0000h to 0EFFFFh 070000h to 077FFFh

0F0000h to 0FFFFFh 078000h to 07FFFFh

100000h to 10FFFFh 080000h to 087FFFh

110000h to 11FFFFh 088000h to 08FFFFh

120000h to 12FFFFh 090000h to 097FFFh

130000h to 13FFFFh 098000h to 09FFFFh

140000h to 14FFFFh 0A0000h to 0A7FFFh

150000h to 15FFFFh 0A8000h to 0AFFFFh

160000h to 16FFFFh 0B0000h to 0B7FFFh

170000h to 17FFFFh 0B8000h to 0BFFFFh

180000h to 18FFFFh 0C0000h to 0C7FFFh

190000h to 19FFFFh 0C8000h to 0CFFFFh

1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

0

1

SA2

0

1

0

SA3

0

1

SA4

1

0

SA5

1

0

1

Bank 1

SA6

1

0

SA7

1

SA8

X

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

Bank 2

18

MB84VD2108XEM/2109XEM-70

Sector Address Table (Top Boot Block, Bank Size=3)

Sector Address

Bank Address

Address Range

(BYTE mode)

Address Range

(WORD mode)

Bank

Sector

A¹⁹

0

1

A¹⁸

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

X

0

A¹³

X

0

A¹²

X

0

SA0

SA1

000000h to 00FFFFh 000000h to 007FFFh

010000h to 01FFFFh 008000h to 00FFFFh

020000h to 02FFFFh 010000h to 017FFFh

030000h to 03FFFFh 018000h to 01FFFFh

040000h to 04FFFFh 020000h to 027FFFh

050000h to 05FFFFh 028000h to 02FFFFh

060000h to 06FFFFh 030000h to 037FFFh

070000h to 07FFFFh 038000h to 03FFFFh

080000h to 08FFFFh 040000h to 047FFFh

090000h to 09FFFFh 048000h to 04FFFFh

0A0000h to 0AFFFFh 050000h to 057FFFh

0B0000h to 0BFFFFh 058000h to 05FFFFh

0C0000h to 0CFFFFh 060000h to 067FFFh

0D0000h to 0DFFFFh 068000h to 06FFFFh

0E0000h to 0EFFFFh 070000h to 077FFFh

0F0000h to 0FFFFFh 078000h to 07FFFFh

100000h to 10FFFFh 080000h to 087FFFh

110000h to 11FFFFh 088000h to 08FFFFh

120000h to 12FFFFh 090000h to 097FFFh

130000h to 13FFFFh 098000h to 09FFFFh

140000h to 14FFFFh 0A0000h to 0A7FFFh

150000h to 15FFFFh 0A8000h to 0AFFFFh

160000h to 16FFFFh 0B0000h to 0B7FFFh

170000h to 17FFFFh 0B8000h to 0BFFFFh

180000h to 18FFFFh 0C0000h to 0C7FFFh

190000h to 19FFFFh 0C8000h to 0CFFFFh

1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

1F0000h to 1F1FFFh 0F8000h to 0F8FFFh

1F2000h to 1F3FFFh 0F9000h to 0F9FFFh

1F4000h to 1F5FFFh 0FA000h to 0FAFFFh

1F6000h to 1F7FFFh 0FB000h to 0FBFFFh

1F8000h to 1F9FFFh 0FC000h to 0FCFFFh

1FA000h to 1FBFFFh 0FD000h to 0FDFFFh

1FC000h to 1FDFFFh 0FE000h to 0FEFFFh

1FE000h to 1FFFFFh 0FF000h to 0FFFFFh

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

Bank 2

Bank 1

0

1

0

1

0

1

0

1

0

1

0

1

19

MB84VD2108XEM/2109XEM-70

Sector Address Table (Bottom Boot Block, Bank Size=3)

Sector Address

Bank Address

Address Range

(BYTE mode)

Address Range

(WORD mode)

Bank

Sector

A¹⁹

0

1

A¹⁸

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

0

A¹³

0

A¹²

0

SA0

SA1

000000h to 001FFFh 000000h to 000FFFh

002000h to 003FFFh 001000h to 001FFFh

004000h to 005FFFh 002000h to 002FFFh

006000h to 007FFFh 003000h to 003FFFh

008000h to 009FFFh 004000h to 004FFFh

00A000h to 00BFFFh 005000h to 005FFFh

00C000h to 00DFFFh 006000h to 006FFFh

00E000h to 00FFFFh 007000h to 007FFFh

010000h to 01FFFFh 008000h to 00FFFFh

020000h to 02FFFFh 010000h to 017FFFh

030000h to 03FFFFh 018000h to 01FFFFh

040000h to 04FFFFh 020000h to 027FFFh

050000h to 05FFFFh 028000h to 02FFFFh

060000h to 06FFFFh 030000h to 037FFFh

070000h to 07FFFFh 038000h to 03FFFFh

080000h to 08FFFFh 040000h to 047FFFh

090000h to 09FFFFh 048000h to 04FFFFh

0A0000h to 0AFFFFh 050000h to 057FFFh

0B0000h to 0BFFFFh 058000h to 05FFFFh

0C0000h to 0CFFFFh 060000h to 067FFFh

0D0000h to 0DFFFFh 068000h to 06FFFFh

0E0000h to 0EFFFFh 070000h to 077FFFh

0F0000h to 0FFFFFh 078000h to 07FFFFh

100000h to 10FFFFh 080000h to 087FFFh

110000h to 11FFFFh 088000h to 08FFFFh

120000h to 12FFFFh 090000h to 097FFFh

130000h to 13FFFFh 098000h to 09FFFFh

140000h to 14FFFFh 0A0000h to 0A7FFFh

150000h to 15FFFFh 0A8000h to 0AFFFFh

160000h to 16FFFFh 0B0000h to 0B7FFFh

170000h to 17FFFFh 0B8000h to 0BFFFFh

180000h to 18FFFFh 0C0000h to 0C7FFFh

190000h to 19FFFFh 0C8000h to 0CFFFFh

1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

0

1

SA2

0

1

0

SA3

0

1

SA4

1

0

SA5

1

0

1

SA6

1

0

SA7

1

Bank 1

SA8

X

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

Bank 2

20

MB84VD2108XEM/2109XEM-70

Sector Address Table (Top Boot Block, Bank Size=4)

Sector Address

Bank Address

Address Range

(BYTE mode)

Address Range

(WORD mode)

Bank

Sector

A¹⁹

0

1

A¹⁸

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

X

0

A¹³

X

0

A¹²

X

0

SA0

SA1

000000h to 00FFFFh 000000h to 007FFFh

010000h to 01FFFFh 008000h to 00FFFFh

020000h to 02FFFFh 010000h to 017FFFh

030000h to 03FFFFh 018000h to 01FFFFh

040000h to 04FFFFh 020000h to 027FFFh

050000h to 05FFFFh 028000h to 02FFFFh

060000h to 06FFFFh 030000h to 037FFFh

070000h to 07FFFFh 038000h to 03FFFFh

080000h to 08FFFFh 040000h to 047FFFh

090000h to 09FFFFh 048000h to 04FFFFh

0A0000h to 0AFFFFh 050000h to 057FFFh

0B0000h to 0BFFFFh 058000h to 05FFFFh

0C0000h to 0CFFFFh 060000h to 067FFFh

0D0000h to 0DFFFFh 068000h to 06FFFFh

0E0000h to 0EFFFFh 070000h to 077FFFh

0F0000h to 0FFFFFh 078000h to 07FFFFh

100000h to 10FFFFh 080000h to 087FFFh

110000h to 11FFFFh 088000h to 08FFFFh

120000h to 12FFFFh 090000h to 097FFFh

130000h to 13FFFFh 098000h to 09FFFFh

140000h to 14FFFFh 0A0000h to 0A7FFFh

150000h to 15FFFFh 0A8000h to 0AFFFFh

160000h to 16FFFFh 0B0000h to 0B7FFFh

170000h to 17FFFFh 0B8000h to 0BFFFFh

180000h to 18FFFFh 0C0000h to 0C7FFFh

190000h to 19FFFFh 0C8000h to 0CFFFFh

1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

1F0000h to 1F1FFFh 0F8000h to 0F8FFFh

1F2000h to 1F3FFFh 0F9000h to 0F9FFFh

1F4000h to 1F5FFFh 0FA000h to 0FAFFFh

1F6000h to 1F7FFFh 0FB000h to 0FBFFFh

1F8000h to 1F9FFFh 0FC000h to 0FCFFFh

1FA000h to 1FBFFFh 0FD000h to 0FDFFFh

1FC000h to 1FDFFFh 0FE000h to 0FEFFFh

1FE000h to 1FFFFFh 0FF000h to 0FFFFFh

SA2

SA3

SA4

SA5

SA6

SA7

Bank 2

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

Bank 1

0

1

0

1

0

1

0

1

0

1

0

1

21

MB84VD2108XEM/2109XEM-70

Sector Address Table (Bottom Boot Block, Bank Size=4)

Sector Address

Bank Address

Address Range

(BYTE mode)

Address Range

(WORD mode)

Bank

Sector

A¹⁹

0

1

A¹⁸

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

0

A¹³

0

A¹²

0

SA0

SA1

000000h to 001FFFh 000000h to 000FFFh

002000h to 003FFFh 001000h to 001FFFh

004000h to 005FFFh 002000h to 002FFFh

006000h to 007FFFh 003000h to 003FFFh

008000h to 009FFFh 004000h to 004FFFh

00A000h to 00BFFFh 005000h to 005FFFh

00C000h to 00DFFFh 006000h to 006FFFh

00E000h to 00FFFFh 007000h to 007FFFh

010000h to 01FFFFh 008000h to 00FFFFh

020000h to 02FFFFh 010000h to 017FFFh

030000h to 03FFFFh 018000h to 01FFFFh

040000h to 04FFFFh 020000h to 027FFFh

050000h to 05FFFFh 028000h to 02FFFFh

060000h to 06FFFFh 030000h to 037FFFh

070000h to 07FFFFh 038000h to 03FFFFh

080000h to 08FFFFh 040000h to 047FFFh

090000h to 09FFFFh 048000h to 04FFFFh

0A0000h to 0AFFFFh 050000h to 057FFFh

0B0000h to 0BFFFFh 058000h to 05FFFFh

0C0000h to 0CFFFFh 060000h to 067FFFh

0D0000h to 0DFFFFh 068000h to 06FFFFh

0E0000h to 0EFFFFh 070000h to 077FFFh

0F0000h to 0FFFFFh 078000h to 07FFFFh

100000h to 10FFFFh 080000h to 087FFFh

110000h to 11FFFFh 088000h to 08FFFFh

120000h to 12FFFFh 090000h to 097FFFh

130000h to 13FFFFh 098000h to 09FFFFh

140000h to 14FFFFh 0A0000h to 0A7FFFh

150000h to 15FFFFh 0A8000h to 0AFFFFh

160000h to 16FFFFh 0B0000h to 0B7FFFh

170000h to 17FFFFh 0B8000h to 0BFFFFh

180000h to 18FFFFh 0C0000h to 0C7FFFh

190000h to 19FFFFh 0C8000h to 0CFFFFh

1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

0

1

SA2

0

1

0

SA3

0

1

SA4

1

0

SA5

1

0

1

SA6

1

0

SA7

1

SA8

X

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

Bank 1

Bank 2

22

MB84VD2108XEM/2109XEM-70

Sector Group Addresses Table (Top Boot Block)

Sector Group

A¹⁹

0

1

A¹⁸

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

A¹⁶

0

1

X

0

1

A¹⁵

0

1

0

1

X

0

1

0

1

A¹⁴

X

0

1

A¹³

X

0

1

0

1

A¹²

X

0

1

0

1

0

1

0

1

Sectors

SA0

SGA0

SGA1

SA1 to SA3

SGA2

SGA3

SGA4

SGA5

SGA6

SGA7

SA4 to SA7

SA8 to SA11

SA12 to SA15

SA16 to SA19

SA20 to SA23

SA24 to SA27

SGA8

SA28 to SA30

SGA9

SGA10

SGA11

SGA12

SGA13

SGA14

SGA15

SGA16

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

1

Sector Group Addresses Table (Bottom Boot Block)

Sector Group

SGA0

A¹⁹

0

1

A¹⁸

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

A¹⁶

0

1

X

0

A¹⁵

0

1

0

1

X

0

A¹⁴

0

1

X

A¹³

0

1

0

1

X

A¹²

0

1

0

1

0

1

0

1

X

Sectors

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SGA1

SGA2

SGA3

SGA4

SGA5

SGA6

SGA7

SGA8

SA8 to SA10

SGA9

SGA10

SGA11

SGA12

SGA13

SGA14

SA11 to SA14

SA15 to SA18

SA19 to SA22

SA23 to SA26

SA27 to SA30

SA31 to SA34

SGA15

SGA16

0

1

0

1

SA35 to SA37

SA38

23

MB84VD2108XEM/2109XEM-70

Flash Memory Autoselect Codes Table

A^–1*¹

V^IL

X

Type

Manufacturer’s Code

A¹⁹to A¹²

A⁶

A¹

A⁰

Code (HEX)

04h

X

V^IL

Byte

Word

Byte

36h

Top Boot Block

Bank Size=1

X

V^IL

V^IH

2236h

39

V^IL

X

Bottom Boot Block

Bank Size=1

Word

Byte

2239h

2D

V^IL

X

Top Boot Block

Bank Size=2

Word

Byte

222Dh

2E

V^IL

X

Bottom Boot Block

Bank Size=2

Word

Byte

222Eh

28h

Device

Code

V^IL

X

Top Boot Block

Bank Size=3

Word

Byte

2228h

2Bh

V^IL

X

Bottom Boot Block

Bank Size=3

Word

Byte

222Bh

33h

V^IL

X

Top Boot Block

Bank Size=4

Word

Byte

2233h

35

V^IL

X

Bottom Boot Block

Bank Size=4

Word

2235h

Sector

Group

Sector Group protect

V^IL

V^IH

V^IL

01h*²

Address

*1: A^–1is for Byte mode.

*2: Output 01h at protected sector address and output 00h at unprotected sector address.

24

MB84VD2108XEM/2109XEM-70

Flash Memory Command Definitions Table

Fourth Bus

Read/Write

Cycle

Bus

Write

Cycles

Req’d

First Bus

Second Bus

Write Cycle

Third Bus

Fifth Bus

Sixth Bus

Command

Sequence

Write Cycle

Write Cycle Write Cycle

Addr. Data Addr.

Data

Addr. Data Addr. Data Addr. Data Addr. Data

Read/Reset *¹

1

3

XXXh F0h

—

Word

Byte

555h

AAh

AAAh

2AAh

555h

AAAh

55h

F0h

RA

RD

—

(BA)

555h

Word

Byte

555h

AAh

2AAh

555h

Autoselect

3

90h

—

(BA)

AAAh

Word

Byte

Word

Byte

Word

Byte

555h

AAh

AAAh

2AAh

555h

2AAh

555h

2AAh

555h

AAAh

555h

AAAh

555h

AAAh

Program

4

6

55h

A0h

80h

PA

PD

—

555h

AAh

AAAh

555h

AAAh

555h

AAAh

2AAh

555h

2AAh

555h

Chip Erase

Sector Erase

AAh

55h

10h

30h

AAAh

555h

AAh

AAAh

SA

Sector Erase

Suspend

1

BA

B0h

30h

—

Sector Erase

Resume

Word

Byte

Word

Byte

Word

Byte

555h

2AAh

555h

Set to

Fast Mode

3

2

AAh

55h

20h

—

AAAh

Fast Program*²

XXXh A0h

PA

PD

—

Reset from

Fast Mode *²

F0h

BA

90h XXXh

—

6

*

Extended

Sector Group

Protection *³

Word

Byte

4

XXXh 60h SPA

55h

60h

SPA

—

40h SPA

SD

—

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Query *⁴

1

3

4

6

98h

AAh

—

AAh

555h

AAAh

555h

AAAh

555h

AAAh

2AAh

555h

2AAh

555h

2AAh

555h

AAAh

555h

AAAh

555h

AAAh

HiddenROM

Entry

55h

88h

A0h

80h

HiddenROM

Program *⁵

PA

PD

AAh

555h

2AAh

555h

HiddenROM

Erase *⁵

55h HRA 30h

AAAh

(HRBA)

555h

Word

Byte

555h

2AAh

555h

HiddenROM

Exit *⁵

4

AAh

55h

90h XXXh 00h

—

(HRBA)

AAAh

25

MB84VD2108XEM/2109XEM-70

*1: Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

*2: This command is valid while Fast Mode.

*3: This command is valid while RESET=V^ID.

*4: The valid Address is A⁶to A⁰.

*5: This command is valid while HiddenROM mode.

*6: The data “00h” is also acceptable.

Notes : • Address bits A¹⁹to A¹²= X = “H” or “L” for all address commands except for Program Address (PA),

Sector Address (SA), and Bank Address (BA).

Bus operations are defined in Table 2 “User Bus Operations”.

RA = Address of the memory location to be read.

PA = Address of the memory location to be programmed.

Addresses are latched on the falling edge of the write pulse.

• SA = Address of the sector to be erased. The combination of A¹⁹, A¹⁸, A¹⁷, A¹⁶, A¹⁵, A¹⁴, A¹³, and A¹²will

uniquely select any sector.

BA = Bank address (A¹⁹to A¹⁵)

SPA = Sector group address to be protected. Set sector group address (SGA) and (A⁶, A¹, A⁰) = (0, 1, 0).

HRA = Address of the HiddenROM area.

Top Boot Block

Word mode : 0F8000h to 0FFFFFh

Byte mode : 1F0000h to 1FFFFFh

Bottom Boot Block Word mode : 000000h to 007FFFh

Byte mode : 000000h to 00FFFFh

HRBA = Bank address of the HiddenROM area.

Top Boot Block : A¹⁵= A¹⁶= A¹⁷= A¹⁸= A¹⁹= A²⁰= 1

Bottom Boot Block : A¹⁵= A¹⁶= A¹⁷= A¹⁸= A¹⁹= A²⁰= 0

RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA.

SD = Sector protection verify data. Output 01h at protected sector addresses and output 00h

at unprotected sector addresses.

• The system should generate the following address patterns;

Word mode : 555h or 2AAh to addresses A¹⁰to A⁰

Byte mode : AAAh or 555h to addresses A¹⁰to A⁰and A^–1

26

MB84VD2108XEM/2109XEM-70

• Read Only Operations Characteristics (Flash)

Symbol

JEDEC Standard

Value*

Parameter

Test Setup

Unit

Min

Max

Read Cycle Time

t^AVAV

t^RC

—

70

—

ns

CEf = V^IL

OE = V^IL

Address to Output Delay

t^AVQV

t^ACC

—

70

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High-Z

Output Enable to Output High-Z

t^ELQV

t^GLQV

t^EHQZ

t^GHQZ

t^CEf

t^OE

t^DF

OE = V^IL

—

70

30

25

ns

—

Output Hold Time From Addresses,

CEf or OE, Whichever Occurs First

t^AXQX

—

t^OH

—

0

—

ns

µs

RESET Pin Low to Read Mode

t^READY

—

20

* : Test Conditions

Output Load : 1 TTL gate and 30 pF

Input rise and fall times: 5 ns

Input pulse levels : 0.0 V to 3.0 V

Timing measurement reference level

Input : 1.5 V

Output : 1.5 V

27

MB84VD2108XEM/2109XEM-70

• Read Cycle (Flash)

tRC

Address Stable

Address

tACC

CEf

OE

tOE

t^DF

tOEH

WE

DQ

tCEf

High-Z

Output Valid

tRC

Address

CEf

Address Stable

tACC

tRH

tCEf

tRP

RESET

DQ

tOH

High-Z

Output Valid

28

MB84VD2108XEM/2109XEM-70

• Erase/Program Operations (Flash)

Symbol

Value

Typ

—

Parameter

Unit

JEDEC Standard Min

Max

—

Write Cycle Time

t^AVAV

t^AVWL

—

t^WC

t^AS

t^ASO

t^AH

70

0

ns

Address Setup Time (WE to Addr.)

Address Setup Time to CEf Low During Toggle Bit Polling

Address Hold Time (WE to Addr.)

—

12

45

—

t^WLAX

—

Address Hold Time from CEf or OE High During Toggle Bit

Polling

—

t^AHT

0

—

ns

Data Setup Time

t^DVWH

t^WHDX

—

t^DS

t^DH

30

0

—

8

—

70

—

90

—

20

ns

µs

s

Data Hold Time

Output Enable Setup Time

t^OES

0

Read

Output Enable Hold Time

0

—

t^OEH

Toggle and Data Polling

10

20

0

CEf High During Toggle Bit Polling

OE High During Toggle Bit Polling

Read Recover Time Before Write (OE to CEf)

Read Recover Time Before Write (OE to WE)

WE Setup Time (CEf to WE)

CEf Setup Time (WE to CEf)

WE Hold Time (CEf to WE)

CEf Hold Time (WE to CEf)

Write Pulse Width

—

t^CEPH

t^OEPH

t^GHEL

t^GHWL

t^WS

—

t^GHEL

t^GHWL

t^WLEL

t^ELWL

t^EHWH

t^WHEH

t^WLWH

t^ELEH

t^WHWL

t^EHEL

0

t^CS

0

t^WH

0

t^CH

0

t^WP

35

25

—

50

4

CEf Pulse Width

t^CP

Write Pulse Width High

t^WPH

t^CPH

CEf Pulse Width High

Byte Programming Operation

Word Programming Operation

Sector Erase Operation *¹

V^CCf Setup Time

Voltage Transition Time *²

Rise Time to V^ID*²

t^WHWH1

16

1

t^WHWH2

—

t^WHWH2

t^VCS

—

µs

ns

µs

—

t^VLHT

t^VIDR

t^VACCR

t^RB

—

500

0

Rise Time to V^ACC

—

Recover Time from RY/BY

RESET Pulse Width

—

t^RP

500

—

200

—

50

—

Delay Time from Embedded Output Enable

RESET Hold Time Before Read

Program/Erase Valid to RY/BY Delay

Erase Time-out Time *³

—

t^EOE

t^RH

—

t^BUSY

t^TOW

t^SPD

—

Erase Suspend Transition Time *⁴

—

29

MB84VD2108XEM/2109XEM-70

*1 : This does not include the preprogramming time.

*2 : This timing is for Sector Protection Operation.

*3 : The time between writes must be less than “t^TOW” otherwise that command will not be accepted and erasure

will start. A time-out or “t^TOW” from the rising edge of last CEf or WE whichever happens first will initiate the

execution of the Sector Erase command(s).

*4 : When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum

of “t^SPD” to suspend the erase operation.

30

MB84VD2108XEM/2109XEM-70

• Write Cycle (WE control) (Flash)

3rd Bus Cycle

Data Polling

PA

555h

PA

Address

tWC

tRC

tAS

tAH

CEf

tCH

tCS

tCEf

OE

tGHWL

tOE

tWHWH1

tWP

tWPH

WE

DQ

tOH

tDS

tDH

PD

DOUT

A0h

DQ7

Notes : • PA is address of the memory location to be programmed.

• PD is data to be programmed at byte address.

• DQ⁷is the output of the complement of the data written to the device.

• D^OUTis the output of the data written to the device.

• Figure indicates last two bus cycles out of four bus cycle sequence.

• These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

31

MB84VD2108XEM/2109XEM-70

• Write Cycle (CEf control) (Flash)

3rd Bus Cycle

Data Polling

Address

WE

PA

555h

tWC

tAH

tAS

tWS

tWH

OE

tGHEL

tWHWH1

tCP

tCPH

CEf

tDS

tDH

PD

D^OUT

DQ7

A0h

DQ

Notes : • PA is address of the memory location to be programmed.

• PD is data to be programmed at byte address.

• DQ⁷is the output of the complement of the data written to the device.

• D^OUTis the output of the data written to the device.

• Figure indicates last two bus cycles out of four bus cycle sequence.

• These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

32

MB84VD2108XEM/2109XEM-70

• AC Waveforms Chip/Sector Erase Operations (Flash)

SA^*1

2AAh

555h

2AAh

555h

Address

CEf

tWC

tAS

tAH

tCS

tCH

OE

tWP

tWPH

tGHWL

WE

tDS

tDH

30h for Sector Erase

10h/

30h

AAh

55h

80h

55h

DQ

tVCS

VCCf

* : SA is the sector address for Sector Erase. Addresses = 555h for Chip Erase.

Note : These waveform are for the ×16 mode. (The addresses differ from ×8 mode.)

33

MB84VD2108XEM/2109XEM-70

• AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)

CEf

tCH

t^DF

tOE

OE

tOEH

WE

tCEf

*

High-Z

DQ7 =

Data In

DQ⁷

DQ7

Valid Data

tWHWH1 or 2

DQ

(DQ6 to DQ0)

DQ⁶to DQ⁰

Valid Data

DQ6 to DQ0 = Output Flag

tBUSY

tEOE

RY/BY

* : DQ⁷= Valid Data (The device has completed the Embedded operation.)

34

MB84VD2108XEM/2109XEM-70

• AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)

Address

CEf

tAHT

tASO

tAHT

tAS

tCEPH

WE

OE

tOEH

tOEPH

*

tOE

tCEf

tDH

Toggle

Data

Toggle

Data

Toggle

Data

Stop

Toggling

Output

Valid

DQ6/DQ2

Data

tBUSY

RY/BY

* : DQ⁶stops toggling (The device has completed the Embedded operation).

35

MB84VD2108XEM/2109XEM-70

• Bank-to-bank Read/Write Timing Diagram (Flash)

Read

Command

Read

Command

Read

tRC

tWC

tRC

tWC

tRC

BA2

(PA)

BA2

(PA)

Address

BA1

(555h)

tACC

tCE

tAS

tAH

tAHT

CEf

tOE

tCEPH

OE

tDF

tGHWL

tOEH

tWP

WE

tDH

tDS

tDF

Valid

Output

Valid

Output

DQ

Status

DQ

Output

Intput

(A0h)

Intput

(PD)

Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.

BA1: Address of Bank 1.

BA2: Address of Bank 2.

36

MB84VD2108XEM/2109XEM-70

• RY/BY Timing Diagram during Write/Erase Operations (Flash)

CEf

WE

Rising edge of the last write pulse

Entire programming

or erase operations

RY/BY

tBUSY

• RESET, RY/BY Timing Diagram (Flash)

WE

RESET

RY/BY

tRP

tRB

tREADY

37

MB84VD2108XEM/2109XEM-70

• Temporary Sector Unprotection (Flash)

VCCf

tVIDR

tVCS

tVLHT

VID

VIH

RESET

CEf

WE

tVLHT

Program or Erase Command Sequence

Unprotection period

RY/BY

• Acceleration Mode Timing Diagram (Flash)

VCCf

tVACCR

tVCS

tVLHT

V^ACC

V^IH

WP/ACC

CEf

WE

tVLHT

RY/BY

Acceleration Mode Period

38

MB84VD2108XEM/2109XEM-70

• Extended Sector Protection (Flash)

VCCf

tVCS

RESET

Add

tVLHT

tVIDR

tWC

SGAx

SGAy

A0

A1

A6

CEf

OE

TIME-OUT

tWP

WE

Data

60h

40h

01h

60h

tOE

SGAx : Sector Group Address to be protected

SGAy : Next Group Sector Address to be protected

TIME-OUT : Time-Out window = 250 µs (Min)

39

MB84VD2108XEM/2109XEM-70

2. Erase and Programming Performance (Flash)

Limit

Parameter

Unit

Comment

Min

Typ

Max

Excludes programming time

prior to erasure

Sector Erase Time

—

1

10

s

Excludes system-level

overhead

Byte Programming Time

Word Programming Time

—

8

300

360

µs

Excludes system-level

overhead

16

Excludes system-level

overhead

Chip Programming Time

Erase/Program Cycle

—

50

—

s

100,000

cycle

40

MB84VD2108XEM/2109XEM-70

■ 2M SRAM CHARACTERISTICS for MCP

1. AC Characteristics

• Read Cycle (SRAM)

Value

Parameter

Symbol

Unit

Min

70

—

5

Max

—

Read Cycle Time

t^RC

t^AA

ns

Address Access Time

70

35

70

—

Chip Enable (CE1s) Access Time

Chip Enable (CE2s) Access Time

Output Enable Access Time

t^CO1

t^CO2

t^OE

LB, UB to Output Valid

t^BA

Chip Enable (CE1s Low and CE2s High) to Output Active

Output Enable Low to Output Active

UB, LB Enable Low to Output Active

Chip Enable (CE1s High or CE2s Low) to Output High-Z

Output Enable High to Output High-Z

UB, LB Output Enable to Output High-Z

Output Data Hold Time

t^COE

t^OEE

t^BE

0

—

0

—

t^OD

—

10

25

—

t^ODO

t^BD

t^OH

Note: Test Conditions

Output Load:1 TTL gate and 30 pF

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to V^CCs

Timing measurement reference level

Input: 0.5×V^CCs

Output: 0.5×V^CCs

41

MB84VD2108XEM/2109XEM-70

• Read Cycle (SRAM)

t^RC

Address

t^AA

t^OH

t^CO1

CE1s

t^COE

t^OD

t^CO2

CE2s

t^OD

t^OE

OE

t^ODO

t^OEE

LB, UB

t^BA

t^BD

t^BE

t^COE

DQ

Valid Data Out

Note : WE remains “H” for the read cycle.

42

MB84VD2108XEM/2109XEM-70

• Write Cycle (SRAM)

Parameter

Value

Symbol

Unit

Min

70

50

55

0

Max

—

25

—

Write Cycle Time

t^WC

t^WP

t^CW

t^AW

t^BW

t^AS

ns

Write Pulse Width

Chip Enable to End of Write

Address valid to End of Write

UB, LB to End of Write

Address Setup Time

Write Recovery Time

WE Low to Output High-Z

WE High to Output Active

Data Setup Time

t^WR

t^ODW

t^OEW

t^DS

0

—

0

30

0

Data Hold Time

t^DH

43

MB84VD2108XEM/2109XEM-70

• Write Cycle *³(WE control) (SRAM)

t^WC

Address

t^AS

t^WP

t^WR

WE

t^AW

t^CW

CE1s

CE2s

t^CW

t^BW

LB, UB

t^OEW

t^ODW

D^OUT

*1

*4

*2

*4

t^DS

t^DH

D^IN

Valid Data In

*1 : If CE1s goes “L” (or CE2s goes “H”) coincident with or after WE goes “L”, the output will

remain at High-Z.

*2 : If CE1s goes “H” (or CE2s goes “L”) coincident with or before WE goes “H”, the output will

remain at High-Z.

*3 : If OE is “H” during the write cycle, the outputs will remain at High-Z.

*4 : Because I/O signals may be in the output state at this Time, input signals of reverse

polarity must not be applied.

44

MB84VD2108XEM/2109XEM-70

• Write Cycle *¹(CE1s control) (SRAM)

t^WC

Address

t^AS

t^WP

t^WR

WE

t^AW

t^CW

CE1s

CE2s

LB, UB

D^OUT

t^CW

t^BW

t^BE

t^COE

t^ODW

t^DS

t^DH

D^IN

*2

Valid Data In

*1 : If OE is “H” during the write cycle, the outputs will remain at High-Z.

*2 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity

must not be applied.

45

MB84VD2108XEM/2109XEM-70

• Write Cycle *¹(CE2s Control) (SRAM)

t^WC

Address

t^AS

t^WP

t^WR

WE

t^CW

CE1s

t^AW

CE2s

t^CW

t^BW

LB, UB

t^BE

t^COE

t^ODW

D^OUT

t^DS

t^DH

D^IN

*2

Valid Data In

*1 : If OE is “H” during the write cycle, the outputs will remain at High-Z.

*2 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity

must not be applied.

46

MB84VD2108XEM/2109XEM-70

• Write Cycle *¹(LB, UB Control) (SRAM)

t^WC

Address

WE

t^WP

t^WR

t^CW

CE1s

CE2s

t^CW

t^AW

t^BW

t^AS

LB, UB

t^BE

t^COE

t^ODW

D^OUT

t^DS

t^DH

*2

Valid Data In

D^IN

*1 : If OE is “H” during the write cycle, the outputs will remain at High-Z.

*2 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity

must not be applied.

47

MB84VD2108XEM/2109XEM-70

2. Data Retention Characteristics (SRAM)

Value

Typ

—

Parameter

Symbol

Unit

Min

1.5

—

Max

3.3

4

Data Retention Supply Voltage

V^DH

I^DDS2

t^CDR

t^R

V

Standby Current

V^DH= 1.5 V

1

µA

ns

Chip Deselect to Data Retention Mode Time

Recovery Time

0

—

t^RC

—

Note : t^RC: Read cycle time

• CE1s Controlled Data Retention Mode *¹

V^CCs

DATA RETENTION MODE

2.7 V

*2

V^IH

V^DH

V^CCS–0.2 V

CE1s

t^CDR

t^R

GND

*1 : In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs–0.2 V or Vss

to 0.2 V during data retention mode. Other input and input/output pins can be used between –0.3 V to

Vccs+0.3 V.

*2 : When CE1s is operating at the V^IHMin level (2.2 V), the standby current is given by I^SB1s during the

transition of V^CCs from 3.3 V to 2.2 V.

• CE2s Controlled Data Retention Mode *

V^CCs

DATA RETENTION MODE

2.7 V

V^DH

V^IH

CE2s

t^CDR

t^R

V^IL

0.2 V

GND

* : In CE2s controlled data retention mode, input and input/output pins can be used between –0.3 V to Vccs+0.3 V.

48

MB84VD2108XEM/2109XEM-70

■ PIN CAPACITANCE

Value

Parameter

Symbol

Test Setup

V^IN= 0

Unit

Typ

11

Max

14

Input Capacitance

C^IN

C^OUT

C^IN2

C^IN3

pF

Output Capacitance

V^OUT= 0

V^IN= 0

12

16

Control Pin Capacitance

WP/ACC Pin Capacitance

14

16

17

20

Note : Test conditions T^A= +25°C, f = 1.0 MHz

■ HANDLING OF PACKAGE

Please handle this package carefully since the sides of package create acute angles.

■ CAUTION

• The high voltage (V^ID) cannot apply to address pins and control pins except RESET.

Exception is when autoselect and sector group protect function are used, then the high voltage (V^ID) can be

applied to RESET.

• Without the high voltage (V^ID) , sector group protection can be achieved by using “Extended Sector Group

Protection” command.

49

MB84VD2108XEM/2109XEM-70

■ ORDERING INFORMATION

MB84VD2108

X

EM

-70

PBS

PACKAGE TYPE

PBS = 56-ball BGA

SPEED OPTION

See Product Selector Guide

Device Revision (Valid Combination)

EM

Bank Size

1 = 0.5Mbit / 15.5Mbit

2 = 2Mbit / 14Mbit

3 = 4Mbit / 12Mbit

4 = 8Mbit / 8Mbit

DEVICE NUMBER/DESCRIPTION

16Mega-bit (2M × 8-bit or 1M × 16-bit) Dual Operation Flash Memory

3.0 V-only Read, Program, and Erase

2Mega-bit (256k × 8-bit or 128K × 16-bit) SRAM

BOOT CODE SECTOR ARCHITECTURE

84VD2108 = Top sector

84VD2109 = Bottom sector

50

MB84VD2108XEM/2109XEM^-70

■ PACKAGE DIMENSION

56-pin plastic FBGA

(BGA-56P-M02)

7.20±0.10(.283±.004)

1.09 –⁺0⁰.^.1¹0¹

B

0.20(.008)

S

B

(Mounting height)

(Stand off)

.043 –⁺.^.0⁰0⁰4⁴

0.39±0.10

(.015±.004)

0.40(.016)

REF

0.80(.031)

REF

0.80(.031)

REF

8

7

6

5

4

3

2

1

A

7.00±0.10

(.276±.004)

0.40(.016)

REF

S

C

H

G

F

E

D

B

A

INDEX-MARK AREA

0.20(.008)

S A

INDEX

+0.10

–0.05

+.004

–.002

56-ø0.45

56-ø.018

M

0.08(.003)

S

A B

0.10(.004)

S

C

2002 FUJITSU LIMITED B56002S-c-1-1

Dimensions in mm (inches)

Note : The values in parentheses are reference values.

51

MB84VD2108XEM/2109XEM^-70

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0306

FUJITSU LIMITED Printed in Japan


型号：	MB84VD21091EM-70PBS
厂家：	SPANSION
描述：	16M (x8/x16) FLASH MEMORY & 2M (x8/x16) STATIC RAM 16M （ X8 / X16 ）Flash存储器和2M （ X8 / X16 ）静态RAM 存储内存集成电路静态存储器
文件：	总53页 (文件大小：866K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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