D324GT90UF_技术文档

Am29DL32xG

Data Sheet

RETIRED

PRODUCT

This product has been retired and is not recommended for designs. For new and current designs,

S29JL032H (for TSOP packages) and S29PL032J (for FBGA packages) supersede AM29DL32xG as

the factory-recommended migration path. Please refer to each respective datasheets for specifica-

tions and ordering information. Availability of this document is retained for reference and historical

purposes only.

The following document contains information on Spansion memory products.

Continuity of Specifications

There is no change to this data sheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal data sheet improvement and are noted in the

document revision summary.

For More Information

Please contact your local sales office for additional information about Spansion memory solutions.

Publication Number 25686 Revision B Amendment 10 Issue Date December 4, 2006

THIS PAGE LEFT INTENTIONALLY BLANK.

DATA SHEET

Am29DL32xG

32 Megabit (4 M x 8-Bit/2 M x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

This product has been retired and is not recommended for designs. For new and current designs, S29JL032H (for TSOP packages) and S29PL032J (for FBGA packages) supersede

AM29DL32xG as the factory-recommended migration path. Please refer to each respective datasheets for specifications and ordering information. Availability of this document is retained

for reference and historical purposes only.”

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

■

Minimum 1 million erase cycles guaranteed per

sector

■

Simultaneous Read/Write operations

— Data can be continuously read from one bank while

executing erase/program functions in other bank

20 year data retention at 125°C

— Reliable operation for the life of the system

— Zero latency between read and write operations

SOFTWARE FEATURES

■

Multiple bank architectures

■

Data Management Software (DMS)

— Three devices available with different bank sizes (refer

to Table 3)

— AMD-supplied software manages data programming,

enabling EEPROM emulation

256-byte Secured Silicon Sector

— Eases historical sector erase flash limitations

— Factory locked and identifiable: 16 bytes available for

secure, random factory Electronic Serial Number;

verifiable as factory locked through autoselect

function. ExpressFlash option allows entire sector to

be available for factory-secured data

■

Supports Common Flash Memory Interface (CFI)

Erase Suspend/Erase Resume

— Suspends erase operations to allow programming in

same bank

— Customer lockable: One time programmable. Once

■

Data# Polling and Toggle Bits

— Provides a software method of detecting the status of

program or erase cycles

locked, data cannot be changed.

■

Zero Power Operation

— Sophisticated power management circuits reduce

power consumed during inactive periods to nearly

zero

Unlock Bypass Program command

— Reduces overall programming time when issuing

multiple program command sequences

Package options

— 63-ball FBGA

— 48-ball FBGA

— 48-pin TSOP

HARDWARE FEATURES

■

Any combination of sectors can be erased

■

Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or erase

cycle completion

— 64-ball Fortified BGA

■

Top or bottom boot block

■

Hardware reset pin (RESET#)

— Hardware method of resetting the internal state

machine to the read mode

Manufactured on 0.17 µm process technology

Compatible with JEDEC standards

WP#/ACC input pin

— Pinout and software compatible with

single-power-supply flash standard

— Write protect (WP#) function allows protection of two

outermost boot sectors, regardless of sector protect

status

PERFORMANCE CHARACTERISTICS

■

High performance

— Access time as fast 70 ns

— Acceleration (ACC) function accelerates program

timing

— Program time: 4 µs/word typical utilizing Accelerate

function

■

Sector protection

— Hardware method of locking a sector, either

in-system or using programming equipment, to

prevent any program or erase operation within that

sector

■

Ultra low power consumption (typical values)

— 2 mA active read current at 1 MHz

— 10 mA active read current at 5 MHz

— 200 nA in standby or automatic sleep mode

— Temporary Sector Unprotect allows changing data in

protected sectors in-system

Publication# 25686 Rev: B Amendment: 10

Issue Date: December 4, 2006

D A T A S H E E T

GENERAL DESCRIPTION

The Am29DL32xG family consists of 32 megabit, 3.0

volt-only flash memory devices, organized as

2,097,152 words of 16 bits each or 4,194,304 bytes of

8 bits each. Word mode data appears on DQ15–DQ0;

byte mode data appears on DQ7–DQ0. The device is

designed to be programmed in-system with the stan-

dard 3.0 volt V_CCsupply, and can also be programmed

in standard EPROM programmers.

(programmed through AMD’s ExpressFlash service),

or both.

DMS (Data Management Software) allows systems

to easily take advantage of the advanced architecture

of the simultaneous read/write product line by allowing

removal of EEPROM devices. DMS will also allow the

system software to be simplified, as it will perform all

functions necessary to modify data in file structures,

as opposed to single-byte modifications. To write or

update a particular piece of data (a phone number or

configuration data, for example), the user only needs

to state which piece of data is to be updated, and

where the updated data is located in the system. This

is an advantage compared to systems where

user-written software must keep track of the old data

location, status, logical to physical translation of the

data onto the Flash memory device (or memory de-

vices), and more. Using DMS, user-written software

does not need to interface with the Flash memory di-

rectly. Instead, the user's software accesses the Flash

memory by calling one of only six functions. AMD pro-

vides this software to simplify system design and soft-

ware integration efforts.

The devices are available with an access time of 70,

90, or 120 ns. The devices are offered in 48-pin TSOP,

48-ball or 63-ball FBGA, and 64-ball Fortified BGA

packages. Standard control pins—chip enable (CE#),

write enable (WE#), and output enable (OE#)—control

normal read and write operations, and avoid bus con-

tention issues.

The devices requires only a single 3.0 volt power

supply for both read and write functions. Internally

generated and regulated voltages are provided for the

program and erase operations.

Simultaneous Read/Write Operations with

Zero Latency

The Simultaneous Read/Write architecture provides

simultaneous operation by dividing the memory

space into two banks. The device can improve overall

system performance by allowing a host system to pro-

gram or erase in one bank, then immediately and si-

multaneously read from the other bank, with zero

latency. This releases the system from waiting for the

completion of program or erase operations.

The device offers complete compatibility with the

JEDEC single-power-supply Flash command set

standard. Commands are written to the command

register using standard microprocessor write timings.

Reading data out of the device is similar to reading

from other Flash or EPROM devices.

The host system can detect whether a program or

erase operation is complete by using the device sta-

tus bits: RY/BY# pin, DQ7 (Data# Polling) and

DQ6/DQ2 (toggle bits). After a program or erase cycle

has been completed, the device automatically returns

to the read mode.

The Am29DL32xG device family uses multiple bank

architectures to provide flexibility for different applica-

tions. Three devices are available with the following

bank sizes:

Device

DL322

DL323

DL324

Bank 1

Bank 2

28

The sector erase architecture allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

4

8

24

16

Am29DL32xG Features

Hardware data protection measures include a low

V_CCdetector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of mem-

ory. This can be achieved in-system or via program-

ming equipment.

The Secured Silicon Sector is an extra sector capable

of being permanently locked by AMD or customers.

The Secured Silicon Indicator Bit (DQ7) is perma-

nently set to a 1 if the part is factory locked, and set

to a 0 if customer lockable. This way, customer lock-

able parts can never be used to replace a factory

locked part. Current version of device has 256

bytes, which differs from previous versions of this

device.

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the automatic sleep mode.

The system can also place the device into the

standby mode. Power consumption is greatly re-

duced in both modes.

Factory locked parts provide several options. The Se-

cured Silicon Sector may store a secure, random 16

byte ESN (Electronic Serial Number), customer code

2

Am29DL32xG

25686B10 December 4, 2006

D A T A S H E E T

TABLE OF CONTENTS

Unlock Bypass Command Sequence ................................... 26

Figure 3. Program Operation.............................................................................................. 26

Chip Erase Command Sequence ............................................ 26

Sector Erase Command Sequence ......................................... 27

Erase Suspend/Erase Resume Commands ............................ 27

Figure 4. Erase Operation................................................................................................... 28

Table 14. Command Definitions......................................................................................... 29

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10

Table 1. Device Bus Operations ........................................................................................ 10

Word/Byte Configuration .......................................................... 10

Requirements for Reading Array Data .....................................10

Writing Commands/Command Sequences ..............................11

Accelerated Program Operation ...........................................11

Autoselect Functions .............................................................11

Simultaneous Read/Write Operations

with Zero Latency .....................................................................11

Standby Mode .......................................................................... 11

Automatic Sleep Mode .............................................................11

RESET#: Hardware Reset Pin .................................................12

Output Disable Mode ...............................................................12

Table 2. Device Bank Divisions .......................................................................................... 12

Table 3. Top Boot Sector Addresses ...............................................................................13

Table 4. Top Boot Secured Silicon Sector Addresses .................................................... 14

Table 5. Bottom Boot Sector Addresses ........................................................................... 15

Table 6. Bottom Boot Secured Silicon Sector Addresses ............................................. 16

Autoselect Mode ...................................................................... 17

Table 7. Autoselect Codes, (High Voltage Method) ....................................................... 17

Sector/Sector Block Protection and Unprotection .................... 18

Table 8. Top Boot Sector/Sector Block Addresses for Protection/Unprotection .........18

Table 9. Bottom Boot Sector/Sector Block Addresses for Protection/Unprotection ...18

Write Protect (WP#) .................................................................19

Temporary Sector Unprotect ....................................................19

Figure 1. Temporary Sector Unprotect Operation........................................................... 19

Figure 2. In-System Sector Protection/

Write Operation Status . . . . . . . . . . . . . . . . . . . . 30

DQ7: Data# Polling .................................................................. 30

Figure 5. Data# Polling Algorithm....................................................................................... 30

RY/BY#: Ready/Busy# ..............................................................31

DQ6: Toggle Bit I ..................................................................... 31

Figure 6. Toggle Bit Algorithm............................................................................................. 31

DQ2: Toggle Bit II .................................................................... 32

Reading Toggle Bits DQ6/DQ2 ................................................ 32

DQ5: Exceeded Timing Limits ................................................. 32

DQ3: Sector Erase Timer ........................................................ 32

Table 15. Write Operation Status .......................................................................................33

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 34

Figure 7. Maximum Negative Overshoot Waveform....................................................... 34

Figure 8. Maximum Positive Overshoot Waveform......................................................... 34

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 9. I_CC1Current vs. Time (Showing Active and Automatic Sleep Currents)...... 36

Figure 10. Typical I_CC1vs. Frequency................................................................................ 36

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 11. Test Setup.......................................................................................................... 37

Figure 12. Input Waveforms and Measurement Levels.................................................. 37

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 13. Read Operation Timings................................................................................... 38

Figure 14. Reset Timings..................................................................................................... 39

Word/Byte Configuration (BYTE#) ........................................... 40

Figure 15. BYTE# Timings for Read Operations............................................................. 40

Figure 16. BYTE# Timings for Write Operations.............................................................. 40

Erase and Program Operations ............................................... 41

Figure 17. Program Operation Timings............................................................................. 42

Figure 18. Accelerated Program Timing Diagram........................................................... 42

Figure 19. Chip/Sector Erase Operation Timings............................................................ 43

Figure 20. Back-to-back Read/Write Cycle Timings........................................................ 44

Figure 21. Data# Polling Timings (During Embedded Algorithms)............................... 44

Figure 22. Toggle Bit Timings (During Embedded Algorithms)..................................... 45

Figure 23. DQ2 vs. DQ6...................................................................................................... 45

Temporary Sector Unprotect ................................................... 46

Figure 24. Temporary Sector Unprotect Timing Diagram.............................................. 46

Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram...................... 47

Alternate CE# Controlled Erase and Program Operations ...... 48

Figure 26. Alternate CE# Controlled Write (Erase/Program) Operation Timings........ 49

Sector Unprotection Algorithms.......................................................................................... 20

Secured Silicon Sector

Flash Memory Region ..............................................................21

Factory Locked: Secured Silicon Sector Programmed and Pro-

tected At the Factory .............................................................21

Customer Lockable: Secured Silicon Sector NOT Programmed

or Protected At the Factory ...................................................21

Hardware Data Protection ........................................................21

Low VCC Write Inhibit ...........................................................22

Write Pulse “Glitch” Protection ..............................................22

Logical Inhibit ........................................................................22

Power-Up Write Inhibit ..........................................................22

Common Flash Memory Interface (CFI) . . . . . . . 22

Table 10. CFI Query Identification String.......................................................................... 22

Table 11. System Interface String...................................................................................... 23

Table 12. Device Geometry Definition............................................................................... 23

Table 13. Primary Vendor-Specific Extended Query...................................................... 24

Erase And Programming Performance . . . . . . . 50

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 50

TSOP Pin and Fine-Pitch BGA Capacitance. . . . 50

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 51

FBD063—63-ball Fine-Pitch Ball Grid Array (FBGA)

8 x 14 mm ................................................................................ 51

FBD048—Fine-Pitch Ball Grid Array, 6 x 12 mm ..................... 52

TS 048—Thin Small Outline Package ..................................... 53

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 55

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 24

Reading Array Data ..................................................................24

Reset Command ......................................................................25

Autoselect Command Sequence ..............................................25

Enter Secured Silicon Sector/Exit Secured Silicon Sector Com-

mand Sequence .......................................................................25

Byte/Word Program Command Sequence ...............................25

December 4, 2006 25686B10

Am29DL32xG

3

D A T A S H E E T

PRODUCT SELECTOR GUIDE

Part Number

Am29DL32xG

Speed Rating

Standard Voltage Range: V_CC= 2.7–3.6 V

70

30

90

40

120

40

Max Access Time (ns)

CE# Access (ns)

OE# Access (ns)

BLOCK DIAGRAM

OE# BYTE#

V

CC

SS

Upper Bank Address

A20–A0

Upper Bank

RY/BY#

X-Decoder

A20–A0

RESET#

STATE

CONTROL

&

COMMAND

REGISTER

WE#

CE#

Status

DQ15–DQ0

BYTE#

Control

WP#/ACC

DQ15–DQ0

X-Decoder

Lower Bank

A20–A0

Lower Bank Address

OE# BYTE#

4

Am29DL32xG

25686B10 December 4, 2006

D A T A S H E E T

CONNECTION DIAGRAMS

A15

A14

A13

A12

A11

A10

A9

A8

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE#

V_SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V_CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

V_SS

CE#

A0

48-Pin Standard TSOP

A19

A20

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

WE#

RESET#

NC

WP#/ACC

RY/BY#

A18

A17

A7

A6

A5

A4

A3

A2

A1

63-Ball Fine-pitch BGA (8 x 14 mm)

L8

M8

A8

B8

Top View, Balls Facing Down

NC

NC*

A7

B7

C7

D7

E7

F7

G7

H7

J7

K7

L7

M7

V_SS

NC

NC*

A13

A12

A14

A15

A16

BYTE# DQ15/A-1

C6

A9

D6

A8

E6

F6

G6

H6

J6

K6

A10

A11

DQ7

DQ14

DQ13

DQ6

C5

D5

E5

F5

G5

H5

J5

K5

V_CC

WE# RESET#

NC

A19

DQ5

DQ12

DQ4

C4 D4

E4

F4

G4

H4

J4

K4

RY/BY# WP#/ACC A18

A20

DQ2

DQ10

DQ11

DQ3

C3

A7

D3

E3

A6

F3

A5

G3

H3

J3

K3

A17

DQ0

DQ8

DQ9

DQ1

C2

A3

D2

A4

E2

A2

F2

A1

G2

A0

H2

J2

K2

L2

M2

A2

V_SS

CE#

OE#

NC*

A1

B1

L1

M1

* Balls are shorted together via the substrate but not connected to the die.

NC*

December 4, 2006 25686B10

Am29DL32xG

5

D A T A S H E E T

CONNECTION DIAGRAMS

48-Ball Fine-pitch BGA (6 x 12 mm)

Top View, Balls Facing Down

A6

B6

C6

D6

E6

F6

G6

H6

V

SS

A13

A12

A14

A15

A16

BYTE# DQ15/A-1

A5

A9

B5

A8

C5

D5

E5

F5

G5

H5

A10

A11

DQ7

DQ14

DQ13

DQ6

A4

B4

C4

NC

D4

E4

F4

G4

H4

V

WE#

RESET#

A19

DQ5

DQ12

CC

DQ4

A3

B3

C3

D3

E3

F3

G3

H3

RY/BY# WP#/ACC

A18

A20

DQ2

DQ10

DQ11

DQ3

A2

A7

B2

C2

A6

D2

A5

E2

F2

G2

H2

A17

DQ0

DQ8

DQ9

DQ1

A1

A3

B1

A4

C1

A2

D1

A1

E1

A0

F1

G1

H1

V

SS

CE#

OE#

64-Ball Fortified BGA (11 x 13 mm)

Top View, Balls Facing Down

A8

B8

C8

D8

E8

F8

G8

H8

RFU

V_CCQ

V_SS

RFU

A7

B7

C7

D7

E7

F7

G7

H7

A13

A12

A14

A15

A16

BYTE#

DQ15

V_SS

A6

A9

B6

A8

C6

D6

E6

F6

G6

H6

DQ6

A10

A11

DQ7

DQ14

DQ13

A5

B5

C5

D5

E5

F5

G5

H5

WE# RESET#

A21

A19

DQ5

DQ12

V_CC

DQ4

A4 B4

C4

D4

E4

F4

G4

H4

RY/BY# WP#/ACC A18

A20

DQ2

DQ10

DQ11

DQ3

A3

A7

B3

C3

A6

D3

A5

E3

F3

G3

H3

A17

DQ0

DQ8

DQ9

DQ1

A2

A3

B2

A4

C2

A2

D2

A1

E2

A0

F2

G2

H2

CE#

OE#

V_SS

A1

B1

C1

D1

E1

F1

G1

H1

RFU

V_CCQ

RFU

The package and/or data integrity may be compromised

if the package body is exposed to temperatures above

150°C for prolonged periods of time.

Special Package Handling Instructions

Special handling is required for Flash Memory prod-

ucts in molded packages (TSOP, BGA, PLCC, SSOP).

6

Am29DL32xG

25686B10 December 4, 2006

D A T A S H E E T

PIN DESCRIPTION

LOGIC SYMBOL

A20–A0

= 21 Addresses

21

DQ14–DQ0 = 15 Data Inputs/Outputs

A20–A0

16 or 8

DQ15/A-1

= DQ15 (Data Input/Output, word

mode), A-1 (LSB Address Input, byte

mode)

DQ15–DQ0

(A-1)

CE#

OE#

CE#

OE#

WE#

= Chip Enable

= Output Enable

= Write Enable

WE#

WP#/ACC

RESET#

BYTE#

WP#/ACC = Hardware Write Protect/

Acceleration Pin

RY/BY#

RESET#

BYTE#

RY/BY#

V_CC

= Hardware Reset Pin, Active Low

= Selects 8-bit or 16-bit mode

= Ready/Busy Output

= 3.0 volt-only single power supply

(see Product Selector Guide for speed

options and voltage supply tolerances)

V_SS

NC

= Device Ground

= Pin Not Connected Internally

= Reserved for Future Use

RFU

December 4, 2006 25686B10

Am29DL32xG

7

D A T A S H E E T

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of the following:

Am29DL32xG

T

70

E

I

OPTIONAL PROCESSING

Blank = Standard Processing

N

=

16-byte ESN devices

(Contact an AMD representative for more information)

TEMPERATURE RANGE

I

=

Industrial (–40°C to +85°C)

Industrial (–40°C to +85°C) with Pb-free package

F

PACKAGE TYPE

E

=

48-Pin Thin Small Outline Package

(TSOP) Standard Pinout (TS 048)

WD

WM

PC

63-Ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 8 x 14 mm package (FBD063)

48-Ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 6 x 12 mm package (FBD048)

64-Ball Fortified Pitch Ball Grid Array (FBGA)

1.00 mm pitch, 11 x 13 mm package (LAA064)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T

B

=

Top sector

Bottom sector

DEVICE NUMBER/DESCRIPTION

Am29DL32xG

32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations for TSOP Packages

AM29DL322GT70,

AM29DL322GB70

Valid Combinations for FBGA Packages

Order Number Package Marking

AM29DL322GT70,

D322GT70U,

D322GB70U

AM29DL323GT70

AM29DL323GB70

AM29DL322GB70

AM29DL323GT70,

AM29DL323GB70

D323GT70U,

D323GB70U

AM29DL324GT70,

AM29DL324GB70

AM29DL324GT70,

AM29DL324GB70

D324GT70U,

D324GB70U

AM29DL322GT90,

AM29DL322GB90

AM29DL322GT90,

AM29DL322GB90

D322GT90U,

D322GB90U

AM29DL323GT90,

AM29DL323GB90

WMI,

WMIN,

WMF

AM29DL323GT90,

AM29DL323GB90

D323GT90U,

D323GB90U

EI, EIN,

EF

I, F

AM29DL324GT90,

AM29DL324GB90

AM29DL324GT90,

AM29DL324GB90

D324GT90U,

D324GB90U

AM29DL322GT120,

AM29DL322GB120

AM29DL323GT120,

AM29DL323GB120

AM29DL324GT120,

AM29DL324GB120

AM29DL322GT120,

AM29DL322GB120

D322GT12U,

D322GB12U

AM29DL323GT120,

AM29DL323GB120

D323GT12U,

D323GB12U

AM29DL324GT120,

AM29DL324GB120

D324GT12U,

D324GB12U

8

Am29DL32xG

25686B10 December 4, 2006

D A T A S H E E T

Valid Combinations for FBGA Packages

Order Number Package Marking

AM29DL322GT70,

Valid Combinations

Valid Combinations list configurations planned to be supported in

volume for this device. Consult the local AMD sales office to con-

firm availability of specific valid combinations and to check on

newly released combinations.

D322GT70V,

D322GB70V

AM29DL322GB70

AM29DL323GT70,

AM29DL323GB70

D323GT70V,

D323GB70V

AM29DL324GT70,

AM29DL324GB70

D324GT70V,

D324GB70V

AM29DL322GT90,

AM29DL322GB90

D322GT90V,

D322GB90V

WDI,

WDIN,

WDF

AM29DL323GT90,

AM29DL323GB90

D323GT90V,

D323GB90V

I, F

AM29DL324GT90,

AM29DL324GB90

D324GT90V,

D324GB90V

AM29DL322GT120,

AM29DL322GB120

D322GT12V,

D322GB12V

AM29DL323GT120,

AM29DL323GB120

D323GT12V,

D323GB12V

AM29DL324GT120,

AM29DL324GB120

D324GT12V,

D324GB12V

Valid Combinations for Fortified BGA Packages

Order Number Package Marking

AM29DL322GT70, D322GT70P,

AM29DL322GB70

D322GB70P

AM29DL323GT70,

AM29DL323GB70

D323GT70P,

D323GB70P

AM29DL324GT70,

AM29DL324GB70

D324GT70P,

D324GB70P

AM29DL322GT90,

AM29DL322GB90

D322GT90P

D322GB90P

AM29DL323GT90,

AM29DL323GB90

PCI,

PCF

D323GT90P,

D323GB90P

I, F

AM29DL324GT90,

AM29DL324GB90

D324GT90P,

D324GB90P

AM29DL322GT120,

AM29DL322GB120

D322GT12P,

D322GB12P

AM29DL323GT120,

AM29DL323GB120

D323GT12P,

D323GB12P

AM29DL324GT120,

AM29DL324GB120

D324GT12P,

D324GB12P

December 4, 2006 25686B10

Am29DL32xG

9

D A T A S H E E T

DEVICE BUS OPERATIONS

This section describes the requirements and use of

the device bus operations, which are initiated through

the internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is a latch used to store the com-

mands, along with the address and data information

needed to execute the command. The contents of the

register serve as inputs to the internal state machine.

The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the in-

puts and control levels they require, and the resulting

output. The following subsections describe each of

these operations in further detail.

Table 1. Device Bus Operations

DQ15–DQ8

BYTE#

Addresses

(Note 2)

BYTE#

= V_IH

DQ7–

DQ0

Operation

CE# OE# WE# RESET# WP#/ACC

= V_IL

Read

Write

L

H

L

H

L/H

A_IN

D_OUT

D_IN

D_OUT

D_IN

DQ8–DQ14 =

High-Z, DQ15 = A-1

H

(Note 3)

V_CC

0.3 V

±

V_CC±

0.3 V

Standby

X

H

X

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

L/H

X

High-Z

X

SA, A6 = L,

A1 = H, A0 = L

Sector Protect (Note 2)

L

H

X

L

V_ID

L/H

X

D_IN

SA, A6 = H,

A1 = H, A0 = L

Sector Unprotect (Note 2)

(Note 3)

Temporary Sector

Unprotect

X

A_IN

D_IN

High-Z

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 8.5–12.5 V, V_HH= 9.0 0.5 V, X = Don’t Care, SA = Sector Address,

A_IN= Address In, D_IN= Data In, D_OUT= Data Out

Notes:

1. Addresses are A20:A0 in word mode (BYTE# = V_IH), A20:A-1 in byte mode (BYTE# = V_IL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector

Block Protection and Unprotection” section.

3. If WP#/ACC = V_IL, the two outermost boot sectors remain protected. If WP#/ACC = V_IH, the two outermost boot sector

protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block

Protection and Unprotection”. If WP#/ACC = V_HH, all sectors will be unprotected.

Word/Byte Configuration

Requirements for Reading Array Data

The BYTE# pin controls whether the device data I/O

pins operate in the byte or word configuration. If the

BYTE# pin is set at logic ‘1’, the device is in word con-

figuration, DQ0–DQ15 are active and controlled by

CE# and OE#.

To read array data from the outputs, the system must

drive the CE# and OE# pins to V_IL. CE# is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE#

should remain at V_IH. The BYTE# pin determines

whether the device outputs array data in words or

bytes.

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ7–DQ0 are

active and controlled by CE# and OE#. The data I/O

pins DQ8–DQ14 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No com-

mand is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid

10

Am29DL32xG

25686B10 December 4, 2006

D A T A S H E E T

data on the device data outputs. Each bank remains

at V_HHfor operations other than accelerated program-

ming, or device damage may result. In addition, the

WP#/ACC pin must not be left floating or unconnected;

inconsistent behavior of the device may result.

enabled for read access until the command register

contents are altered.

See “Requirements for Reading Array Data” for more

information. Refer to the AC Read-Only Operations

table for timing specifications and to Figure 13 for the

timing diagram. I_CC1in the DC Characteristics table

represents the active current specification for reading

array data.

Autoselect Functions

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in

this mode. Refer to the Autoselect Mode and Autose-

lect Command Sequence sections for more informa-

tion.

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V_IL, and OE# to V_IH.

Simultaneous Read/Write Operations

with Zero Latency

For program operations, the BYTE# pin determines

whether the device accepts program data in bytes or

words. Refer to “Word/Byte Configuration” for more in-

formation.

This device is capable of reading data from one bank

of memory while programming or erasing in the other

bank of memory. An erase operation may also be sus-

pended to read from or program to another location

within the same bank (except the sector being

erased). Figure 20 shows how read and write cycles

may be initiated for simultaneous operation with zero

latency. I_CC6and I_CC7in the DC Characteristics table

represent the current specifications for read-while-pro-

gram and read-while-erase, respectively.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once a bank enters the Un-

lock Bypass mode, only two write cycles are required

to program a word or byte, instead of four. The

“Word/Byte Configuration” section has details on pro-

gramming data to the device using both standard and

Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Tables 3–6 indicate the ad-

dress space that each sector occupies. The device

address space is divided into two banks: Bank 1 con-

tains the boot/parameter sectors, and Bank 2 contains

the larger, code sectors of uniform size. A “bank ad-

dress” is the address bits required to uniquely select a

bank. Similarly, a “sector address” is the address bits

required to uniquely select a sector.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V_CC0.3 V.

(Note that this is a more restricted voltage range than

V_IH.) If CE# and RESET# are held at V_IH, but not within

V_CC0.3 V, the device will be in the standby mode,

but the standby current will be greater. The device re-

quires standard access time (t_CE) for read access

when the device is in either of these standby modes,

before it is ready to read data.

I_CC2in the DC Characteristics table represents the ac-

tive current specification for the write mode. The AC

Characteristics section contains timing specification

tables and timing diagrams for write operations.

Accelerated Program Operation

The device offers accelerated program operations

through the ACC function. This is one of two functions

provided by the WP#/ACC pin. This function is prima-

rily intended to allow faster manufacturing throughput

at the factory.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

I_CC3in the DC Characteristics table represents the

standby current specification.

If the system asserts V_HHon this pin, the device auto-

matically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sectors,

and uses the higher voltage on the pin to reduce the

time required for program operations. The system

would use a two-cycle program command sequence

as required by the Unlock Bypass mode. Removing

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

this mode when addresses remain stable for t_ACC

+

30 ns. The automatic sleep mode is independent of

the CE#, WE#, and OE# control signals. Standard ad-

dress access timings provide new data when ad-

V

_HHfrom the WP#/ACC pin returns the device to nor-

mal operation. Note that the WP#/ACC pin must not be

December 4, 2006 25686B10

Am29DL32xG

11

D A T A S H E E T

dresses are changed. While in sleep mode, output

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

data is latched and always available to the system.

I_CC5in the DC Characteristics table represents the

automatic sleep mode current specification.

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of t_READY(during Embedded Algorithms). The sys-

tem can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of t_READY(not during Embedded Algo-

rithms). The system can read data t_RHafter the RE-

SET# pin returns to V_IH.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of t_RP, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is

ready to accept another command sequence, to en-

sure data integrity.

I_CC4in the DC Characteristics table represents the

reset current. Also refer to AC Characteristics tables

for RESET# timing parameters and to Figure 14 for the

timing diagram.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V_SS0.3 V, the device

draws CMOS standby current (I_CC4). If RESET# is held

at V_ILbut not within V_SS0.3 V, the standby current will

be greater.

Output Disable Mode

When the OE# input is at V_IH, output from the device is

disabled. The output pins are placed in the high

impedance state.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

Table 2. Device Bank Divisions

Bank 1

Bank 2

Sector Sizes

Device

Part Number

Megabits

Sector Sizes

Megabits

Eight 8 Kbyte/4 Kword,

seven 64 Kbyte/32 Kword

Fifty-six

64 Kbyte/32 Kword

Am29DL322G

4 Mbit

28 Mbit

Eight 8 Kbyte/4 Kword,

fifteen 64 Kbyte/32 Kword

Forty-eight

64 Kbyte/32 Kword

Am29DL323G

Am29DL324G

8 Mbit

24 Mbit

16 Mbit

Eight 8 Kbyte/4 Kword,

thirty-one 64 Kbyte/32 Kword

Thirty-two

64 Kbyte/32 Kword

16 Mbit

12

Am29DL32xG

25686B10 December 4, 2006

D A T A S H E E T

Table 3. Top Boot Sector Addresses

Sector Address

Sector Size

(Kbytes/Kwords)

(x8)

(x16)

Address Range

Sector

A20–A12

Address Range

SA0

SA1

000000xxx

000001xxx

000010xxx

000011xxx

000100xxx

000101xxx

000110xxx

000111xxx

001000xxx

001001xxx

001010xxx

001011xxx

001100xxx

001101xxx

001110xxx

001111xxx

010000xxx

010001xxx

010010xxx

010011xxx

010100xxx

010101xxx

010110xxx

010111xxx

011000xxx

011001xxx

011010xxx

011011xxx

011100xxx

011101xxx

011110xxx

011111xxx

100000xxx

100001xxx

100010xxx

100011xxx

100100xxx

100101xxx

100110xxx

100111xxx

101000xxx

101001xxx

101010xxx

101011xxx

101100xxx

101101xxx

101110xxx

101111xxx

64/32

000000h–00FFFFh

010000h–01FFFFh

020000h–02FFFFh

030000h–03FFFFh

040000h–04FFFFh

050000h–05FFFFh

060000h–06FFFFh

070000h–07FFFFh

080000h–08FFFFh

090000h–09FFFFh

0A0000h–0AFFFFh

0B0000h–0BFFFFh

0C0000h–0CFFFFh

0D0000h–0DFFFFh

0E0000h–0EFFFFh

0F0000h–0FFFFFh

100000h–10FFFFh

110000h–11FFFFh

120000h–12FFFFh

130000h–13FFFFh

140000h–14FFFFh

150000h–15FFFFh

160000h–16FFFFh

170000h–17FFFFh

180000h–18FFFFh

190000h–19FFFFh

1A0000h–1AFFFFh

1B0000h–1BFFFFh

1C0000h–1CFFFFh

1D0000h–1DFFFFh

1E0000h–1EFFFFh

1F0000h–1FFFFFh

200000h–20FFFFh

210000h–21FFFFh

220000h–22FFFFh

230000h–23FFFFh

240000h–24FFFFh

250000h–25FFFFh

260000h–26FFFFh

270000h–27FFFFh

280000h–28FFFFh

290000h–29FFFFh

2A0000h–2AFFFFh

2B0000h–2BFFFFh

2C0000h–2CFFFFh

2D0000h–2DFFFFh

2E0000h–2EFFFFh

2F0000h–2FFFFFh

000000h–07FFFh

008000h–0FFFFh

010000h–17FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

December 4, 2006 25686B10

Am29DL32xG

13

D A T A S H E E T

Table 3. Top Boot Sector Addresses (Continued)

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

(x16)

Address Range

Sector

Address Range

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

110000xxx

110001xxx

110010xxx

110011xxx

110100xxx

110101xxx

110110xxx

110111xxx

111000xxx

111001xxx

111010xxx

111011xxx

111100xxx

111101xxx

111110xxx

111111000

111111001

111111010

111111011

111111100

111111101

111111110

111111111

64/32

8/4

300000h–30FFFFh

310000h–31FFFFh

320000h–32FFFFh

330000h–33FFFFh

340000h–34FFFFh

350000h–35FFFFh

360000h–36FFFFh

370000h–37FFFFh

380000h–38FFFFh

390000h–39FFFFh

3A0000h–3AFFFFh

3B0000h–3BFFFFh

3C0000h–3CFFFFh

3D0000h–3DFFFFh

3E0000h–3EFFFFh

3F0000h–3F1FFFh

3F2000h–3F3FFFh

3F4000h–3F5FFFh

3F6000h–3F7FFFh

3F8000h–3F9FFFh

3FA000h–3FBFFFh

3FC000h–3FDFFFh

3FE000h–3FFFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1F8FFFh

1F9000h–1F9FFFh

1FA000h–1FAFFFh

1FB000h–1FBFFFh

1FC000h–1FCFFFh

1FD000h–1FDFFFh

1FE000h–1FEFFFh

1FF000h–1FFFFFh

8/4

Note: The address range is A20:A-1 in byte mode (BYTE#=V_IL) or A20:A0 in word mode (BYTE#=V_IH). The bank address bits are A20–A18 for

Am29DL322, A20 and A19 for Am29DL323, and A20 for Am29DL324.

Table 4. Top Boot Secured Silicon Sector Addresses

Sector Address

A20–A12

Sector Size

(bytes/words)

(x8)

(x16)

Address Range

Device

Address Range

Am29DL32xGT

111111xxx

256/128

3FE000h–3FE0FFh

1FF000h–1FF07Fh

14

Am29DL32xG

25686B10 December 4, 2006

D A T A S H E E T

Table 5. Bottom Boot Sector Addresses

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

(x16)

Address Range

Sector

Address Range

SA0

SA1

000000000

000000001

000000010

000000011

000000100

000000101

000000110

000000111

000001xxx

000010xxx

000011xxx

000100xxx

000101xxx

000110xxx

000111xxx

001000xxx

001001xxx

001010xxx

001011xxx

001100xxx

001101xxx

001110xxx

001111xxx

010000xxx

010001xxx

010010xxx

010011xxx

010100xxx

010101xxx

010110xxx

010111xxx

011000xxx

011001xxx

011010xxx

011011xxx

011100xxx

011101xxx

011110xxx

011111xxx

8/4

000000h-001FFFh

002000h-003FFFh

004000h-005FFFh

006000h-007FFFh

008000h-009FFFh

00A000h-00BFFFh

00C000h-00DFFFh

00E000h-00FFFFh

010000h-01FFFFh

020000h-02FFFFh

030000h-03FFFFh

040000h-04FFFFh

050000h-05FFFFh

060000h-06FFFFh

070000h-07FFFFh

080000h-08FFFFh

090000h-09FFFFh

0A0000h-0AFFFFh

0B0000h-0BFFFFh

0C0000h-0CFFFFh

0D0000h-0DFFFFh

0E0000h-0EFFFFh

0F0000h-0FFFFFh

100000h-10FFFFh

110000h-11FFFFh

120000h-12FFFFh

130000h-13FFFFh

140000h-14FFFFh

150000h-15FFFFh

160000h-16FFFFh

170000h-17FFFFh

180000h-18FFFFh

190000h-19FFFFh

1A0000h-1AFFFFh

1B0000h-1BFFFFh

1C0000h-1CFFFFh

1D0000h-1DFFFFh

1E0000h-1EFFFFh

1F0000h-1FFFFFh

000000h–000FFFh

001000h–001FFFh

002000h–002FFFh

003000h–003FFFh

004000h–004FFFh

005000h–005FFFh

006000h–006FFFh

007000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

8/4

SA2

8/4

SA3

8/4

SA4

8/4

SA5

8/4

SA6

8/4

SA7

8/4

SA8

64/32

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

December 4, 2006 25686B10

Am29DL32xG

15

D A T A S H E E T

Table 5. Bottom Boot Sector Addresses (Continued)

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

(x16)

Address Range

Sector

Address Range

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

100000xxx

100001xxx

100010xxx

100011xxx

100100xxx

100101xxx

100110xxx

100111xxx

101000xxx

101001xxx

101010xxx

101011xxx

101100xxx

101101xxx

101110xxx

101111xxx

111000xxx

110001xxx

110010xxx

110011xxx

110100xxx

110101xxx

110110xxx

110111xxx

111000xxx

111001xxx

111010xxx

111011xxx

111100xxx

111101xxx

111110xxx

111111xxx

64/32

200000h-20FFFFh

210000h-21FFFFh

220000h-22FFFFh

230000h-23FFFFh

240000h-24FFFFh

250000h-25FFFFh

260000h-26FFFFh

270000h-27FFFFh

280000h-28FFFFh

290000h-29FFFFh

2A0000h-2AFFFFh

2B0000h-2BFFFFh

2C0000h-2CFFFFh

2D0000h-2DFFFFh

2E0000h-2EFFFFh

2F0000h-2FFFFFh

300000h-30FFFFh

310000h-31FFFFh

320000h-32FFFFh

330000h-33FFFFh

340000h-34FFFFh

350000h-35FFFFh

360000h-36FFFFh

370000h-37FFFFh

380000h-38FFFFh

390000h-39FFFFh

3A0000h-3AFFFFh

3B0000h-3BFFFFh

3C0000h-3CFFFFh

3D0000h-3DFFFFh

3E0000h-3EFFFFh

3F0000h-3FFFFFh

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

Note: The address range is A20:A-1 in byte mode (BYTE#=V_IL) or A20:A0 in word mode (BYTE#=V_IH). The bank address bits

are A20–A18 for Am29DL322G, A20 and A19 for Am29DL323G, and A20 for Am29DL324G.

Table 6. Bottom Boot Secured Silicon Sector Addresses

Sector Address

A20–A12

Sector Size

(Bytes/Words)

(x8)

(x16)

Address Range

Device

Address Range

Am29DL32xGB

000000xxx

256/128

000000h–0000FFh

00000h–00007Fh

16

Am29DL32xG

25686B10 December 4, 2006

D A T A S H E E T

Table 7. In addition, when verifying sector protection,

Autoselect Mode

the sector address must appear on the appropriate

highest order address bits (see Tables 3–6). Table 7

shows the remaining address bits that are don’t care.

When all necessary bits have been set as required,

the programming equipment may then read the corre-

sponding identifier code on DQ7–DQ0.

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equip-

ment to automatically match a device to be pro-

grammed with its corresponding programming

algorithm. However, the autoselect codes can also be

accessed in-system through the command register.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 14. This method

does not require V_ID. Refer to the Autoselect Com-

mand Sequence section for more information.

When using programming equipment, the autoselect

mode requires V_ID(8.5 V to 12.5 V) on address pin A9.

Address pins A6, A1, and A0 must be as shown in

Table 7. Autoselect Codes, (High Voltage Method)

DQ8 to DQ15

A20

to

A11

to

A8

to

A5

to

DQ7

to

BYTE# BYTE#

Description

CE# OE# WE# A12

A10 A9 A7 A6 A2 A1 A0

= V_IH

= V_IL

DQ0

V_ID

Manufacturer ID: AMD

Device ID: Am29DL322G

Device ID: Am29DL323G

Device ID: Am29DL324G

L

H

BA

X

L

X

L

H

X

01h

22h

X

55h (T), 56h (B)

50h (T), 53h (B)

5Ch (T), 5Fh (B)

X

Sector Protection

Verification

01h (protected),

00h (unprotected)

V_ID

L

H

SA

BA

X

L

X

H

L

X

82h (factory locked),

02h (not factory

locked)

Secured Silicon Indicator

Bit (DQ7)

H

Legend: T = Top Boot Block, B = Bottom Boot Block, L = Logic Low = V_IL, H = Logic High = V_IH, BA = Bank Address, SA = Sector Address, X =

Don’t care.

December 4, 2006 25686B10

Am29DL32xG

17

D A T A S H E E T

Table 9. Bottom Boot Sector/Sector Block

Addresses for Protection/Unprotection

Sector/Sector Block Protection and

Unprotection

Sector/Sector Block

Size

(Note: For the following discussion, the term “sector”

applies to both sectors and sector blocks. A sector

block consists of two or more adjacent sectors that are

protected or unprotected at the same time (see Tables

8 and 9).

Sector

A20–A12

SA70

111111XXX

64 Kbytes

111110XXX,

111101XXX,

111100XXX

SA69-SA67

192 (3x64) Kbytes

The hardware sector protection feature disables both

program and erase operations in any sector. The hard-

ware sector unprotection feature re-enables both pro-

gram and erase operations in previously protected

sectors. Sector protection/unprotection can be imple-

mented via two methods.

SA66-SA63

SA62-SA59

SA58-SA55

SA54-SA51

SA50-SA47

SA46-SA43

SA42-SA39

SA38-SA35

SA34-SA31

SA30-SA27

SA26-SA23

SA22–SA19

SA18-SA15

SA14-SA11

1110XXXXX

1101XXXXX

1100XXXXX

1011XXXXX

1010XXXXX

1001XXXXX

1000XXXXX

0111XXXXX

0110XXXXX

0101XXXXX

0100XXXXX

0011XXXXX

0010XXXXX

0001XXXXX

256 (4x64) Kbytes

Table 8. Top Boot Sector/Sector Block Addresses

for Protection/Unprotection

Sector/

Sector

A20–A12

Sector Block Size

SA0

000000XXX

64 Kbytes

000001XXX,

000010XXX

000011XXX

SA1-SA3

192 (3x64) Kbytes

SA4-SA7

0001XXXXX

0010XXXXX

0011XXXXX

0100XXXXX

0101XXXXX

0110XXXXX

0111XXXXX

1000XXXXX

1001XXXXX

1010XXXXX

1011XXXXX

1100XXXXX

1101XXXXX

1110XXXXX

256 (4x64) Kbytes

000011XXX,

000010XXX,

000001XXX

SA8-SA11

SA10-SA8

192 (3x64) Kbytes

SA12-SA15

SA16-SA19

SA20-SA23

SA24-SA27

SA28-SA31

SA32-SA35

SA36-SA39

SA40-SA43

SA44-SA47

SA48-SA51

SA52-SA55

SA56-SA59

SA7

SA6

SA5

SA4

SA3

SA2

SA1

SA0

000000111

000000110

000000101

000000100

000000011

000000010

000000001

000000000

8 Kbytes

Sector protection/unprotection requires V_IDon the RE-

SET# pin only, and can be implemented either in-sys-

tem or via programming equipment. Figure 2 shows

the algorithms and Figure 25 shows the timing dia-

gram. This method uses standard microprocessor bus

cycle timing. For sector unprotect, all unprotected sec-

tors must first be protected prior to the first sector un-

protect write cycle.

111100XXX,

111101XXX,

111110XXX

SA60-SA62

192 (3x64) Kbytes

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

111111000

111111001

111111010

111111011

111111100

111111101

111111110

111111111

8 Kbytes

The sector unprotect algorithm unprotects all sectors

in parallel. All previously protected sectors must be in-

dividually re-protected. To change data in protected

sectors efficiently, the temporary sector unprotect

function is available. See “Temporary Sector Unpro-

tect”.

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

18

Am29DL32xG

25686B10 December 4, 2006

D A T A S H E E T

It is possible to determine whether a sector is pro-

tected or unprotected. See the Autoselect Mode sec-

tion for details.

Temporary Sector Unprotect

(Note: For the following discussion, the term “sector”

applies to both sectors and sector blocks. A sector

block consists of two or more adjacent sectors that are

protected or unprotected at the same time (see Tables

8 and 9).

Write Protect (WP#)

The Write Protect function provides a hardware

method of protecting certain boot sectors without

using V_ID. This function is one of two provided by the

WP#/ACC pin.

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The

Sector Unprotect mode is activated by setting the RE-

SET# pin to V_ID(8.5 V – 12.5 V). During this mode, for-

merly protected sectors can be programmed or erased

by selecting the sector addresses. Once V_IDis re-

moved from the RESET# pin, all the previously pro-

tected sectors are protected again. Figure 1 shows the

algorithm, and Figure 24 shows the timing diagrams,

for this feature.

If the system asserts V_ILon the WP#/ACC pin, the de-

vice disables program and erase functions in the two

“outermost” 8 Kbyte boot sectors independently of

whether those sectors were protected or unprotected

using the method described in “Sector/Sector Block

Protection and Unprotection”. The two outermost 8

Kbyte boot sectors are the two sectors containing the

lowest addresses in a bottom-boot-configured device,

or the two sectors containing the highest addresses in

a top-boot-configured device.

If the system asserts V_IHon the WP#/ACC pin, the de-

vice reverts to whether the two outermost 8K Byte

boot sectors were last set to be protected or unpro-

tected. That is, sector protection or unprotection for

these two sectors depends on whether they were last

protected or unprotected using the method described

in “Sector/Sector Block Protection and Unprotection”.

START

RESET# = V_ID

(Note 1)

Perform Erase or

Program Operations

Note that the WP#/ACC pin must not be left floating or

unconnected; inconsistent behavior of the device may

result.

RESET# = V_IH

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected (If WP#/ACC = V_IL,

outermost boot sectors will remain protected).

2. All previously protected sectors are protected once

again.

Figure 1. Temporary Sector Unprotect Operation

December 4, 2006 25686B10

Am29DL32xG

19

D A T A S H E E T

START

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

PLSCNT = 1

RESET# = V_ID

unprotected sectors

prior to issuing the

first sector

Wait 1 μs

unprotect address

No

First Write

Cycle = 60h?

No

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Yes

Set up first sector

address

Sector Unprotect:

Write 60h to any

address with

A6 = 1, A1 = 1,

A0 = 0

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

A1 = 1, A0 = 0

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Increment

PLSCNT

No

PLSCNT

= 25?

Read from

sector address

with A6 = 1,

Data = 01h?

Yes

A1 = 1, A0 = 0

No

Yes

Set up

next sector

address

Yes

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

No

Last sector

verified?

Device failed

Write reset

command

Yes

Remove V_ID

Sector Unprotect

Algorithm

from RESET#

Sector Protect

Algorithm

Sector Protect

complete

Write reset

command

Sector Unprotect

complete

Figure 2. In-System Sector Protection/

Sector Unprotection Algorithms

20

Am29DL32xG

25686B10 December 4, 2006

D A T A S H E E T

vice the ESN will be at addresses

Secured Silicon Sector

Flash Memory Region

1FF000h–1FF007Fh in word mode (or addresses

3FE000h–3FE0FFh in byte mode).

The Secured Silicon Sector feature provides a

256-byte Flash memory region that enables perma-

nent part identification through an Electronic Serial

Number (ESN). The Secured Silicon Sector uses a

Secured Silicon Sector Indicator Bit (DQ7) to indicate

whether or not the Secured Silicon Sector is locked

when shipped from the factory. This bit is permanently

set at the factory and cannot be changed, which pre-

vents cloning of a factory locked part. This ensures the

security of the ESN once the product is shipped to the

field.

Customers may opt to have their code programmed by

AMD through the AMD ExpressFlash service. AMD

programs the customer’s code, with or without the ran-

dom ESN. The devices are then shipped from AMD’s

factory with the Secured Silicon Sector permanently

locked. Contact an AMD representative for details on

using AMD’s ExpressFlash service.

Customer Lockable: Secured Silicon Sector NOT

Programmed or Protected At the Factory

If the security feature is not required, the Secured Sili-

con Sector can be treated as an additional 256-byte

Flash memory space, expanding the size of the avail-

able Flash array. Additionally, note the difference in

the location of the ESN compared to previous

Am29DL32x top boot factory locked devices. The

Secured Silicon Sector is one-time programmable,

may not be erased, and can be locked only once. Note

that the accelerated programming (ACC) and unlock

bypass functions are not available when programming

the Secured Silicon Sector.

AMD offers the device with the Secured Silicon Sector

either factory locked or customer lockable. The fac-

tory-locked version is always protected when shipped

from the factory, and has the Secured Silicon Sector

Indicator Bit permanently set to a “1.” The cus-

tomer-lockable version is shipped with the Secured

Silicon Sector unprotected, allowing customers to uti-

lize the that sector in any manner they choose. The

customer-lockable version has the Secured Silicon

Sector Indicator Bit permanently set to a “0.” Thus, the

Secured Silicon Sector Indicator Bit prevents cus-

tomer-lockable devices from being used to replace de-

vices that are factory locked.

The Secured Silicon Sector area can be protected

using one of the following procedures:

The system accesses the Secured Silicon Sector

through a command sequence (see “Enter Secured

Silicon Sector/Exit Secured Silicon Sector Command

Sequence”). After the system has written the Enter

Secured Silicon Sector command sequence, it may

read the Secured Silicon Sector by using the ad-

dresses normally occupied by the boot sectors. This

mode of operation continues until the system issues

the Exit Secured Silicon Sector command sequence,

or until power is removed from the device. On

power-up, or following a hardware reset, the device re-

verts to sending commands to the boot sectors.

■ Write the three-cycle Enter Secured Silicon Sector

Region command sequence, and then follow the

in-system sector protect algorithm as shown in Fig-

ure 2, except that RESET# may be at either V_IHor

V_ID. This allows in-system protection of the Secured

Silicon Sector without raising any device pin to a

high voltage. Note that this method is only applica-

ble to the Secured Silicon Sector.

■ Write the three-cycle Enter Secured Silicon Sector

Region command sequence, and then use the alter-

nate method of sector protection described in the

“Sector/Sector Block Protection and Unprotection”

section.

Factory Locked: Secured Silicon Sector

Programmed and Protected At the Factory

The Secured Silicon Sector is one-time programma-

ble. Once the Secured Silicon Sector is locked and

verified, the system must write the Exit Secured Sili-

con Sector Region command sequence to return to

reading and writing the remainder of the array.

In a factory locked device, the Secured Silicon Sector

is protected when the device is shipped from the fac-

tory. The Secured Silicon Sector cannot be modified in

any way. The device is available preprogrammed with

one of the following:

The Secured Silicon Sector protection must be used

with caution since, once protected, there is no proce-

dure available for unprotecting the Secured Silicon

Sector area and none of the bits in the Secured Silicon

Sector memory space can be modified in any way.

■ A random, secure ESN only

■ Customer code through the ExpressFlash service

■ Both a random, secure ESN and customer code

through the ExpressFlash service.

Hardware Data Protection

In devices that have an ESN, a Bottom Boot device will

have the 16-byte ESN at addresses

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 14 for com-

mand definitions). In addition, the following hardware

000000h–000007h

in

word

mode

(or

000000h–00000Fh in byte mode). In the Top Boot de-

December 4, 2006 25686B10

Am29DL32xG

21

D A T A S H E E T

data protection measures prevent accidental erasure

COMMON FLASH MEMORY INTERFACE

(CFI)

or programming, which might otherwise be caused by

spurious system level signals during V_CCpower-up

and power-down transitions, or from system noise.

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-inde-

pendent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device

families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

Low V_CCWrite Inhibit

When V_CCis less than V_LKO, the device does not ac-

cept any write cycles. This protects data during V_CC

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets to the read mode. Subsequent

writes are ignored until V_CCis greater than V_LKO. The

system must provide the proper signals to the control

pins to prevent unintentional writes when V_CCis

This device enters the CFI Query mode when the sys-

tem writes the CFI Query command, 98h, to address

55h in word mode (or address AAh in byte mode), any

time the device is ready to read array data. The

system can read CFI information at the addresses

given in Tables 10–13. To terminate reading CFI data,

the system must write the reset command. The CFI

Query mode is not accessible when the device is exe-

cuting an Embedded Program or Embedded Erase al-

gorithm.

greater than V_LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE#

or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

V_IL, CE# = V_IHor WE# = V_IH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 10–13. The

system must write the reset command to return the

device to reading array data.

Power-Up Write Inhibit

If WE# = CE# = V_ILand OE# = V_IHduring power up,

the device does not accept commands on the rising

edge of WE#. The internal state machine is automati-

cally reset to the read mode on power-up.

For further information, please refer to the CFI Specifi-

cation and CFI Publication 100, available via the World

Wide Web at http://www.amd.com/flash/cfi. Alterna-

tively, contact an AMD representative for copies of

these documents.

Table 10. CFI Query Identification String

Addresses

(Word Mode)

(Byte Mode)

Data

Description

10h

11h

12h

20h

22h

24h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

26h

28h

0002h

0000h

Primary OEM Command Set

15h

16h

2Ah

2Ch

0040h

0000h

Address for Primary Extended Table

17h

18h

2Eh

30h

0000h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

32h

34h

0000h

22

Am29DL32xG

25686B10 December 4, 2006

D A T A S H E E T

Table 11. System Interface String

Addresses

(Word Mode)

(Byte Mode)

Data

Description

V_CCMin. (write/erase)

0027h

1Bh

1Ch

36h

38h

D7–D4: volt, D3–D0: 100 millivolt

V_CCMax. (write/erase)

0036h

D7–D4: volt, D3–D0: 100 millivolt

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

3Ah

3Ch

3Eh

40h

42h

44h

46h

48h

4Ah

4Ch

0000h

0004h

0000h

000Ah

0000h

0005h

0000h

0004h

0000h

V_PPMin. voltage (00h = no V_PPpin present)

V_PPMax. voltage (00h = no V_PPpin present)

Typical timeout per single byte/word write 2^Nµs

Typical timeout for Min. size buffer write 2^Nµs (00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

Table 12. Device Geometry Definition

Addresses

(Word Mode)

(Byte Mode)

Data

Description

27h

4Eh

0016h

Device Size = 2^Nbyte

28h

29h

50h

52h

0002h

0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

54h

56h

0000h

Max. number of bytes in multi-byte write = 2^N

(00h = not supported)

2Ch

58h

0002h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

5Ah

5Ch

5Eh

60h

0007h

0000h

0020h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

62h

64h

66h

68h

003Eh

0000h

0001h

Erase Block Region 2 Information

Erase Block Region 3 Information

Erase Block Region 4 Information

35h

36h

37h

38h

6Ah

6Ch

6Eh

70h

0000h

39h

3Ah

3Bh

3Ch

72h

74h

76h

78h

0000h

December 4, 2006 25686B10

Am29DL32xG

23

D A T A S H E E T

Table 13. Primary Vendor-Specific Extended Query

Addresses

(Word Mode)

(Byte Mode)

Data

Description

40h

41h

42h

80h

82h

84h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

86h

88h

0031h

0033h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

45h

8Ah

0004h

Silicon Revision Number (Bits 7-2)

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

46h

47h

48h

49h

4Ah

4Bh

4Ch

8Ch

8Eh

90h

92h

94h

96h

98h

0002h

0001h

0004h

Sector Protect

0 = Not Supported, X = Number of sectors per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

04 = 29LV800 mode

00XXh

(See Note)

Simultaneous Operation

00 = Not Supported, X = Number of Sectors in Bank 2 (Uniform Bank)

Burst Mode Type

00 = Not Supported, 01 = Supported

0000h

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

ACC (Acceleration) Supply Minimum

4Dh

4Eh

4Fh

9Ah

9Ch

9Eh

0085h

0095h

000Xh

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

Top/Bottom Boot Sector Flag

02h = Bottom Boot Device, 03h = Top Boot Device

Note:

The number of sectors in Bank 2 is device dependent.

Am29DL322 = 38h, Am29DL323 = 30h, Am29DL324 = 20h

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device op-

erations. Table 14 defines the valid register command

sequences. Writing incorrect address and data values

or writing them in the improper sequence may place

the device in an unknown state. A reset command is

then required to return the device to reading array

data.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. Each bank is ready to read array data

after completing an Embedded Program or Embedded

Erase algorithm.

After the device accepts an Erase Suspend command,

the corresponding bank enters the erase-sus-

pend-read mode, after which the system can read

data from any non-erase-suspended sector within the

same bank. After completing a programming operation

in the Erase Suspend mode, the system may once

All addresses are latched on the falling edge of WE#

or CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the AC Characteristics section for timing

diagrams.

24

Am29DL32xG

25686B10 December 4, 2006

D A T A S H E E T

again read array data with the same exception. See

the Erase Suspend/Erase Resume Commands sec-

tion for more information.

mode. The autoselect command may not be written

while the device is actively programming or erasing in

the other bank.

The system must issue the reset command to return a

bank to the read (or erase-suspend-read) mode if DQ5

goes high during an active program or erase opera-

tion, or if the bank is in the autoselect mode. See the

next section, Reset Command, for more information.

The autoselect command sequence is initiated by first

writing two unlock cycles. This is followed by a third

write cycle that contains the bank address and the au-

toselect command. The bank then enters the autose-

lect mode. The system may read at any address within

the same bank any number of times without initiating

another autoselect command sequence:

See also Requirements for Reading Array Data in the

Device Bus Operations section for more information.

The Read-Only Operations table provides the read pa-

rameters, and Figure 13 shows the timing diagram.

■ A read cycle at address (BA)XX00h (where BA is

the bank address) returns the manufacturer code.

■ A read cycle at address (BA)XX01h in word mode

(or (BA)XX02h in byte mode) returns the device

code.

Reset Command

Writing the reset command resets the banks to the

read or erase-suspend-read mode. Address bits are

don’t cares for this command.

■ A read cycle to an address containing a sector ad-

dress (SA) within the same bank, and the address

02h on A7–A0 in word mode (or the address 04h on

A6–A-1 in byte mode) returns 01h if the sector is

protected, or 00h if it is unprotected. (Refer to Ta-

bles 3–6 for valid sector addresses).

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the bank to which the sys-

tem was writing to the read mode. Once erasure be-

gins, however, the device ignores reset commands

until the operation is complete.

The system must write the reset command to return to

the read mode (or erase-suspend-read mode if the

bank was previously in Erase Suspend).

The reset command may be written between the

sequence cycles in a program command sequence

before programming begins. This resets the bank to

which the system was writing to the read mode. If the

program command sequence is written to a bank that

is in the Erase Suspend mode, writing the reset

command returns that bank to the erase-sus-

pend-read mode. Once programming begins, however,

the device ignores reset commands until the operation

is complete.

Enter Secured Silicon Sector/Exit Secured

Silicon Sector Command Sequence

The Secured Silicon Sector region provides a secured

data area containing a random, sixteen-byte electronic

serial number (ESN). The system can access the Se-

cured Silicon Sector region by issuing the three-cycle

Enter Secured Silicon Sector command sequence.

The device continues to access the Secured Silicon

Sector region until the system issues the four-cycle

Exit Secured Silicon Sector command sequence. The

Exit Secured Silicon Sector command sequence re-

turns the device to normal operation. The Secured Sil-

icon Sector is not accessible when the device is

executing an Embedded Program or Embedded Erase

algorithm. Table 14 shows the address and data re-

quirements for both command sequences. See also

“Secured Silicon Sector Flash Memory Region” for fur-

ther information.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command

must be written to return to the read mode. If a bank

entered the autoselect mode while in the Erase Sus-

pend mode, writing the reset command returns that

bank to the erase-suspend-read mode.

If DQ5 goes high during a program or erase operation,

writing the reset command returns the banks to the

read mode (or erase-suspend-read mode if that bank

was in Erase Suspend).

Byte/Word Program Command Sequence

The system may program the device by word or byte,

depending on the state of the BYTE# pin. Program-

ming is a four-bus-cycle operation. The program com-

mand sequence is initiated by writing two unlock write

cycles, followed by the program set-up command. The

program address and data are written next, which in

turn initiate the Embedded Program algorithm. The

system is not required to provide further controls or

timings. The device automatically provides internally

generated program pulses and verifies the pro-

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and device codes,

and determine whether or not a sector is protected.

Table 14 shows the address and data requirements.

This method is an alternative to that shown in Table 7,

which is intended for PROM programmers and re-

quires V_IDon address pin A9. The autoselect com-

mand sequence may be written to an address within a

bank that is either in the read or erase-suspend-read

December 4, 2006 25686B10

Am29DL32xG

25

D A T A S H E E T

grammed cell margin. Table 14 shows the address and

WP#/ACC pin to accelerate the operation. Note that

the WP#/ACC pin must not be at V_HHany operation

other than accelerated programming, or device dam-

age may result. In addition, the WP#/ACC pin must not

be left floating or unconnected; inconsistent behavior

of the device may result.

data requirements for the byte program command se-

quence.

When the Embedded Program algorithm is complete,

that bank then returns to the read mode and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using

DQ7, DQ6, or RY/BY#. Refer to the Write Operation

Status section for information on these status bits.

Figure 3 illustrates the algorithm for the program oper-

ation. Refer to the Erase and Program Operations

table in the AC Characteristics section for parameters,

and Figure 17 for timing diagrams.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program

operation. The program command sequence should

be reinitiated once that bank has returned to the read

mode, to ensure data integrity.

START

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from “0” back to a “1.” Attempting to do so may

cause that bank to set DQ5 = 1, or cause the DQ7 and

DQ6 status bits to indicate the operation was success-

ful. However, a succeeding read will show that the

data is still “0.” Only erase operations can convert a “0”

to a “1.”

Write Program

Command Sequence

Data Poll

from System

Embedded

Program

algorithm

Unlock Bypass Command Sequence

in progress

The unlock bypass feature allows the system to pro-

gram bytes or words to a bank faster than using the

standard program command sequence. The unlock

bypass command sequence is initiated by first writing

two unlock cycles. This is followed by a third write

cycle containing the unlock bypass command, 20h.

That bank then enters the unlock bypass mode. A

two-cycle unlock bypass program command sequence

is all that is required to program in this mode. The first

cycle in this sequence contains the unlock bypass pro-

gram command, A0h; the second cycle contains the

program address and data. Additional data is pro-

grammed in the same manner. This mode dispenses

with the initial two unlock cycles required in the stan-

dard program command sequence, resulting in faster

total programming time. Table 14 shows the require-

ments for the command sequence.

Verify Data?

No

Yes

No

Increment Address

Last Address?

Yes

Programming

Completed

Note: See Table 14 for program command sequence.

Figure 3. Program Operation

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset com-

mand sequence. The first cycle must contain the bank

address and the data 90h. The second cycle need

only contain the data 00h. The bank then returns to

the read mode.

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 14

The device offers accelerated program operations

through the WP#/ACC pin. When the system asserts

V

_HHon the WP#/ACC pin, the device automatically en-

ters the Unlock Bypass mode. The system may then

write the two-cycle Unlock Bypass program command

sequence. The device uses the higher voltage on the

26

Am29DL32xG

25686B10 December 4, 2006

D A T A S H E E T

shows the address and data requirements for the chip

erase command sequence.

Sector Erase Timer.). The time-out begins from the ris-

ing edge of the final WE# pulse in the command

sequence.

When the Embedded Erase algorithm is complete,

that bank returns to the read mode and addresses are

no longer latched. The system can determine the sta-

tus of the erase operation by using DQ7, DQ6, DQ2,

or RY/BY#. Refer to the Write Operation Status sec-

tion for information on these status bits.

When the Embedded Erase algorithm is complete, the

bank returns to reading array data and addresses are

no longer latched. Note that while the Embedded

Erase operation is in progress, the system can read

data from the non-erasing bank. The system can de-

termine the status of the erase operation by reading

DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer

to the Write Operation Status section for information

on these status bits.

Any commands written during the chip erase operation

are ignored. However, note that a hardware reset im-

mediately terminates the erase operation. If that oc-

curs, the chip erase command sequence should be

reinitiated once that bank has returned to reading

array data, to ensure data integrity.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other com-

mands are ignored. However, note that a hardware

reset immediately terminates the erase operation. If

that occurs, the sector erase command sequence

should be reinitiated once that bank has returned to

reading array data, to ensure data integrity.

Figure 4 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations ta-

bles in the AC Characteristics section for parameters,

and Figure 19 section for timing diagrams.

Sector Erase Command Sequence

Figure 4 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations ta-

bles in the AC Characteristics section for parameters,

and Figure 19 section for timing diagrams.

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two ad-

ditional unlock cycles are written, and are then fol-

lowed by the address of the sector to be erased, and

the sector erase command. Table 14 shows the ad-

dress and data requirements for the sector erase com-

mand sequence.

Erase Suspend/Erase Resume

Commands

The Erase Suspend command, B0h, allows the sys-

tem to interrupt a sector erase operation and then read

data from, or program data to, any sector not selected

for erasure. The bank address is required when writing

this command. This command is valid only during the

sector erase operation, including the 50 µs time-out

period during the sector erase command sequence.

The Erase Suspend command is ignored if written dur-

ing the chip erase operation or Embedded Program

algorithm.

The device does not require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-

matically programs and verifies the entire memory for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

After the command sequence is written, a sector erase

time-out of 50 µs occurs. During the time-out period,

additional sector addresses and sector erase com-

mands (for sectors within the same bank) may be writ-

ten. Loading the sector erase buffer may be done in

any sequence, and the number of sectors may be from

one sector to all sectors. The time between these ad-

ditional cycles must be less than 50 µs, otherwise era-

sure may begin. Any sector erase address and

command following the exceeded time-out may or may

not be accepted. It is recommended that processor in-

terrupts be disabled during this time to ensure all com-

mands are accepted. The interrupts can be re-enabled

after the last Sector Erase command is written. Any

command other than Sector Erase or Erase Sus-

pend during the time-out period resets that bank

to the read mode. The system must rewrite the com-

mand sequence and any additional addresses and

commands.

When the Erase Suspend command is written during

the sector erase operation, the device requires a max-

imum of 20 µs to suspend the erase operation. How-

ever, when the Erase Suspend command is written

during the sector erase time-out, the device immedi-

ately terminates the time-out period and suspends the

erase operation.

After the erase operation has been suspended, the

bank enters the erase-suspend-read mode. The sys-

tem can read data from or program data to any sector

not selected for erasure. (The device “erase sus-

pends” all sectors selected for erasure.) Reading at

any address within erase-suspended sectors pro-

duces status information on DQ7–DQ0. The system

can use DQ7, or DQ6 and DQ2 together, to determine

if a sector is actively erasing or is erase-suspended.

Refer to the Write Operation Status section for infor-

mation on these status bits.

The system can monitor DQ3 to determine if the sec-

tor erase timer has timed out (See the section on DQ3:

December 4, 2006 25686B10

Am29DL32xG

27

D A T A S H E E T

After an erase-suspended program operation is com-

plete, the bank returns to the erase-suspend-read

mode. The system can determine the status of the

program operation using the DQ7 or DQ6 status bits,

just as in the standard Byte Program operation.

Refer to the Write Operation Status section for more

information.

START

Write Erase

Command Sequence

(Notes 1, 2)

In the erase-suspend-read mode, the system can also

issue the autoselect command sequence. Refer to the

Autoselect Mode and Autoselect Command Sequence

sections for details.

Data Poll to Erasing

Bank from System

To resume the sector erase operation, the system

must write the Erase Resume command. The bank

address of the erase-suspended bank is required

when writing this command. Further writes of the Re-

sume command are ignored. Another Erase Suspend

command can be written after the chip has resumed

erasing.

Embedded

Erase

algorithm

in progress

No

Data = FFh?

Yes

Erasure Completed

Notes:

1. See Table 14 for erase command sequence.

2. See the section on DQ3 for information on the sector

erase timer.

Figure 4. Erase Operation

28

Am29DL32xG

25686B10 December 4, 2006

D A T A S H E E T

Table 14. Command Definitions

Bus Cycles (Notes 2–5)

Third Fourth

Addr

Command

Sequence

(Note 1)

First

Second

Fifth

Sixth

Addr Data Addr Data

Data

Addr

Data

Addr Data Addr Data

Read (Note 6)

Reset (Note 7)

1

RA

XXX

555

AAA

555

AAA

555

RD

F0

Word

Byte

Word

Byte

2AA

555

2AA

555

2AA

(BA)555

(BA)AAA

(BA)555

(BA)AAA

(BA)555

Manufacturer ID

Device ID

4

AA

55

90 (BA)X00

01

(BA)X01

90

(see

Table 7)

(BA)X02

Secured Silicon Sector Word

Factory Protect (Note

9)

(BA)X03

4

AA

55

90

82/02

00/01

Byte

AAA

555

2AA

555

(BA)AAA

(BA)555

(BA)AAA

(BA)X06

Sector/Sector Block

Protect Verify

(Note 10)

Word

Byte

(SA)X02

90

AAA

(SA)X04

Word

Byte

Word

Byte

Word

Byte

Word

Byte

555

AAA

555

2AA

555

2AA

555

2AA

555

2AA

555

PA

555

AAA

555

Enter Secured Silicon

Sector Region

3

4

3

AA

55

88

Exit Secured Silicon Sector

Region

90

A0

20

XXX

PA

00

AAA

555

AAA

555

Program

PD

AAA

555

AAA

555

Unlock Bypass

AAA

XXX

AAA

Unlock Bypass Program (Note 11)

Unlock Bypass Reset (Note 12)

A0

90

PD

00

2

BA

555

AAA

555

AAA

BA

XXX

2AA

555

2AA

555

Word

555

AAA

555

AAA

555

2AA

555

2AA

555

Chip Erase

Byte

6

AA

55

80

AA

55

10

30

AAA

Word

Sector Erase

Byte

6

SA

AAA

Erase Suspend (Note 13)

Erase Resume (Note 14)

1

B0

30

BA

Word

CFI Query (Note 15)

Byte

55

1

98

AA

Legend:

X = Don’t care

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses

latch on the falling edge of the WE# or CE# pulse, whichever happens

later.

PD = Data to be programmed at location PA. Data latches on the rising

edge of WE# or CE# pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or

erased. Address bits A20–A12 uniquely select any sector.

BA = Address of the bank that is being switched to autoselect mode, is

in bypass mode, or is being erased.

Notes:

1. See Table 1 for description of bus operations.

9. The data is 82h for factory locked and 02h for not factory locked.

2. All values are in hexadecimal.

10. The data is 00h for an unprotected sector/sector block and 01h for

a protected sector/sector block.

3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

11. The Unlock Bypass command is required prior to the Unlock

Bypass Program command.

4. Data bits DQ15–DQ8 are don’t care in command sequences,

except for RD and PD.

12. The Unlock Bypass Reset command is required to return to the

read mode when the bank is in the unlock bypass mode.

5. Unless otherwise noted, address bits A20–A11 are don’t cares.

13. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase

operation, and requires the bank address.

6. No unlock or command cycles required when bank is reading

array data.

7. The Reset command is required to return to the read mode (or to

the erase-suspend-read mode if previously in Erase Suspend)

when a bank is in the autoselect mode, or if DQ5 goes high (while

the bank is providing status information).

14. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

15. Command is valid when device is ready to read array data or when

device is in autoselect mode.

8. The fourth cycle of the autoselect command sequence is a read

cycle. The system must provide the bank address to obtain the

manufacturer ID, device ID, or Secured Silicon Sector factory

protect information. Data bits DQ15–DQ8 are don’t care. See the

Autoselect Command Sequence section for more information.

December 4, 2006 25686B10

Am29DL32xG

29

D A T A S H E E T

WRITE OPERATION STATUS

The device provides several bits to determine the status of a

program or erase operation: DQ2, DQ3, DQ5, DQ6, and

DQ7. Table 15 and the following subsections describe the

function of these bits. DQ7 and DQ6 each offer a method for

determining whether a program or erase operation is com-

plete or in progress. The device also provides a hard-

ware-based output signal, RY/BY#, to determine whether

an Embedded Program or Erase operation is in progress or

has been completed.

valid data, the data outputs on DQ0–DQ6 may be still

invalid. Valid data on DQ7–DQ0 will appear on suc-

cessive read cycles.

Table 15 shows the outputs for Data# Polling on DQ7.

Figure 5 shows the Data# Polling algorithm. Figure 21

in the AC Characteristics section shows the Data#

Polling timing diagram.

DQ7: Data# Polling

START

The Data# Polling bit, DQ7, indicates to the host system

whether an Embedded Program or Erase algorithm is in

progress or completed, or whether a bank is in Erase Sus-

pend. Data# Polling is valid after the rising edge of the final

WE# pulse in the command sequence.

Read DQ7–DQ0

Addr = VA

During the Embedded Program algorithm, the device out-

puts on DQ7 the complement of the datum programmed to

DQ7. This DQ7 status also applies to programming during

Erase Suspend. When the Embedded Program algorithm is

complete, the device outputs the datum programmed to

DQ7. The system must provide the program address to

read valid status information on DQ7. If a program address

falls within a protected sector, Data# Polling on DQ7 is ac-

tive for approximately 1 µs, then that bank returns to the

read mode.

Yes

DQ7 = Data?

No

DQ5 = 1?

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the bank enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

The system must provide an address within any of the

sectors selected for erasure to read valid status infor-

mation on DQ7.

Yes

Read DQ7–DQ0

Addr = VA

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data# Poll-

ing on DQ7 is active for approximately 100 µs, then the

bank returns to the read mode. If not all selected sec-

tors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected. However, if the sys-

tem reads DQ7 at an address within a protected

sector, the status may not be valid.

Yes

DQ7 = Data?

No

PASS

FAIL

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address

within the sector being erased. During chip erase, a

valid address is any non-protected sector address.

Just prior to the completion of an Embedded Program

or Erase operation, DQ7 may change asynchronously

with DQ0–DQ6 while Output Enable (OE#) is asserted

low. That is, the device may change from providing

status information to valid data on DQ7. Depending on

when the system samples the DQ7 output, it may read

the status or valid data. Even if the device has com-

pleted the program or erase operation and DQ7 has

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Figure 5. Data# Polling Algorithm

30

Am29DL32xG

25686B10 December 4, 2006

D A T A S H E E T

the “AC Characteristics” section shows the toggle bit

RY/BY#: Ready/Busy#

timing diagrams. Figure 23 shows the differences be-

tween DQ2 and DQ6 in graphical form. See also the

subsection on DQ2: Toggle Bit II.

The RY/BY# is a dedicated, open-drain output pin

which indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open-drain output, sev-

eral RY/BY# pins can be tied together in parallel with a

START

pull-up resistor to V_CC

.

If the output is low (Busy), the device is actively eras-

ing or programming. (This includes programming in

the Erase Suspend mode.) If the output is high

(Ready), the device is in the read mode, the standby

mode, or one of the banks is in the erase-sus-

pend-read mode.

Read DQ7–DQ0

Table 15 shows the outputs for RY/BY#.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or com-

plete, or whether the device has entered the Erase

Suspend mode. Toggle Bit I may be read at any ad-

dress, and is valid after the rising edge of the final

WE# pulse in the command sequence (prior to the

program or erase operation), and during the sector

erase time-out.

No

Toggle Bit

= Toggle?

Yes

No

DQ5 = 1?

Yes

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. The system may use either OE# or

CE# to control the read cycles. When the operation is

complete, DQ6 stops toggling.

Read DQ7–DQ0

Twice

After an erase command sequence is written, if all sectors

selected for erasing are protected, DQ6 toggles for approxi-

mately 100 µs, then returns to reading array data. If not all

selected sectors are protected, the Embedded Erase algo-

rithm erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

Toggle Bit

= Toggle?

No

Yes

The system can use DQ6 and DQ2 together to determine

whether a sector is actively erasing or is erase-suspended.

When the device is actively erasing (that is, the Embedded

Erase algorithm is in progress), DQ6 toggles. When the de-

vice enters the Erase Suspend mode, DQ6 stops toggling.

However, the system must also use DQ2 to determine

which sectors are erasing or erase-suspended. Alterna-

tively, the system can use DQ7 (see the subsection on

DQ7: Data# Polling).

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Note: The system should recheck the toggle bit even if DQ5

= “1” because the toggle bit may stop toggling as DQ5

changes to “1.” See the subsections on DQ6 and DQ2 for

more information.

If a program address falls within a protected sector,

DQ6 toggles for approximately 1 µs after the program

command sequence is written, then returns to reading

array data.

Figure 6. Toggle Bit Algorithm

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

Table 15 shows the outputs for Toggle Bit I on DQ6.

Figure 6 shows the toggle bit algorithm. Figure 22 in

December 4, 2006 25686B10

Am29DL32xG

31

D A T A S H E E T

the toggle bit and DQ5 through successive read cy-

DQ2: Toggle Bit II

cles, determining the status as described in the previ-

ous paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to de-

termine the status of the operation (top of Figure 6).

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

DQ5: Exceeded Timing Limits

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. (The system may use either OE# or CE# to con-

trol the read cycles.) But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-sus-

pended. DQ6, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but

cannot distinguish which sectors are selected for era-

sure. Thus, both status bits are required for sector and

mode information. Refer to Table 15 to compare out-

puts for DQ2 and DQ6.

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under these

conditions DQ5 produces a “1,” indicating that the program

or erase cycle was not successfully completed.

The device may output a “1” on DQ5 if the system tries

to program a “1” to a location that was previously pro-

grammed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the timing limit

has been exceeded, DQ5 produces a “1.”

Under both these conditions, the system must write

the reset command to return to the read mode (or to

the erase-suspend-read mode if a bank was previ-

ously in the erase-suspend-program mode).

Figure 6 shows the toggle bit algorithm in flowchart

form, and the section “DQ2: Toggle Bit II” explains the

algorithm. See also the DQ6: Toggle Bit I subsection.

Figure 22 shows the toggle bit timing diagram. Figure

23 shows the differences between DQ2 and DQ6 in

graphical form.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not

erasure has begun. (The sector erase timer does not

apply to the chip erase command.) If additional

sectors are selected for erasure, the entire time-out

also applies after each additional sector erase com-

mand. When the time-out period is complete, DQ3

switches from a “0” to a “1.” If the time between addi-

tional sector erase commands from the system can be

assumed to be less than 50 µs, the system need not

monitor DQ3. See also the Sector Erase Command

Sequence section.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 6 for the following discussion. When-

ever the system initially begins reading toggle bit sta-

tus, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically,

the system would note and store the value of the tog-

gle bit after the first read. After the second read, the

system would compare the new value of the toggle bit

with the first. If the toggle bit is not toggling, the device

has completed the program or erase operation. The

system can read array data on DQ7–DQ0 on the fol-

lowing read cycle.

After the sector erase command is written, the system

should read the status of DQ7 (Data# Polling) or DQ6

(Toggle Bit I) to ensure that the device has accepted

the command sequence, and then read DQ3. If DQ3 is

“1,” the Embedded Erase algorithm has begun; all fur-

ther commands (except Erase Suspend) are ignored

until the erase operation is complete. If DQ3 is “0,” the

device will accept additional sector erase commands.

To ensure the command has been accepted, the sys-

tem software should check the status of DQ3 prior to

and following each subsequent sector erase com-

mand. If DQ3 is high on the second status check, the

last command might not have been accepted.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should

then determine again whether the toggle bit is tog-

gling, since the toggle bit may have stopped toggling

just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the de-

vice did not completed the operation successfully, and

the system must write the reset command to return to

reading array data.

Table 15 shows the status of DQ3 relative to the other

status bits.

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor

32

Am29DL32xG

25686B10 December 4, 2006

D A T A S H E E T

Table 15. Write Operation Status

DQ7

DQ5

DQ2

Status

(Note 2)

DQ6

(Note 1)

DQ3

N/A

1

(Note 2)

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

Erase

Erase-Suspend-

Read

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

1

No toggle

0

N/A

Toggle

1

Suspended Sector

Erase

Suspend

Mode

Non-Erase

Suspended Sector

Data

0

Data

N/A

Data

N/A

1

0

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

December 4, 2006 25686B10

Am29DL32xG

33

D A T A S H E E T

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

20 ns

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

+0.8 V

Voltage with Respect to Ground

–0.5 V

–2.0 V

V

_CC(Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

A9, OE#, and RESET#

(Note 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V

20 ns

WP#/ACC . . . . . . . . . . . . . . . . . .–0.5 V to +10.5 V

All other pins (Note 1). . . . . . –0.5 V to V_CC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Figure 7. Maximum Negative

Overshoot Waveform

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V.

During voltage transitions, input or I/O pins may

overshoot V_SSto –2.0 V for periods of up to 20 ns.

Maximum DC voltage on input or I/O pins is V_CC+0.5 V.

See Figure 7. During voltage transitions, input or I/O pins

may overshoot to V_CC+2.0 V for periods up to 20 ns. See

Figure 8.

20 ns

V_CC

+2.0 V

V_CC

+0.5 V

2. Minimum DC input voltage on pins A9, OE#, RESET#,

and WP#/ACC is –0.5 V. During voltage transitions, A9,

OE#, WP#/ACC, and RESET# may overshoot V_SSto

–2.0 V for periods of up to 20 ns. See Figure 7. Maximum

DC input voltage on pin A9 is +12.5 V which may

overshoot to +14.0 V for periods up to 20 ns. Maximum

DC input voltage on WP#/ACC is +9.5 V which may

overshoot to +12.0 V for periods up to 20 ns.

2.0 V

20 ns

Figure 8. Maximum Positive

Overshoot Waveform

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This

is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

OPERATING RANGES

Industrial (I) Devices

Ambient Temperature (T_A) . . . . . . . . . –40°C to +85°C

V_CCSupply Voltages

V

_CCfor standard voltage range . . . . . . .2.7 V to 3.6 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

34

Am29DL32xG

25686B10 December 4, 2006

D A T A S H E E T

DC CHARACTERISTICS

CMOS Compatible

Parameter

Symbol

Parameter Description

Test Conditions

V_IN= V_SSto V_CC

Min

Typ

Max

±1.0

35

Unit

µA

,

I_LI

Input Load Current

V_CC= V_{CC max}

I_LIT

A9 Input Load Current

Output Leakage Current

V_CC= V_{CC max}; A9 = 12.5 V

µA

V

_OUT= V_SSto V_CC

,

I_LO

±1.0

µA

V_CC= V_{CC max}

5 MHz

1 MHz

5 MHz

1 MHz

10

2

16

4

CE# = V_IL,OE# = V_IH,

Byte Mode

V_CCActive Read Current

(Notes 1, 2)

I_CC1

mA

10

2

16

4

CE# = V_IL,OE# = V_IH,

Word Mode

I_CC2

I_CC3

I_CC4

V_CCActive Write Current (Notes 2, 3) CE# = V_IL,OE# = V_IH, WE# = V_IL

15

0.2

30

5

mA

µA

V_CCStandby Current (Note 2)

V_CCReset Current (Note 2)

CE#, RESET# = V_CC± 0.3 V

RESET# = V_SS± 0.3 V

5

V_IH= V_CC± 0.3 V;

V_IL= V_SS± 0.3 V

I_CC5

Automatic Sleep Mode (Notes 2, 4)

0.2

5

µA

Byte

21

45

V_CCActive Read-While-Program

Current (Notes 1, 2)

I_CC6

CE# = V_IL, OE# = V_IH

mA

Word

Byte

V_CCActive Read-While-Erase

Current (Notes 1, 2)

I_CC7

mA

Word

V_CCActive

Program-While-Erase-Suspended

Current (Notes 2, 5)

I_CC8

CE# = V_IL, OE# = V_IH

17

35

V_IL

V_IH

Input Low Voltage

Input High Voltage

–0.5

0.8

V

0.7 x V_CC

V_CC+ 0.3

Voltage for WP#/ACC Sector

Protect/Unprotect and Program

Acceleration

V_HH

V_CC= 3.0 V 10%

8.5

9.5

V

Voltage for Autoselect and Temporary

Sector Unprotect

V_ID

V_CC= 3.0 V ± 10%

12.5

0.45

V_OL

V_OH1

V_OH2

V_LKO

Output Low Voltage

I_OL= 4.0 mA, V_CC= V_{CC min}

I_OH= –2.0 mA, V_CC= V_{CC min}

I_OH= –100 µA, V_CC= V_{CC min}

V

0.85 V_CC

V_CC–0.4

2.3

Output High Voltage

Low V_CCLock-Out Voltage (Note 5)

2.5

V

Notes:

1. The I_CCcurrent listed is typically less than 2 mA/MHz, with OE# at V_IH.

2. Maximum I_CCspecifications are tested with V_CC= V_CCmax.

3. I_CCactive while Embedded Erase or Embedded Program is in progress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for t_ACC+ 30 ns. Typical sleep mode current is

200 nA.

5. Not 100% tested.

December 4, 2006 25686B10

Am29DL32xG

35

D A T A S H E E T

DC CHARACTERISTICS

Zero-Power Flash

25

20

15

10

5

0

500

1000

1500

2000

2500

3000

3500

4000

Time in ns

Note: Addresses are switching at 1 MHz

Figure 9. I_CC1Current vs. Time (Showing Active and Automatic Sleep Currents)

12

10

8

3.6 V

2.7 V

6

4

2

0

1

2

3

4

5

Frequency in MHz

Note: T = 25 °C

Figure 10. Typical I_CC1vs. Frequency

36

Am29DL32xG

25686B10 December 4, 2006

D A T A S H E E T

TEST CONDITIONS

Table 16. Test Specifications

3.3 V

Test Condition

70

90, 120 Unit

Output Load

1 TTL gate

2.7 kΩ

Device

Under

Test

Output Load Capacitance, C_L

(including jig capacitance)

30

100

5

pF

Input Rise and Fall Times

Input Pulse Levels

ns

V

C

L

6.2 kΩ

0.0–3.0

Input timing measurement

reference levels

1.5

V

Output timing measurement

reference levels

Note: Diodes are IN3064 or equivalent

Figure 11. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

3.0 V

0.0 V

1.5 V

Input

Measurement Level

Output

Figure 12. Input Waveforms and Measurement Levels

December 4, 2006 25686B10

Am29DL32xG

37

D A T A S H E E T

AC CHARACTERISTICS

Read-Only Operations

Parameter

Speed Options

JEDEC Std. Description

Test Setup

70

90

40

16

120 Unit

t_AVAV

t_AVQV

t_ELQV

t_GLQV

t_EHQZ

t_GHQZ

t_RCRead Cycle Time (Note 1)

Min

Max

70

30

120 ns

t_ACCAddress to Output Delay

CE#, OE# = V_IL

OE# = V_IL

t_CEChip Enable to Output Delay

t_OEOutput Enable to Output Delay

t_DFChip Enable to Output High Z (Note 1)

t_DFOutput Enable to Output High Z (Note 1)

50

ns

Output Hold Time From Addresses, CE# or OE#,

Whichever Occurs First

t_AXQX

t_OH

Min

0

ns

Read

Output Enable Hold Time

t_OEH

Toggle and

Data# Polling

(Note 1)

10

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 16 for test specifications.

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_RH

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

Figure 13. Read Operation Timings

38

Am29DL32xG

25686B10 December 4, 2006

D A T A S H E E T

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std

Description

All Speed Options

Unit

RESET# Pin Low (During Embedded Algorithms)

to Read Mode (See Note)

t_Ready

Max

20

µs

RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note)

t_Ready

500

ns

t_RP

t_RH

t_RPD

t_RB

RESET# Pulse Width

Min

500

50

20

0

ns

µs

ns

Reset High Time Before Read (See Note)

RESET# Low to Standby Mode

RY/BY# Recovery Time

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

Figure 14. Reset Timings

December 4, 2006 25686B10

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39

D A T A S H E E T

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

Speed Options

JEDEC

Std

t_ELFL/t_ELFH

t_FLQZ

Description

70

90

5

120

Unit

ns

CE# to BYTE# Switching Low or High

BYTE# Switching Low to Output HIGH Z

BYTE# Switching High to Output Active

Max

Min

16

90

ns

t_FHQV

70

120

ns

CE#

OE#

BYTE#

t_ELFL

Data Output

(DQ14–DQ0)

Data Output

(DQ7–DQ0)

BYTE#

DQ14–DQ0

Switching

from word

to byte

Address

Input

DQ15

Output

mode

DQ15/A-1

BYTE#

t_FLQZ

t_ELFH

BYTE#

Switching

from byte

to word

Data Output

(DQ7–DQ0)

Data Output

(DQ14–DQ0)

DQ14–DQ0

DQ15/A-1

mode

Address

Input

DQ15

Output

t_FHQV

Figure 15. BYTE# Timings for Read Operations

CE#

The falling edge of the last WE# signal

WE#

BYTE#

t_SET

(t_AS

)

t_HOLD(t_AH

)

Note: Refer to the Erase/Program Operations table for t_ASand t_AHspecifications.

Figure 16. BYTE# Timings for Write Operations

Am29DL32xG

40

25686B10 December 4, 2006

D A T A S H E E T

AC CHARACTERISTICS

Erase and Program Operations

Parameter

Speed Options

JEDEC

t_AVAV

Std

t_WC

t_AS

Description

70

90

0

120 Unit

Write Cycle Time (Note 1)

Min

70

120

ns

t_AVWL

Address Setup Time

t_ASO

t_AH

Address Setup Time to OE# low during toggle bit polling

Address Hold Time

15

45

15

t_WLAX

45

0

50

Address Hold Time From CE# or OE# high

during toggle bit polling

t_AHT

Min

ns

t_DVWH

t_WHDX

t_DS

t_DH

Data Setup Time

Data Hold Time

Min

35

45

0

ns

20

t_OEPH

Output Enable High during toggle bit polling

Min

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHWL

0

t_ELWL

t_WHEH

t_WLWH

t_WHDL

t_CS

t_CH

CE# Setup Time

Min

Typ

0

ns

CE# Hold Time

t_WP

Write Pulse Width

30

35

30

0

50

t_WPH

t_SR/W

Write Pulse Width High

Latency Between Read and Write Operations

Byte

5

t_WHWH1

t_WHWH1Programming Operation (Note 2)

µs

Word

7

Accelerated Programming Operation,

Word or Byte (Note 2)

t_WHWH1

t_WHWH2

t_WHWH1

Typ

4

t_WHWH2Sector Erase Operation (Note 2)

Typ

Min

Max

0.4

50

0

sec

µs

t_VCS

t_RB

V_CCSetup Time (Note 1)

Write Recovery Time from RY/BY#

Program/Erase Valid to RY/BY# Delay

ns

t_BUSY

90

ns

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

December 4, 2006 25686B10

Am29DL32xG

41

D A T A S H E E T

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

PA

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D_OUTis the true data at the program address.

2. Illustration shows device in word mode.

Figure 17. Program Operation Timings

V_HH

V_ILor V_IH

WP#/ACC

V_ILor V_IH

t_VHH

Figure 18. Accelerated Program Timing Diagram

42

Am29DL32xG

25686B10 December 4, 2006

D A T A S H E E T

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.

2. These waveforms are for the word mode.

Figure 19. Chip/Sector Erase Operation Timings

December 4, 2006 25686B10

Am29DL32xG

43

D A T A S H E E T

AC CHARACTERISTICS

t_WC

Valid PA

t_WC

t_RC

t_WC

Valid PA

Valid RA

Valid PA

Addresses

t_AH

t_CPH

t_ACC

t_CE

CE#

t_CP

t_OE

OE#

t_OEH

t_GHWL

t_WP

WE#

t_DF

t_WPH

t_DS

t_OH

t_DH

Valid

Out

Valid

In

Valid

In

Valid

In

Data

t_SR/W

WE# Controlled Write Cycle

Read Cycle

CE# Controlled Write Cycles

Figure 20. Back-to-back Read/Write Cycle Timings

t_RC

Addresses

CE#

VA

t_ACC

t_CE

VA

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

True

DQ0–DQ6

Valid Data

Status Data

True

Status Data

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

Figure 21. Data# Polling Timings (During Embedded Algorithms)

44

Am29DL32xG

25686B10 December 4, 2006

D A T A S H E E T

AC CHARACTERISTICS

t_AHT

t_AS

Addresses

t_AHT

t_ASO

CE#

t_OEH

WE#

t_CEPH

t_OEPH

OE#

t_DH

Valid Data

t_OE

Valid

Status

Valid

Status

Valid

Status

DQ6/DQ2

Valid Data

(first read)

(second read)

(stops toggling)

RY/BY#

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle

Figure 22. Toggle Bit Timings (During Embedded Algorithms)

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle

DQ2 and DQ6.

Figure 23. DQ2 vs. DQ6

December 4, 2006 25686B10

Am29DL32xG

45

D A T A S H E E T

AC CHARACTERISTICS

Temporary Sector Unprotect

Parameter

JEDEC

Std

t_VIDR

t_VHH

Description

All Speed Options

Unit

ns

V_IDRise and Fall Time (See Note)

V_HHRise and Fall Time (See Note)

Min

500

250

ns

RESET# Setup Time for Temporary Sector

Unprotect

t_RSP

Min

4

µs

RESET# Hold Time from RY/BY# High for

Temporary Sector Unprotect

t_RRB

Note: Not 100% tested.

V_ID

RESET#

V_SS, V_IL,

or V_IH

V_SS, V_IL,

or V_IH

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RRB

t_RSP

RY/BY#

Figure 24. Temporary Sector Unprotect Timing Diagram

46

Am29DL32xG

25686B10 December 4, 2006

D A T A S H E E T

AC CHARACTERISTICS

V

ID

V

IH

RESET#

SA, A6,

A1, A0

Valid*

Status

Sector/Sector Block Protect or Unprotect

60h 60h

Verify

40h

Data

Sector/Sector Block Protect: 150 µs,

Sector/Sector Block Unprotect: 15 ms

1 µs

CE#

WE#

OE#

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram

December 4, 2006 25686B10

Am29DL32xG

47

D A T A S H E E T

AC CHARACTERISTICS

Alternate CE# Controlled Erase and Program Operations

Parameter

Speed Options

JEDEC

t_AVAV

Std

t_WC

t_AS

Description

70

90

0

120

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

Min

70

120

t_AVWL

t_ELAX

t_DVEH

t_EHDX

ns

t_AH

t_DS

t_DH

45

35

45

0

50

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

0

ns

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_WS

t_WH

t_CP

WE# Setup Time

WE# Hold Time

Min

Typ

0

ns

CE# Pulse Width

CE# Pulse Width High

30

35

30

5

50

t_CPH

Byte

Programming Operation

(Note 2)

t_WHWH1

µs

Word

7

Accelerated Programming Operation,

Word or Byte (Note 2)

t_WHWH1

t_WHWH2

Notes:

t_WHWH1

t_WHWH2

Typ

4

µs

Sector Erase Operation (Note 2)

0.4

sec

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

48

Am29DL32xG

25686B10 December 4, 2006

D A T A S H E E T

AC CHARACTERISTICS

555 for program

PA for program

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. D_OUTis the data written to the device.

4. Waveforms are for the word mode.

Figure 26. Alternate CE# Controlled Write (Erase/Program) Operation Timings

December 4, 2006 25686B10

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49

D A T A S H E E T

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1) Max (Note 2)

Unit

sec

µs

Comments

Sector Erase Time

0.4

28

5

Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time

Byte Program Time

Accelerated Byte/Word Program Time

Word Program Time

150

120

210

63

4

µs

Excludes system level

overhead (Note 5)

7

µs

Byte Mode

Word Mode

21

14

Chip Program Time

(Note 3)

sec

42

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V_CC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V_CC= 2.7 V (3.0 V for regulated devices), 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table

14 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V_SSon all pins except I/O pins

(including A9, OE#, and RESET#)

–1.0 V

12.5 V

Input voltage with respect to V_SSon all I/O pins

V_CCCurrent

–1.0 V

V_CC+ 1.0 V

+100 mA

–100 mA

Note: Includes all pins except V_CC. Test conditions: V_CC= 3.0 V, one pin at a time.

TSOP PIN AND FINE-PITCH BGA CAPACITANCE

Parameter Symbol

Parameter Description

Test Setup

Typ

6

Max

7.5

5.0

12

Unit

pF

TSOP

C_IN

Input Capacitance

V_IN= 0

V_OUT= 0

V_IN= 0

Fine-pitch BGA

TSOP

4.2

8.5

5.4

7.5

3.9

C_OUT

Output Capacitance

Fine-pitch BGA

TSOP

6.5

9

C_IN2

Control Pin Capacitance

Fine-pitch BGA

4.7

Notes:

1. Sampled, not 100% tested.

2. Test conditions T_A= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Description

Test Conditions

150°C

Min

10

Unit

Years

Minimum Pattern Data Retention Time

125°C

20

50

Am29DL32xG

25686B10 December 4, 2006

D A T A S H E E T

PHYSICAL DIMENSIONS

FBD063—63-ball Fine-Pitch Ball Grid Array (FBGA)

8 x 14 mm

Dwg rev AF; 10/99

December 4, 2006 25686B10

Am29DL32xG

51

D A T A S H E E T

PHYSICAL DIMENSIONS

FBD048—Fine-Pitch Ball Grid Array, 6 x 12 mm

Dwg rev AG; 7/2000

FBD 048

6.00 mm x 12.00 mm

PACKAGE

1.20

0.20

0.84

12.00 BSC

0.94

6.00 BSC

5.60 BSC

4.00 BSC

8

6

48

0.25 0.30

0.35

0.80 BSC

0.40 BSC

52

Am29DL32xG

25686B10 December 4, 2006

D A T A S H E E T

PHYSICAL DIMENSIONS

TS 048—Thin Small Outline Package

Dwg rev AA; 10/99

December 4, 2006 25686B10

Am29DL32xG

53

D A T A S H E E T

PHYSICAL DIMENSIONS

LAA064—64-ball Fortified Ball Grid Array (FBGA)

11 x 13 mm package

54

Am29DL32xG

25686B10 December 4, 2006

D A T A S H E E T

REVISION SUMMARY

DC Characteristics, CMOS Compatible

Revision A (November 7, 2001)

Removed IACC from table.

Global

AC Characteristics, Alternate CE# Controlled Erase

and Program Operations

Initial release. This device replaces the AM29DL32xD.

Revision B (July 31, 2002)

Change t_BHELfrom 0b to 0.

Global

TSOP and SO Pin Capacitance

Added LAA064 package.

Added Fine-Pitch BGA capacitance to table.

Ordering Information

Revision B + 2 (November 6, 2002)

Corrected package marking for FBGA.

Global

AC Characteristics

Removed 60 ns speed option and references to 80 ns

speed option.

Added 70 ns speed grade to Test Specifications and

Read-Only Operations

Removed reverse 48-pin TSOP package option.

Revision B + 1 (August 27, 2002)

Connection Diagrams, 64-Ball Fortified BGA

Distinctive Characteristics

Changed RFU to NC.

Changed write cycles guaranteed per sector to erase

cycles guaranteed per sector.

Package Capacitance

Removed references to SO package.

Connection Diagrams, Special Handling

Instructions for FBGA Package

Revision B + 3 (April 21, 2003)

Changed text to reflect revised handling instructions.

Connection Diagrams

Updated 64-Ball Fortified FBA (11 x 13 mm); changed

C5 from A21 to NC.

Ordering Information

Added 120 ns to Valid Combinations for TSOP Pack-

ages.

Revision B + 4 (March 26, 2004)

Table 7, Autoselect Codes, (High Voltage Method)

Connection Diagrams

Changed Secured Silicon Indicator Bit (DQ7 to DQ0)

from 81h to 82h (factory locked); 01h to 02h (not fac-

tory locked).

Updated array numbering scheme of 48-Ball

Fine-pitch FBA (6 x 12 mm) to match the physical dia-

gram.

Revision B + 5 (May 20, 2004)

Sector/Sector Block Protection and Unprotection

Removed paragraph referring to programming equip-

ment.

Global

Converted document to full datasheet version.

Common Flash Memory Interface (CFI)

Table 5, “Bottom Boot Sector Addresses”

Corrected third paragraph text to indicate that reset

command will return device to reading array data.

Added table.

Revision B + 6 (June 4, 2004)

Changed CFI URL to current link.

Command Definitions

Ordering Information

Corrected first paragraph text regarding incorrect ad-

dress and data values.

Added Lead-free (Pb-free) options to the Temperature

Range breakout of the OPN table and the Valid Com-

binations table.

Table 14, Command Definitions

Revision B + 7 (September 27, 2004)

Changed Sector/Sector Block Protect Verify fourth bus

cycle from 81/01 to 82/02.

Cover sheet and title page

Added notation to superseding documents.

December 4, 2006 25686B10

Am29DL32xG

55

D A T A S H E E T

Revision B + 8 (February 9, 2005)

Revision B10 (December 4, 2006)

Connection Diagrams

Global

Updated the 64-ball FBGA diagram.

Changed SecSi to Secured Silicon.

Pin Description

Erase and Program Operations table

Added RFU to the list of pins

Changed t_BUSYto a maximum specification.

Revision B + 9 (June 7, 2005)

Cover sheet and title page

Modified notation to superseding documents.

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-

tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-

templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the

public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,

aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for

any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion, Inc. will not be liable

to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor

devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design

measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating

conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign

Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-

thorization by the respective government entity will be required for export of those products.

Trademarks

marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are

for identification purposes only and may be trademarks of their respective companies.

trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.

56

Am29DL32xG

25686B10 December 4, 2006


型号：	D324GT90UF
厂家：	SPANSION
描述：	32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory 32兆位（ 4米×8位/ 2的M× 16位） CMOS 3.0伏只，同时操作闪存闪存
文件：	总58页 (文件大小：1293K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

D324GT90UF [SPANSION]

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