AM54BDS128AGTD9IS_技术文档

ADVANCE INFORMATION

Am54BDS128AG

Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

Two Am29BDS640G 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation,

Burst Mode Flash Memory and 16 Mbit (1 M x 16-Bit) Static RAM

DISTINCTIVE CHARACTERISTICS

■ Power dissipation (typical values, C_L= 30 pF)

MCP Features

■ Power supply voltage of 1.65 to 1.95 volt

— Burst Mode Read: 10 mA

— Simultaneous Operation: 25 mA

■ High performance

— Program/Erase: 15 mA

— Access time as fast as 70 ns/ 54 Mhz Burst

— Standby mode: 0.4 µA

■ Package

Hardware features

— 93-Ball FBGA

■ Software command sector locking

■ Operating Temperature

— –40°C to +85°C

■ Handshaking: host monitors operations via RDY

output

Flash Memory Features

■ Hardware reset input (RESET#)

■ WP# input

ARCHITECTURAL ADVANTAGES

— Write protect (WP#) function protects sectors 0, 1

(bottom boot) or sectors 132 and 133 (top boot),

regardless of sector protect status

■ Single 1.8 volt read, program and erase (1.65 to 1.95

volt)

■ Manufactured on 0.17 µm process technology

■ Simultaneous Read/Write operation

■ ACC input: Acceleration function reduces

programming time; all sectors locked when ACC = V_IL

— Data can be continuously read from one bank while

executing erase/program functions in other bank

■ CMOS compatible inputs, CMOS compatible outputs

■ Low V_CCwrite inhibit

— Zero latency between read and write operations

— Four bank architecture: 16Mb/16Mb/16Mb/16Mb

SOFTWARE FEATURES

■ Programmable Burst Interface

■ Supports Common Flash Memory Interface (CFI)

— 2 Modes of Burst Read Operation

— Linear Burst: 8, 16, and 32 words with wrap-around

— Continuous Sequential Burst

■ Software command set compatible with JEDEC 42.4

standards

■ Data# Polling and toggle bits

■ Erase Suspend/Resume

■ Sector Architecture

— Eight 8 Kword sectors and one hundred twenty-six 32

Kword sectors

— Suspends or resumes an erase operation in one

sector to read data from, or program data to, other

sectors

— Banks A and D each contain four 8 Kword sectors

and thirty-one 32 Kword sectors; Banks B and C

each contain thirty-two 32 Kword sectors

■ Unlock Bypass Program command

— Eight 8 Kword boot sectors, four at the top of the

address range, and four at the bottom of the address

range

— Reduces overall programming time when issuing

multiple program command sequences

SRAM Features

■ Power dissipation

■ Minimum 1 million erase cycle guarantee per sector

■ 20-year data retention at 125°C

— Operating: 3 mA maximum

— Standby: 15 µA maximum

PERFORMANCE CHARCTERISTICS

■ Read access times at 54/40 MHz

■ CE1s# and CE2s Chip Select

— Burst access times of 13.5/20 ns @ 30 pF at industrial

temperature range

■ Power down features using CE1s# and CE2s

■ Data retention supply voltage: 1.0 to 2.2 volt

— Asynchronous random access times of 70 ns (at 30

pF)

■ Byte data control: LB#s (DQ7–DQ0), UB#s

(DQ15–DQ8)

— Synchronous latency of 87.5/95 ns

Publication# 26628 Rev: A+1Amendment/+0

Issue Date: December 8, 2002

This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you

evaluate this product. Do not design in this product without contacting the factory. AMD reserves the right to change or discontinue work

on this proposed product without notice.

Refer to AMD’s Website (www.amd.com) for the latest information.

A D V A N C E I N F O R M A T I O N

GENERAL DESCRIPTION

The Am29BDS640G is a 64 Mbit, 1.8 Volt-only, simulta-

neous Read/Write, Burst Mode Flash memory device, orga-

nized as 4,194,304 words of 16 bits each. This device uses

a single V_CCof 1.65 to 1.95 V to read, program, and erase

the memory array. A 12.0-volt V_IDmay be used for faster pro-

gram performance if desired. The device can also be pro-

grammed in standard EPROM programmers.

mands are written to the command register using standard

microprocessor write timing. Register contents serve as in-

puts to an internal state-machine that controls the erase and

programming circuitry. Write cycles also internally latch ad-

dresses and data needed for the programming and erase

operations. Reading data out of the device is similar to read-

ing from other Flash or EPROM devices.

At 54 MHz, the device provides a burst access of 13.5 ns at

30 pF with a latency of 87.5 ns at 30 pF. At 40 MHz, the de-

vice provides a burst access of 20 ns at 30 pF with a latency

of 95 ns at 30 pF. The device operates within the industrial

temperature range of -40°C to +85°C. The device is offered

in a 93-ball FBGA package.

The Erase Suspend/Erase Resume feature enables the

user to put erase on hold for any period of time to read data

from, or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation in

progress and resets the internal state machine to reading

array data. The RESET# pin may be tied to the system reset

circuitry. A system reset would thus also reset the device,

enabling the system microprocessor to read boot-up firm-

ware from the Flash memory device.

The Simultaneous Read/Write architecture provides simul-

taneous operation by dividing the memory space into four

banks. The device can improve overall system performance

by allowing a host system to program or erase in one bank,

then immediately and simultaneously read from another

bank, with zero latency. This releases the system from wait-

ing for the completion of program or erase operations.

The host system can detect whether a program or erase op-

eration is complete by using the device status bit DQ7

(Data# Polling) and DQ6/DQ2 (toggle bits). After a program

or erase cycle has been completed, the device automatically

returns to reading array data.

The device is divided as shown in the following table:

Bank

Quantity

Size

The sector erase architecture allows memory sectors to be

erased and reprogrammed without affecting the data con-

tents of other sectors. The device is fully erased when

shipped from the factory.

4

8 Kwords

32 Kwords

8 Kwords

A

31

32

31

4

B

C

Hardware data protection measures include a low V_CCde-

tector that automatically inhibits write operations during

power transitions. The device also offers two types of data

protection at the sector level. The sector lock/unlock com-

mand sequence disables or re-enables both program and

erase operations in any sector. When at V_IL, WP# locks sec-

tors 0 and 1 (bottom boot device) or sectors 132 and 133

(top boot device).

D

The device uses Chip Enable (CE#), Write Enable (WE#),

Address Valid (AVD#) and Output Enable (OE#) to control

asynchronous read and write operations. For burst opera-

tions, the device additionally requires Ready (RDY), and

Clock (CLK). This implementation allows easy interface with

minimal glue logic to a wide range of microprocessors/micro-

controllers for high performance read operations.

The device offers two power-saving features. When ad-

dresses have been stable for a specified amount of time, the

device enters the automatic sleep mode. The system can

also place the device into the standby mode. Power con-

sumption is greatly reduced in both modes.

The burst read mode feature gives system designers flexibil-

ity in the interface to the device. The user can preset the

burst length and wrap through the same memory space, or

read the flash array in continuous mode.

AMD’s Flash technology combines years of Flash memory

manufacturing experience to produce the highest levels of

quality, reliability and cost effectiveness. The device electri-

cally erases all bits within a sector simultaneously via

Fowler-Nordheim tunnelling. The data is programmed using

hot electron injection.

The clock polarity feature provides system designers a

choice of active clock edges, either rising or falling. The ac-

tive clock edge initiates burst accesses and determines

when data will be output.

The device is entirely command set compatible with the

JEDEC 42.4 single-power-supply Flash standard. Com-

December 8, 2002

Am54BDS128AG

2

A D V A N C E I N F O R M A T I O N

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5

MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 6

Flash Memory Block Diagram. . . . . . . . . . . . . . . . 7

Flash Memory Simultaneous Operation Diagram 8

Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 9

Special Package Handling Instructions .................................... 9

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Flash Logic Symbol . . . . . . . . . . . . . . . . . . . . . . .10

Ordering Information . . . . . . . . . . . . . . . . . . . . . . 11

MCP Device Bus Operations. . . . . . . . . . . . . . . . 12

Flash Device Bus Operations . . . . . . . . . . . . . . . 14

Requirements for Asynchronous Read

Reading Toggle Bits DQ6/DQ2 ............................................... 34

DQ5: Exceeded Timing Limits ................................................ 34

DQ3: Sector Erase Timer ....................................................... 34

Table 15. Write Operation Status ................................................... 35

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 36

Figure 6. Maximum Negative Overshoot Waveform ...................... 36

Figure 7. Maximum Positive Overshoot Waveform........................ 36

Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 36

Flash DC Characteristics . . . . . . . . . . . . . . . . . . 37

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 8. Test Setup....................................................................... 39

Table 16. Test Specifications ......................................................... 39

Key to Switching Waveforms. . . . . . . . . . . . . . . . 39

Figure 9. Input Waveforms and Measurement Levels ................... 39

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 40

SRAM CE#s Timing ................................................................ 40

Figure 10. Timing Diagram for Alternating

Operation (Non-Burst) ............................................................ 14

Requirements for Synchronous (Burst) Read Operation ........ 14

Table 2. Burst Address Groups .......................................................14

Burst Mode Configuration Register ........................................ 15

Reduced Wait-State Handshaking Option .............................. 15

Simultaneous Read/Write Operations with Zero Latency ....... 15

Writing Commands/Command Sequences ............................ 15

Standby Mode ........................................................................ 16

Automatic Sleep Mode ........................................................... 16

RESET#: Hardware Reset Input ............................................. 16

Output Disable Mode .............................................................. 16

Hardware Data Protection ...................................................... 16

Common Flash Memory Interface (CFI) . . . . . . .17

Table 3. CFI Query Identification String ..........................................17

System Interface String................................................................... 18

Table 6. Primary Vendor-Specific Extended Query ........................19

Table 7. Am29BDS640G Sector Address Table .............................20

Flash Command Definitions . . . . . . . . . . . . . . . . 23

Reading Array Data ................................................................ 23

Set Burst Mode Configuration Register Command Sequence 24

Figure 1. Synchronous/Asynchronous State Diagram .................... 24

Table 8. Programmable Wait State Settings ...................................25

Table 9. Initial Access Codes ..........................................................25

Table 10. Wait States for Standard Handshaking ...........................25

Table 11. Burst Read Mode Settings ..............................................26

Configuration Register ............................................................ 27

Table 12. Burst Mode Configuration Register .................................27

Sector Lock/Unlock Command Sequence .............................. 27

Reset Command ..................................................................... 27

Autoselect Command Sequence ............................................ 27

Program Command Sequence ............................................... 28

Figure 2. Erase Operation............................................................... 29

Chip Erase Command Sequence ........................................... 29

Sector Erase Command Sequence ........................................ 29

Erase Suspend/Erase Resume Commands ........................... 30

Figure 3. Program Operation .......................................................... 30

Command Definitions ............................................................. 31

Table 13. Command Definitions .....................................................31

Flash Write Operation Status . . . . . . . . . . . . . . . . 32

DQ7: Data# Polling ................................................................. 32

Figure 4. Data# Polling Algorithm ................................................... 32

RDY: Ready ............................................................................ 33

DQ6: Toggle Bit I .................................................................... 33

Figure 5. Toggle Bit Algorithm......................................................... 33

DQ2: Toggle Bit II ................................................................... 33

Table 14. DQ6 and DQ2 Indications ...............................................34

Between SRAM and Flash............................................................. 40

Synchronous/Burst Read ........................................................ 41

Figure 11. CLK Synchronous Burst Mode Read

(rising active CLK).......................................................................... 42

Figure 12. CLK Synchronous Burst Mode Read

(Falling Active Clock) ..................................................................... 43

Figure 13. Synchronous Burst Mode Read.................................... 44

Figure 14. 8-word Linear Burst with Wrap Around......................... 44

Figure 15. Burst with RDY Set One Cycle Before Data ................. 45

Figure 16. Reduced Wait-State Handshaking Burst Mode Read

Starting at an Even Address .......................................................... 46

Figure 17. Reduced Wait-State Handshaking Burst Mode Read

Starting at an Odd Address............................................................ 47

Asynchronous Read ............................................................... 48

Figure 18. Asynchronous Mode Read with Latched Addresses .... 48

Figure 19. Asynchronous Mode Read............................................ 49

Figure 20. Reset Timings............................................................... 50

Erase/Program Operations ..................................................... 51

Figure 21. Asynchronous Program Operation Timings.................. 52

Figure 22. Alternate Asynchronous Program Operation Timings... 53

Figure 23. Synchronous Program Operation Timings.................... 54

Figure 24. Alternate Synchronous Program Operation Timings .... 55

Figure 25. Chip/Sector Erase Command Sequence...................... 56

Figure 26. Accelerated Unlock Bypass Programming Timing........ 57

Figure 27. Data# Polling Timings (During Embedded Algorithm) .. 58

Figure 28. Toggle Bit Timings (During Embedded Algorithm)........ 58

Figure 29. Synchronous Data Polling Timings/Toggle Bit Timings 59

Figure 30. Latency with Boundary Crossing .................................. 59

Figure 31. Latency with Boundary Crossing

into Program/Erase Bank............................................................... 60

Figure 32. Example of Wait States Insertion (Standard

Handshaking Device)..................................................................... 61

Figure 33. Back-to-Back Read/Write Cycle Timings...................... 62

SRAM AC Characteristics . . . . . . . . . . . . . . . . . . 63

Read Cycle ............................................................................. 63

Figure 34. SRAM Read Cycle—Address Controlled...................... 63

Figure 35. SRAM Read Cycle........................................................ 64

Write Cycle ............................................................................. 65

Figure 36. SRAM Write Cycle—WE# Control ................................ 65

Figure 37. SRAM Write Cycle—CE1#s Control ............................. 66

Figure 38. SRAM Write Cycle—UB#s and LB#s Control............... 67

Flash Erase And Programming Performance . 68

Flash Latchup Characteristics. . . . . . . . . . . . . . . 68

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Am54BDS128AG

December 8, 2002

A D V A N C E I N F O R M A T I O N

Package Pin Capacitance . . . . . . . . . . . . . . . . . . 68

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 70

FMA093—93-Ball Fine-Pitch Grid Array 10 x 10mm .............. 70

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 71

Revision A (July 16, 2002) ...................................................... 71

Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 68

SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . . 69

Figure 39. CE1#s Controlled Data Retention Mode........................ 69

Figure 40. CE2s Controlled Data Retention Mode.......................... 69

December 8, 2002

Am54BDS128AG

4

A D V A N C E I N F O R M A T I O N

PRODUCT SELECTOR GUIDE

Part Number

Am54BDS128AG

54 MHz

Burst Frequency

40 MHz

C8, C9

V

_CC,V_IO

=

Speed Option

D8, D9

1.65 – 1.95 V

Max Initial Synchronous Access Time, ns (t_IACC) Reduced

Wait-state Handshaking: Even Address

87.5

95

Max Initial Synchronous Access Time, ns (t_IACC) Reduced

Wait-state Handshaking: Odd Address; or Standard Handshaking

106

120

20

Max Burst Access Time, ns (t_BACC

Max Asynchronous Access Time, ns (t_ACC

Max CE# Access, ns (t_CE

Max OE# Access, ns (t_OE

Max Access Time, ns (t_ACC

Max CE# Access, ns (t_CE

Max OE# Access, ns (t_OE

)

13.5

)

70

13.5

70

85

20

85

40

)

35

5

Am54BDS128AG

December 8, 2002

A D V A N C E I N F O R M A T I O N

MCP BLOCK DIAGRAM

V_CCf/V_IO

f

V_SS

A21 to A0

RDY

64 MBit

Flash Memory

#1

CE#f1

DQ15 to DQ0

V_CCf/V_IO

f

V_SS

A21 to A0

CLK

ACC

WP#

RESET#

AVD#

RDY

64 MBit

Flash Memory

#2

DQ15 to DQ0

CE#f2

DQ15 to DQ0

V_CCs

V_SS

A19 to A0

16 MBit

Static

RAM

LB#s

UB#s

WE#

OE#

CE1#s

CE2s

DQ15 to DQ0

December 8, 2002

Am54BDS128AG

6

A D V A N C E I N F O R M A T I O N

FLASH MEMORY BLOCK DIAGRAM

V_CC

V_SS

V_SSIO

V_IO

DQ15–DQ0

RDY

Buffer

RDY

Erase Voltage

Generator

Input/Output

Buffers

WE#

RESET#

WP#

State

Control

Command

Register

ACC

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

CE#

OE#

Y-Decoder

Y-Gating

V_CC

Detector

Timer

Cell Matrix

X-Decoder

Burst

State

Control

Burst

Address

Counter

AVD#

CLK

A21–A0

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Am54BDS128AG

December 8, 2002

A D V A N C E I N F O R M A T I O N

FLASH MEMORY SIMULTANEOUS OPERATION DIAGRAM

V

CC

V

SS

IO

V

SSIO

Bank A Address

DQ15–DQ0

Bank A

A21–A0

X-Decoder

OE#

Bank B Address

DQ15–DQ0

Bank B

WP#

ACC

X-Decoder

A21–A0

STATE

CONTROL

&

COMMAND

REGISTER

RESET#

WE#

DQ15–DQ0

Status

CE#

AVD#

RDY

Control

A21–A0

DQ15–DQ0

X-Decoder

Bank C

DQ15–DQ0

Bank C Address

A21–A0

X-Decoder

Bank D

Bank D Address

DQ15–DQ0

December 8, 2002

Am54BDS128AG

8

A D V A N C E I N F O R M A T I O N

CONNECTION DIAGRAM

93-Ball FBGA

Top View

A1

A10

NC

B2

B3

B10

B8

B9

B1

B4

B6

B5

B7

CLK

NC

AVD#

C2

NC

C1

C5

C3

A7

D3

A6

E3

A5

C4

LB#

D4

C7

A8

C9

C6

C8

NC

WP#

NC

ACC

WE#

A11

D2

A3

D6

CE2s

E6

D7

A19

E7

D8

A12

E8

D9

D5

2nd Flash Only

A15

RESET#

UB#

E4

E2

A2

E5

E9

A18

RDY

A20

A9

A13

A21

F1

F2

A1

F3

A4

F4

F5

F7

F8

F9

F10

NC

F6

NC

A17

NC

A10

A14

CE#f2

NC

G5

NC

G6

NC

G1

NC

G2

A0

G3

G4

G7

G8

NC

G9

G10

NC

VSS

DQ1

DQ6

A16

H5

H2

H3

H4

H6

H7

H8

H9

DQ3

CE#f1

OE#

DQ9

DQ4

DQ13 DQ15

NC

J2

J3

J4

J5

J6

J7

J8

J9

CE1#s DQ0

DQ10 VCCf VCCs DQ12

DQ7

VSS

K2

K3

K4

K5

K6

K7

K8

K9

NC

DQ8

DQ2

DQ11

NC

DQ5

DQ14

NC

L2

L3

L4

L6

L7

L8

L9

L10

RFU

L1

L5

NC

V

ss

NC

VIOf

M1

NC

M10

NC

No Connection

NC

Flash 1,2 and SRAM

Flash 1 and 2 shared

Flash1 only

SRAM only

Note:V_IOf must be the same as V_CC

f

SSOP). The package and/or data integrity may be

compromised if the package body is exposed to tem-

perature about 150°C for prolonged periods of time.

Special Package Handling Instructions

Special handling is required for Flash Memory prod-

ucts in molded packages (TOSP, BGA, PLCC, PDIP,

9

Am54BDS128AG

December 8, 2002

A D V A N C E I N F O R M A T I O N

Low = for asynchronous mode, indi-

PIN DESCRIPTION

cates valid address; for burst mode,

causes starting address to be latched.

A19–A0

= 20 Address Inputs (Common)

= 2 Address Inputs (Flash)

A21–A20

High = device ignores address inputs

DQ15–DQ0 = 16 Data Inputs/Outputs (Common)

WP#

ACC

= Hardware write protect input. At V_IL,

disables program and erase functions

in the two outermost sectors. Should

be at V_IHfor all other conditions.

CE#f1

CE#f2

CE1#s

CE2s

OE#

= Chip Enable 1 (Flash)

= Chip Enable 2 (Flash)

= Chip Enable 1 (SRAM)

= Chip Enable 2 (SRAM)

= Output Enable (Common)

= Write Enable (Common)

= Upper Byte Control (SRAM)

= Lower Byte Control (SRAM)

= Hardware Reset Pin, Active Low

= At V_ID, accelerates programming; au-

tomatically places device in unlock by-

pass mode. At V_IL, locks all sectors.

Should be at V_IHfor all other condi-

tions.

WE#

UB#s

LB#s

FLASH LOGIC SYMBOL

RESET#

20

V_CCf

= Flash 1.8 volt-only single power

supply (see Product Selector Guide

for speed options and voltage supply

tolerances)

A19–A0

A21–A20

CE#f1

V_IOf

= Input & Output Buffer Power Supply

must be tied to V_CCf.

CE#f2

16

CE1#s

CE2s

OE#

DQ15–DQ0

RDY

V

_CCs

_SSIOf

= SRAM Power Supply

V

= Output Buffer Ground

V_SS

NC

= Device Ground (Common)

= Pin Not Connected Internally

WE#

WP#

RDY

= Ready output; indicates the status of

the Burst read. Low = data not valid at

expected time. High = data valid.

RESET#

UB#s

LB#s

ACC

CLK

= CLK is not required in asynchronous

mode. In burst mode, after the initial

word is output, subsequent active

edges of CLK increment the internal

address counter.

AVD#

CLK

AVD#

= Address Valid input. Indicates to de-

vice that the valid address is present

on the address inputs (A21–A0).

December 8, 2002

Am54BDS128AG

10

A D V A N C E I N F O R M A T I O N

ORDERING INFORMATION

The order number (Valid Combination) is formed by the following:

Am54BDS128

A

G

T

D

8

I

T

TAPE AND REEL

T

S

=

7 inches

13 inches

TEMPERATURE RANGE

Industrial (–40°C to +85°C)

I

=

V_IOAND HANDSHAKING FEATURES

8

9

=

1.8 V V_IO, reduced wait-state handshaking

1.8 V V_IO, standard handshaking

CLOCK RATE/ASYNCHRONOUS SPEED/SRAM SPEED

D

C

=

54 MHz/70 ns/70 ns

40 MHz/85 ns/85 ns

BOOT SECTOR PROTECTION

T

B

=

Top Boot Sectors (protection under WP#)

Bottom Boot Sectors (protection under WP#)

PROCESS TECHNOLOGY

0.17 µm

G

=

SRAM DEVICE DENSITY

16 Mbits

A

=

AMD DEVICE NUMBER/DESCRIPTION

Am54BDS128AG

Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

Two Am29BDS640G 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous

Operation

Burst Mode Flash Memory and 16 Mbit (1 M x 16-Bit) Static RAM

93-Ball Fine-pitch Ball Grid Array Package, 10.0 x 10.0 mm, 0.8 mm ball pitch (FMA093)

Valid Combinations

Order Number

Burst Frequency

(MHz)

V_IORange

Package Marking

Am54BDS128AGTD8I

Am54BDS128AGBD8I

M540000004

M540000005

54

40

Am54BDS128AGTD9I

Am54BDS128AGBD9I

M540000006

M540000007

1.65 –

1.95 V

T, S

Am54BDS128AGTC8I

Am54BDS128AGBC8I

M540000008

M540000009

Am54BDS128AGTC9I

Am54BDS128AGBC9I

M540000010

M540000011

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

11

Am54BDS128AG

December 8, 2002

A D V A N C E I N F O R M A T I O N

MCP DEVICE BUS OPERATIONS

This section describes the requirements and use of

the device bus operations, which are initiated through

the internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is a latch used to store the com-

mands, along with the address and data information

needed to execute the command. The contents of the

register serve as inputs to the internal state machine.

The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the in-

puts and control levels they require, and the resulting

output. The following subsections describe each of

these operations in further detail.

December 8, 2002

Am54BDS128AG

12

A D V A N C E I N F O R M A T I O N

Table 1. Device Bus Operations

CE#f

Active Inactive

CE#f

CE1#

s

CE2s

LB#s UB#s

(Note 4)

A

DQ

Operation

OE# WE#

RESET# CLK AVD#

[21–0] [15–8] [7–0]

(Note 9)

(Note 3)

Asynchronous Read from

Flash,

Addresses Latched

A_IN

L

H

L

H

I/O

X

H

X

Asynchronous Read from

Flash,

L

Addresses Steady State

A_IN

Asynchronous Write to Flash

Synchronous Write to Flash

CE# Standby

L

H

L

H

X

L

X

I/O

X

H

L

X

H

L

Hi-Z

X

L

X

L

X

Output Disable

Hardware Reset

L

H

X

H

X

Hi-Z

H

L

X

L

X

Hi-Z

X

L

D_OUT

A_IN

D_OUT

Read from SRAM

Write to SRAM

H

L

H

L

H

L

Hi-Z

D_OUT

D_IN

H

L

H

L

H

X

Hi-Z

D_IN

L

A_IN

D_IN

X

Hi-Z

D_IN

H

L

HI-Z

H

Flash Burst Read Operations

Load Starting Burst Address

L

H

L

X

L

H

Addr In

X

H

Advance Burst to next

address with appropriate

Data presented on the Data

Bus

HIGH

Z

Burst

Data Out

H

Terminate current Burst read

cycle

H

X

H

L

X

H

Hi-Z

X

H

L

X

Terminate current Burst read

cycle via RESET#

X

Terminate current Burst read

cycle and start new Burst

read cycle

L

H

L

X

H

Hi-Z

I/O

X

H

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 9–11 V, V_HH

= 9.0 ± 0.5 V, X = Don’t Care, A_IN= Address In, D_IN= Data In, D_OUT

=Data Out

= Rising edge of Pulse Low

= Active edge of CLK,

= Pulse Low,

Notes:

1. Other operations except for those indicated in this column are

inhibited.

6. The sector protect and sector unprotect functions may also be

implemented via programming equipment. See the “Sector

Lock/Unlock Command Sequence”section.

2. Do not apply CE#f = V_IL, CE1#s = V_ILand CE2s = V_IHat the same

time.

7. If ACC = V_HH, all sectors will be protected.

3. Either CE1#s = V_IHor CE2s = V_ILwill disable the SRAM. If one of

these conditions is true, the other CE input is don’t care.

8. If WP# = V_IL, sectors 0,1 (bottom boot) or sectors 132, 133 (top

boot) are protected. If WP# = V_IH, the protection applied to the

aforementioned sectors depends on whether they were last

protected or unprotected using the method described in “Sector

Lock/Unlock Command Sequence”. Note that WP# must not be

left floating or unconnected.

4. X = Don’t care or open LB#s or UB#s.

5. Default edge of CLK is the rising edge.

9. Active flash is device being addressed.

13

Am54BDS128AG

December 8, 2002

A D V A N C E I N F O R M A T I O N

by pulsing low. For standard handshaking devices,

there is no two cycle latency between 3Fh and 40h (or

multiple thereof). See Table 10.

FLASH DEVICE BUS OPERATIONS

Requirements for Asynchronous Read

Operation (Non-Burst)

For reduced wait-state handshaking devices, if the ad-

dress latched is 3Dh (or 64 multiple), an additional

cycle latency occurs prior to the initial access. If the

address latched is 3Eh (or 64 multiple) two additional

cycle latency occurs prior to the initial access and the

2 cycle latency between 3Fh and 40h (or 64 multiple)

will not occur. For 3Fh latched addresses (or 64 multi-

ple) three additional cycle latency occurs prior to the

initial access and the 2 cycle latency between 3Fh and

40h (or 64 multiple) will not occur.

To read data from the memory array, the system must

first assert a valid address on A21–A0, while driving

AVD# and CE# to V_IL. WE# should remain at V_IH. The

rising edge of AVD# latches the address. The data will

appear on DQ15–DQ0. Since the memory array is di-

vided into four banks, each bank remains enabled for

read access until the command register contents are

altered.

Address access time (t_ACC) is equal to the delay from

stable addresses to valid output data. The chip enable

access time (t_CE) is the delay from the stable ad-

dresses and stable CE# to valid data at the outputs.

The output enable access time (t_OE) is the delay from

the falling edge of OE# to valid data at the output.

The device will continue to output sequential burst

data, wrapping around to address 000000h after it

reaches the highest addressable memory location,

until the system drives CE# high, RESET# low, or

AVD# low in conjunction with a new address. See

Table 1, “Device Bus Operations,” on page 13.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition.

If the host system crosses the bank boundary while

reading in burst mode, and the device is not program-

ming or erasing, a two-cycle latency will occur as de-

scribed above in the subsequent bank. If the host

system crosses the bank boundary while the device is

programming or erasing, the device will provide read

status information. The clock will be ignored. After the

host has completed status reads, or the device has

completed the program or erase operation, the host

can restart a burst operation using a new address and

AVD# pulse.

Requirements for Synchronous (Burst)

Read Operation

The device is capable of continuous sequential burst

operation and linear burst operation of a preset length.

When the device first powers up, it is enabled for

asynchronous read operation.

Prior to entering burst mode, the system should deter-

mine how many wait states are desired for the initial

word (t_IACC) of each burst access, what mode of burst

operation is desired, which edge of the clock will be

the active clock edge, and how the RDY signal will

transition with valid data. The system would then write

the burst mode configuration register command se-

quence. See “Set Burst Mode Configuration Register

Command Sequence” and “Flash Command Defini-

tions” for further details.

If the clock frequency is less than 6 MHz during a burst

mode operation, additional latencies will occur. RDY

indicates the length of the latency by pulsing low.

8-, 16-, and 32-Word Linear Burst with Wrap Around

The remaining three modes are of the linear wrap

around design, in which a fixed number of words are

read from consecutive addresses. In each of these

modes, the burst addresses read are determined by

the group within which the starting address falls. The

groups are sized according to the number of words

read in a single burst sequence for a given mode (see

Table 2.)

Once the system has written the “Set Burst Mode Con-

figuration Register” command sequence, the device is

enabled for synchronous reads only.

The initial word is output t_IACCafter the active edge of

the first CLK cycle. Subsequent words are output t_BACC

after the active edge of each successive clock cycle,

which automatically increments the internal address

counter. Note that the device has a fixed internal ad-

dress boundary that occurs every 64 words, starting at

address 00003Fh. During the time the device is out-

putting data at this fixed internal address boundary

(address 00003Fh, 00007Fh, 0000BFh, etc.), a two

cycle latency occurs before data appears for the next

address (address 000040h, 000080h, 0000C0h, etc.).

The RDY output indicates this condition to the system

Table 2. Burst Address Groups

Mode

8-word

16-word

32-word

Group Size Group Address Ranges

8 words 0-7h, 8-Fh, 10-17h, ...

16 words 0-Fh, 10-1Fh, 20-2Fh, ...

32 words 00-1Fh, 20-3Fh, 40-5Fh, ...

As an example: if the starting address in the 8-word

mode is 39h, the address range to be read would be

38-3Fh, and the burst sequence would be

39-3A-3B-3C-3D-3E-3F-38h-etc. The burst sequence

begins with the starting address written to the device,

December 8, 2002

Am54BDS128AG

14

A D V A N C E I N F O R M A T I O N

but wraps back to the first address in the selected

pended to read from or program to another location

within the same bank (except the sector being

erased). Figure 33, “Back-to-Back Read/Write Cycle

Timings,” on page 62 shows how read and write cy-

cles may be initiated for simultaneous operation with

zero latency. Refer to the DC Characteristics table for

read-while-program and read-while-erase current

specifications.

group. In a similar fashion, the 16-word and 32-word

Linear Wrap modes begin their burst sequence on the

starting address written to the device, and then wrap

back to the first address in the selected address

group. Note that in these three burst read modes

the address pointer does not cross the boundary

that occurs every 64 words; thus, no wait states

are inserted (except during the initial access).

Writing Commands/Command Sequences

The RDY pin indicates when data is valid on the bus.

The devices can wrap through a maximum of 128

words of data (8 words up to 16 times, 16 words up to

8 times, or 32 words up to 4 times) before requiring a

new synchronous access (latching of a new address).

The device has the capability of performing an asyn-

chronous or synchronous write operation. During a

synchronous write operation, to write a command or

command sequence (which includes programming

data to the device and erasing sectors of memory), the

system must drive AVD# and CE# to V_IL, and OE# to

V_IHwhen providing an address to the device, and drive

WE# and CE# to V_IL, and OE# to V_IH. when writing

commands or data. During an asynchronous write op-

eration, the system must drive CE# and WE# to V_IL

and OE# to V_IHwhen providing an address, command,

and data. The asynchronous and synchronous pro-

graming operation is independent of the Set Device

Read Mode bit in the Burst Mode Configuration Regis-

ter.

Burst Mode Configuration Register

The device uses a configuration register to set the var-

ious burst parameters: number of wait states, burst

read mode, active clock edge, RDY configuration, and

synchronous mode active.

Reduced Wait-State Handshaking Option

The device can be equipped with a reduced wait-state

handshaking feature that allows the host system to

simply monitor the RDY signal from the device to de-

termine when the initial word of burst data is ready to

be read. The host system should use the programma-

ble wait state configuration to set the number of wait

states for optimal burst mode operation. The initial

word of burst data is indicated by the rising edge of

RDY after OE# goes low.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are re-

quired to program a word, instead of four.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 8, “Programmable

Wait State Settings,” on page 25 indicates the address

space that each sector occupies. The device address

space is divided into four banks: Banks B and C con-

tain only 32 Kword sectors, while Banks A and D con-

tain both 8 Kword boot sectors in addition to 32 Kword

sectors. A “bank address” is the address bits required

to uniquely select a bank. Similarly, a “sector address”

is the address bits required to uniquely select a sector.

The presence of the reduced wait-state handshaking

feature may be verified by writing the autoselect com-

mand sequence to the device. See “Autoselect Com-

mand Sequence” for details.

For optimal burst mode performance on devices with-

out the reduced wait-state handshaking option, the

host system must set the appropriate number of wait

states in the flash device depending on clock fre-

quency and the presence of a boundary crossing. See

“Set Burst Mode Configuration Register Command

Sequence” section on page 24 section for more infor-

mation. The device will automatically delay RDY and

data by one additional clock cycle when the starting

address is odd.

I_CC2in the DC Characteristics table represents the ac-

tive current specification for the write mode. The AC

Characteristics section contains timing specification

tables and timing diagrams for write operations.

Accelerated Program Operation

The device offers accelerated program operations

through the ACC function. ACC is primarily intended to

allow faster manufacturing throughput at the factory.

The autoselect function allows the host system to de-

termine whether the flash device is enabled for re-

duced wait-state handshaking. See the “Autoselect

Command Sequence” section for more information.

If the system asserts V_IDon this input, the device auto-

matically enters the aforementioned Unlock Bypass

mode and uses the higher voltage on the input to re-

duce the time required for program operations. The

system would use a two-cycle program command se-

quence as required by the Unlock Bypass mode. Re-

moving V_IDfrom the ACC input returns the device to

Simultaneous Read/Write Operations with

Zero Latency

This device is capable of reading data from one bank

of memory while programming or erasing in another

bank of memory. An erase operation may also be sus-

15

Am54BDS128AG

December 8, 2002

A D V A N C E I N F O R M A T I O N

normal operation. Note that sectors must be unlocked

RESET#: Hardware Reset Input

prior to raising ACC to V_ID. Note that the ACC pin must

not be at V_IDfor operations other than accelerated pro-

gramming, or device damage may result. In addition,

the ACC pin must not be left floating or unconnected;

inconsistent behavior of the device may result.

The RESET# input provides a hardware method of re-

setting the device to reading array data. When RE-

SET# is driven low for at least a period of t_RP, the

device immediately terminates any operation in

progress, tristates all outputs, resets the configuration

register, and ignores all read/write commands for the

duration of the RESET# pulse. The device also resets

the internal state machine to reading array data. The

operation that was interrupted should be reinitiated

once the device is ready to accept another command

sequence, to ensure data integrity.

When at V_IL, ACC locks all sectors. ACC should be at

V_IHfor all other conditions.

Autoselect Functions

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ15–DQ0. Autoselect mode may only be entered

and used when in the asynchronous read mode. Refer

to the “Autoselect Command Sequence” section on

page 27 section for more information.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V_SS± 0.2 V, the de-

vice draws CMOS standby current (I_CC4). If RESET# is

held at V_ILbut not within V_SS± 0.2 V, the standby cur-

rent will be greater.

RESET# may be tied to the system reset circuitry. A

system reset would thus also reset the Flash memory,

enabling the system to read the boot-up firmware from

the Flash memory.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

If RESET# is asserted during a program or erase op-

eration, the device requires a time of t_READY(during

Embedded Algorithms) before the device is ready to

read data again. If RESET# is asserted when a pro-

gram or erase operation is not executing, the reset op-

eration is completed within a time of t_READY(not during

Embedded Algorithms). The system can read data t_RH

after RESET# returns to V_IH.

The device enters the CMOS standby mode when the

CE# and RESET# inputs are both held at V_CC± 0.2 V.

The device requires standard access time (t_CE) for

read access, before it is ready to read data.

If the device is deselected during erasure or program-

ming, the device draws active current until the opera-

tion is completed.

Refer to the AC Characteristics tables for RESET# pa-

rameters and to Figure 20, “Reset Timings,” on

page 50 for the timing diagram.

I_CC3in the DC Characteristics table represents the

standby current specification.

Output Disable Mode

When the OE# input is at V_IH, output from the device is

disabled. The outputs are placed in the high imped-

ance state.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. While in asynchronous mode, the

device automatically enables this mode when ad-

dresses remain stable for t_ACC+ 60 ns. The automatic

sleep mode is independent of the CE#, WE#, and OE#

control signals. Standard address access timings pro-

vide new data when addresses are changed. While in

sleep mode, output data is latched and always avail-

able to the system. While in synchronous mode, the

device automatically enables this mode when either

the first active CLK edge occurs after t_ACCor the CLK

runs slower than 5MHz. Note that a new burst opera-

tion is required to provide new data.

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 14, “Com-

mand Definitions,” on page 31 for command defini-

tions).

The device offers two types of data protection at the

sector level:

■ The sector lock/unlock command sequence dis-

ables or re-enables both program and erase opera-

tions in any sector.

I_CC4in the “Flash DC Characteristics” section on page

37 represents the automatic sleep mode current spec-

ification.

■ When WP# is at V_IL, sectors 0 and 1 (bottom boot)

or sectors 132 and 133 (top boot) are locked.

■ When ACC is at V_IL, all sectors are locked.

December 8, 2002

Am54BDS128AG

16

A D V A N C E I N F O R M A T I O N

The following hardware data protection measures pre-

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets to reading array data. Subse-

vent accidental erasure or programming, which might

otherwise be caused by spurious system level signals

during V_CCpower-up and power-down transitions, or

from system noise.

quent writes are ignored until V_CCis greater than V_LKO

.

The system must provide the proper signals to the

control inputs to prevent unintentional writes when V_CC

Write Protect (WP#)

is greater than V_LKO

.

The Write Protect (WP#) input provides a hardware

method of protecting data without using V_ID.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE#

or WE# do not initiate a write cycle.

If the system asserts V_ILon the WP# pin, the device

disables program and erase functions in sectors 0 and

1 (bottom boot) or sectors 132 and 133 (top boot).

Logical Inhibit

If the system asserts V_IHon the WP# pin, the device

reverts to whether the two outermost 8K Byte boot

sectors were last set to be protected or unprotected.

Write cycles are inhibited by holding any one of OE# =

V_IL, CE# = V_IHor WE# = V_IH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

Note that the WP# pin must not be left floating or un-

connected; inconsistent behavior of the device may re-

sult.

Power-Up Write Inhibit

If WE# = CE# = RESET# = V_ILand OE# = V_IHduring

power up, the device does not accept commands on

the rising edge of WE#. The internal state machine is

automatically reset to the read mode on power-up.

Low V_CCWrite Inhibit

When V_CCis less than V_LKO, the device does not ac-

cept any write cycles. This protects data during V_CC

given in Tables 3-6. To terminate reading CFI data, the

system must write the reset command.

COMMON FLASH MEMORY INTERFACE

(CFI)

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 3-6. The

system must write the reset command to return the de-

vice to the autoselect mode.

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-inde-

pendent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device

families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

For further information, please refer to the CFI Specifi-

cation and CFI Publication 100, available via the AMD

site at the following URL:

http://www.amd.com/us-en/FlashMemory/Technical-

Resources/0,,37_1693_1780_1834^1955,00.html. Al-

ternatively, contact an AMD representative for copies

of these documents.

This device enters the CFI Query mode when the sys-

tem writes the CFI Query command, 98h, to address

55h any time the device is ready to read array data.

The system can read CFI information at the addresses

Table 3. CFI Query Identification String

Description

Addresses

Data

10h

11h

12h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

Primary OEM Command Set

13h

14h

0002h

0000h

15h

16h

0040h

0000h

Address for Primary Extended Table

17h

18h

0000h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

0000h

17

Am54BDS128AG

December 8, 2002

A D V A N C E I N F O R M A T I O N

Table 4. System Interface String

Description

Addresses

Data

V_CCMin. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Bh

0017h

V_CCMax. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Ch

0019h

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

0000h

0004h

0000h

0009h

0000h

0004h

0000h

0004h

0000h

V_PPMin. voltage (00h = no V_PPpin present)

V_PPMax. voltage (00h = no V_PPpin present)

Typical timeout per single byte/word write 2^Nµs

Typical timeout for Min. size buffer write 2^Nµs (00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

December 8, 2002

Am54BDS128AG

18

A D V A N C E I N F O R M A T I O N

Table 5. Device Geometry Definition

Addresses

Data

Description

27h

0017h

Device Size = 2^Nbyte

28h

29h

0001h

0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

0000h

Max. number of bytes in multi-byte write = 2^N

(00h = not supported)

2Ch

0003h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

0003h

0000h

0040h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

007Dh

0000h

0001h

Erase Block Region 2 Information

Erase Block Region 3 Information

Erase Block Region 4 Information

35h

36h

37h

38h

0003h

0000h

0040h

0000h

39h

3Ah

3Bh

3Ch

0000h

Table 6. Primary Vendor-Specific Extended Query

Data Description

Addresses

40h

41h

42h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

0031h

0033h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

45h

0004h

Silicon Technology (Bits 5-2) 0001 = 0.17 µm

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

46h

47h

48h

49h

4Ah

4Bh

4Ch

0002h

0001h

0000h

0005h

0063h

0001h

0000h

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

04 = 29LV800 mode

Simultaneous Operation

Number of Sectors in all banks except boot block

Burst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

ACC (Acceleration) Supply Minimum

4Dh

4Eh

4Fh

00B5h

00C5h

00xxh

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

Top/Bottom Boot Sector Flag

02h = Bottom Boot Device, 03h = Top Boot Device

Program Suspend. 00h = not supported

Bank Organization: X = Number of banks

50h

57h

0000h

0004h

19

Am54BDS128AG

December 8, 2002

A D V A N C E I N F O R M A T I O N

Table 6. Primary Vendor-Specific Extended Query

Addresses

58h

Data

Description

0023h

0020h

0023h

Bank A Region Information. X = Number of sectors in bank

Bank B Region Information. X = Number of sectors in bank

Bank C Region Information. X = Number of sectors in bank

Bank D Region Information. X = Number of sectors in bank

59h

5Ah

5Bh

Table 7. Am29BDS640G Sector Address Table

Sector

SA0

Sector Size

8 Kwords

(x16) Address Range

000000h-001FFFh

002000h-003FFFh

004000h-005FFFh

006000h-007FFFh

008000h-00FFFFh

010000h-017FFFh

018000h-01FFFFh

020000h-027FFFh

028000h-02FFFFh

030000h-037FFFh

038000h-03FFFFh

040000h-047FFFh

048000h-04FFFFh

050000h-057FFFh

058000h-05FFFFh

060000h-067FFFh

068000h-06FFFFh

070000h-077FFFh

078000h-07FFFFh

080000h-087FFFh

088000h-08FFFFh

090000h-097FFFh

098000h-09FFFFh

0A0000h-0A7FFFh

0A8000h-0AFFFFh

0B0000h-0B7FFFh

0B8000h-0BFFFFh

0C0000h-0C7FFFh

0C8000h-0CFFFFh

0D0000h-0D7FFFh

0D8000h-0DFFFFh

0E0000h-0E7FFFh

0E8000h-0EFFFFh

0F0000h-0F7FFFh

0F8000h-0FFFFFh

SA1

8 Kwords

SA2

8 Kwords

SA3

8 Kwords

SA4

32 Kwords

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

Bank D

December 8, 2002

Am54BDS128AG

20

A D V A N C E I N F O R M A T I O N

Table 7. Am29BDS640G Sector Address Table

Sector

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

Sector Size

32 Kwords

(x16) Address Range

100000h-107FFFh

108000h-10FFFFh

110000h-117FFFh

118000h-11FFFFh

120000h-127FFFh

128000h-12FFFFh

130000h-137FFFh

138000h-13FFFFh

140000h-147FFFh

148000h-14FFFFh

150000h-157FFFh

158000h-15FFFFh

160000h-167FFFh

168000h-16FFFFh

170000h-177FFFh

178000h-17FFFFh

180000h-187FFFh

188000h-18FFFFh

190000h-197FFFh

198000h-19FFFFh

1A0000h-1A7FFFh

1A8000h-1AFFFFh

1B0000h-1B7FFFh

1B8000h-1BFFFFh

1C0000h-1C7FFFh

1C8000h-1CFFFFh

1D0000h-1D7FFFh

1D8000h-1DFFFFh

1E0000h-1E7FFFh

1E8000h-1EFFFFh

1F0000h-1F7FFFh

1F8000h-1FFFFFh

Bank C

21

Am54BDS128AG

December 8, 2002

A D V A N C E I N F O R M A T I O N

Table 7. Am29BDS640G Sector Address Table

Sector

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

Sector Size

32 Kwords

(x16) Address Range

200000h-207FFFh

208000h-20FFFFh

210000h-217FFFh

218000h-21FFFFh

220000h-227FFFh

228000h-22FFFFh

230000h-237FFFh

238000h-23FFFFh

240000h-247FFFh

248000h-24FFFFh

250000h-257FFFh

258000h-25FFFFh

260000h-267FFFh

268000h-26FFFFh

270000h-277FFFh

278000h-27FFFFh

280000h-287FFFh

288000h-28FFFFh

290000h-297FFFh

298000h-29FFFFh

2A0000h-2A7FFFh

2A8000h-2AFFFFh

2B0000h-2B7FFFh

2B8000h-2BFFFFh

2C0000h-2C7FFFh

2C8000h-2CFFFFh

2D0000h-2D7FFFh

2D8000h-2DFFFFh

2E0000h-2E7FFFh

2E8000h-2EFFFFh

2F0000h-2F7FFFh

2F8000h-2FFFFFh

Bank B

December 8, 2002

Am54BDS128AG

22

A D V A N C E I N F O R M A T I O N

Table 7. Am29BDS640G Sector Address Table

Sector

SA99

Sector Size

32K words

8K words

(x16) Address Range

300000h-307FFFh

308000h-30FFFFh

310000h-317FFFh

318000h-31FFFFh

320000h-327FFFh

328000h-32FFFFh

330000h-337FFFh

338000h-33FFFFh

340000h-347FFFh

348000h-34FFFFh

350000h-357FFFh

358000h-35FFFFh

360000h-367FFFh

368000h-36FFFFh

370000h-377FFFh

378000h-37FFFFh

380000h-387FFFh

388000h-38FFFFh

390000h-397FFFh

398000h-39FFFFh

3A0000h-3A7FFFh

3A8000h-3AFFFFh

3B0000h-3B7FFFh

3B8000h-3BFFFFh

3C0000h-3C7FFFh

3C8000h-3CFFFFh

3D0000h-3D7FFFh

3D8000h-3DFFFFh

3E0000h-3E7FFFh

3E8000h-3EFFFFh

3F0000h-3F7FFFh

3F8000h-3F9FFFh

3FA000h-3FBFFFh

3FC000h-3FDFFFh

3FE000h-3FFFFFh

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

SA130

SA131

SA132

SA133

Bank A

8K words

FLASH COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device op-

erations. Table 14, “Command Definitions,” on

page 31 defines the valid register command se-

quences. Writing incorrect address and data values or

writing them in the improper sequence resets the de-

vice to reading array data.

ready to read array data after completing an Embed-

ded Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command,

the corresponding bank enters the erase-sus-

pend-read mode, after which the system can read

data from any non-erase-suspended sector within the

same bank. After completing a programming operation

in the Erase Suspend mode, the system may once

again read array data with the same exception. See

the “Erase Suspend/Erase Resume Commands” sec-

tion on page 30 section for more information.

Refer to the AC Characteristics section for timing dia-

grams.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data in asynchronous mode. Each bank is

The system must issue the reset command to return a

bank to the read (or erase-suspend-read) mode if DQ5

23

Am54BDS128AG

December 8, 2002

A D V A N C E I N F O R M A T I O N

goes high during an active program or erase opera-

tion, or if the bank is in the autoselect mode. See the

“Reset Command” section on page 27 section for

more information.

Power-up/

Hardware Reset

See also “Requirements for Asynchronous Read Op-

eration (Non-Burst)” and “Requirements for Synchro-

nous (Burst) Read Operation” sections for more

information. The Asynchronous Read and Synchro-

nous/Burst Read tables provide the read parameters,

and Figures 11, 13, and 18 show the timings.

Asynchronous Read

Mode Only

Set Burst Mode Configuration Register

Command Sequence

Set Burst Mode

Configuration Register

Command for

Synchronous Mode

(A19 = 0)

Set Burst Mode

Configuration Register

Command for

Asynchronous Mode

(A19 = 1)

The device uses a burst mode configuration register to

set the various burst parameters: number of wait

states, burst read mode, active clock edge, RDY con-

figuration, and synchronous mode active. The burst

mode configuration register must be set before the de-

vice will enter burst mode.

Synchronous Read

Mode Only

The burst mode configuration register is loaded with a

three-cycle command sequence. The first two cycles

are standard unlock sequences. On the third cycle, the

data should be C0h, address bits A11–A0 should be

555h, and address bits A19–A12 set the code to be

latched. The device will power up or after a hardware

reset with the default setting, which is in asynchronous

mode. The register must be set before the device can

enter synchronous mode. The burst mode configura-

tion register can not be changed during device opera-

tions (program, erase, or sector lock).

Figure 1. Synchronous/Asynchronous State

Diagram

Read Mode Setting

On power-up or hardware reset, the device is set to be

in asynchronous read mode. This setting allows the

system to enable or disable burst mode during system

operations. Address A19 determines this setting: “1’

for asynchronous mode, “0” for synchronous mode.

Programmable Wait State Configuration

The programmable wait state feature informs the de-

vice of the number of clock cycles that must elapse

after AVD# is driven active before data will be avail-

able. This value is determined by the input frequency

of the device. Address bits A14–A12 determine the

setting (see Table 8).

The wait state command sequence instructs the de-

vice to set a particular number of clock cycles for the

initial access in burst mode. The number of wait states

that should be programmed into the device is directly

related to the clock frequency.

December 8, 2002

Am54BDS128AG

24

A D V A N C E I N F O R M A T I O N

Table 8. Programmable Wait State Settings

Total Initial Access

Cycles

A14

0

A13

0

A12

0

2

3

4

5

6

7

0

1

0

1

0

1

0

1

0

1

Notes:

1. Upon power-up or hardware reset, the default setting is seven wait states.

2. RDY will default to being active with data when the Wait

State Setting is set to a total initial access cycle of 2.

3. Assumes even address.

Standard Handshaking Operation

It is recommended that the wait state command se-

quence be written, even if the default wait state value

is desired, to ensure the device is set as expected. A

hardware reset will set the wait state to the default set-

ting.

For optimal burst mode performance on devices with

standard handshaking option, the host system must

set the appropriate number of wait states in the flash

device depending on the clock frequency.

Table 10 describes the typical number of clock cycles

(wait states) for various conditions with A14–A12 set

to 101.

Handshaking Option

If the device is equipped with the reduced wait-state

handshaking option, the host system should set ad-

dress bits A14–A12 to 010 for a clock frequency of 40

MHz or to 011 for a clock frequency of 54 MHz for the

system/device to execute at maximum speed.

Table 10. Wait States for Standard Handshaking

Typical No. of Clock

Cycles after AVD# Low

Conditions at Address

Initial address is even

Initial address is odd

40/54 MHz

7

Table 9 describes the typical number of clock cycles

(wait states) for various conditions.

Initial address is even,

and is at boundary crossing*

7

Table 9. Initial Access Codes

Initial address is odd,

and is at boundary crossing*

* In the 8-, 16- and 32-word burst read modes, the address

pointer does not cross 64-word boundaries (addresses

which are multiples of 3Fh).

System

Frequency

Range

Device

Speed

Rating

Burst Read Mode Configuration

6–11 MHz

2

3

4

5

2

3

4

5

6

3

4

5

6

7

4

5

6

7

8

The device supports four different burst read modes:

continuous mode, and 8, 16, and 32 word linear wrap

around modes. A continuous sequence begins at the

starting address and advances the address pointer

until the burst operation is complete. If the highest ad-

dress in the device is reached during the continuous

burst read mode, the address pointer wraps around to

the lowest address.

12–23 MHz

24–33 MHz

34–40 MHz

40–47 MHz

48–54 MHz

40 MHz

54 MHz

* In the 8-, 16- and 32-word burst read modes, the address

pointer does not cross 64-word boundaries (addresses

which are multiples of 3Fh).

For example, an eight-word linear burst with wrap

around begins on the starting burst address written to

the device and then proceeds until the next 8 word

boundary. The address pointer then returns to the first

word of the boundary, wrapping back to the starting lo-

cation. The sixteen- and thirty-two linear wrap around

The autoselect function allows the host system to de-

termine whether the flash device is enabled for re-

duced wait-state handshaking. See the “Autoselect

Command Sequence” section for more information.

25

Am54BDS128AG

December 8, 2002

A D V A N C E I N F O R M A T I O N

modes operate in a fashion similar to the eight-word

Burst Active Clock Edge Configuration

mode.

By default, the device will deliver data on the rising

edge of the clock after the initial synchronous access

time. Subsequent outputs will also be on the following

rising edges, barring any delays. The device can be

set so that the falling clock edge is active for all syn-

chronous accesses. Address bit A17 determines this

setting; “1” for rising active, “0” for falling active.

Table 11 shows the address bits and settings for the

four burst read modes.

Table 11. Burst Read Mode Settings

Address Bits

Burst Modes

A16

0

A15

0

Continuous

RDY Configuration

8-word linear wrap around

16-word linear wrap around

32-word linear wrap around

0

1

By default, the device is set so that the RDY pin will

output V_OHwhenever there is valid data on the out-

puts. The device can be set so that RDY goes active

one data cycle before active data. Address bit A18 de-

termines this setting; “1” for RDY active with data, “0”

for RDY active one clock cycle before valid data.

1

0

1

Note: Upon power-up or hardware reset the default setting

is continuous.

December 8, 2002

Am54BDS128AG

26

A D V A N C E I N F O R M A T I O N

Configuration Register

Table 12 shows the address bits that determine the

configuration register settings for various device func-

tions.

Table 12. Burst Mode Configuration Register

Settings (Binary)

Address BIt

Function

0 = Synchronous Read (Burst Mode) Enabled

1 = Asynchronous Mode (default)

A19

Set Device Read Mode

0 = RDY active one clock cycle before data

1 = RDY active with data (default)

A18

RDY

0 = Burst starts and data is output on the falling edge of CLK

1 = Burst starts and data is output on the rising edge of CLK (default)

A17

A16

Clock

00 = Continuous (default)

01 = 8-word linear with wrap around

10 = 16-word linear with wrap around

11 = 32-word linear with wrap around

Burst Read Mode

A15

A14

A13

000 = Data is valid on the 2nd active CLK edge after AVD# transition to V_IH

001 = Data is valid on the 3rd active CLK edge after AVD# transition to V_IH

010 = Data is valid on the 4th active CLK edge after AVD# transition to V_IH

011 = Data is valid on the 5th active CLK edge after AVD# transition to V_IH

100 = Data is valid on the 6th active CLK edge after AVD# transition to V_IH

101 = Data is valid on the 7th active CLK edge after AVD# transition to V_IH(default)

Programmable

Wait State

A12

Note:Device will be in the default state upon power-up or hardware reset.

fore programming begins (prior to the third cycle). This

Sector Lock/Unlock Command Sequence

resets the bank to which the system was writing to the

read mode. If the program command sequence is writ-

ten to a bank that is in the Erase Suspend mode, writ-

ing the reset command returns that bank to the

erase-suspend-read mode. Once programming be-

gins, however, the device ignores reset commands

until the operation is complete.

The sector lock/unlock command sequence allows the

system to determine which sectors are protected from

accidental writes. When the device is first powered up,

all sectors are locked. To unlock a sector, the system

must write the sector lock/unlock command sequence.

Two cycles are first written: addresses are don’t care

and data is 60h. During the third cycle, the sector ad-

dress (SLA) and unlock command (60h) is written,

while specifying with address A6 whether that sector

should be locked (A6 = V_IL) or unlocked (A6 = V_IH).

After the third cycle, the system can continue to lock or

unlock additional cycles, or exit the sequence by writ-

ing F0h (reset command).

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command

must be written to return to the read mode. If a bank

entered the autoselect mode while in the Erase Sus-

pend mode, writing the reset command returns that

bank to the erase-suspend-read mode.

Note that the last two outermost boot sectors can be

locked by taking the WP# signal to V_IL.

If DQ5 goes high during a program or erase operation,

writing the reset command returns the banks to the

read mode (or erase-suspend-read mode if that bank

was in Erase Suspend).

Reset Command

Writing the reset command resets the banks to the

read or erase-suspend-read mode. Address bits are

don’t cares for this command.

The reset command is used to exit the sector lock/un-

lock sequence.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the bank to which the sys-

tem was writing to the read mode. Once erasure be-

gins, however, the device ignores reset commands

until the operation is complete.

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and device codes,

and determine whether or not a sector is protected.

Table 14, “Command Definitions,” on page 31 shows

the address and data requirements. The autoselect

command sequence may be written to an address

The reset command may be written between the se-

quence cycles in a program command sequence be-

27

Am54BDS128AG

December 8, 2002

A D V A N C E I N F O R M A T I O N

within a bank that is either in the read or erase-sus-

Write Operation Status” section on page 32 section for

information on these status bits.

pend-read mode. The autoselect command may not

be written while the device is actively programming or

erasing in the other bank.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program

operation. The program command sequence should

be reinitiated once that bank has returned to the read

mode, to ensure data integrity.

The autoselect command sequence is initiated by first

writing two unlock cycles. This is followed by a third

write cycle that contains the bank address and the au-

toselect command. The bank then enters the autose-

lect mode. No subsequent data will be made available

if the autoselect data is read in synchronous mode.

The system may read at any address within the same

bank any number of times without initiating another

autoselect command sequence. The following table

describes the address requirements for the various

autoselect functions, and the resulting data. BA repre-

sents the bank address, and SA represents the sector

address. The device ID is read in three cycles.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed from

“0” back to a “1.” Attempting to do so may cause that

bank to set DQ5 = 1, or cause the DQ7 and DQ6 sta-

tus bit to indicate the operation was successful. How-

ever, a succeeding read will show that the data is still

“0.” Only erase operations can convert a “0” to a “1.”

Unlock Bypass Command Sequence

Table 13. Device IDs

The unlock bypass feature allows the system to prima-

rily program to a bank faster than using the standard

program command sequence. The unlock bypass

command sequence is initiated by first writing two un-

lock cycles. This is followed by a third write cycle con-

taining the unlock bypass command, 20h. That bank

then enters the unlock bypass mode. A two-cycle un-

lock bypass program command sequence is all that is

required to program in this mode. The first cycle in this

sequence contains the unlock bypass program com-

mand, A0h; the second cycle contains the program

address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial

two unlock cycles required in the standard program

command sequence, resulting in faster total program-

ming time. The host system may also initiate the chip

erase and sector erase sequences in the unlock by-

pass mode. The erase command sequences are four

cycles in length instead of six cycles. Table 14, “Com-

mand Definitions,” on page 31 shows the require-

ments for the unlock bypass command sequences.

Description

Manufacturer ID

Device ID, Word 1

Address

(BA) + 00h

(BA) + 01h

Read Data

0001h

227Eh

Device ID, Word 2,

Top Boot

(BA) + 0Eh

2204h (1.8 V V_IO)

Device ID, Word 2,

Bottom Boot

(BA) + 0Eh

(BA) + 0Fh

(SA) + 02h

2224h (1.8 V V_IO)

2201h

Device ID, Word 3

Sector Block

Lock/Unlock

0001 (locked),

0000 (unlocked)

43h (reduced

wait-state),

Handshaking

(BA) + 03h

42h (standard)

The system must write the reset command to return to

the read mode (or erase-suspend-read mode if the

bank was previously in Erase Suspend).

Program Command Sequence

During the unlock bypass mode, only the Unlock By-

pass Program, Unlock Bypass Sector Erase, Unlock

Bypass Chip Erase, and Unlock Bypass Reset com-

mands are valid. To exit the unlock bypass mode, the

system must issue the two-cycle unlock bypass reset

command sequence. The first cycle must contain the

bank address and the data 90h. The second cycle

need only contain the data 00h. The bank then returns

to the read mode.

Programming is a four-bus-cycle operation. The pro-

gram command sequence is initiated by writing two

unlock write cycles, followed by the program set-up

command. The program address and data are written

next, which in turn initiate the Embedded Program al-

gorithm. The system is not required to provide further

controls or timings. The device automatically provides

internally generated program pulses and verifies the

programmed cell margin. Table 14 shows the address

and data requirements for the program command se-

quence.

The device offers accelerated program operations

through the ACC input. When the system asserts V_ID

on this input, the device automatically enters the Un-

lock Bypass mode. The system may then write the

two-cycle Unlock Bypass program command se-

quence. The device uses the higher voltage on the

ACC input to accelerate the operation.

When the Embedded Program algorithm is complete,

that bank then returns to the read mode and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by

monitoring DQ7 or DQ6/DQ2. Refer to the “Flash

December 8, 2002

Am54BDS128AG

28

A D V A N C E I N F O R M A T I O N

Figure 2 illustrates the algorithm for the program oper-

no longer latched. The system can determine the sta-

tus of the erase operation by using DQ7 or DQ6/DQ2.

Refer to the “Flash Write Operation Status” section on

page 32 section for information on these status bits.

ation. Refer to the Erase/Program Operations table in

the AC Characteristics section for parameters, and

Figure 21, “Asynchronous Program Operation Tim-

ings,” on page 52 for timing diagrams.

Any commands written during the chip erase operation

are ignored. However, note that a hardware reset im-

mediately terminates the erase operation. If that oc-

curs, the chip erase command sequence should be

reinitiated once that bank has returned to reading

array data, to ensure data integrity.

START

The host system may also initiate the chip erase com-

mand sequence while the device is in the unlock by-

pass mode. The command sequence is two cycles

cycles in length instead of six cycles. See Table 14 for

details on the unlock bypass command sequences.

Write Erase

Command Sequence

Data Poll

from System

Embedded

Figure 2 illustrates the algorithm for the erase opera-

tion. Refer to the Erase/Program Operations table in

the AC Characteristics section for parameters and tim-

ing diagrams.

Erase

algorithm

in progress

Sector Erase Command Sequence

No

Data = FFh?

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two ad-

ditional unlock cycles are written, and are then fol-

lowed by the address of the sector to be erased, and

the sector erase command. Table 14 shows the ad-

dress and data requirements for the sector erase com-

mand sequence.

Yes

Erasure Completed

Notes:

The device does not require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-

matically programs and verifies the entire memory for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

1. See Table 14 for erase command sequence.

2. See the section on DQ3 for information on the sector

erase timer.

Figure 2. Erase Operation

After the command sequence is written, a sector erase

time-out of no less than 35 µs occurs. During the

time-out period, additional sector addresses and sec-

tor erase commands may be written. Loading the sec-

tor erase buffer may be done in any sequence, and

the number of sectors may be from one sector to all

sectors. The time between these additional cycles

must be less than 50 µs, otherwise erasure may begin.

Any sector erase address and command following the

exceeded time-out may or may not be accepted. It is

recommended that processor interrupts be disabled

during this time to ensure all commands are accepted.

The interrupts can be re-enabled after the last Sector

Erase command is written. Any command other than

Sector Erase or Erase Suspend during the time-out

period resets that bank to the read mode. The system

must rewrite the command sequence and any addi-

tional addresses and commands.

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 14,

“Command Definitions,” on page 31 shows the ad-

dress and data requirements for the chip erase com-

mand sequence.

When the Embedded Erase algorithm is complete,

that bank returns to the read mode and addresses are

29

Am54BDS128AG

December 8, 2002

A D V A N C E I N F O R M A T I O N

The system can monitor DQ3 to determine if the sec-

any address within erase-suspended sectors pro-

duces status information on DQ7–DQ0. The system

can use DQ7, or DQ6 and DQ2 together, to determine

if a sector is actively erasing or is erase-suspended.

Refer to the Write Operation Status section for infor-

mation on these status bits.

tor erase timer has timed out (See “DQ3: Sector Erase

Timer” section on page 34.). The time-out begins from

the rising edge of the final WE# pulse in the command

sequence.

When the Embedded Erase algorithm is complete, the

bank returns to reading array data and addresses are

no longer latched. Note that while the Embedded

Erase operation is in progress, the system can read

data from the non-erasing bank. The system can de-

termine the status of the erase operation by reading

DQ7 or DQ6/DQ2 in the erasing bank. Refer to the

“Flash Write Operation Status” section on page 32

section for information on these status bits.

After an erase-suspended program operation is com-

plete, the bank returns to the erase-suspend-read

mode. The system can determine the status of the

program operation using the DQ7 or DQ6 status bits,

just as in the standard program operation. Refer to the

“Flash Write Operation Status” section on page 32

section for more information.

In the erase-suspend-read mode, the system can also

issue the autoselect command sequence. Refer to the

“Autoselect Functions” section on page 16 and “Au-

toselect Command Sequence” section on page 27

sections for details.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other com-

mands are ignored. However, note that a hardware

reset immediately terminates the erase operation. If

that occurs, the sector erase command sequence

should be reinitiated once that bank has returned to

reading array data, to ensure data integrity.

To resume the sector erase operation, the system

must write the Erase Resume command. The bank

address of the erase-suspended bank is required

when writing this command. Further writes of the Re-

sume command are ignored. Another Erase Suspend

command can be written after the chip has resumed

erasing.

The host system may also initiate the sector erase

command sequence while the device is in the unlock

bypass mode. The command sequence is four cycles

cycles in length instead of six cycles.

Figure 2 illustrates the algorithm for the erase opera-

tion. Refer to the Erase/Program Operations table in

the AC Characteristics section for parameters and tim-

ing diagrams.

START

Erase Suspend/Erase Resume

Commands

Write Program

Command Sequence

The Erase Suspend command, B0h, allows the sys-

tem to interrupt a sector erase operation and then read

data from, or program data to, any sector not selected

for erasure. The bank address is required when writing

this command. This command is valid only during the

sector erase operation, including the minimum 50 µs

time-out period during the sector erase command se-

quence. The Erase Suspend command is ignored if

written during the chip erase operation or Embedded

Program algorithm.

Data Poll

from System

Embedded

Program

algorithm

in progress

Verify Data?

No

Yes

When the Erase Suspend command is written during

the sector erase operation, the device requires a max-

imum of 35 µs to suspend the erase operation. How-

ever, when the Erase Suspend command is written

during the sector erase time-out, the device immedi-

ately terminates the time-out period and suspends the

erase operation.

No

Increment Address

Last Address?

Yes

Programming

Completed

After the erase operation has been suspended, the

bank enters the erase-suspend-read mode. The sys-

tem can read data from or program data to any sector

not selected for erasure. (The device “erase sus-

pends” all sectors selected for erasure.) Reading at

Note: See Table 14 for program command sequence.

December 8, 2002

Am54BDS128AG

30

A D V A N C E I N F O R M A T I O N

Figure 3. Program Operation

Command Definitions

Table 14. Command Definitions

Bus Cycles (Notes 1–5)

Third Fourth

Addr Data

Command Sequence

(Notes)

First

Second

Fifth

Sixth

Addr Data Addr Data

Addr

Data

Addr Data

Asynchronous Read (6)

Reset (7)

1

4

RA

XXX

555

RD

F0

Manufacturer ID

AA

2AA

55 (BA)555 90

(BA)X00

(BA)X01

0001

227E

(BA)X

(Note 9)

0E

(BA)

2201

X0F

Device ID (9)

6

555

AA

Sector Lock Verify (10)

Handshaking Option (11)

Program

4

3

2

6

1

3

555

XXX

BA

AA

A0

80

2AA

PA

55 (SA)555 90

55 (BA)555 90

(SA)X02 0000/0001

(BA)X03 0042/0043

55

PD

30

10

00

55

555

A0

20

PA

PD

Unlock Bypass

Unlock Bypass Program (12)

Unlock Bypass Sector Erase (12)

Unlock Bypass Chip Erase (12)

Unlock Bypass Reset (13)

Chip Erase

SA

80

XXX

2AA

90

555

BA

AA

B0

30

555

80

555

AA

2AA

55

555

SA

10

30

Sector Erase

Erase Suspend (14)

Erase Resume (15)

Sector Lock/Unlock

BA

XXX

60

XXX

2AA

60

SLA

60

Set Burst Mode

Configuration Register (16)

3

1

555

55

AA

98

55 (CR)555 C0

CFI Query (17)

Legend:

X = Don’t care

SA = Address of the sector to be verified (in autoselect mode) or

erased. Address bits A21–A14 uniquely select any sector.

BA = Address of the bank (A21, A20) that is being switched to

autoselect mode, is in bypass mode, or is being erased.

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses

latch on the rising edge of the AVD# pulse.

SLA = Address of the sector to be locked. Set sector address (SA) and

either A6 = 1 for unlocked or A6 = 0 for locked.

PD = Data to be programmed at location PA. Data latches on the rising

edge of WE# pulse.

CR = Configuration Register address bits A19–A12.

Notes:

1. See Table 1 for description of bus operations.

10. The data is 0000h for an unlocked sector and 0001h for a locked

sector

2. All values are in hexadecimal.

11. The data is 0043h for reduced wait-state handshaking and 0042h

for standard handshaking.

3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

12. The Unlock Bypass command sequence is required prior to this

command sequence.

4. Data bits DQ15–DQ8 are don’t care in command sequences,

except for RD and PD.

13. The Unlock Bypass Reset command is required to return to

reading array data when the bank is in the unlock bypass mode.

5. Unless otherwise noted, address bits A21–A12 are don’t cares.

6. No unlock or command cycles required when bank is reading

array data.

14. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase

operation, and requires the bank address.

7. The Reset command is required to return to reading array data

(or to the erase-suspend-read mode if previously in Erase

Suspend) when a bank is in the autoselect mode, or if DQ5 goes

high (while the bank is providing status information) or performing

sector lock/unlock.

15. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

16. See “Set Burst Mode Configuration Register Command

Sequence” for details.

8. The fourth cycle of the autoselect command sequence is a read

cycle. The system must provide the bank address. See the

Autoselect Command Sequence section for more information.

17. Command is valid when device is ready to read array data or when

device is in autoselect mode.

9. The data in the fifth cycle is 2204h for top boot, 2224h for bottom

boot.

31

Am54BDS128AG

December 8, 2002

A D V A N C E I N F O R M A T I O N

FLASH WRITE OPERATION STATUS

The device provides several bits to determine the sta-

tus of a program or erase operation: DQ2, DQ3, DQ5,

DQ6, and DQ7. Table 16, “Write Operation Status,” on

page 35 and the following subsections describe the

function of these bits. DQ7 and DQ6 each offers a

method for determining whether a program or erase

operation is complete or in progress.

status information to valid data on DQ7. Depending on

when the system samples the DQ7 output, it may read

the status or valid data. Even if the device has com-

pleted the program or erase operation and DQ7 has

valid data, the data outputs on DQ6–DQ0 may be still

invalid. Valid data on DQ7–DQ0 will appear on suc-

cessive read cycles.

Table 16 shows the outputs for Data# Polling on DQ7.

Figure 3 shows the Data# Polling algorithm. Figure 27,

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host sys-

tem whether an Embedded Program or Erase algo-

rithm is in progress or completed, or whether a bank is

in Erase Suspend. Data# Polling is valid after the ris-

ing edge of the final WE# pulse in the command se-

quence.

“Data#

Polling

Timings

(During Embedded Algorithm),” on page 58 in the AC

Characteristics section shows the Data# Polling timing

diagram.

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to pro-

gramming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active for

approximately 1 µs, then that bank returns to the read

mode.

START

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the bank enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

The system must provide an address within any of the

sectors selected for erasure to read valid status infor-

mation on DQ7.

No

DQ5 = 1?

Yes

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data# Poll-

ing on DQ7 is active for approximately 100 µs, then

the bank returns to the read mode. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected. However, if the sys-

tem reads DQ7 at an address within a protected

sector, the status may not be valid.

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

No

Just prior to the completion of an Embedded Program

or Erase operation, DQ7 may change asynchronously

with DQ6–DQ0 while Output Enable (OE#) is asserted

low. That is, the device may change from providing

PASS

FAIL

Notes:

1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the

sector being erased. During chip erase, a valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

Figure 4. Data# Polling Algorithm

December 8, 2002

Am54BDS128AG

32

A D V A N C E I N F O R M A T I O N

Figure 28, “Toggle

Bit

Timings

RDY: Ready

(During Embedded Algorithm),” on page 58 (toggle bit

timing diagram), and Table 15, “DQ6 and DQ2 Indica-

tions,” on page 34.

The RDY is a dedicated output that, by default, indi-

cates (when at logic low) the system should wait 1

clock cycle before expecting the next word of data.

Using the RDY Configuration Command Sequence,

RDY can be set so that a logic low indicates the sys-

tem should wait 2 clock cycles before expecting valid

data.

START

RDY functions only while reading data in burst mode.

The following conditions cause the RDY output to be

low: during the initial access (in burst mode), and after

the boundary that occurs every 64 words beginning

with the 64th address, 3Fh.

Read Byte

(DQ7–DQ0)

Address = VA

Read Byte

(DQ7–DQ0)

Address = VA

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or com-

plete, or whether the device has entered the Erase

Suspend mode. Toggle Bit I may be read at any ad-

dress in the same bank, and is valid after the rising

edge of the final WE# pulse in the command sequence

(prior to the program or erase operation), and during

the sector erase time-out.

No

DQ6 = Toggle?

Yes

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. When the operation is complete, DQ6

stops toggling.

No

DQ5 = 1?

Yes

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6 tog-

gles for approximately 100 µs, then returns to reading

array data. If not all selected sectors are protected, the

Embedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are pro-

tected.

Read Byte Twice

(DQ7–DQ0)

Adrdess = VA

No

DQ6 = Toggle?

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is

erase-suspended. When the device is actively erasing

(that is, the Embedded Erase algorithm is in progress),

DQ6 toggles. When the device enters the Erase Sus-

pend mode, DQ6 stops toggling. However, the system

must also use DQ2 to determine which sectors are

erasing or erase-suspended. Alternatively, the system

can use DQ7 (see the subsection on DQ7: Data# Poll-

ing).

Yes

FAIL

PASS

Note: The system should recheck the toggle bit even if DQ5

= “1” because the toggle bit may stop toggling as DQ5

changes to “1.” See the subsections on DQ6 and DQ2 for

more information.

If a program address falls within a protected sector,

DQ6 toggles for approximately 1 ms after the program

command sequence is written, then returns to reading

array data.

Figure 5. Toggle Bit Algorithm

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

See the following for additional information: Figure 4

(toggle bit flowchart), DQ6: Toggle Bit I (description),

33

Am54BDS128AG

December 8, 2002

A D V A N C E I N F O R M A T I O N

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

which sectors are selected for erasure. Thus, both sta-

tus bits are required for sector and mode information.

Refer to Table 15 to compare outputs for DQ2 and

DQ6.

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. But DQ2 cannot distinguish whether the sector is

actively erasing or is erase-suspended. DQ6, by com-

parison, indicates whether the device is actively eras-

ing, or is in Erase Suspend, but cannot distinguish

See the following for additional information: Figure 5,

“Toggle Bit Algorithm,” on page 33, See “DQ6: Toggle

Bit I” on page 33., Figure 28, “Toggle Bit Timings

(During Embedded Algorithm),” on page 58, and

Table 15, “DQ6 and DQ2 Indications,” on page 34.

Table 15. DQ6 and DQ2 Indications

and the system reads then DQ6

If device is

and DQ2

programming,

at any address,

toggles,

does not toggle.

at an address within a sector

selected for erasure,

toggles,

also toggles.

does not toggle.

toggles.

actively erasing,

at an address within sectors not

toggles,

does not toggle,

returns array data,

toggles,

selected for erasure,

at an address within a sector

selected for erasure,

erase suspended,

at an address within sectors not

returns array data. The system can read

from any sector not selected for erasure.

selected for erasure,

programming in

erase suspend

at any address,

is not applicable.

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to de-

termine the status of the operation (top of Figure 4).

Reading Toggle Bits DQ6/DQ2

Refer to Figure 4 for the following discussion. When-

ever the system initially begins reading toggle bit sta-

tus, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically,

the system would note and store the value of the tog-

gle bit after the first read. After the second read, the

system would compare the new value of the toggle bit

with the first. If the toggle bit is not toggling, the device

has completed the program or erase operation. The

system can read array data on DQ7–DQ0 on the fol-

lowing read cycle.

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1,” indicating that

the program or erase cycle was not successfully com-

pleted.

The device may output a “1” on DQ5 if the system tries

to program a “1” to a location that was previously pro-

grammed to “0.” Only an erase operation can change

a “0” back to a “1.” Under this condition, the device

halts the operation, and when the timing limit has been

exceeded, DQ5 produces a “1.”

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should

then determine again whether the toggle bit is tog-

gling, since the toggle bit may have stopped toggling

just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the de-

vice did not completed the operation successfully, and

the system must write the reset command to return to

reading array data.

Under both these conditions, the system must write

the reset command to return to the read mode (or to

the erase-suspend-read mode if a bank was previ-

ously in the erase-suspend-program mode).

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not

erasure has begun. (The sector erase timer does not

apply to the chip erase command.) If additional sec-

tors are selected for erasure, the entire time-out also

applies after each additional sector erase command.

When the time-out period is complete, DQ3 switches

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor

the toggle bit and DQ5 through successive read cy-

cles, determining the status as described in the previ-

ous paragraph. Alternatively, it may choose to perform

December 8, 2002

Am54BDS128AG

34

A D V A N C E I N F O R M A T I O N

from a “0” to a “1.” If the time between additional sec-

ther commands (except Erase Suspend) are ignored

until the erase operation is complete. If DQ3 is “0,” the

device will accept additional sector erase commands.

To ensure the command has been accepted, the sys-

tem software should check the status of DQ3 prior to

and following each subsequent sector erase com-

mand. If DQ3 is high on the second status check, the

last command might not have been accepted.

tor erase commands from the system can be assumed

to be less than 50 µs, the system need not monitor

DQ3. See also the Sector Erase Command Sequence

section.

After the sector erase command is written, the system

should read the status of DQ7 (Data# Polling) or DQ6

(Toggle Bit I) to ensure that the device has accepted

the command sequence, and then read DQ3. If DQ3 is

“1,” the Embedded Erase algorithm has begun; all fur-

Table 16 shows the status of DQ3 relative to the other

status bits.

Table 16. Write Operation Status

DQ7

DQ5

DQ2

Status

(Note 2)

DQ6

(Note 1)

DQ3

N/A

1

(Note 2)

Embedded Program Algorithm

Embedded Erase Algorithm

Erase

Erase-Suspend-

Read (Note 4)

DQ7#

0

Toggle

0

No toggle

Toggle

Standard

Mode

1

No toggle

0

N/A

Toggle

Suspended Sector

Erase

Suspend

Mode

Non-EraseSuspended

Sector

Data

0

Data

N/A

Data

N/A

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status

information. Refer to the appropriate subsection for further

details.

3. When reading write operation status bits, the system must

always provide the bank address where the Embedded

Algorithm is in progress. The device outputs array data if

the system addresses a non-busy bank.

4. The system may read either asynchronously or synchronously (burst) while in erase suspend. RDY will function exactly as in

non-erase-suspended mode.

35

Am54BDS128AG

December 8, 2002

A D V A N C E I N F O R M A T I O N

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

20 ns

Ambient Temperature

with Power Applied . . . . . . . . . . . . . –65°C to +125°C

+0.8 V

Voltage with Respect to Ground:

All Inputs and I/Os except

as noted below (Note 1). . . . . . . –0.5 V to V_IO+ 0.5 V

–0.5 V

–2.0 V

V_CCf/V_CCs (Note 1) . . . . . . . . . . . . . . .–0.5 V to +2.5 V

V_IO. . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +1.95 V

ACC . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V

Output Short Circuit Current (Note 3) . . . . . . 100 mA

Notes:

20 ns

Figure 6. Maximum Negative

Overshoot Waveform

1. Minimum DC voltage on input or I/Os is –0.5 V. During

voltage transitions, inputs or I/Os may undershoot V_SSto

–2.0 V for periods of up to 20 ns during voltage

transitions inputs might overshoot to V_CC+0.5 V for

periods up to 20 ns. See Figure 6. Maximum DC voltage

on input or I/Os is V_CC+ 0.5 V. During voltage transitions

outputs may overshoot to V_CC+ 2.0 V for periods up to

20 ns. See Figure 7.

20 ns

V_CC

+2.0 V

V_CC

+0.5 V

2. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater than

one second.

1.0 V

3. Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This

is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device

reliability.

20 ns

Figure 7. Maximum Positive

Overshoot Waveform

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T_A) . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature (T_A) . . . . . . . . . –40°C to +85°C

Supply Voltages

V_CCSupply Voltages . . . . . . . . . . .+1.65 V to +1.95 V

V_IOSupply Voltages:

V_IO≤ V_CC. . . . . . . . . . . . . . . . . . . +1.65 V to +1.95 V

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

December 8, 2002

Am54BDS128AG

36

A D V A N C E I N F O R M A T I O N

FLASH DC CHARACTERISTICS

CMOS Compatible

Parameter Description

Test Conditions (Note 1)

Min

Typ

Max

±1

Unit

µA

I_LI

I_LO

Input Load Current

V_IN= V_SSto V_CC, V_CC= V_CCmax

V_OUT= V_SSto V_CC, V_CC= V_CCmax

CE#f = V_IL, OE# = V_IL, WE# = V_IH

Output Leakage Current

±1

µA

I_CCB

V_CCActive Burst Read Current

10

15

20

mA

V_IO= 1.8 V, CE#f = V_IL, OE# = V_IL,

WE# = V_IH

I_IO1

I_IO2

I_CC1

V_IOActive Read Current

30

mA

V_IONon-active Output

V_IO= 1.8 V, OE# = V_IH

0.4

12

10

16

5

µA

mA

5 MHz

1 MHz

V_CCActive Asynchronous Read

Current (Note 2)

CE#f = V_IL, OE# = V_IH,

WE# = V_IH

3.5

CE#1F=CE#2f = V_IL, OE# = V_IH,

V_PP= V_IH

I_CC2

V_CCActive Write Current (Note 3)

15

40

mA

CE#1f=CE#2f = RESET# = V_CC

0.2 V

±

I_CC3

I_CC4

I_CC5

V_CCStandby Current (Note 4)

V_CCReset Current

0.4

25

10

60

µA

RESET# = V_IL,CLK = V_IL

V_CCActive Current

(Read While Write)

CE#f= V_IL, OE# = V_IH

mA

V_ACC

V_CC

7

5

15

10

mA

V

Accelerated Program Current

(Note 5)

CE#f = V_IL, OE# = V_IH,

V_ACC= 12.0 ± 0.5 V

I_ACC

V_IL

Input Low Voltage

Input High Voltage

V_IO= 1.8 V

–0.5

0.2

V_IH

V_IO– 0.2

V_IO+ 0.2

V

I_OL= 100 µA, V_CC= V_{CC min}

V_IO= V_{IO min}

,

V_OL

V_OH

Output Low Voltage

Output High Voltage

0.1

V

I_OH= –100 µA, V_CC= V_{CC min}

V_IO= V_{IO min}

,

V_IO– 0.1

V_ID

Voltage for Accelerated Program

Low V_CCLock-out Voltage

11.5

1.0

12.5

1.4

V

V_LKO

Note:

1. Maximum I_CCspecifications are tested with V_CC= V_CCmax.

2. The I_CCcurrent listed is typically less than 2 mA/MHz, with OE# at V_IH.

3. I_CCactive while Embedded Erase or Embedded Program is in progress.

4. Device enters automatic sleep mode when addresses are stable for t_ACC+ 60 ns. Typical sleep mode current is equal to I_CC3

5. Total current during accelerated programming is the sum of V_ACCand V_CCcurrents.

6. CE#f refers to active flash.

.

37

Am54BDS128AG

December 8, 2002

A D V A N C E I N F O R M A T I O N

Parameter

Symbol

Parameter Description

Test Conditions

V_IN= V_SSto V_CC

Min

Typ

Max

Unit

I_LI

Input Leakage Current

–1.0

1.0

µA

CE1#s = V_IH, CE2s = V_ILor OE# =

V_IHor WE# = V_IL, V_IO= V_SSto V_CC

I_LO

Output Leakage Current

–1.0

1.0

5

µA

I_IO= 0 mA, CE1#s = V_IL, CE2s =

WE# = V_IH, V_IN= V_IHor V_IL

I_CC

Operating Power Supply Current

Average Operating Current

mA

Cycle time = 1 µs, 100% duty,

I_IO= 0 mA, CE1#s ≤ 0.2 V,

CE2 ≥ V_CC– 0.2 V, V_IN≤ 0.2 V or

I

_CC1s

1

8

3

mA

V_IN≥ V_CC– 0.2 V

Cycle time = Min., I_IO= 0 mA, 100%

duty, CE1#s = V_IL, CE2s = V_IH, V_IN

= V_IL= or V_IH

_CC2s

Average Operating Current

25

mA

V_OL

V_OH

Output Low Voltage

Output High Voltage

I_OL= 0.1 mA

0.2

V

I_OH= –0.1 mA

1.4

CE1#s ≥ V_CC– 0.2 V, CE2 ≥ V_CC

–

0.2 V (CE1#s controlled) or CE2 ≤

0.2 V (CE2s controlled), CIOs =

V_SSor V_CC, Other input = 0 ~ V_CC

I_SB1

Standby Current (CMOS)

15

µA

–0.2

(Note 2)

V_IL

V_IH

Input Low Voltage

Input High Voltage

0.4

V

V_CC+0.2

(Note 3)

1.4

Notes:

1. Typical values measured at V_CC= 2.0 V, T_A= 25°C. Not 100% tested.

2. Undershoot is –1.0 V when pulse width ≤ 20 ns.

3. Overshoot is V_CC+ 1.0 V when pulse width ≤ 20 ns.

4. Overshoot and undershoot are sampled, not 100% tested.

December 8, 2002

Am54BDS128AG

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A D V A N C E I N F O R M A T I O N

Table 17. Test Specifications

TEST CONDITIONS

All speed

options

Test Condition

Output Load

Unit

1 TTL gate

Output Load Capacitance, C_L

(including jig capacitance)

30

pF

Device

Under

Test

Input Rise and Fall Times

Input Pulse Levels

5

ns

V

0.0–V_IO

Input timing measurement reference

levels

C

V_IO/2

V

L

Output timing measurement

reference levels

Figure 8. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

3.0 V

1.5 V

Input

Measurement Level

Output

0.0 V

Figure 9. Input Waveforms and Measurement Levels

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Am54BDS128AG

December 8, 2002

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

SRAM CE#s Timing

Parameter

JEDEC

Std

Description

Test Setup

AllSpeeds

Unit

—

t_CCR

CE#s Recover Time

—

Min

0

ns

CE#f

t_CCR

CE1#s

CE2s

t_CCR

Figure 10. Timing Diagram for Alternating

Between SRAM and Flash

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A D V A N C E I N F O R M A T I O N

FLASH AC CHARACTERISTICS

Synchronous/Burst Read

Parameter

D8

C8

Description

(54 MHz)

(40 MHz)

Unit

JEDEC

Standard

Latency (Even Address in Reduced Wait-State

Handshake Mode)

t_IACC

Max

87.5

95

ns

Parameter

D8, D9

(54 MHz)

C8, C9

(40 MHz)

Description

Unit

JEDEC

Standard

Latency—(Odd Address in Handshaking mode or

Standard Handshaking)

t_IACC

106

120

20

ns

t_BACC

t_ACS

t_ACH

t_BDH

t_OE

Burst Access Time Valid Clock to Output Delay

Address Setup Time to CLK (Note 1)

Address Hold Time from CLK (Note 1)

Data Hold Time from Next Clock Cycle

Output Enable to Output Valid

Chip Enable to High Z

Max

Min

Max

Min

Max

Min

Max

13.5

ns

5

7

4

13.5

20

t_CEZ

t_OEZ

t_CES

t_RDYS

t_RACC

t_AAS

t_AAH

t_CAS

t_AVC

t_AVD

t_ACC

10

5

Output Enable to High Z

CE# Setup Time to CLK

RDY Setup Time to CLK

5

Ready Access Time from CLK

Address Setup Time to AVD# (Note 1)

Address Hold Time to AVD# (Note 1)

CE# Setup Time to AVD#

5

7

0

AVD# Low to CLK

5

AVD# Pulse

12

70

Access Time

Note:

1. Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#.

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A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

7 cycles for initial access shown.

t_CEZ

t_CES

CE#f

1

2

3

4

5

6

7

CLK

t_AVC

AVD#

t_AVD

t_ACS

t_BDH

A21-A0

Aa

t_BACC

t_ACH

Hi-Z

DQ15-DQ0

t_IACC

t_ACC

Da

Da + 1

Da + n

t_OEZ

OE#

RDY

t_RACC

t_OE

Hi-Z

t_RDYS

Notes:

1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two

cycles to seven cycles.

2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.

3. The device is in synchronous mode.

4. CE#f refers to active flash die.

Figure 11. CLK Synchronous Burst Mode Read

(rising active CLK)

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A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

4 cycles for initial access shown.

t_CEZ

t_CES

CE#f

CLK

1

2

3

4

5

t_AVC

AVD#

t_AVD

t_ACS

t_BDH

Aa

A21-A0

t_BACC

t_ACH

Hi-Z

DQ15-DQ0

t_IACC

Da

Da + 1

Da + n

t_ACC

t_OEZ

OE#

RDY

t_RACC

t_OE

Hi-Z

t_RDYS

Notes:

1. Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from two

cycles to seven cycles. Clock is set for active falling edge.

2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.

3. The device is in synchronous mode.

4. CE#f refers to active flash die.

Figure 12. CLK Synchronous Burst Mode Read

(Falling Active Clock)

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A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

7 cycles for initial access shown.

t_CEZ

t_CAS

f

CE#

CLK

1

2

3

4

5

6

7

t_AVC

AVD#

t_AVD

t_AAS

t_BDH

A21-A0

Aa

t_BACC

t_AAH

Hi-Z

DQ15

-

DQ0

t_IACC

Da

Da + 1

Da + n

t_ACC

t_OEZ

OE#

RDY

t_RACC

t_OE

Hi-Z

t_RDYS

Notes:

1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two

cycles to seven cycles. Clock is set for active rising edge.

2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.

3. The device is in synchronous mode.

4. CE#f refers to active flash die.

Figure 13. Synchronous Burst Mode Read

7

cycles for initial access shown.

18.5 ns typ. (54 MHz)

t_CES

CE#f

CLK

1

2

3

4

5

6

7

t_AVDS

AVD#

t_AVD

t_ACS

t_BDH

Aa

A21-A0

t_BACC

t_ACH

DQ15-DQ0

t_IACC

t_ACC

D6

D7

D0

D1

D5

D6

OE#

RDY

t_RACC

t_OE

Hi-Z

t_RDYS

Note: Figure assumes 7 wait states for initial access, 54 MHz clock, and automatic detect synchronous read. D0–D7 in data

waveform indicate the order of data within a given 8-word address range, from lowest to highest. Data will wrap around within

the 8 words non-stop unless the RESET# is asserted low, or AVD# latches in another address. Starting address in figure is the

7th address in range (A6). See “Requirements for Synchronous (Burst) Read Operation”. The Set Configuration Register

command sequence has been written with A18=1; device will output RDY with valid data. CE#f refers to active flash die.

Figure 14. 8-word Linear Burst with Wrap Around

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Am54BDS128AG

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A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

6

wait cycles for initial access shown.

25 ns typ. (40 MHz)

t_CEZ

t_CES

CE#f

1

2

3

4

5

6

CLK

t_AVDS

AVD#

t_AVD

t_ACS

t_BDH

Aa

A21-A0

t_BACC

t_ACH

Hi-Z

DQ15

-

DQ0

t_IACC

D0

D1

D2

D3

Da + n

t_ACC

t_OEZ

t_RACC

OE#

RDY

t_OE

Hi-Z

t_RDYS

Note: Figure assumes 6 wait states for initial access, 40 MHz clock, and synchronous read. The Set Configuration Register

command sequence has been written with A18=0; device will output RDY one cycle before valid data. CE#f refers to active flash

die.

Figure 15. Burst with RDY Set One Cycle Before Data

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December 8, 2002

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

7 cycles for initial access shown.

t_CEZ

t_CAS

CE#f

1

2

3

4

5

6

7

CLK

t_AVC

AVD#

t_AVD

t_AAS

t_BDH

A21-A0

Aa

t_BACC

t_AAH

Hi-Z

DQ15-DQ0

t_IACC

Da

Da + 1

Da + n

t_ACC

t_OEZ

OE#

RDY

t_RACC

t_OE

Hi-Z

t_RDYS

Notes:

1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two

cycles to seven cycles. Clock is set for active rising edge.

2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.

3. The device is in synchronous mode.

4. This waveform represents a synchronous burst mode, the device will also operate in reduced wait-state handshaking under a

CLK synchronous burst mode.

5. CE#f refers to active flash die.

Figure 16. Reduced Wait-State Handshaking Burst Mode Read

Starting at an Even Address

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Am54BDS128AG

46

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

7 cycles for initial access shown.

t_CEZ

t_CAS

CE#f

1

2

3

4

5

6

7

8

CLK

t_AVC

AVD#

t_AVD

t_AAS

t_BDH

Aa

A21-A0

t_BACC

t_AAH

Hi-Z

DQ15

-DQ0

Da

Da + 1

Da + n

t_IACC

t_ACC

t_OEZ

OE#

RDY

t_RACC

t_OE

Hi-Z

t_RDYS

Figure 17. Reduced Wait-State Handshaking Burst Mode Read

Starting at an Odd Address

Notes:

1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two

cycles to seven cycles. Clock is set for active rising edge.

2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.

3. The device is in synchronous mode.

4. This waveform represents a synchronous burst mode, the device will also operate in reduced wait-state handshaking under a

CLK synchronous burst mode.

5. CE#f refers to active flash die.

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A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Asynchronous Read

Parameter

D8, D9

C8, C9

JEDEC Standard Description

(54 MHz)

(40 MHz)

Unit

ns

t_CE

t_ACC

Access Time from CE# Low

Max

Min

Max

Min

70

85

Asynchronous Access Time (Note 1)

AVD# Low Time

ns

t_AVDP

t_AAVDS

t_AAVDH

t_OE

12

5

ns

Address Setup Time to Rising Edge of AVD

Address Hold Time from Rising Edge of AVD

Output Enable to Output Valid

Read

ns

7

ns

20

10

20.5

10.5

ns

0

ns

t_OEH

Output Enable Hold Time

Toggle and

Min

10

ns

Data# Polling

t_OEZ

t_CAS

Output Enable to High Z (Note 2)

CE# Setup Time to AVD#

Max

Min

ns

0

Notes:

1. Asynchronous Access Time is from the last of either stable addresses or the falling edge of AVD#.

2. Not 100% tested.

CE#f

t_OE

OE#

t_OEH

WE#

DQ0

t_CE

t_OEZ

DQ15

-

Valid RD

t_ACC

RA

A21-A0

t_AAVDH

t_CAS

AVD#

t_AVDP

t_AAVDS

Note: RA = Read Address, RD = Read Data. CE#f refers to active flash die.

Figure 18. Asynchronous Mode Read with Latched Addresses

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Am54BDS128AG

48

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

CE#f

t_OE

OE#

WE#

t_OEH

t_CE

t_OEZ

DQ15-DQ0

Valid RD

t_ACC

RA

A21-A0

AVD#

Note: RA = Read Address, RD = Read Data. CE#f refers to active flash die

Figure 19. Asynchronous Mode Read

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Am54BDS128AG

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A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

All Speed

Options

JEDEC

Std

Description

Unit

RESET# Pin Low (During Embedded Algorithms)

to Read Mode (See Note)

t_Readyw

Max

35

µs

RESET# Pin Low (NOT During Embedded Algorithms)

to Read Mode (See Note)

t_Ready

500

ns

t_RP

t_RH

RESET# Pulse Width

Min

500

200

20

ns

µs

Reset High Time Before Read (See Note)

RESET# Low to Standby Mode

t_RPD

Note: Not 100% tested.

CE#f, OE#

t_RH

RESET#

t_RP

t_Readyw

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

CE#f, OE#

RESET#

t_Ready

t_RP

Note: CE#f refers to active flash die.

Figure 20. Reset Timings

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A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Erase/Program Operations

Parameter

All Speed

Options

JEDEC

Standard

Description

Unit

t_AVAV

t_WC

Write Cycle Time (Note 1)

Min

80

5

ns

Synchronous

Address Setup Time

(Note 2)

t_AVWL

t_WLAX

t_AS

t_AH

ns

Asynchronous

Synchronous

Asynchronous

0

7

Address Hold Time

(Note 2)

Min

45

5

t_ACS

t_ACH

Address Setup Time to CLK (Note 2)

Address Hold Time to CLK (Note 2)

Data Setup Time

Min

Typ

ns

µs

7

t_DVWH

t_WHDX

t_GHWL

t_DS

45

0

t_DH

Data Hold Time

t_GHWL

t_CAS

Read Recovery Time Before Write

CE# Setup Time to AVD#

0

t_WHEH

t_WLWH

t_WHWL

t_CH

CE# Hold Time

0

t_WP

Write Pulse Width

50

30

0

t_WPH

t_SR/W

t_WHWH1

Write Pulse Width High

Latency Between Read and Write Operations

Programming Operation (Note 3)

Accelerated Programming Operation (Note 3)

Sector Erase Operation (Notes 3, 4)

Chip Erase Operation (Notes 3, 4)

V_ACCRise and Fall Time

t_WHWH1

8

2.5

0.2

26.8

500

1

t_WHWH2

Typ

sec

t_VID

t_VIDS

t_VCS

Min

ns

µs

ns

V_ACCSetup Time (During Accelerated Programming)

V_CCSetup Time

50

5

t_CSW1

t_CSW2

t_CHW

t_CS

Clock Setup Time to WE# (Asynchronous)

Clock Setup Time to WE# (Synchronous)

Clock Hold Time from WE#

CE# Setup Time to WE#

1

t_ELWL

0

t_AVSW

t_AVHW

t_AVHC

t_AVDP

AVD# Setup Time to WE#

5

AVD# Hold Time to WE#

5

AVD# Hold Time to CLK

5

AVD# Low Time

12

Notes:

1. Not 100% tested.

2. In asynchronous timing, addresses are latched on the falling edge of WE#. In synchronous mode, addresses are latched on the

first of either the rising edge of AVD# or the active edge of CLK.

3. See the “Flash Erase And Programming Performance” section for more information.

4. Does not include the preprogramming time.

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A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data

t_CSW1

V

IH

(Note 4)

CLK

V

IL

t_AVSW

t_AVHW

(Note 6)

AVD#

t_AVDP

t_AS

t_AH

Addresses

Data

555h

VA

PA

In

A0h

Complete

PD

Progress

t_DS

t_DH

CE#f

t_CH

OE#

WE#

t_WP

t_WHWH1

t_CS

t_WPH

t_WC

t_VCS

V_CC

Notes:

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. “In progress” and “complete” refer to status of program operation.

3. A21–A12 are don’t care during command sequence unlock cycles.

4. CLK can be either V_ILor V_IH.

5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Burst Mode Configuration

Register.

6. AVD# must toggle during command sequence if CLK is at V_IH.

7. CE#f refers to active flash die.

Figure 21. Asynchronous Program Operation Timings

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Am54BDS128AG

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A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data

t_CHW

V

IH

(Note 4)

CLK

V

IL

t_AVSW

t_AVHW

AVD#

t_AVDP

t_AS

t_AH

Addresses

Data

555h

VA

PA

In

A0h

Complete

PD

Progress

t_DS

t_DH

CE#f

t_CH

OE#

WE#

t_WP

t_WHWH1

t_CS

t_WPH

t_WC

t_VCS

V_CC

Notes:

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. “In progress” and “complete” refer to status of program operation.

3. A21–A12 are don’t care during command sequence unlock cycles.

4. CLK can be either V_ILor V_IH.

5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Burst Mode Configuration

Register.

6. AVD# must toggle during command sequence if CLK is at V_IH.

7. CE#f refers to active flash die.

Figure 22. Alternate Asynchronous Program Operation Timings

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Am54BDS128AG

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A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data

CLK

t_ACS

t_AS

t_ACH

AVD#

t_AH

555h

t_AVDP

Addresses

Data

PA

VA

In

Complete

A0h

PD

t_DS

t_DH

Progress

t_CAS

CE#f

t_CH

OE#

WE#

t_AHW

t_WP

t_WHWH1

t_WPH

t_WC

t_VCS

V_CC

Notes:

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. “In progress” and “complete” refer to status of program operation.

3. A21–A12 are don’t care during command sequence unlock cycles.

4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK.

5. Either CS# or AVD# is required to go from low to high in between programming command sequences.

6. The Synchronous programming operation is independent of the Set Device Read Mode bit in the Burst Mode Configuration

Register.

7. CLK must not have an active edge while WE# is at V_IL.

8. AVD# must toggle during command sequence unlock cycles.

9. CE#f refers to active flash die.

Figure 23. Synchronous Program Operation Timings

December 8, 2002

Am54BDS128AG

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A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

t_AVCH

Read Status Data

CLK

t_ACS

t_AS

t_ACH

AVD#

t_AH

(Note 8)

t_AVDP

Addresses

Data

PA

VA

555h

In

Complete

A0h

PD

t_DS

t_DH

Progress

t_CAS

CE#f

t_CH

OE#

WE#

t_CSW2

t_WP

t_WHWH1

t_WPH

t_WC

t_VCS

V_CC

Notes:

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. “In progress” and “complete” refer to status of program operation.

3. A21–A12 are don’t care during command sequence unlock cycles.

4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK.

5. Either CS# or AVD# is required to go from low to high in between programming command sequences.

6. The Synchronous programming operation is independent of the Set Device Read Mode bit in the Burst Mode Configuration

Register.

7. AVD# must toggle during command sequence unlock cycles.

8. t_AH= 45 ns.

9. CLK must not have an active edge while WE# is at V_IL.

10. CE#f refers to active flash die

Figure 24. Alternate Synchronous Program Operation Timings

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Am54BDS128AG

December 8, 2002

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

V

IH

CLK

V

IL

t_AVDP

AVD#

t_AH

t_AS

SA

555h for

chip erase

VA

Addresses

Data

2AAh

10h for

chip erase

In

Complete

55h

30h

Progress

t_DS

t_DH

CE#f

t_CH

OE#

WE#

t_WP

t_WHWH2

t_CS

t_WPH

t_WC

t_VCS

V_CC

Figure 25. Chip/Sector Erase Command Sequence

Notes:

1. SA is the sector address for Sector Erase.

2. Address bits A21–A12 are don’t cares during unlock cycles

in the command sequence.

3. CE#f refers to active flash die.

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Am54BDS128AG

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A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

CE#f

AVD#

WE#

Addresses

Data

PA

Don't Care

A0h

Don't Care

PD

Don't Care

OE#

t_VIDS

1 µs

V

ID

ACC

t_VID

V

or V

IH

IL

Note: Use setup and hold times from conventional program operation. CE#f refers to active flash die.

Figure 26. Accelerated Unlock Bypass Programming Timing

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Am54BDS128AG

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A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

AVD#

t_CEZ

t_CE

CE#f

t_OEZ

t_CH

t_OE

OE#

t_OEH

WE#

t_ACC

VA

Addresses

Data

VA

Status Data

Notes:

1. Status reads in figure are shown as asynchronous.

2. VA = Valid Address. Two read cycles are required to

determine status. When the Embedded Algorithm operation

is complete, and Data# Polling will output true data.

4. CE#f refers to active flash die.

3. AVD# must toggle between data reads.

Figure 27. Data# Polling Timings (During Embedded Algorithm)

AVD#

CE#f

t_CEZ

t_CE

t_OEZ

t_CH

t_OE

OE#

WE#

t_OEH

t_ACC

VA

Addresses

Data

VA

Status Data

Notes:

1. Status reads in figure are shown as asynchronous.

2. VA = Valid Address. Two read cycles are required to

determine status. When the Embedded Algorithm operation

is complete, the toggle bits will stop toggling.

3. AVD# must toggle between data reads.

4. CE#f refers to active flash die.

Figure 28. Toggle Bit Timings (During Embedded Algorithm)

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A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

CE#f

CLK

AVD#

Addresses

OE#

VA

t_IACC

Data

Status Data

RDY

Notes:

1. The timings are similar to synchronous read timings.

2. VA = Valid Address. Two read cycles are required to

determine status. When the Embedded Algorithm operation

is complete, the toggle bits will stop toggling.

Configuration Register, RDY is active one clock cycle

before data.

4. AVD# must toggle between data reads.

5. CE#f refers to active flash die.

3. RDY is active with data (A18 = 0 in the Burst Mode

Configuration Register). When A18 = 1 in the Burst Mode

Figure 29. Synchronous Data Polling Timings/Toggle Bit Timings

Address boundary occurs every 64 words, beginning at address

00003Fh (00007Fh, 0000BFh, etc.). Address 000000h is also a boundary crossing.

C60

C61

3D

C62

3E

C63

3F

C63

3F

C63

3F

C64

40

C65

41

C66

42

C67

43

CLK

3C

Address (hex)

(stays high)

AVD#

RDY

t_RACC

(Note 1)

(Note 2)

latency

t_RACC

latency

Data

D60

D61

D62

D63

D64

D65

D66

D67

Notes:

1. RDY active with data (A18 = 0 in the Burst Mode Configuration Register).

2. RDY active one clock cycle before data (A18 = 1 in the Burst Mode Configuration Register).

3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device not

crossing a bank in the process of performing an erase or program.

Figure 30. Latency with Boundary Crossing

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A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Address boundary occurs every 64 words, beginning at address

00003Fh (00007Fh, 0000BFh, etc.). Address 000000h is also a boundary crossing

C60

C61

3D

C62

3E

C63

3F

C63

3F

C63

3F

C64

40

CLK

3C

Address (hex)

(stays high)

AVD#

RDY

t_RACC

(Note 1)

(Note 2)

latency

t_RACC

latency

Data

Invalid

D60

D61

D62

D63

Read Status

OE#,

CE#f

(stays low)

Notes:

1. RDY active with data (A18 = 0 in the Burst Mode Configuration Register).

2. RDY active one clock cycle before data (A18 = 1 in the Burst Mode Configuration Register).

3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device crossing a bank

in the process of performing an erase or program.

4. CE#f refers to active flash die.

Figure 31. Latency with Boundary Crossing

into Program/Erase Bank

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Am54BDS128AG

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A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Data

D0

D1

Rising edge of next clock cycle

following last wait state triggers

next burst data

AVD#

OE#

total number of clock cycles

following AVD# falling edge

1

2

0

3

1

4

5

6

4

7

5

CLK

2

3

number of clock cycles

programmed

Note:

A14, A13, A12 = “101”

A14, A13, A12 = “100”

A14, A13, A12 = “011”

A14, A13, A12 = “010”

A14, A13, A12 = “001”

A14, A13, A12 = “000”

5 programmed, 7 total

4 programmed, 6 total

3 programmed, 5 total

2 programmed, 4 total

1 programmed, 3 total

0 programmed, 2 total

Note: Figure assumes address D0 is not at an address boundary, active clock edge is rising, and wait state is set to “101”.

Figure 32. Example of Wait States Insertion (Standard Handshaking Device)

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A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Last Cycle in

Program or

Sector Erase

Read status (at least two cycles) in same bank

and/or array data from other bank

Begin another

write or program

command sequence

Command Sequence

t_WC

t_RC

t_WC

CE#f

OE#

t_OE

t_GHWL

t_OEH

WE#

Data

t_WPH

t_OEZ

t_WP

t_DS

t_ACC

t_OEH

t_DH

PD/30h

RD

AAh

t_SR/W

RA

Addresses

AVD#

PA/SA

t_AS

RA

555h

t_AH

Note: Breakpoints in waveforms indicate that system may alternately read array data from the “non-busy bank” while checking

the status of the program or erase operation in the “busy” bank. The system should read status twice to ensure valid information.

CE#f refers to active flash die.

Figure 33. Back-to-Back Read/Write Cycle Timings

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A D V A N C E I N F O R M A T I O N

SRAM AC CHARACTERISTICS

Read Cycle

Parameter

Symbol

D8, D9

(54 MHz) (40 MHz)

C8, C9

Description

Unit

ns

t_RC

t_AA

_CO1, t_CO2

t_OE

Read Cycle Time

Min

Max

Min

70

35

70

85

40

85

Address Access Time

t

Chip Enable to Output

Output Enable Access Time

LB#s, UB#s to Access Time

Chip Enable (CE1#s Low and CE2s High) to Low-Z Output

UB#, LB# Enable to Low-Z Output

Output Enable to Low-Z Output

Chip Disable to High-Z Output

UB#s, LB#s Disable to High-Z Output

Output Disable to High-Z Output

Output Data Hold from Address Change

t_BA

t

_LZ1, t_LZ2

t_BLZ

10

5

Min

t_OLZ

Min

t

_HZ1, t_HZ2

t_BHZ

Max

Min

25

10

t_OHZ

t_OH

t_RC

Address

t_AA

t_OH

Data Valid

Data Out

Previous Data Valid

Note:

CE1#s = OE# = V_IL, CE2s = WE# = V_IH, UB#s and/or LB#s = V_IL

Figure 34. SRAM Read Cycle—Address Controlled

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A D V A N C E I N F O R M A T I O N

SRAM AC CHARACTERISTICS

t_RC

Address

t_AA

t_CO1

t_OH

CS#1

CS2

t_CO2

t_BA

t_HZ

UB#, LB#

OE#

t_BHZ

t_OE

t_OLZ

t_BLZ

t_LZ

t_OHZ

Data Out

High-Z

Data Valid

Figure 35. SRAM Read Cycle

Notes:

1. WE# = V_IH.

2. t_HZand t_OHZare defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output

voltage levels.

3. At any given temperature and voltage condition, t_HZ(Max.) is less than t_LZ(Min.) both for a given device and from device to device

interconnection.

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A D V A N C E I N F O R M A T I O N

SRAM AC CHARACTERISTICS

Write Cycle

Parameter

Symbol

D8, D9

(54 MHz) (40 MHz)

C8, C9

Description

Unit

ns

t_WC

t_Cw

t_AS

Write Cycle Time

Min

Max

Min

min

70

60

85

70

Chip Enable to End of Write

Address Setup Time

Address Valid to End of Write

UB#s, LB#s to End of Write

Write Pulse Time

ns

0

ns

t_AW

t_BW

t_WP

t_WR

60

50

70

60

ns

Write Recovery Time

0

ns

t_WHZ

Write to Output High-Z

ns

20

30

0

t_DW

t_DH

t_OW

Data to Write Time Overlap

Data Hold from Write Time

End Write to Output Low-Z

ns

5

t_WC

Address

CS1#s

CS2s

t_CW

(See Note 2)

t_WR(See Note 3)

t_AW

t_CW

(See Note 2)

t_BW

UB#s, LB#s

t_WP

(See Note 5)

WE#

t_AS

(See Note 4)

t_DH

t_DW

(See Note 9)

(See Note 6)

(See Note 9)

High-Z

Data In

Data Out

High-Z

Data Valid

t_WHZ

t_OW

(See Note 7)

Notes:

1. WE# controlled.

2. t_CWis measured from CE1#s going low to the end of write.

3. t_WRis measured from the end of write to the address change. t_WRapplied in case a write ends as CE1#s or WE# going high.

4. t_ASis measured from the address valid to the beginning of write.

5. A write occurs during the overlap (t_WP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A

write ends at the earliest transition when CE1#s goes high and WE# goes high. The t_WPis measured from the beginning of write

to the end of write.

Figure 36. SRAM Write Cycle—WE# Control

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A D V A N C E I N F O R M A T I O N

SRAM AC CHARACTERISTICS

t_WC

Address

t_AS(See Note 2)

t_CW

t_WR(See Note 4)

(See Note 3)

CE1#s

t_AW

CE2s

t_BW

UB#s, LB#s

t_WP

(See Note 5)

WE#

t_DW

t_DH

(See Note 6)

High-Z

Data Valid

Data In

Data Out

High-Z

Notes:

1. CE1#s controlled.

2. t_CWis measured from CE1#s going low to the end of write.

3. t_WRis measured from the end of write to the address change. t_WRapplied in case a write ends as CE1#s or WE# going high.

4. t_ASis measured from the address valid to the beginning of write.

5. A write occurs during the overlap (t_WP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A

write ends at the earliest transition when CE1#s goes high and WE# goes high. The t_WPis measured from the beginning of write

to the end of write.

Figure 37. SRAM Write Cycle—CE1#s Control

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A D V A N C E I N F O R M A T I O N

SRAM AC CHARACTERISTICS

t_WC

Address

CE1#s

t_CW

(See Note 2)

t_WR(See Note 3)

t_AW

t_CW(See Note 2)

CE2s

t_BW

UB#s, LB#s

t_AS

t_WP

(See Note 4)

(See Note 5)

WE#

t_DW

t_DH

Data In

Data Out

Data Valid

High-Z

Notes:

1. UB#s and LB#s controlled.

2. t_CWis measured from CE1#s going low to the end of write.

3. t_WRis measured from the end of write to the address change. t_WRapplied in case a write ends as CE1#s or WE# going high.

4. t_ASis measured from the address valid to the beginning of write.

5. A write occurs during the overlap (t_WP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A

write ends at the earliest transition when CE1#s goes high and WE# goes high. The t_WPis measured from the beginning of write

to the end of write.

Figure 38. SRAM Write Cycle—UB#s and LB#s Control

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A D V A N C E I N F O R M A T I O N

FLASH ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1) Max (Note 2)

Unit

sec

µs

Comments

Sector Erase Time (32 Kword or 8 Kword)

Chip Erase Time

0.4

54

5

Excludes 00h programming

prior to erasure (Note 4)

Word Program Time

11.5

4

210

120

144

48

Accelerated Word Program Time

Chip Program Time (Note 3)

Accelerated Chip Program Time

µs

Excludes system level

overhead (Note 5)

48

sec

16

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 2.0 V V_CC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V_CC= 1.8 V,

4. In the pre-programming step of the Embedded Erase

algorithm, all bytes are programmed to 00h before erasure.

1,000,000 cycles.

3. The typical chip programming time is considerably less than

the maximum chip programming time listed, since most

bytes program faster than the maximum program times

listed.

5. System-level overhead is the time required to execute the

two- or four-bus-cycle sequence for the program command.

See Table 14 for further information on command

definitions.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

FLASH LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V_SSon all pins except I/O pins

(including OE#, and RESET#)

–1.0 V

12.5 V

Input voltage with respect to V_SSon all I/O pins

V_CCCurrent

–1.0 V

V_CC+ 1.0 V

+100 mA

–100 mA

Note: Includes all pins except V_CC. Test conditions: V_CC= 3.0 V, one pin at a time.

PACKAGE PIN CAPACITANCE

Parameter

Symbol

Description

Test Setup

V_IN= 0

Typ

11

Max

14

Unit

pF

C_IN

Input Capacitance

C_OUT

C_IN2

Output Capacitance

Control Pin Capacitance

WP#/ACC Pin Capacitance

V_OUT= 0

V_IN= 0

12

14

17

16

pF

16

pF

C_IN3

V_IN= 0

20

pF

Note:Test conditions T_A= 25°C, f = 1.0 MHz.

FLASH DATA RETENTION

Parameter Description

Test Conditions

Min

10

Unit

Years

150°C

125°C

Minimum Pattern Data Retention Time

20

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A D V A N C E I N F O R M A T I O N

SRAM DATA RETENTION

Parameter

Symbol

Parameter Description

V_CCfor Data Retention

Test Setup

Min

Typ

Max

Unit

V_DR

I_DR

t_SDR

t_RDR

CS1#s ≥ V_CC– 0.2 V (Note 1)

1.0

2.2

V

V_CC= 1.2 V, CE1#s ≥ V_CC– 0.2 V

(Note 1)

1.0

(Note 2)

Data Retention Current

8

µA

Data Retention Set-Up Time

Recovery Time

0

ns

See data retention waveforms

t_RC

Notes:

1. CE1#s ≥ V_CC– 0.2 V, CE2s ≥ V_CC– 0.2 V (CE1#s controlled) or CE2s ≤ 0.2 V (CE2s controlled).

2. Typical values are not 100% tested.

Data Retention Mode

t_RDR

t_SDR

V_CC

2.7V

2.2V

V_DR

CE1#s ≥ V_CC

-0.2 V

CE1#s

GND

Figure 39. CE1#s Controlled Data Retention Mode

Data Retention Mode

V_CC

2.7 V

CE2s

t_SDR

t_RDR

V_DR

<

CE2s 0.2 V

0.4 V

GND

Figure 40. CE2s Controlled Data Retention Mode

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A D V A N C E I N F O R M A T I O N

PHYSICAL DIMENSIONS

FMA093—93-Ball Fine-Pitch Grid Array 10 x 10mm

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Am54BDS128AG

70

A D V A N C E I N F O R M A T I O N

REVISION SUMMARY

Product Selector Guide

Revised with renamed speed options and added Syn-

Revision A (July 16, 2002)

Initial release.

chronous Access Time with Reduced Wait-state

Handshaking.

Revision A+1 (December 8, 2002)

Added Asynchronous Access Time

Global

Ordering Information

Renamed Handshaking Enabled to Reduced

Wait-State Handshaking

Revised with global changes

Revised Valid Combinations with updated ordering

information.

Renamed non-Handshaking to Standard Handshaking

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

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型号：	AM54BDS128AGTD9IS
厂家：	SPANSION
描述：	Memory Circuit, 8MX16, CMOS, PBGA93, 10 X 10 MM, FPBGA-93 静态存储器内存集成电路
文件：	总71页 (文件大小：1179K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM54BDS128AGTD9IS [SPANSION]

相关型号：

AM54BDS128AGTD9IT

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