AM29LV800DB120SC_技术文档

Am29LV800D

Data Sheet

RETIRED

PRODUCT

This product has been retired and is not recommended for designs. For new and current designs,

S29AL008D supersedes Am29LV800D and is the factory-recommended migration path for this

device. Please refer to the S29AL008D data sheet for specifications and ordering information. Avail-

ability of this document is retained for reference and historical purposes only.

The following document contains information on Spansion memory products.

Continuity of Specifications

There is no change to this data sheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal data sheet improvement and are noted in the

document revision summary.

For More Information

Please contact your local sales office for additional information about Spansion memory solutions.

Publication Number Am29LV800_00 Revision A Amendment 7 Issue Date December 4, 2006

THIS PAGE LEFT INTENTIONALLY BLANK.

DATA SHEET

Am29LV800D

8 Megabit (1 M x 8-Bit/512 K x 16-Bit)

CMOS 3.0 Volt-only Boot Sector Flash Memory

This product has been retired and is not recommended for designs. For new and current designs, S29AL008D supersedes Am29LV800D and is the factory-recommended migration path

for this device. Please refer to the S29AL008D data sheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.

DISTINCTIVE CHARACTERISTICS

■ Single power supply operation

■ Embedded Algorithms

— 2.7 to 3.6 volt read and write operations for

battery-powered applications

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any

combination of designated sectors

■ Manufactured on 0.23 µm process technology

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

— Compatible with 0.32 µm Am29LV800 device

■ High performance

■ Minimum 1 million write cycle guarantee

— Access times as fast as 70 ns

per sector

■ Ultra low power consumption (typical values at

■ 20-year data retention at 125°C

— Reliable operation for the life of the system

■ Package option

5 MHz)

— 200 nA Automatic Sleep mode current

— 200 nA standby mode current

— 7 mA read current

— 48-ball FBGA

— 48-pin TSOP

— 15 mA program/erase current

— 44-pin SO

■ Flexible sector architecture

■ Compatibility with JEDEC standards

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

fifteen 64 Kbyte sectors (byte mode)

— Pinout and software compatible with

single-power supply Flash

— One 8 Kword, two 4 Kword, one 16 Kword, and

fifteen 32 Kword sectors (word mode)

— Superior inadvertent write protection

■ Data# Polling and toggle bits

— Supports full chip erase

— Provides a software method of detecting

program or erase operation completion

— Sector Protection features:

A hardware method of locking a sector to

prevent any program or erase operations within

that sector

Sectors can be locked in-system or via

programming equipment

■ Ready/Busy# pin (RY/BY#)

— Provides a hardware method of detecting

program or erase cycle completion

■ Erase Suspend/Erase Resume

Temporary Sector Unprotect feature allows code

changes in previously locked sectors

— Suspends an erase operation to read data from,

or program data to, a sector that is not being

erased, then resumes the erase operation

■ Unlock Bypass Program Command

■ Hardware reset pin (RESET#)

— Reduces overall programming time when

issuing multiple program command sequences

— Hardware method to reset the device to reading

array data

■ Top or bottom boot block configurations

available

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data

Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Publication # Am29LV800D_00 Revision: A

Amendment: 7 Issue Date: December 4, 2006

D A T A S H E E T

GENERAL DESCRIPTION

The Am29LV800D is an 8 Mbit, 3.0 volt-only Flash

memory organized as 1,048,576 bytes or 524,288

words. The device is offered in 48-ball FBGA, 44-pin

SO, and 48-pin TSOP packages. For more informa-

tion, refer to publication number 21536. The

word-wide data (x16) appears on DQ15–DQ0; the

byte-wide (x8) data appears on DQ7–DQ0. This de-

vice requires only a single, 3.0 volt V_CCsupply to per-

form read, program, and erase operations. A standard

EPROM programmer can also be used to program and

erase the device.

before executing the erase operation. During erase,

the device automatically times the erase pulse widths

and verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(toggle) status bits. After a program or erase cycle

has been completed, the device is ready to read array

data or accept another command.

The sector erase architecture allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

This device is manufactured using AMD’s 0.23 µm pro-

cess technology, and offers all the features and bene-

fits of the Am29LV800B, which was manufactured

using 0.32 µm process technology.

Hardware data protection measures include a low

V_CCdetector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of mem-

ory. This can be achieved in-system or via program-

ming equipment.

The standard device offers access times of 70, 90, and

120 ns, allowing high speed microprocessors to oper-

ate without wait states. To eliminate bus contention the

device has separate chip enable (CE#), write enable

(WE#) and output enable (OE#) controls.

The device requires only a single 3.0 volt power sup-

ply for both read and write functions. Internally gener-

ated and regulated voltages are provided for the

program and erase operations.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved.

The device is entirely command set compatible with

the JEDEC single-power-supply Flash standard.

Commands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as input to an internal state-machine that

controls the erase and programming circuitry. Write

cycles also internally latch addresses and data

needed for the programming and erase operations.

Reading data out of the device is similar to reading

from other Flash or EPROM devices.

The hardware RESET# pin terminates any operation

in progress and resets the internal state machine to

reading array data. The RESET# pin may be tied to

the system reset circuitry. A system reset would thus

also reset the device, enabling the system micropro-

cessor to read the boot-up firmware from the Flash

memory.

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the automatic sleep mode.

The system can also place the device into the

standby mode. Power consumption is greatly re-

duced in both these modes.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin. The Unlock Bypass mode facili-

tates faster programming times by requiring only two

write cycles to program data instead of four.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The device electrically erases all bits within

a sector simultaneously via Fowler-Nordheim tunnel-

ing. The data is programmed using hot electron injec-

tion.

Device erasure occurs by executing the erase com-

mand sequence. This initiates the Embedded Erase

algorithm—an internal algorithm that automatically

preprograms the array (if it is not already programmed)

2

Am29LV800D

Am29LV800D_00_A7 December 4, 2006

D A T A S H E E T

TABLE OF CONTENTS

Figure 6. Toggle Bit Algorithm..................................... 22

Table 6. Write Operation Status ..................................23

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 24

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 24

Commercial (C) Devices ...................................... 24

Industrial (I) Devices ............................................. 24

Product Selector Guide . . . . . . . . . . . . . . . . . . . . .4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5

Special Handling Instructions for FBGA Package ..6

Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Ordering Information . . . . . . . . . . . . . . . . . . . . . . .8

Standard Products ..................................................8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .9

Table 1. Am29LV800D Device Bus Operations ............9

Word/Byte Configuration ........................................9

Requirements for Reading Array Data ...................9

Writing Commands/Command Sequences ..........10

Program and Erase Operation Status ..................10

Standby Mode ......................................................10

Automatic Sleep Mode .........................................10

RESET#: Hardware Reset Pin .............................10

Output Disable Mode ............................................11

Table 2. Am29LV800DT Top Boot Block

Sector Addresses ........................................................11

Table 3. Am29LV800DB Bottom Boot Block

Sector Addresses ........................................................12

Autoselect Mode ...................................................12

Table 4. Am29LV800D Autoselect Codes

(High Voltage Method) ................................................13

Sector Protection/Unprotection ............................13

Temporary Sector Unprotect ................................13

Figure 1. Temporary Sector Unprotect Operation....... 13

Figure 2. In-System Sector Protect/

V

_CCSupply Voltages ............................................ 24

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 25

CMOS Compatible ............................................... 25

Figure 9. I_CC1Current vs. Time (Showing Active and

Automatic Sleep Currents) .......................................... 26

Figure 10. Typical I_CC1vs. Frequency ......................... 26

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 11. Test Setup.................................................. 27

Table 7. Test Specifications ........................................27

Key to Switching Waveforms. . . . . . . . . . . . . . . . 27

Figure 12. Input Waveforms and

Measurement Levels................................................... 27

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28

Read Operations .................................................. 28

Figure 13. Read Operations Timings .......................... 28

Hardware Reset (RESET#) .................................. 29

Figure 14. RESET# Timings........................................ 29

Word/Byte Configuration (BYTE#) ..................... 30

Figure 15. BYTE# Timings for Read Operations......... 30

Figure 16. BYTE# Timings for Write Operations......... 30

Erase/Program Operations ................................... 31

Figure 17. Program Operation Timings....................... 32

Figure 18. Chip/Sector Erase Operation Timings........ 33

Figure 19. Data# Polling Timings (During

Sector Unprotect Algorithms ....................................... 14

Hardware Data Protection ....................................15

Low V_CCWrite Inhibit ............................................15

Write Pulse “Glitch” Protection .............................15

Logical Inhibit .......................................................15

Power-Up Write Inhibit .........................................15

Command Definitions . . . . . . . . . . . . . . . . . . . . . 15

Reading Array Data ..............................................15

Reset Command ..................................................15

Autoselect Command Sequence ..........................15

Word/Byte Program Command Sequence ...........16

Unlock Bypass Command Sequence ...................16

Figure 3. Program Operation ...................................... 17

Chip Erase Command Sequence .........................17

Sector Erase Command Sequence ......................17

Erase Suspend/Erase Resume Commands .........18

Figure 4. Erase Operation........................................... 18

Table 5. Am29LV800D Command Definitions ............19

Write Operation Status . . . . . . . . . . . . . . . . . . . . 20

DQ7: Data# Polling ...............................................20

Figure 5. Data# Polling Algorithm ............................... 20

RY/BY#: Ready/Busy# .........................................21

DQ6: Toggle Bit I ..................................................21

DQ2: Toggle Bit II .................................................21

Reading Toggle Bits DQ6/DQ2 ............................21

DQ5: Exceeded Timing Limits ..............................22

DQ3: Sector Erase Timer .....................................22

Embedded Algorithms)................................................ 34

Figure 20. Toggle Bit Timings (During

Embedded Algorithms)................................................ 34

Figure 21. DQ2 vs. DQ6.............................................. 35

Temporary Sector Unprotect ................................ 35

Figure 22. Temporary Sector Unprotect

Timing Diagram........................................................... 35

Figure 23. Sector Protect/Unprotect

Timing Diagram........................................................... 36

Alternate CE# Controlled

Erase/Program Operations ................................... 37

Figure 24. Alternate CE# Controlled Write

Operation Timings....................................................... 38

Erase and Programming Performance . . . . . . . 39

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 39

TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 39

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Physical Dimensions* . . . . . . . . . . . . . . . . . . . . . 40

TS 048—48-Pin Standard TSOP ........................ 40

FBB 048—48-Ball Fine-Pitch Ball Grid Array

(FBGA) 6 x 9 mm ................................................ 41

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 42

VBK 048 - 48 Ball Fine-Pitch Ball Grid Array (FBGA)

6.15 x 8.15 mm ..................................................... 42

SO 044—44-Pin Small Outline Package ............. 43

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 44

Am29LV800D_00_A7 December 4, 2006

Am29LV800D

3

D A T A S H E E T

PRODUCT SELECTOR GUIDE

Family Part Number

Am29LV800D

Speed Options

Full Voltage Range: V_CC= 2.7–3.6 V

-70

70

30

-90

90

35

-120

120

50

Max access time, ns (t_ACC

)

Max CE# access time, ns (t_CE

)

Max OE# access time, ns (t_OE

)

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

DQ0–DQ15 (A-1)

RY/BY#

V_CC

Sector Switches

V_SS

Erase Voltage

Generator

Input/Output

Buffers

RESET#

State

Control

WE#

BYTE#

Command

Register

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

Y-Gating

STB

V_CCDetector

Timer

Cell Matrix

X-Decoder

A0–A18

4

Am29LV800D

Am29LV800D_00_A7 December 4, 2006

D A T A S H E E T

CONNECTION DIAGRAMS

A15

A14

A13

A12

A11

A10

A9

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE#

V_SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V_CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

V_SS

CE#

A0

A8

NC

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

WE#

RESET#

NC

Standard TSOP

NC

RY/BY#

A18

A17

A7

A6

A5

A4

A3

A2

A1

RY/BY#

A18

A17

A7

1

2

3

4

5

6

7

8

9

44 RESET#

43 WE#

42 A8

41 A9

A6

40 A10

A5

39 A11

A4

38 A12

A3

37 A13

A2

36 A14

A1 10

A0 11

35 A15

34 A16

SO

CE# 12

V_SS13

33 BYTE#

32 V_SS

OE# 14

DQ0 15

DQ8 16

DQ1 17

DQ9 18

DQ2 19

DQ10 20

DQ3 21

DQ11 22

31 DQ15/A-1

30 DQ7

29 DQ14

28 DQ6

27 DQ13

26 DQ5

25 DQ12

24 DQ4

23 V_CC

Am29LV800D_00_A7 December 4, 2006

Am29LV800D

5

D A T A S H E E T

CONNECTION DIAGRAMS

FBGA

Top View, Balls Facing Down

A6

B6

C6

D6

E6

F6

G6

H6

A13

A12

A14

A15

A16

BYTE# DQ15/A-1 V_SS

A5

A9

B5

A8

C5

D5

E5

F5

G5

H5

A10

A11

DQ7

DQ14

DQ13

DQ6

A4

B4

C4

D4

E4

F4

G4

H4

WE# RESET#

NC

DQ5

DQ12

V_CC

DQ4

A3

B3

C3

D3

E3

F3

G3

H3

RY/BY#

NC

A18

NC

DQ2

DQ10

DQ11

DQ3

A2

A7

B2

C2

A6

D2

A5

E2

F2

G2

H2

A17

DQ0

DQ8

DQ9

DQ1

A1

A3

B1

A4

C1

A2

D1

A1

E1

A0

F1

G1

H1

CE#

OE#

V_SS

Flash memory devices in FBGA packages may be

damaged if exposed to ultrasonic cleaning methods.

The package and/or data integrity may be compro-

mised if the package body is exposed to temperatures

above 150°C for prolonged periods of time.

Special Handling Instructions for FBGA

Package

Special handling is required for Flash Memory prod-

ucts in FBGA packages.

6

Am29LV800D

Am29LV800D_00_A7 December 4, 2006

D A T A S H E E T

PIN CONFIGURATION

LOGIC SYMBOL

A0–A18

= 19 addresses

19

DQ0–DQ14 = 15 data inputs/outputs

A0–A18

16 or 8

DQ15/A-1

= DQ15 (data input/output, word mode),

DQ0–DQ15

(A-1)

A-1 (LSB address input, byte mode)

= Selects 8-bit or 16-bit mode

= Chip enable

BYTE#

CE#

OE#

= Output enable

WE#

= Write enable

RESET#

BYTE#

RESET#

RY/BY#

V_CC

= Hardware reset pin, active low

= Ready/Busy# output

RY/BY#

= 3.0 volt-only single power supply

(see Product Selector Guide for speed

options and voltage supply tolerances)

V_SS

NC

= Device ground

= Pin not connected internally

Am29LV800D_00_A7 December 4, 2006

Am29LV800D

7

D A T A S H E E T

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-

nation) is formed by a combination of the elements below.

Am29LV800D

T

-70

E

C

TEMPERATURE RANGE

C

D

I

=

Commercial (0°C to +70°C)

Commercial (0°C to +70°C) with Pb-Free Package

Industrial (–40°C to +85°C)

Industrial (–40°C to +85°C) with Pb-Free Package

F

PACKAGE TYPE

E

=

48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)

44-Pin Small Outline Package (SO 044)

S

WB

48-Ball Fine Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 6 x 9 mm package (FBB048)

WC

=

48-Ball Fine Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 6.15 x 8.15 mm package (VBK 048)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T

B

=

Top sector

Bottom sector

DEVICE NUMBER/DESCRIPTION

Am29LV800D

8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations for TSOP and SO Packages

Valid Combinations for FBGA Packages

Order Number Package Marking

AM29LV800DT-70,

AM29LV800DB-70

AM29LV800DT-70,

WBC, WBI L800DT70V,

AM29LV800DT-90,

AM29LV800DB-90

EC, EI, ED, EF,

SC, SD, SF, SI

AM29LV800DB-70

L800DB70V

WBD, WBF

WCC, WCI

WCD, WCF

AM29LV800DT-90,

AM29LV800DB-90

L800DT90V,

L800DB90V

C, I,

D, F

AM29LV800DT-120,

AM29LV800DB-120

WBC, WBI

WBD, WBF

AM29LV800DT-120,

AM29LV800DB-120

L800DT12V,

L800DB12V

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

8

Am29LV800D

Am29LV800D_00_A7 December 4, 2006

D A T A S H E E T

DEVICE BUS OPERATIONS

This section describes the requirements and use of

the device bus operations, which are initiated through

the internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is composed of latches that store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state ma-

chine. The state machine outputs dictate the function

of the device. Table 1 lists the device bus operations,

the inputs and control levels they require, and the re-

sulting output. The following subsections describe

each of these operations in further detail.

Table 1. Am29LV800D Device Bus Operations

DQ8–DQ15

BYTE#

Addresses

(Note 1)

DQ0– BYTE#

Operation

CE# OE# WE# RESET#

DQ7

D_OUT

D_IN

= V_IH

D_OUT

D_IN

= V_IL

Read

Write

L

H

L

H

A_IN

DQ8–DQ14 = High-Z,

DQ15 = A-1

H

V_CC

0.3 V

±

V_CC±

0.3 V

Standby

X

High-Z High-Z

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

X

High-Z High-Z

High-Z

X

Sector Address,

A6 = L, A1 = H,

A0 = L

Sector Protect (Note 2)

L

H

L

V_ID

D_IN

X

Sector Address,

A6 = H, A1 = H,

A0 = L

Sector Unprotect (Note 2)

L

H

X

L

V_ID

D_IN

X

Temporary Sector Unprotect

X

A_IN

D_IN

High-Z

Legend:

L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 12.0 ± 0.5 V, X = Don’t Care, A_IN= Address In, D_IN= Data In, D_OUT= Data Out

Notes:

1. Addresses are A18:A0 in word mode (BYTE# = V_IH), A18:A-1 in byte mode (BYTE# = V_IL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Protection/Unprotection” section.

whether the device outputs array data in words or

bytes.

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins DQ15–DQ0 operate in the byte or word configura-

tion. If the BYTE# pin is set at logic ‘1’, the device is in

word configuration, DQ15–DQ0 are active and con-

trolled by CE# and OE#.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No com-

mand is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid

data on the device data outputs. The device remains

enabled for read access until the command register

contents are altered.

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ0–DQ7 are

active and controlled by CE# and OE#. The data I/O

pins DQ8–DQ14 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specifica-

tions and to Figure 13 for the timing diagram. I_CC1in

the DC Characteristics table represents the active cur-

rent specification for reading array data.

To read array data from the outputs, the system must

drive the CE# and OE# pins to V_IL. CE# is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE#

should remain at V_IH. The BYTE# pin determines

Am29LV800D_00_A7 December 4, 2006

Am29LV800D

9

D A T A S H E E T

and the outputs are placed in the high impedance

state, independent of the OE# input.

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V_IL, and OE# to V_IH.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V_CC± 0.3 V.

(Note that this is a more restricted voltage range than

V_IH.) If CE# and RESET# are held at V_IH, but not within

V_CC± 0.3 V, the device will be in the standby mode, but

the standby current will be greater. The device re-

quires standard access time (t_CE) for read access

when the device is in either of these standby modes,

before it is ready to read data.

For program operations, the BYTE# pin determines

whether the device accepts program data in bytes or

words. Refer to “Word/Byte Configuration” for more in-

formation.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are re-

quired to program a word or byte, instead of four. The

“Word/Byte Program Command Sequence” section

has details on programming data to the device using

both standard and Unlock Bypass command se-

quences.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

In the DC Characteristics table, I_CC3and I_CC4repre-

sents the standby current specification.

Automatic Sleep Mode

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Tables 2 and 3 indicate the

address space that each sector occupies. A “sector

address” consists of the address bits required to

uniquely select a sector. The “Command Definitions”

section has details on erasing a sector or the entire

chip, or suspending/resuming the erase operation.

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

this mode when addresses remain stable for t_ACC+ 30

ns. The automatic sleep mode is independent of the

CE#, WE#, and OE# control signals. Standard ad-

dress access timings provide new data when ad-

dresses are changed. While in sleep mode, output

data is latched and always available to the system.

After the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in

this mode. Refer to the “Autoselect Mode” and “Au-

toselect Command Sequence” sections for more infor-

mation.

I_CC4in the DC Characteristics table represents the au-

tomatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of t_RP, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is

ready to accept another command sequence, to en-

sure data integrity.

I_CC2in the DC Characteristics table represents the ac-

tive current specification for the write mode. The “AC

Characteristics” section contains timing specification

tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system

may check the status of the operation by reading the

status bits on DQ7–DQ0. Standard read cycle timings

and I_CCread specifications apply. Refer to “Write Op-

eration Status” for more information, and to “AC Char-

acteristics” for timing diagrams.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V_SS0.3 V, the device

draws CMOS standby current (I_CC4). If RESET# is held

at V_ILbut not within V_SS0.3 V, the standby current will

be greater.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

10

Am29LV800D

Am29LV800D_00_A7 December 4, 2006

D A T A S H E E T

If RESET# is asserted during a program or erase op-

rithms). The system can read data t_RHafter the RE-

SET# pin returns to V_IH.

eration, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of t_READY(during Embedded Algorithms). The sys-

tem can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of t_READY(not during Embedded Algo-

Refer to the AC Characteristics tables for RESET# pa-

rameters and to Figure 14 for the timing diagram.

Output Disable Mode

When the OE# input is at V_IH, output from the device is

disabled. The output pins are placed in the high im-

pedance state.

Table 2. Am29LV800DT Top Boot Block Sector Addresses

Address Range (in hexadecimal)

Sector Size

(Kbytes/

(x8)

(x16)

Sector

SA0

A18

0

A17

0

A16

0

A15

0

A14

X

0

A13

X

0

A12

X

0

Kwords)

Address Range

64/32

32/16

8/4

00000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–3FFFFh

40000h–4FFFFh

50000h–5FFFFh

60000h–6FFFFh

70000h–7FFFFh

80000h–8FFFFh

90000h–9FFFFh

A0000h–AFFFFh

B0000h–BFFFFh

C0000h–CFFFFh

D0000h–DFFFFh

E0000h–EFFFFh

F0000h–F7FFFh

F8000h–F9FFFh

FA000h–FBFFFh

FC000h–FFFFFh

00000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

40000h–47FFFh

48000h–4FFFFh

50000h–57FFFh

58000h–5FFFFh

60000h–67FFFh

68000h–6FFFFh

70000h–77FFFh

78000h–7BFFFh

7C000h–7CFFFh

7D000h–7DFFFh

7E000h–7FFFFh

SA1

0

1

SA2

0

1

0

SA3

0

1

SA4

0

1

0

SA5

0

1

0

1

SA6

0

1

0

SA7

0

1

SA8

1

0

SA9

1

0

1

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

8/4

1

X

16/8

Am29LV800D_00_A7 December 4, 2006

Am29LV800D

11

D A T A S H E E T

Table 3. Am29LV800DB Bottom Boot Block Sector Addresses

Address Range (in hexadecimal)

Sector Size

(Kbytes/

(x8)

(x16)

Sector

SA0

A18

0

A17

0

A16

0

A15

0

A14

0

A13

0

A12

X

0

Kwords)

Address Range

16/8

8/4

00000h–03FFFh

04000h–05FFFh

06000h–07FFFh

08000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–3FFFFh

40000h–4FFFFh

50000h–5FFFFh

60000h–6FFFFh

70000h–7FFFFh

80000h–8FFFFh

90000h–9FFFFh

A0000h–AFFFFh

B0000h–BFFFFh

C0000h–CFFFFh

D0000h–DFFFFh

E0000h–EFFFFh

F0000h–FFFFFh

00000h–01FFFh

02000h–02FFFh

03000h–03FFFh

04000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

40000h–47FFFh

48000h–4FFFFh

50000h–57FFFh

58000h–5FFFFh

60000h–67FFFh

68000h–6FFFFh

70000h–77FFFh

78000h–7FFFFh

SA1

0

1

SA2

0

1

8/4

SA3

0

1

X

32/16

64/32

SA4

0

1

X

SA5

0

1

0

SA6

0

1

SA7

0

1

0

SA8

0

1

0

1

SA9

0

1

0

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Note for Tables 2 and 3: Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration”

section.

Table 4. In addition, when verifying sector protection,

Autoselect Mode

the sector address must appear on the appropriate

The autoselect mode provides manufacturer and de-

highest order address bits (see Tables 2 and 3). Table

vice identification, and sector protection verification,

4 shows the remaining address bits that are don’t

through identifier codes output on DQ7–DQ0. This

care. When all necessary bits have been set as re-

mode is primarily intended for programming equip-

quired, the programming equipment may then read the

ment to automatically match a device to be pro-

corresponding identifier code on DQ7–DQ0.

grammed with its corresponding programming

algorithm. However, the autoselect codes can also be

accessed in-system through the command register.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 5. This method

does not require V_ID. See “Command Definitions” for

details on using the autoselect mode.

When using programming equipment, the autoselect

mode requires V_ID(11.5 V to 12.5 V) on address pin

A9. Address pins A6, A1, and A0 must be as shown in

12

Am29LV800D

Am29LV800D_00_A7 December 4, 2006

D A T A S H E E T

Table 4. Am29LV800D Autoselect Codes (High Voltage Method)

A18 A11

to to

Mode CE# OE# WE# A12 A10 A9

A8

to

A7

A5

to

A2

DQ8

to

A0 DQ15

DQ7

to

DQ0

Description

A6

A1

Manufacturer ID: AMD

L

H

X

V_ID

X

L

X

L

X

01h

Device ID:

Am29LV800B

(Top Boot Block)

Word

Byte

Word

Byte

22h

DAh

X

V_ID

L

H

L

H

X

22h

X

DAh

5Bh

Device ID:

Am29LV800B

(Bottom Boot Block)

X

V_ID

X

H

L

01h

(protected)

X

Sector Protection Verification

L

H

SA

V_ID

L

H

00h

(unprotected)

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, SA = Sector Address, X = Don’t care.

Sector Protection/Unprotection

Temporary Sector Unprotect

The hardware sector protection feature disables both

program and erase operations in any sector. The hard-

ware sector unprotection feature re-enables both pro-

gram and erase operations in previously protected

sectors.

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The

Sector Unprotect mode is activated by setting the RE-

SET# pin to V_ID. During this mode, formerly protected

sectors can be programmed or erased by selecting the

sector addresses. Once V_IDis removed from the RE-

SET# pin, all the previously protected sectors are

protected again. Figure 1 shows the algorithm, and

Figure 22 shows the timing diagrams, for this feature.

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

START

It is possible to determine whether a sector is pro-

tected or unprotected. See “Autoselect Mode” for de-

tails.

RESET# = V_ID

(Note 1)

Sector Protection/unprotection can be implemented

via two methods.

Perform Erase or

The primary method requires V_IDon the RESET# pin

only, and can be implemented either in-system or via

programming equipment. Figure 2 shows the algo-

rithms and Figure 23 shows the timing diagram. This

method uses standard microprocessor bus cycle tim-

ing. For sector unprotect, all unprotected sectors must

first be protected prior to the first sector unprotect

write cycle.

Program Operations

RESET# = V_IH

Temporary Sector

Unprotect Completed

(Note 2)

The alternate method intended only for programming

equipment requires V_IDon address pin A9 and OE#.

This method is compatible with programmer routines

written for earlier 3.0 volt-only AMD flash devices.

Publication number 20536 contains further details;

contact an AMD representative to request a copy.

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once

again.

Figure 1. Temporary Sector Unprotect Operation

Am29LV800D_00_A7 December 4, 2006

Am29LV800D

13

D A T A S H E E T

START

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

PLSCNT = 1

RESET# = V_ID

Wait 1 ms

unprotect address

No

First Write

Cycle = 60h?

No

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Yes

Set up first sector

address

Sector Unprotect:

Wait 150 µs

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

A1 = 1, A0 = 0

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Increment

PLSCNT

No

PLSCNT

= 25?

Read from

sector address

with A6 = 1,

Data = 01h?

Yes

A1 = 1, A0 = 0

No

Yes

Set up

next sector

address

Yes

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

No

Last sector

verified?

Device failed

Write reset

command

Yes

Remove V_ID

from RESET#

Sector Unprotect

Algorithm

Sector Protect

Algorithm

Sector Protect

complete

Write reset

command

Sector Unprotect

complete

Figure 2. In-System Sector Protect/

Sector Unprotect Algorithms

14

Am29LV800D

Am29LV800D_00_A7 December 4, 2006

D A T A S H E E T

vide the proper signals to the control pins to prevent

unintentional writes when V_CCis greater than V_LKO

Hardware Data Protection

.

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 5 for com-

mand definitions). In addition, the following hardware

data protection measures prevent accidental erasure

or programming, which might otherwise be caused by

spurious system level signals during V_CCpower-up

and power-down transitions, or from system noise.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE#

or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

V_IL, CE# = V_IHor WE# = V_IH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

Low V_CCWrite Inhibit

When V_CCis less than V_LKO, the device does not ac-

cept any write cycles. This protects data during V_CC

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets. Subsequent writes are ignored

until V_CCis greater than V_LKO. The system must pro-

Power-Up Write Inhibit

If WE# = CE# = V_ILand OE# = V_IHduring power up,

the device does not accept commands on the rising

edge of WE#. The internal state machine is automati-

cally reset to reading array data on power-up.

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device op-

erations. Table 5 defines the valid register command

sequences. Writing incorrect address and data val-

ues or writing them in the improper sequence resets

the device to reading array data.

See also “Requirements for Reading Array Data” in

the “Device Bus Operations” section for more informa-

tion. The Read Operations table provides the read pa-

rameters, and Figure 13 shows the timing diagram.

Reset Command

Writing the reset command to the device resets the

device to reading array data. Address bits are don’t

care for this command.

All addresses are latched on the falling edge of WE#

or CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to reading array

data. Once erasure begins, however, the device ig-

nores reset commands until the operation is complete.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is also ready to read array

data after completing an Embedded Program or Em-

bedded Erase algorithm.

The reset command may be written between the se-

quence cycles in a program command sequence be-

fore programming begins. This resets the device to

reading array data (also applies to programming in

Erase Suspend mode). Once programming begins,

however, the device ignores reset commands until the

operation is complete.

After the device accepts an Erase Suspend command,

the device enters the Erase Suspend mode. The sys-

tem can read array data using the standard read tim-

ings, except that if it reads at an address within

erase-suspended sectors, the device outputs status

data. After completing a programming operation in the

Erase Suspend mode, the system may once again

read array data with the same exception. See “Erase

Suspend/Erase Resume Commands” for more infor-

mation on this mode.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command

must be written to return to reading array data (also

applies to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to read-

ing array data (also applies during Erase Suspend).

The system must issue the reset command to re-en-

able the device for reading array data if DQ5 goes

high, or while in the autoselect mode. See the “Reset

Command” section, next.

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and devices

Am29LV800D_00_A7 December 4, 2006

Am29LV800D

15

D A T A S H E E T

codes, and determine whether or not a sector is pro-

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program-

ming operation. The program command sequence

should be reinitiated once the device has reset to

reading array data, to ensure data integrity.

tected. Table 5 shows the address and data require-

ments. This method is an alternative to that shown in

Table 4, which is intended for PROM programmers

and requires V_IDon address bit A9.

The autoselect command sequence is initiated by writ-

ing two unlock cycles, followed by the autoselect com-

mand. The device then enters the autoselect mode,

and the system may read at any address any number

of times, without initiating another command se-

quence.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may

halt the operation and set DQ5 to “1”, or cause the

Data# Polling algorithm to indicate the operation was

successful. However, a succeeding read will show that

the data is still “0”. Only erase operations can convert

a “0” to a “1”.

A read cycle at address XX00h retrieves the manufac-

turer code. A read cycle at address XX01h in word

mode (or 02h in byte mode) returns the device code. A

read cycle containing a sector address (SA) and the

address 02h in word mode (or 04h in byte mode) re-

turns 01h if that sector is protected, or 00h if it is un-

protected. Refer to Tables 2 and 3 for valid sector

addresses.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-

gram bytes or words to the device faster than using the

standard program command sequence. The unlock

bypass command sequence is initiated by first writing

two unlock cycles. This is followed by a third write

cycle containing the unlock bypass command, 20h.

The device then enters the unlock bypass mode. A

two-cycle unlock bypass program command sequence

is all that is required to program in this mode. The first

cycle in this sequence contains the unlock bypass pro-

gram command, A0h; the second cycle contains the

program address and data. Additional data is pro-

grammed in the same manner. This mode dispenses

with the initial two unlock cycles required in the stan-

dard program command sequence, resulting in faster

total programming time. Table 5 shows the require-

ments for the command sequence.

The system must write the reset command to exit the

autoselect mode and return to reading array data.

Word/Byte Program Command Sequence

The system may program the device by word or byte,

depending on the state of the BYTE# pin. Program-

ming is a four-bus-cycle operation. The program com-

mand sequence is initiated by writing two unlock write

cycles, followed by the program set-up command. The

program address and data are written next, which in

turn initiate the Embedded Program algorithm. The

system is not required to provide further controls or

timings. The device automatically provides internally

generated program pulses and verifies the pro-

grammed cell margin. Table 5 shows the address and

data requirements for the byte program command se-

quence.

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset com-

mand sequence. The first cycle must contain the data

90h; the second cycle the data 00h. Addresses are

don’t care for both cycles. The device then returns to

reading array data.

When the Embedded Program algorithm is complete,

the device then returns to reading array data and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using

DQ7, DQ6, or RY/BY#. See “Write Operation Status”

for information on these status bits.

Figure 3 illustrates the algorithm for the program oper-

ation. See the Erase/Program Operations table in “AC

Characteristics” for parameters, and to Figure 17 for

timing diagrams.

16

Am29LV800D

Am29LV800D_00_A7 December 4, 2006

D A T A S H E E T

vice has returned to reading array data, to ensure data

integrity.

START

The system can determine the status of the erase op-

eration by using DQ7, DQ6, DQ2, or RY/BY#. See

“Write Operation Status” for information on these sta-

tus bits. When the Embedded Erase algorithm is com-

plete, the device returns to reading array data and

addresses are no longer latched.

Write Program

Command Sequence

Figure 4 illustrates the algorithm for the erase opera-

tion. See the Erase/Program Operations tables in “AC

Characteristics” for parameters, and to Figure 18 for

timing diagrams.

Data Poll

from System

Embedded

Program

algorithm

in progress

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two ad-

ditional unlock write cycles are then followed by the

address of the sector to be erased, and the sector

erase command. Table 5 shows the address and data

requirements for the sector erase command se-

quence.

Verify Data?

Yes

No

Increment Address

Last Address?

Yes

The device does not require the system to preprogram

the memory prior to erase. The Embedded Erase al-

gorithm automatically programs and verifies the sector

for an all zero data pattern prior to electrical erase.

The system is not required to provide any controls or

timings during these operations.

Programming

Completed

After the command sequence is written, a sector erase

time-out of 50 µs begins. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time

between these additional cycles must be less than 50

µs, otherwise the last address and command might

not be accepted, and erasure may begin. It is recom-

mended that processor interrupts be disabled during

this time to ensure all commands are accepted. The

interrupts can be re-enabled after the last Sector

Erase command is written. If the time between addi-

tional sector erase commands can be assumed to be

less than 50 µs, the system need not monitor DQ3.

Any command other than Sector Erase or Erase

Suspend during the time-out period resets the de-

vice to reading array data. The system must rewrite

the command sequence and any additional sector ad-

dresses and commands.

Note: See Table 5 for program command sequence.

Figure 3. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 5 shows

the address and data requirements for the chip erase

command sequence.

The system can monitor DQ3 to determine if the sec-

tor erase timer has timed out. (See the “DQ3: Sector

Erase Timer” section.) The time-out begins from the

rising edge of the final WE# pulse in the command se-

quence.

Any commands written to the chip during the Embed-

ded Erase algorithm are ignored. Note that a hard-

ware reset during the chip erase operation

immediately terminates the operation. The Chip Erase

command sequence should be reinitiated once the de-

Am29LV800D_00_A7 December 4, 2006

Am29LV800D

17

D A T A S H E E T

Once the sector erase operation has begun, only the

After an erase-suspended program operation is com-

plete, the system can once again read array data

within non-suspended sectors. The system can deter-

mine the status of the program operation using the

DQ7 or DQ6 status bits, just as in the standard pro-

gram operation. See “Write Operation Status” for more

information.

Erase Suspend command is valid. All other com-

mands are ignored. Note that a hardware reset dur-

ing the sector erase operation immediately terminates

the operation. The Sector Erase command sequence

should be reinitiated once the device has returned to

reading array data, to ensure data integrity.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses

are no longer latched. The system can determine the

status of the erase operation by using DQ7, DQ6,

DQ2, or RY/BY#. Refer to “Write Operation Status” for

information on these status bits.

The system may also write the autoselect command

sequence when the device is in the Erase Suspend

mode. The device allows reading autoselect codes

even at addresses within erasing sectors, since the

codes are not stored in the memory array. When the

device exits the autoselect mode, the device reverts to

the Erase Suspend mode, and is ready for another

valid operation. See “Autoselect Command Sequence”

for more information.

Figure 4 illustrates the algorithm for the erase opera-

tion. Refer to the Erase/Program Operations tables in

the “AC Characteristics” section for parameters, and to

Figure 18 for timing diagrams.

The system must write the Erase Resume command

(address bits are “don’t care”) to exit the erase sus-

pend mode and continue the sector erase operation.

Further writes of the Resume command are ignored.

Another Erase Suspend command can be written after

the device has resumed erasing.

Erase Suspend/Erase Resume

Commands

The Erase Suspend command allows the system to in-

terrupt a sector erase operation and then read data

from, or program data to, any sector not selected for

erasure. This command is valid only during the sector

erase operation, including the 50 µs time-out period

during the sector erase command sequence. The

Erase Suspend command is ignored if written during

the chip erase operation or Embedded Program algo-

rithm. Writing the Erase Suspend command during the

Sector Erase time-out immediately terminates the

time-out period and suspends the erase operation. Ad-

dresses are “don’t-cares” when writing the Erase Sus-

pend command.

START

Write Erase

Command Sequence

Data Poll

When the Erase Suspend command is written during a

sector erase operation, the device requires a maxi-

mum of 20 µs to suspend the erase operation. How-

ever, when the Erase Suspend command is written

during the sector erase time-out, the device immedi-

ately terminates the time-out period and suspends the

erase operation.

from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

After the erase operation has been suspended, the

system can read array data from or program data to

any sector not selected for erasure. (The device “erase

suspends” all sectors selected for erasure.) Normal

read and write timings and command definitions apply.

Reading at any address within erase-suspended sec-

tors produces status data on DQ7–DQ0. The system

can use DQ7, or DQ6 and DQ2 together, to determine

if a sector is actively erasing or is erase-suspended.

See “Write Operation Status” for information on these

status bits.

Yes

Erasure Completed

Notes:

1. See Table 5 for erase command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Figure 4. Erase Operation

18

Am29LV800D

Am29LV800D_00_A7 December 4, 2006

D A T A S H E E T

Table 5. Am29LV800D Command Definitions

Bus Cycles (Notes 2-5)

Command

Sequence

(Note 1)

First

Second

Third

Addr

Fourth

Data Addr Data

Fifth

Sixth

Addr Data Addr Data

Read (Note 6)

Reset (Note 7)

1

RA

XXX

555

AAA

555

AAA

555

AAA

RD

F0

Word

Byte

Word

Byte

Word

Byte

2AA

555

2AA

555

2AA

555

AAA

555

4

AA

55

90

X00

01

Manufacturer ID

X01

X02

X01

X02

22DA

DA

Device ID,

Top Boot Block

AAA

555

225B

5B

Device ID,

Bottom Boot Block

AAA

XX00

XX01

00

(SA)

X02

Word

Byte

555

2AA

555

Sector Protect Verify

(Note 9)

4

AA

55

90

(SA)

X04

AAA

01

Word

Byte

555

AAA

555

2AA

555

2AA

555

AAA

555

Program

4

AA

55

A0

20

PA

PD

Word

Unlock Bypass

3

Byte

555

PA

AAA

A0

90

PD

00

Unlock Bypass Program (Note 10) 2 XXX

XXX

2AA

555

2AA

555

Unlock Bypass Reset (Note 11)

2

XXX

555

Word

555

AAA

555

AAA

555

2AA

555

2AA

555

Chip Erase

6

AA

55

80

AA

55

10

30

Byte

Word

Byte

AAA

555

AAA

Sector Erase

6

SA

AAA

XXX

AAA

Erase Suspend (Note 12)

Erase Resume (Note 13)

1

B0

30

Legend:

X = Don’t care

PD = Data to be programmed at location PA. Data latches on

the rising edge of WE# or CE# pulse, whichever happens

first.

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

SA = Address of the sector to be verified (in autoselect

mode) or erased. Address bits A18–A12 uniquely select any

sector.

PA = Address of the memory location to be programmed.

Addresses latch on the falling edge of the WE# or CE#

pulse, whichever happens later.

Notes:

1. See Table 1 for description of bus operations.

9. The data is 00h for an unprotected sector and 01h for a

protected sector. See “Autoselect Command Sequence” for

more information.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus

cycles are write operations.

10. The Unlock Bypass command is required prior to the

Unlock Bypass Program command.

4. Data bits DQ15–DQ8 are don’t cares for unlock and

command cycles.

11. The Unlock Bypass Reset command is required to return to

reading array data when the device is in the unlock bypass

mode.

5. Address bits A18–A11 are don’t cares for unlock and

command cycles, unless PA or SA required.

12. The system may read and program in non-erasing sectors,

or enter the autoselect mode, when in the Erase Suspend

mode. The Erase Suspend command is valid only during a

sector erase operation.

6. No unlock or command cycles required when reading array

data.

7. The Reset command is required to return to reading array

data when device is in the autoselect mode, or if DQ5 goes

high (while the device is providing status data).

13. The Erase Resume command is valid only during the

Erase Suspend mode.

8. The fourth cycle of the autoselect command sequence is a

read cycle.

Am29LV800D_00_A7 December 4, 2006

Am29LV800D

19

D A T A S H E E T

WRITE OPERATION STATUS

The device provides several bits to determine the sta-

tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,

and RY/BY#. Table 6 and the following subsections

describe the functions of these bits. DQ7, RY/BY#,

and DQ6 each offer a method for determining whether

a program or erase operation is complete or in

progress. These three bits are discussed first.

Table 6 shows the outputs for Data# Polling on DQ7.

Figure 5 shows the Data# Polling algorithm.

START

DQ7: Data# Polling

Read DQ7–DQ0

Addr = VA

The Data# Polling bit, DQ7, indicates to the host sys-

tem whether an Embedded Algorithm is in progress or

completed, or whether the device is in Erase Suspend.

Data# Polling is valid after the rising edge of the final

WE# pulse in the program or erase command se-

quence.

Yes

DQ7 = Data?

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to pro-

gramming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active for

approximately 1 µs, then the device returns to reading

array data.

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

This is analogous to the complement/true datum out-

put described for the Embedded Program algorithm:

the erase function changes all the bits in a sector to

“1”; prior to this, the device outputs the “complement,”

or “0.” The system must provide an address within any

of the sectors selected for erasure to read valid status

information on DQ7.

Yes

DQ7 = Data?

No

PASS

FAIL

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data# Poll-

ing on DQ7 is active for approximately 100 µs, then the

device returns to reading array data. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within

any sector selected for erasure. During chip erase, a

valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at

DQ7–DQ0 on the following read cycles. This is be-

cause DQ7 may change asynchronously with

DQ0–DQ6 while Output Enable (OE#) is asserted low.

Figure 19, Data# Polling Timings (During

Embedded Algorithms), in the “AC Characteristics”

section illustrates this.

Figure 5. Data# Polling Algorithm

20

Am29LV800D

Am29LV800D_00_A7 December 4, 2006

D A T A S H E E T

DQ6 also toggles during the erase-suspend-program

RY/BY#: Ready/Busy#

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

The RY/BY# is a dedicated, open-drain output pin that

indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open-drain output, sev-

eral RY/BY# pins can be tied together in parallel with a

Table 6 shows the outputs for Toggle Bit I on DQ6. Fig-

ure 6 shows the toggle bit algorithm. Figure 20 in the

“AC Characteristics” section shows the toggle bit tim-

ing diagrams. Figure 21 shows the differences be-

tween DQ2 and DQ6 in graphical form. See also the

subsection on “DQ2: Toggle Bit II”.

pull-up resistor to V_CC

.

If the output is low (Busy), the device is actively eras-

ing or programming. (This includes programming in

the Erase Suspend mode.) If the output is high

(Ready), the device is ready to read array data (includ-

ing during the Erase Suspend mode), or is in the

standby mode.

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

Table 6 shows the outputs for RY/BY#. Figures 13, 14,

17 and 18 shows RY/BY# for read, reset, program,

and erase operations, respectively.

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. (The system may use either OE# or CE# to con-

trol the read cycles.) But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-sus-

pended. DQ6, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but

cannot distinguish which sectors are selected for era-

sure. Thus, both status bits are required for sector and

mode information. Refer to Table 6 to compare outputs

for DQ2 and DQ6.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or com-

plete, or whether the device has entered the Erase

Suspend mode. Toggle Bit I may be read at any ad-

dress, and is valid after the rising edge of the final

WE# pulse in the command sequence (prior to the

program or erase operation), and during the sector

erase time-out.

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. (The system may use either OE# or

CE# to control the read cycles.) When the operation is

complete, DQ6 stops toggling.

Figure 6 shows the toggle bit algorithm in flowchart

form, and the section “DQ2: Toggle Bit II” explains the

algorithm. See also the “DQ6: Toggle Bit I” subsection.

Figure 20 shows the toggle bit timing diagram. Figure

21 shows the differences between DQ2 and DQ6 in

graphical form.

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6 tog-

gles for approximately 100 µs, then returns to reading

array data. If not all selected sectors are protected, the

Embedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are pro-

tected.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 6 for the following discussion. When-

ever the system initially begins reading toggle bit sta-

tus, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically,

the system would note and store the value of the tog-

gle bit after the first read. After the second read, the

system would compare the new value of the toggle bit

with the first. If the toggle bit is not toggling, the device

has completed the program or erase operation. The

system can read array data on DQ7–DQ0 on the fol-

lowing read cycle.

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is

erase-suspended. When the device is actively erasing

(that is, the Embedded Erase algorithm is in progress),

DQ6 toggles. When the device enters the Erase Sus-

pend mode, DQ6 stops toggling. However, the system

must also use DQ2 to determine which sectors are

erasing or erase-suspended. Alternatively, the system

can use DQ7 (see the subsection on “DQ7: Data#

Polling”).

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should

then determine again whether the toggle bit is tog-

gling, since the toggle bit may have stopped toggling

just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

If a program address falls within a protected sector,

DQ6 toggles for approximately 1 µs after the program

command sequence is written, then returns to reading

array data.

Am29LV800D_00_A7 December 4, 2006

Am29LV800D

21

D A T A S H E E T

program or erase operation. If it is still toggling, the de-

status of DQ3 prior to and following each subsequent

sector erase command. If DQ3 is high on the second

status check, the last command might not have been

accepted. Table 6 shows the outputs for DQ3.

vice did not completed the operation successfully, and

the system must write the reset command to return to

reading array data.

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor

the toggle bit and DQ5 through successive read cy-

cles, determining the status as described in the previ-

ous paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to de-

termine the status of the operation (top of Figure 6).

START

Read DQ7–DQ0

(Note 1)

DQ5: Exceeded Timing Limits

Read DQ7–DQ0

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure

condition that indicates the program or erase cycle

was not successfully completed.

No

Toggle Bit

= Toggle?

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is previously

programmed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the operation

has exceeded the timing limits, DQ5 produces a “1.”

Yes

No

DQ5 = 1?

Yes

Under both these conditions, the system must issue

the reset command to return the device to reading

array data.

(Notes

1, 2)

Read DQ7–DQ0

Twice

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not an

erase operation has begun. (The sector erase timer

does not apply to the chip erase command.) If addi-

tional sectors are selected for erasure, the entire

time-out also applies after each additional sector

erase command. When the time-out is complete, DQ3

switches from “0” to “1.” The system may ignore DQ3

if the system can guarantee that the time between

additional sector erase commands will always be less

than 50 µs. See also the “Sector Erase Command Se-

quence” section.

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

After the sector erase command sequence is written,

the system should read the status on DQ7 (Data# Poll-

ing) or DQ6 (Toggle Bit I) to ensure the device has ac-

cepted the command sequence, and then read DQ3. If

DQ3 is “1”, the internally controlled erase cycle has

begun; all further commands (other than Erase Sus-

pend) are ignored until the erase operation is com-

plete. If DQ3 is “0”, the device will accept additional

sector erase commands. To ensure the command has

been accepted, the system software should check the

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1”. See text.

Figure 6. Toggle Bit Algorithm

22

Am29LV800D

Am29LV800D_00_A7 December 4, 2006

D A T A S H E E T

Table 6. Write Operation Status

DQ7

DQ5

DQ2

Operation

(Note 2)

DQ6

(Note 1)

DQ3

N/A

1

(Note 2)

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

Reading within Erase

Suspended Sector

1

No toggle

0

N/A

Toggle

1

Erase

Suspend

Mode

Reading within Non-Erase

Suspended Sector

Data

0

Data

N/A

Data

N/A

1

0

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

Am29LV800D_00_A7 December 4, 2006

Am29LV800D

23

D A T A S H E E T

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

20 ns

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . . –65°C to +85°C

+0.8 V

Voltage with Respect to Ground

–0.5 V

–2.0 V

V

_CC(Note 1). . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

A9, OE#, and

RESET# (Note 2). . . . . . . . . . . .–0.5 V to +12.5 V

20 ns

All other pins (Note 1) . . . . . .–0.5 V to V_CC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V.

During voltage transitions, input or I/O pins may

undershoot V_SSto –2.0 V for periods of up to 20 ns. See

Figure 7. Maximum DC voltage on input or I/O pins is

Figure 7. Maximum Negative Overshoot

Waveform

V_CC+0.5 V. During voltage transitions, input or I/O pins

may overshoot to V_CC+2.0 V for periods up to 20 ns. See

Figure 8.

2. Minimum DC input voltage on pins A9, OE#, and RESET#

is –0.5 V. During voltage transitions, A9, OE#, and RESET#

may undershoot V_SSto –2.0 V for periods of up to 20 ns.

See Figure 7. Maximum DC input voltage on pin A9 is

+12.5 V which may overshoot to 14.0 V for periods up to 20

ns.

20 ns

V_CC

+2.0 V

V_CC

+0.5 V

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater than

one second.

2.0 V

20 ns

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is

a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

Figure 8. Maximum Positive Overshoot

Waveform

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T_A) . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature (T_A) . . . . . . . . . –40°C to +85°C

V

_CCSupply Voltages

_CCfor regulated voltage range . . . . .+3.0 V to +3.6 V

_CCfor full voltage range . . . . . . . . . .+2.7 V to +3.6 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

24

Am29LV800D

Am29LV800D_00_A7 December 4, 2006

D A T A S H E E T

DC CHARACTERISTICS

CMOS Compatible

Parameter

Description

Test Conditions

V_IN= V_SSto V_CC

Min

Typ

Max

±1.0

35

Unit

µA

,

I_LI

Input Load Current

V_CC= V_{CC max}

I_LIT

I_LO

A9 Input Load Current

Output Leakage Current

V_CC= V_{CC max}; A9 = 12.5 V

µA

V_OUT= V_SSto V_CC

,

±1.0

µA

V_CC= V_{CC max}

5 MHz

1 MHz

5 MHz

1 MHz

7

2

7

2

15

4

CE# = V_IL,OE# ₌V_IH,

Byte Mode

V_CCActive Read Current

(Notes 1, 2)

I_CC1

mA

15

4

CE# = V_IL,OE# ₌V_IH,

Word Mode

V_CCActive Write Current

(Notes 2, 3, 5)

I_CC2

CE# = V_IL,OE# ₌V_IH

15

30

I_CC3

I_CC4

V_CCStandby Current (Note 2)

V_CCReset Current (Note 2)

CE#, RESET# = V_CC±0.3 V

RESET# = V_SS± 0.3 V

0.2

5

µA

Automatic Sleep Mode

(Notes 2, 4)

V_IH= V_CC± 0.3 V;

V_IL= V_SS± 0.3 V

I_CC5

0.2

5

µA

V_IL

V_IH

Input Low Voltage

Input High Voltage

–0.5

0.8

V

0.7 x V_CC

V_CC+ 0.3

Voltage for Autoselect and

Temporary Sector Unprotect

V_ID

V_CC= 3.3 V

11.5

12.5

0.45

V

V_OL

V_OH1

V_OH2

Output Low Voltage

I_OL= 4.0 mA, V_CC= V_{CC min}

V

I

_OH= –2.0 mA, V_CC= V_{CC min}

0.85 V_CC

V_CC–0.4

Output High Voltage

I_OH= –100 µA, V_CC= V_{CC min}

Low V_CCLock-Out Voltage

(Note 4)

V_LKO

2.3

2.5

V

Notes:

1. The I_CCcurrent listed is typically less than 2 mA/MHz, with OE# at V_IH. Typical V_CCis 3.0 V.

2. Maximum I_CCspecifications are tested with V_CC= V_CCmax

.

3. I_CCactive while Embedded Erase or Embedded Program is in progress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for t_ACC+ 30 ns.

5. Not 100% tested.

Am29LV800D_00_A7 December 4, 2006

Am29LV800D

25

D A T A S H E E T

DC CHARACTERISTICS (Continued)

Zero Power Flash

20

15

10

5

0

500

1000

1500

2000

2500

3000

3500

4000

Time in ns

Note: Addresses are switching at 1 MHz

Figure 9. I_CC1Current vs. Time (Showing Active and Automatic Sleep Currents)

10

8

3.6 V

2.7 V

6

4

2

0

1

2

3

4

5

Frequency in MHz

Note: T = 25 °C

Figure 10. Typical I_CC1vs. Frequency

26

Am29LV800D

Am29LV800D_00_A7 December 4, 2006

D A T A S H E E T

TEST CONDITIONS

Table 7. Test Specifications

-90,

3.3

Test Condition

-70

-120

Unit

2.7 kΩ

Output Load

1 TTL gate

Device

Under

Test

Output Load Capacitance, C_L

(including jig capacitance)

30

100

5

pF

C

L

6.2 kΩ

Input Rise and Fall Times

Input Pulse Levels

ns

V

0.0–3.0

Input timing measurement

reference levels

1.5

V

Output timing measurement

reference levels

Note: Diodes are IN3064 or equivalent

Figure 11. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

3.0 V

0.0 V

1.5 V

Input

Measurement Level

Output

Figure 12. Input Waveforms and

Measurement Levels

Am29LV800D_00_A7 December 4, 2006

Am29LV800D

27

D A T A S H E E T

AC CHARACTERISTICS

Read Operations

Parameter

Speed Options

JEDEC

Std

Description

Read Cycle Time (Note 1)

Test Setup

-70

-90

-120 Unit

t_AVAV

t_RC

Min

70

90

120

ns

CE# = V_IL

OE# = V_IL

t_AVQV

t_ACCAddress to Output Delay

Max

70

90

120

ns

t_ELQV

t_GLQV

t_EHQZ

t_GHQZ

t_CE

t_OE

t_DF

Chip Enable to Output Delay

OE# = V_IL

Max

Min

70

30

25

90

35

30

0

120

50

ns

Output Enable to Output Delay

Chip Enable to Output High Z (Note 1)

Output Enable to Output High Z (Note 1)

30

Read

Output Enable

Hold Time (Note 1)

t_OEH

Toggle and

Data# Polling

Min

10

0

ns

Output Hold Time From Addresses, CE# or OE#,

Whichever Occurs First (Note 1)

t_AXQX

t_OH

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 7 for test specifications.

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

Figure 13. Read Operations Timings

28

Am29LV800D

Am29LV800D_00_A7 December 4, 2006

D A T A S H E E T

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std

Description

Test Setup

Max

All Speed Options

Unit

RESET# Pin Low (During Embedded

Algorithms) to Read or Write (See Note)

t_READY

20

µs

RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (See Note)

t_READY

Max

500

ns

t_RP

t_RH

RESET# Pulse Width

Min

500

50

20

0

ns

µs

ns

RESET# High Time Before Read (See Note)

t_RPDRESET# Low to Standby Mode

t_RBRY/BY# Recovery Time

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

Figure 14. RESET# Timings

Am29LV800D_00_A7 December 4, 2006

Am29LV800D

29

D A T A S H E E T

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

Speed Options

JEDEC

Std

t_{ELFL/ ELFH}

t_FLQZ

Description

-70

-90

5

-120

Unit

ns

t

CE# to BYTE# Switching Low or High

BYTE# Switching Low to Output HIGH Z

BYTE# Switching High to Output Active

Max

Min

25

70

30

90

30

ns

t_FHQV

120

ns

CE#

OE#

BYTE#

t_ELFL

Data Output

(DQ0–DQ14)

Data Output

(DQ0–DQ7)

BYTE#

Switching

DQ0–DQ14

from word

to byte

Address

Input

DQ15

Output

mode

DQ15/A-1

t_FLQZ

t_ELFH

BYTE#

Switching

from byte

to word

Data Output

(DQ0–DQ7)

Data Output

(DQ0–DQ14)

DQ0–DQ14

DQ15/A-1

mode

Address

Input

DQ15

Output

t_FHQV

Figure 15. BYTE# Timings for Read Operations

CE#

The falling edge of the last WE# signal

WE#

BYTE#

t_SET

(t_AS

)

t_HOLD(t_AH

)

Note: Refer to the Erase/Program Operations table for t_ASand t_AHspecifications.

Figure 16. BYTE# Timings for Write Operations

30

Am29LV800D

Am29LV800D_00_A7 December 4, 2006

D A T A S H E E T

AC CHARACTERISTICS

Erase/Program Operations

Parameter

Speed Options

JEDEC

t_AVAV

Std

t_WC

t_AS

Description

Write Cycle Time (Note 1)

-70

-90

90

0

-120

Unit

ns

Min

70

120

t_AVWL

t_WLAX

t_DVWH

t_WHDX

Address Setup Time

Address Hold Time

Data Setup Time

ns

t_AH

45

35

45

0

50

ns

t_DS

ns

t_DH

t_OES

Data Hold Time

ns

Output Enable Setup Time

0

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHWL

Min

0

ns

t_ELWL

t_WHEH

t_WLWH

t_WHWL

t_CS

t_CH

CE# Setup Time

Min

Typ

Min

Max

0

ns

CE# Hold Time

t_WP

Write Pulse Width

Write Pulse Width High

35

30

8

50

t_WPH

Byte

t_WHWH1

t_WHWH2

t_WHWH1Programming Operation (Note 2)

µs

Word

16

1

t_WHWH2Sector Erase Operation (Note 2)

sec

µs

t_VCS

t_RB

V_CCSetup Time (Note 1)

50

0

Recovery Time from RY/BY#

ns

t_BUSYProgram/Erase Valid to RY/BY# Delay

90

ns

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Am29LV800D_00_A7 December 4, 2006

Am29LV800D

31

D A T A S H E E T

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

PA

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D_OUTis the true data at the program address.

2. Illustration shows device in word mode.

Figure 17. Program Operation Timings

32

Am29LV800D

Am29LV800D_00_A7 December 4, 2006

D A T A S H E E T

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

2. Illustration shows device in word mode.

Figure 18. Chip/Sector Erase Operation Timings

Am29LV800D_00_A7 December 4, 2006

Am29LV800D

33

D A T A S H E E T

AC CHARACTERISTICS

t_RC

VA

Addresses

VA

t_ACC

t_CE

CE#

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

Status Data

True

DQ0–DQ6

Valid Data

Status Data

True

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

Figure 19. Data# Polling Timings (During Embedded Algorithms)

t_RC

Addresses

CE#

VA

t_ACC

t_CE

VA

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ6/DQ2

RY/BY#

Valid Status

(first read)

Valid Status

Valid Data

(second read)

(stops toggling)

t_BUSY

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle.

Figure 20. Toggle Bit Timings (During Embedded Algorithms)

34

Am29LV800D

Am29LV800D_00_A7 December 4, 2006

D A T A S H E E T

AC CHARACTERISTICS

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an

erase-suspended sector.

Figure 21. DQ2 vs. DQ6

Temporary Sector Unprotect

Parameter

JEDEC

Std

Description

All Speed Options

Unit

t_VIDR

V_IDRise and Fall Time (See Note)

Min

500

ns

RESET# Setup Time for Temporary Sector

Unprotect

t_RSP

4

µs

Note: Not 100% tested.

12 V

RESET#

0 or 3 V

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RSP

RY/BY#

Figure 22. Temporary Sector Unprotect

Timing Diagram

Am29LV800D_00_A7 December 4, 2006

Am29LV800D

35

D A T A S H E E T

AC CHARACTERISTICS

V_ID

V_IH

RESET#

SA, A6,

A1, A0

Valid*

Sector Protect/Unprotect

60h 60h

Valid*

Status

Verify

40h

Data

Sector Protect: 150 µs

Sector Unprotect: 15 ms

1 µs

CE#

WE#

OE#

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 23. Sector Protect/Unprotect

Timing Diagram

36

Am29LV800D

Am29LV800D_00_A7 December 4, 2006

D A T A S H E E T

AC CHARACTERISTICS

Alternate CE# Controlled

Erase/Program Operations

Parameter

Speed Options

JEDEC

t_AVAV

Std

t_WC

t_AS

Description

-70

-90

90

0

-120

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min

70

120

t_AVEL

ns

t_ELAX

t_AH

45

35

45

0

50

ns

t_DVEH

t_EHDX

t_DS

ns

t_DH

t_OES

Data Hold Time

ns

Output Enable Setup Time

0

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

0

ns

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_WS

t_WH

t_CP

WE# Setup Time

WE# Hold Time

Min

Typ

0

ns

CE# Pulse Width

CE# Pulse Width High

35

30

8

50

t_CPH

Byte

Programming Operation

(Note 2)

t_WHWH1

t_WHWH2

Notes:

t_WHWH1

t_WHWH2

µs

Word

16

1

Sector Erase Operation (Note 2)

sec

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Am29LV800D_00_A7 December 4, 2006

Am29LV800D

37

D A T A S H E E T

AC CHARACTERISTICS

555 for program

PA for program

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, D_OUT= data written to the

device.

2. Figure indicates the last two bus cycles of command sequence.

3. Word mode address used as an example.

Figure 24. Alternate CE# Controlled Write Operation Timings

38

Am29LV800D

Am29LV800D_00_A7 December 4, 2006

D A T A S H E E T

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1)

Max (Note 2)

Unit

s

Comments

Sector Erase Time

Chip Erase Time

1

10

Excludes 00h programming

prior to erasure

14

8

s

Byte Programming Time

Word Programming Time

300

360

25

µs

s

16

8.4

5.8

Excludes system level overhead

(Note 5)

Byte Mode

Word Mode

Chip Programming Time

(Note 3)

17

s

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V_CC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V_CC= 2.7 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 5

for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V_SSon all pins except I/O pins

(including A9, OE#, and RESET#)

–1.0 V

12.5 V

Input voltage with respect to V_SSon all I/O pins

–1.0 V

V_CC+ 1.0 V

+100 mA

V_CCCurrent

–100 mA

Includes all pins except V_CC. Test conditions: V_CC= 3.0 V, one pin at a time.

TSOP AND SO PIN CAPACITANCE

Parameter

Symbol

Parameter Description

Input Capacitance

Test Setup

V_IN= 0

Typ

6

Max

7.5

12

Unit

pF

C_IN

C_OUT

C_IN2

Output Capacitance

Control Pin Capacitance

V_OUT= 0

V_IN= 0

8.5

7.5

pF

9

pF

Notes:

1. Sampled, not 100% tested.

2. Test conditions T_A= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter

Test Conditions

Min

10

Unit

Years

150°C

125°C

Minimum Pattern Data Retention Time

20

Am29LV800D_00_A7 December 4, 2006

Am29LV800D

39

D A T A S H E E T

PHYSICAL DIMENSIONS*

TS 048—48-Pin Standard TSOP

Dwg rev AA; 10/99

* For reference only. BSC is an ANSI standard for Basic

Space Centering.

40

Am29LV800D

Am29LV800D_00_A7 December 4, 2006

D A T A S H E E T

PHYSICAL DIMENSIONS

FBB 048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 9 mm

Dwg rev AF; 10/99

Am29LV800D_00_A7 December 4, 2006

Am29LV800D

41

D A T A S H E E T

PHYSICAL DIMENSIONS

VBK 048 - 48 Ball Fine-Pitch Ball Grid Array (FBGA) 6.15 x 8.15 mm

0.10 (4X)

D1

A

D

6

5

4

3

2

1

7

e

SE

E1

E

H

G

F

E

D

C

B

A

INDEX MARK

10

6

B

A1 CORNER

PIN A1

CORNER

7

fb

SD

f 0.08 M

C

TOP VIEW

f 0.15 M C A B

BOTTOM VIEW

0.10 C

0.08 C

A2

A

SEATING PLANE

SIDE VIEW

C

A1

NOTES:

PACKAGE

JEDEC

VBK 048

N/A

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

6.15 mm x 8.15 mm NOM

PACKAGE

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT

AS NOTED).

SYMBOL

MIN

---

NOM

MAX

1.00 OVERALL THICKNESS

--- BALL HEIGHT

NOTE

4.

e

REPRESENTS THE SOLDER BALL GRID PITCH.

A

A1

A2

D

---

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE

"D" DIRECTION.

0.18

0.62

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE

"E" DIRECTION.

---

0.76 BODY THICKNESS

BODY SIZE

8.15 BSC.

6.15 BSC.

5.60 BSC.

4.00 BSC.

8

N IS THE TOTAL NUMBER OF SOLDER BALLS.

E

BODY SIZE

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

D1

E1

BALL FOOTPRINT

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER

SOLDER BALL IN THE OUTER ROW.

MD

ME

N

ROW MATRIX SIZE D DIRECTION

ROW MATRIX SIZE E DIRECTION

TOTAL BALL COUNT

6

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN

THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,

RESPECTIVELY, SD OR SE = 0.000.

48

fb

0.33

---

0.43 BALL DIAMETER

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN

THE OUTER ROW, SD OR SE = e/2

e

0.80 BSC.

0.40 BSC.

---

BALL PITCH

SD / SE

SOLDER BALL PLACEMENT

DEPOPULATED SOLDER BALLS

8. NOT USED.

9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

3338 \ 16-038.25b

42

Am29LV800D

Am29LV800D_00_A7 December 4, 2006

D A T A S H E E T

PHYSICAL DIMENSIONS

SO 044—44-Pin Small Outline Package

Dwg rev AC; 10/99

Am29LV800D_00_A7 December 4, 2006

Am29LV800D

43

D A T A S H E E T

REVISION SUMMARY

Revision A (January 19, 2004)

Revision A+3 (June 23, 2004)

Changed data sheet status to Advance Information to

indicate new 0.23 µm process technology. The base

device part number has changed from Am29LV800B

Global change

Changed all Helvetica/Times Roman fonts to Gill Sans

For AMD or Verdana.

to Am29LV800D. Specifications for I_CC1, t_WHWH1

,

t_WHWH2have changed. Extended temperature is no

longer available. All other specifications in the data

sheet remain unchanged. Deleted references to KGD

option in Connection Diagrams section. (This docu-

ment was formerly released as publication 21490, revi-

sion H.)

“Physical Dimensions” on page 45

Added VBK048 Package Drawing.

“Ordering Information” on page 10

Added “WC =...” to Standard Products table.

Added “WCC, WCI, WCD, WCF” to Valid combinations

table.

Revision A+1 (February 3, 2004)

Added Colophon.

Distinctive Characteristics, General Description,

Ordering Information

Revision A+4 (January 21, 2005)

Added migration statement.

Deleted references to KGD option. (This document

was formerly released as publication 21490, revision

H1.)

Revision A5 (February 16, 2006)

Revision A+2 (April 2, 2004)

Updated migration statement on cover page and first

page of data sheet.

General Description

Removed Reverse TSOP material.

Updated trademarks.

Removed unlock bypass section.

Global

Converted datasheet to Preliminary.

Revision A6 (May 5, 2006)

Ordering Information

Updated migration/obsolescence statement on cover

page and first page of data sheet.

Added Pb-Free packages and updated Valid Combina-

tions tables to include changes.

Revision A7 (December 4, 2006)

Absolute Maximum Rating

AC Characteristics

Changed ambient with power applied from 125°C to

85°C.

Erase and Program Operations table: Changed t_BUSY

to a maximum specification.

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-

tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-

templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the

public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,

aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for

any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable

to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor

devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design

measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating

conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign

Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-

thorization by the respective government entity will be required for export of those products.

Trademarks

marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are

for identification purposes only and may be trademarks of their respective companies.

trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.

44

Am29LV800D

Am29LV800D_00_A7 December 4, 2006


型号：	AM29LV800DB120SC
厂家：	SPANSION
描述：	8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory 8兆位（ 1一M× 8位/ 512的K× 16位） CMOS 3.0伏只引导扇区闪存闪存
文件：	总46页 (文件大小：1037K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM29LV800DB120SC [SPANSION]

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