AM29LV128ML112PCI [SPANSION]

Flash, 8MX16, 110ns, PBGA64, 13 X 11 MM, 1 MM PITCH, FBGA-64;


型号：	AM29LV128ML112PCI
厂家：	SPANSION
描述：	Flash, 8MX16, 110ns, PBGA64, 13 X 11 MM, 1 MM PITCH, FBGA-64
文件：	总10页 (文件大小：273K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADVANCE INFORMATION

Am29LV128M

128 Megabit (8 M x 16-Bit/16 M x 8-Bit) MirrorBit 3.0 Volt-only

Uniform Sector Flash Memory with VersatileI/O Control

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

— 4-word/8-byte page read buffer

— 16-word/32-byte write buffer

■ Single power supply operation

— 3 volt read, erase, and program operations

■ Low power consumption (typical values at 3.0 V, 5

MHz)

■ VersatileI/O control

— 30 mA typical active read current

— 50 mA typical erase/program current

— 1 µA typical standby mode current

— Device generates and tolerates voltages on CE# and

DQ I/O as determined by the voltage on the V_IOpin;

operates from 1.65 to 3.6 V

■ Manufactured on 0.23 µm MirrorBit process

■ Package options

— 56-pin TSOP

technology

■ SecSi (Secured Silicon) Sector region

— 64-ball Fortified BGA

— 128-word/256-byte sector for permanent, secure

identification through an 8-word/16-byte random

Electronic Serial Number, accessible through a

command sequence

SOFTWARE & HARDWARE FEATURES

■ Software features

— Program Suspend & Resume: read other sectors

before programming operation is completed

— May be programmed and locked at the factory or by

the customer

— Erase Suspend & Resume: read/program other

sectors before an erase operation is completed

■ Flexible sector architecture

— Data# polling & toggle bits provide status

— Two hundred fifty-six 32 Kword (64 Kbyte) sectors

— Unlock Bypass Program command reduces overall

■ Compatibility with JEDEC standards

multiple-word or byte programming time

— Provides pinout and software compatibility for

single-power supply flash, and superior inadvertent

write protection

— CFI (Common Flash Interface) compliant: allows host

system to identify and accommodate multiple flash

devices

■ Minimum 100,000 erase cycle guarantee per sector

■ 20-year data retention at 125°C

■ Hardware features

— Sector Group Protection: hardware-level method of

preventing write operations within a sector group

PERFORMANCE CHARACTERISTICS

■ High performance

— Temporary Sector Unprotect: V_ID-level method of

changing code in locked sectors

— 90 ns access time

— WP#/ACC input accelerates programming time

(when high voltage is applied) for greater throughput

during system production. Protects first or last sector

regardless of sector protection settings

— 25 ns page read times

— 0.4 s typical sector erase time

— 5.9 µs typical write buffer word programming time:

16-word/32-byte write buffer reduces overall

programming time for multiple-word updates

— Hardware reset input (RESET#) resets device

— Ready/Busy# output (RY/BY#) detects program or

erase cycle completion

Publication# 25270 Rev: A Amendment/+2

Issue Date: April 26, 2002

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data

Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Refer to AMD’s Website (www.amd.com) for the latest information.

A D V A N C E I N F O R M A T I O N

GENERAL DESCRIPTION

The Am29LV128M is a 128 Mbit, 3.0 volt single power

supply flash memory devices organized as 8,388,608

words or 16,777,216 bytes. The device has a 16-bit

wide data bus that can also function as an 8-bit wide

data bus by using the BYTE# input. The device can be

programmed either in the host system or in standard

EPROM programmers.

and tolerates voltages on CE# and DQ I/Os to the

same voltage level that is asserted on the V_IOpin. This

allows the device to operate in a 1.8 V or 3 V system

environment as required.

Hardware data protection measures include a low

V_CCdetector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of sectors of memory.

This can be achieved in-system or via programming

equipment.

An access time of 90, 100, 110, or 120 ns is available.

Note that each access time has a specific operating

voltage range (V_CC) and an I/O voltage range (V_IO), as

specified in the Product Selector Guide and the Order-

ing Information sections. The device is offered in a

56-pin TSOP or Fortified BGA package. Each device

has separate chip enable (CE#), write enable (WE#)

and output enable (OE#) controls.

The Erase Suspend/Erase Resume feature allows

the host system to pause an erase operation in a

given sector to read or program any other sector and

then complete the erase operation. The Program

Suspend/Program Resume feature enables the host

system to pause a program operation in a given sector

to read any other sector and then complete the pro-

gram operation.

Each device requires only a single 3.0 volt power

supply for both read and write functions. In addition to

a V_CCinput, a high-voltage accelerated program

(WP#/ACC) input provides shorter programming times

through increased current. This feature is intended to

facilitate factory throughput during system production,

but may also be used in the field if desired.

The hardware RESET# pin terminates any operation

in progress and resets the device, after which it is then

ready for a new operation. The RESET# pin may be

tied to the system reset circuitry. A system reset would

thus also reset the device, enabling the host system to

read boot-up firmware from the Flash memory device.

The device is entirely command set compatible with

the JEDEC single-power-supply Flash standard.

Commands are written to the device using standard

microprocessor write timing. Write cycles also inter-

nally latch addresses and data needed for the pro-

gramming and erase operations.

The device reduces power consumption in the

standby mode when it detects specific voltage levels

on CE# and RESET#, or when addresses have been

stable for a specified period of time.

The sector erase architecture allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

The SecSi (Secured Silicon) Sector provides a

128-word/256-byte area for code or data that can be

permanently protected. Once this sector is protected,

no further changes within the sector can occur.

Device programming and erasure are initiated through

command sequences. Once a program or erase oper-

ation has begun, the host system need only poll the

DQ7 (Data# Polling) or DQ6 (toggle) status bits or

monitor the Ready/Busy# (RY/BY#) output to deter-

mine whether the operation is complete. To facilitate

programming, an Unlock Bypass mode reduces com-

mand sequence overhead by requiring only two write

cycles to program data instead of four.

The Write Protect (WP#/ACC) feature protects the

first or last sector by asserting a logic low on the WP#

pin.

AMD MirrorBit flash technology combines years of

Flash memory manufacturing experience to produce

the highest levels of quality, reliability and cost effec-

tiveness. The device electrically erases all bits within a

sector simultaneously via hot-hole assisted erase. The

data is programmed using hot electron injection.

The VersatileI/O™ (V_IO) control allows the host sys-

tem to set the voltage levels that the device generates

Am29LV128M

A D V A N C E I N F O R M A T I O N

PRODUCT SELECTOR GUIDE

Part Number

Am29LV128M

90R

V_CC= 3.0–3.6 V

V_CC= 2.7–3.6 V

(V_IO= 3.0–3.6 V)

Speed

Option

101

112

120

(V_IO= 2.7–3.6 V)

(V_IO= 1.65–3.6 V)

Max. Access Time (ns)

100

110

120

Max. CE# Access Time (ns)

Max. Page access time (t_PACC

Max. OE# Access Time (ns)

)

BLOCK DIAGRAM

DQ0–DQ15 (A-1)

RY/BY#

V_CC

Sector Switches

V_SS

V_IO

Erase Voltage

Generator

Input/Output

Buffers

RESET#

WE#

State

WP#/ACC

Control

BYTE#

Command

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

Y-Gating

STB

V_CCDetector

Timer

Cell Matrix

X-Decoder

A22–A0

Am29LV128M

A D V A N C E I N F O R M A T I O N

CONNECTION DIAGRAMS

A22

A15

A14

A13

A12

A11

A10

56 NC

55 NC

54 A16

53 BYTE#

52 V_SS

51 DQ15/A-1

50 DQ7

49 DQ14

48 DQ6

47 DQ13

46 DQ5

45 DQ12

44 DQ4

43 V_CC

42 DQ11

41 DQ3

40 DQ10

39 DQ2

38 DQ9

37 DQ1

36 DQ8

35 DQ0

34 OE#

33 V_SS

56-Pin Standard TSOP

A8 10

A19 11

A20 12

WE# 13

RESET# 14

A21 15

WP#/ACC 16

RY/BY# 17

A18 18

A17 19

A7 20

A6 21

A5 22

A4 23

A3 24

A2 25

32 CE#

31 A0

30 NC

29 V_IO

A1 26

NC 27

NC 28

56 NC

55 A22

54 A15

53 A14

52 A13

51 A12

50 A11

49 A10

48 A9

A16

BYTE#

V_SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13 10

DQ5 11

DQ12 12

DQ4 13

V_CC14

DQ11 15

DQ3 16

DQ10 17

DQ2 18

DQ9 19

DQ1 20

DQ8 21

DQ0 22

OE# 23

V_SS24

47 A8

46 A19

45 A20

44 WE#

43 RESET#

42 A21

41 WP#/ACC

40 RY/BY#

39 A18

38 A17

37 A7

56-Pin Reverse TSOP

36 A6

35 A5

34 A4

33 A3

CE# 25

A0 26

32 A2

31 A1

NC 27

30 NC

V_IO28

29 NC

Am29LV128M

A D V A N C E I N F O R M A T I O N

CONNECTION DIAGRAMS

Fortified BGA

Top View, Balls Facing Down

A22

V_IO

V_SS

A13

A12

A14

A15

A16

BYTE# DQ15/A-1

A10

A11

DQ7

DQ14

DQ13

DQ6

V_CC

WE# RESET#

A21

A19

DQ5

DQ12

DQ4

A4 B4

RY/BY# WP#/ACC A18

A20

DQ2

DQ10

DQ11

DQ3

A17

DQ0

DQ8

DQ9

DQ1

V_SS

CE#

OE#

V_IO

Note: The FBGA package pinout configuration shown is preliminary. The ball count and package physical dimensions have not

yet been determined. Contact AMD for further information.

compromised if the package body is exposed to

temperatures above 150°C for prolonged periods of

Special Package Handling Instructions

Special handling is required for Flash Memory products

time.

in molded packages (TSOP, BGA, SSOP, PLCC,

PDIP). The package and/or data integrity may be

Am29LV128M

A D V A N C E I N F O R M A T I O N

PIN DESCRIPTION

LOGIC SYMBOL

A22–A0

= 23 Address inputs

DQ14–DQ0 = 15 Data inputs/outputs

A22–A0

16 or 8

DQ15/A-1

= DQ15 (Data input/output, word mode),

DQ15–DQ0

CE#

(A-1)

A-1 (LSB Address input, byte mode)

OE#

CE#

OE#

WE#

= Chip Enable input

WE#

= Output Enable input

WP#/ACC

RESET#

V_IO

= Write Enable input

WP#/ACC = Hardware Write Protect input;

Acceleration input

RY/BY#

RESET#

BYTE#

RY/BY#

V_CC

= Hardware Reset Pin input

= Selects 8-bit or 16-bit mode

= Ready/Busy output

BYTE#

= 3.0 volt-only single power supply

(see Product Selector Guide for

speed options and voltage

supply tolerances)

V_IO

V_SS

= Output Buffer power

= Device Ground

= Pin Not Connected Internally

Am29LV128M

A D V A N C E I N F O R M A T I O N

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of the following:

Am29LV128M

90R

TEMPERATURE RANGE

Industrial (–40°C to +85°C)

PACKAGE TYPE

56-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 056)

56-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR056)

64-Ball Fortified Ball Grid Array (FBGA),

13 x 11 mm, 1.0 mm pitch (LAA064)

SPEED OPTION

See Product Selector Guide and Valid Combinations

SECTOR ARCHITECTURE AND SECTOR WRITE PROTECTION (WP# = V_IL)

Uniform sector device, highest address sector protected

Uniform sector device, lowest address sector protected

DEVICE NUMBER/DESCRIPTION

Am29LV128MH/L

128 Megabit (8 M x 16-Bit/16 M x 8-Bit) MirrorBit Uniform Sector Flash Memory with VersatileIO Control

3.0 Volt-only Read, Program, and Erase

Valid Combinations for

TSOP Package

Speed(

ns)

V_IO

Range

V_CC

Range

Valid Combinations for

Fortified BGA Package

Speed

(ns)

V_IO

V_CC

Range Range

Am29LV128MH90R,

Am29LV128ML90R

Order Number

Package Marking

3.0–3.6 V

2.7–3.6 V

1.65–3.6 V

3.0–3.6 V

Am29LV128MH90R,

Am29LV128ML90R

L128MH90R,

L128ML90R

3.0–

3.6 V

3.0–

3.6 V

Am29LV128MH101,

100

110

120

Am29LV128ML101

EI,

Am29LV128MH101,

Am29LV128ML101

L128MH01V,

L128ML01V

2.7–

3.6 V

100

110

120

Am29LV128MH112,

Am29LV128ML112

2.7–3.6 V

PCI

Am29LV128MH112,

Am29LV128ML112

L128MH11V,

L128ML11V

1.65–

3.6 V

2.7–

3.6 V

Am29LV128MH120,

Am29LV128ML120

Am29LV128MH120,

Am29LV128ML120

L128MH12V,

L128ML12V

1.65–

3.6 V

Valid Combinations

Valid Combinations list configurations planned to be supported in vol-

ume for this device. Consult the local AMD sales office to confirm

availability of specific valid combinations and to check on newly re-

leased combinations.

Am29LV128M

A D V A N C E I N F O R M A T I O N

PHYSICAL DIMENSIONS

TS056/TSR056—56-Pin Standard/Reverse Thin Small Outline Package (TSOP)

NOTES:

PACKAGE

TS/TSR 56

JEDEC

MO-142 (B) EC

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).

(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982.)

SYMBOL

MIN.

---

NOM.

---

MAX.

1.20

0.15

1.05

0.23

0.27

0.16

0.21

PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).

PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.

0.05

0.95

0.17

0.10

---

1.00

0.20

0.22

---

TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS

DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE

LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.

DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE

MOLD PROTUSION IS 0.15 mm PER SIDE.

---

DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE

DAMBAR PROTUSION SHALL BE 0.08 mm TOTAL IN EXCESS OF b

DIMENSION AT MAX MATERIAL CONDITION. MINIMUM SPACE BETWEEN

PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 mm.

19.90

18.30

20.00

18.40

20.20

18.50

13.90

14.00

14.10

THESE DIMESIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN

0.10 mm AND 0.25 mm FROM THE LEAD TIP.

0.50 BASIC

0.50

0˚

0.60

3˚

0.70

5˚

8. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE

SEATING PLANE.

0.08

---

0.20

DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.

3160\38.10A

Am29LV128M

A D V A N C E I N F O R M A T I O N

PHYSICAL DIMENSIONS

LAA064—64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm Package

Am29LV128M

A D V A N C E I N F O R M A T I O N

Physical Dimensions

REVISION SUMMARY

Revision A (October 3, 2001)

Added drawing that shows both TS056 and TSR056

specifications.

Initial release as abbreviated Advance Information

data sheet.

Revision A+2 (April 26, 2002)

Revision A+1 (March 20, 2002)

Distinctive Characteristics

Disitinctive Characteristics

Deleted “Enhanced” from VersatileIO and mofified

decscription.

Clarified description of Enhanced VersatileIO control.

Ordering Information

Corrected device density in device number/descrip-

tion.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Am29LV128M

AM29LV128ML112PCI [SPANSION]

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