AM29LV128MH129PCF [SPANSION]
Flash, 8MX16, 120ns, PBGA64, 13 X 11 MM, 1 MM PITCH, FORTIFIED, BGA-64;型号: | AM29LV128MH129PCF |
厂家: | SPANSION |
描述: | Flash, 8MX16, 120ns, PBGA64, 13 X 11 MM, 1 MM PITCH, FORTIFIED, BGA-64 内存集成电路 |
文件: | 总57页 (文件大小:1136K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ADVANCE INFORMATION
Am29LV128M
128 Megabit (8 M x 16-Bit/16 M x 8-Bit) MirrorBit 3.0 Volt-only
Uniform Sector Flash Memory with Enhanced VersatileI/O Control
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
— 4-word/8-byte page read buffer
— 16-word/32-byte write buffer
■ Single power supply operation
— 3 volt read, erase, and program operations
■ Low power consumption (typical values at 3.0 V, 5
MHz)
■ Enhanced VersatileI/O control
— 30 mA typical active read current
— 50 mA typical erase/program current
— 1 µA typical standby mode current
— Device generates and tolerates voltages on all I/Os
and control inputs as determined by the voltage on the
VIO pin; operates from 1.65 to 3.6 V (see page 8)
■ Manufactured on 0.23 µm MirrorBit process
■ Package options
— 56-pin TSOP
technology
■ SecSi (Secured Silicon) Sector region
— 64-ball Fortified BGA
— 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
SOFTWARE & HARDWARE FEATURES
■ Software features
— Program Suspend & Resume: read other sectors
before programming operation is completed
— May be programmed and locked at the factory or by
the customer
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
■ Flexible sector architecture
— Data# polling & toggle bits provide status
— Two hundred fifty-six 32 Kword (64 Kbyte) sectors
— Unlock Bypass Program command reduces overall
multiple-word or byte programming time
■ Compatibility with JEDEC standards
— Provides pinout and software compatibility for
single-power supply flash, and superior inadvertent
write protection
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
■ Minimum 100,000 erase cycle guarantee per sector
■ 20-year data retention at 125°C
■ Hardware features
— Sector Protection: hardware-level method of
preventing write operations within a sector
PERFORMANCE CHARACTERISTICS
■ High performance
— Temporary Sector Unprotect: VID-level method of
changing code in locked sectors
— 90 ns access time
— WP#/ACC input accelerates programming time
(when high voltage is applied) for greater throughput
during system production. Protects first or last sector
regardless of sector protection settings
— 25 ns page read times
— 0.4 s typical sector erase time
— 5.9 µs typical write buffer word programming time:
16-word/32-byte write buffer reduces overall
programming time for multiple-word updates
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) detects program or
erase cycle completion
Publication# 25270 Rev: B Amendment/0
Issue Date: July 1, 2002
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
A D V A N C E I N F O R M A T I O N
GENERAL DESCRIPTION
The Am29LV128M is a 128 Mbit, 3.0 volt single power
supply flash memory devices organized as 8,388,608
words or 16,777,216 bytes. The device has a 16-bit
wide data bus that can also function as an 8-bit wide
data bus by using the BYTE# input. The device can be
programmed either in the host system or in standard
EPROM programmers.
generates and tolerates on all I/Os and control inputs
to the same voltage level that is asserted on the VIO
pin. This allows the device to operate in a 1.8 V or 3 V
system environment as required.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
An access time of 90, 100, 110, or 120 ns is available.
Note that each access time has a specific operating
voltage range (VCC) and an I/O voltage range (VIO), as
specified in the Product Selector Guide and the Order-
ing Information sections. The device is offered in a
56-pin TSOP or 64-ball Fortified BGA package. Each
device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
The Erase Suspend/Erase Resume feature allows
the host system to pause an erase operation in a
given sector to read or program any other sector and
then complete the erase operation. The Program
Suspend/Program Resume feature enables the host
system to pause a program operation in a given sector
to read any other sector and then complete the pro-
gram operation.
Each device requires only a single 3.0 volt power
supply for both read and write functions. In addition to
a VCC input, a high-voltage accelerated program
(WP#/ACC) input provides shorter programming times
through increased current. This feature is intended to
facilitate factory throughput during system production,
but may also be used in the field if desired.
The hardware RESET# pin terminates any operation
in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would
thus also reset the device, enabling the host system to
read boot-up firmware from the Flash memory device.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the device using standard
microprocessor write timing. Write cycles also inter-
nally latch addresses and data needed for the pro-
gramming and erase operations.
The device reduces power consumption in the
standby mode when it detects specific voltage levels
on CE# and RESET#, or when addresses have been
stable for a specified period of time.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
The SecSi (Secured Silicon) Sector provides a
128-word/256-byte area for code or data that can be
permanently protected. Once this sector is protected,
no further changes within the sector can occur.
Device programming and erasure are initiated through
command sequences. Once a program or erase oper-
ation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle) status bits or
monitor the Ready/Busy# (RY/BY#) output to deter-
mine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces com-
mand sequence overhead by requiring only two write
cycles to program data instead of four.
The Write Protect (WP#/ACC) feature protects the
first or last sector by asserting a logic low on the WP#
pin.
AMD MirrorBit flash technology combines years of
Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effec-
tiveness. The device electrically erases all bits within a
sector simultaneously via hot-hole assisted erase. The
data is programmed using hot electron injection.
The Enhanced VersatileI/O™ (VIO) control allows the
host system to set the voltage levels that the device
RELATED DOCUMENTS
For a comprehensive information on MirrorBit prod-
ucts, including migration information, data sheets, ap-
plication notes, and software drivers, please see
www.amd.com→Flash Memory→Product Informa-
tion→MirrorBit→Flash Information→Technical Docu-
mentation. The following is a partial list of documents
closely related to this product:
MirrorBit™ Flash Memory Write Buffer Programming
and Page Buffer Read
Implementing a Common Layout for AMD MirrorBit
and Intel StrataFlash Memory Devices
Migrating from Single-byte to Three-byte Device IDs
Am29LV256M, 256 Mbit MirrorBit Flash device
(in 64-ball, 18 x 12 mm Fortified BGA package)
2
Am29LV128M
July 1, 2002
A D V A N C E I N F O R M A T I O N
TABLE OF CONTENTS
Figure 6. Erase Operation .............................................................. 32
Command Definitions ............................................................. 33
Table 9. Command Definitions (x16 Mode, BYTE# = VIH) ............. 33
Table 10. Command Definitions (x8 Mode, BYTE# = VIL).............. 34
Write Operation Status. . . . . . . . . . . . . . . . . . . . . 35
DQ7: Data# Polling ................................................................. 35
Figure 7. Data# Polling Algorithm .................................................. 35
RY/BY#: Ready/Busy# ............................................................36
DQ6: Toggle Bit I .................................................................... 36
Figure 8. Toggle Bit Algorithm ........................................................ 37
DQ2: Toggle Bit II ................................................................... 37
Reading Toggle Bits DQ6/DQ2 ............................................... 37
DQ5: Exceeded Timing Limits ................................................ 38
DQ3: Sector Erase Timer .......................................................38
DQ1: Write-to-Buffer Abort ..................................................... 38
Table 11. Write Operation Status................................................... 38
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 39
Figure 9. Maximum Negative Overshoot Waveform ..................... 39
Figure 10. Maximum Positive Overshoot Waveform ..................... 39
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 39
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 40
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 11. Test Setup .................................................................... 41
Table 12. Test Specifications......................................................... 41
Key to Switching Waveforms. . . . . . . . . . . . . . . . 41
Figure 12. Input Waveforms and
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5
Special Package Handling Instructions .................................... 6
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Device Bus Operations ....................................................... 9
Word/Byte Configuration .......................................................... 9
Enhanced VersatileIO (VIO) Control ...................................... 9
Requirements for Reading Array Data ...................................10
Page Mode Read ............................................................................10
Writing Commands/Command Sequences ............................ 10
Write Buffer .....................................................................................10
Accelerated Program Operation ......................................................10
Autoselect Functions .......................................................................10
Standby Mode ........................................................................10
Automatic Sleep Mode ........................................................... 11
RESET#: Hardware Reset Pin ............................................... 11
Output Disable Mode .............................................................. 11
Table 2. Sector Address Table........................................................ 12
Autoselect Mode ..................................................................... 18
Table 3. Autoselect Codes, (High Voltage Method) ....................... 18
Sector Protection and Unprotection ........................................ 18
Write Protect (WP#) ................................................................ 19
Temporary Sector Unprotect .................................................. 19
Figure 1. Temporary Sector Unprotect Operation ...........................19
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ...20
SecSi (Secured Silicon) Sector Flash Memory Region .......... 21
Table 4. SecSi Sector Contents...................................................... 21
Hardware Data Protection ......................................................21
Low VCC Write Inhibit .....................................................................21
Write Pulse “Glitch” Protection ........................................................22
Logical Inhibit ..................................................................................22
Power-Up Write Inhibit ....................................................................22
Common Flash Memory Interface (CFI) . . . . . . . 22
Table 5. CFI Query Identification String ..........................................22
Table 6. System Interface String..................................................... 23
Table 7. Device Geometry Definition ..............................................23
Table 8. Primary Vendor-Specific Extended Query ........................24
Command Definitions . . . . . . . . . . . . . . . . . . . . . 24
Reading Array Data ................................................................ 24
Reset Command ..................................................................... 25
Autoselect Command Sequence ............................................ 25
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 25
Word/Byte Program Command Sequence ............................. 25
Unlock Bypass Command Sequence ..............................................26
Write Buffer Programming ...............................................................26
Accelerated Program ......................................................................27
Figure 3. Write Buffer Programming Operation ...............................28
Figure 4. Program Operation ..........................................................29
Program Suspend/Program Resume Command Sequence ... 29
Figure 5. Program Suspend/Program Resume ...............................30
Chip Erase Command Sequence ........................................... 30
Sector Erase Command Sequence ........................................ 30
Erase Suspend/Erase Resume Commands ........................... 31
Measurement Levels ...................................................................... 41
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42
Read-Only Operations ........................................................... 42
Figure 13. Read Operation Timings ............................................... 42
Figure 14. Page Read Timings ...................................................... 43
Hardware Reset (RESET#) .................................................... 44
Figure 15. Reset Timings ............................................................... 44
Erase and Program Operations .............................................. 45
Figure 16. Program Operation Timings .......................................... 46
Figure 17. Accelerated Program Timing Diagram .......................... 46
Figure 18. Chip/Sector Erase Operation Timings .......................... 47
Figure 19. Data# Polling Timings (During Embedded Algorithms) . 48
Figure 20. Toggle Bit Timings (During Embedded Algorithms) ...... 49
Figure 21. DQ2 vs. DQ6 ................................................................. 49
Temporary Sector Unprotect .................................................. 50
Figure 22. Temporary Sector Group Unprotect Timing Diagram ... 50
Figure 23. Sector Group Protect and Unprotect Timing Diagram .. 51
Alternate CE# Controlled Erase and Program Operations ..... 52
Figure 24. Alternate CE# Controlled Write (Erase/Program)
Operation Timings .......................................................................... 53
Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 53
Erase And Programming Performance. . . . . . . . 54
TSOP Pin and BGA Package Capacitance . . . . . 54
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 55
TS056/TSR056—56-Pin Standard/Reverse Thin Small Outline
Package (TSOP) .....................................................................55
LAA064—64-Ball Fortified Ball Grid Array
13 x 11 mm Package .............................................................. 56
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 57
July 1, 2002
Am29LV128M
3
A D V A N C E I N F O R M A T I O N
PRODUCT SELECTOR GUIDE
Part Number
Am29LV128M
VIO = 3.0–3.6 V
94R
99R
Regulated Voltage Range
VCC = 3.0–3.6 V
Speed/
Voltage
Option
V
V
V
IO = 1.65–1.95 V
IO = 2.7–3.6 V
104
109
100
100
30
114
119
110
110
40
124
129
120
120
40
Full Voltage Range
V
CC = 2.7–3.6 V
IO = 1.65–1.95 V
Max. Access Time (ns)
90
90
25
25
Max. CE# Access Time (ns)
Max. Page access time (tPACC
Max. OE# Access Time (ns)
)
30
40
40
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0–DQ15 (A-1)
RY/BY#
VCC
Sector Switches
VSS
VIO
Erase Voltage
Generator
Input/Output
Buffers
RESET#
WE#
State
WP#/ACC
Control
BYTE#
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
VCC Detector
Timer
Cell Matrix
X-Decoder
A22–A0
4
Am29LV128M
July 1, 2002
A D V A N C E I N F O R M A T I O N
CONNECTION DIAGRAMS
NC
A22
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
8
9
56 NC
55 NC
54 A16
53 BYTE#
52 VSS
51 DQ15/A-1
50 DQ7
49 DQ14
48 DQ6
47 DQ13
46 DQ5
45 DQ12
44 DQ4
43 VCC
42 DQ11
41 DQ3
40 DQ10
39 DQ2
38 DQ9
37 DQ1
36 DQ8
35 DQ0
34 OE#
33 VSS
56-Pin Standard TSOP
A8 10
A19 11
A20 12
WE# 13
RESET# 14
A21 15
WP#/ACC 16
RY/BY# 17
A18 18
A17 19
A7 20
A6 21
A5 22
A4 23
A3 24
A2 25
32 CE#
31 A0
30 NC
29 VIO
A1 26
NC 27
NC 28
NC
NC
1
2
3
4
5
6
7
8
9
56 NC
55 A22
54 A15
53 A14
52 A13
51 A12
50 A11
49 A10
48 A9
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13 10
DQ5 11
DQ12 12
DQ4 13
VCC 14
DQ11 15
DQ3 16
DQ10 17
DQ2 18
DQ9 19
DQ1 20
DQ8 21
DQ0 22
OE# 23
VSS 24
47 A8
46 A19
45 A20
44 WE#
43 RESET#
42 A21
41 WP#/ACC
40 RY/BY#
39 A18
38 A17
37 A7
56-Pin Reverse TSOP
36 A6
35 A5
34 A4
33 A3
CE# 25
A0 26
NC 27
VIO 28
32 A2
31 A1
30 NC
29 NC
July 1, 2002
Am29LV128M
5
A D V A N C E I N F O R M A T I O N
CONNECTION DIAGRAMS
Fortified BGA
Top View, Balls Facing Down
A8
B8
C8
D8
E8
F8
G8
NC
H8
NC
NC
A22
NC
VIO
VSS
NC
A7
B7
C7
D7
E7
F7
G7
H7
VSS
A13
A12
A14
A15
A16
BYTE# DQ15/A-1
A6
A9
B6
A8
C6
D6
E6
F6
G6
H6
A10
A11
DQ7
DQ14
DQ13
DQ6
A5
B5
C5
D5
E5
F5
G5
H5
VCC
WE# RESET#
A21
A19
DQ5
DQ12
DQ4
A4 B4
C4
D4
E4
F4
G4
H4
RY/BY# WP#/ACC A18
A20
DQ2
DQ10
DQ11
DQ3
A3
A7
B3
C3
A6
D3
A5
E3
F3
G3
H3
A17
DQ0
DQ8
DQ9
DQ1
A2
A3
B2
A4
C2
A2
D2
A1
E2
A0
F2
G2
H2
VSS
CE#
OE#
A1
B1
C1
D1
E1
F1
G1
NC
H1
NC
NC
NC
NC
NC
NC
VIO
Note: The FBGA package pinout configuration shown is preliminary. The ball count and package physical dimensions have not
yet been determined. Contact AMD for further information.
compromised if the package body is exposed to
temperatures above 150°C for prolonged periods of
Special Package Handling Instructions
Special handling is required for Flash Memory products
time.
in molded packages (TSOP, BGA, SSOP, PLCC,
PDIP). The package and/or data integrity may be
6
Am29LV128M
July 1, 2002
A D V A N C E I N F O R M A T I O N
PIN DESCRIPTION
LOGIC SYMBOL
A22–A0
= 23 Address inputs
23
DQ14–DQ0 = 15 Data inputs/outputs
A22–A0
16 or 8
DQ15/A-1
= DQ15 (Data input/output, word mode),
DQ15–DQ0
(A-1)
CE#
A-1 (LSB Address input, byte mode)
OE#
CE#
OE#
WE#
= Chip Enable input
WE#
= Output Enable input
WP#/ACC
RESET#
VIO
= Write Enable input
WP#/ACC = Hardware Write Protect input;
Acceleration input
RY/BY#
RESET#
BYTE#
RY/BY#
VCC
= Hardware Reset Pin input
= Selects 8-bit or 16-bit mode
= Ready/Busy output
BYTE#
= 3.0 volt-only single power supply
(see Product Selector Guide for
speed options and voltage
supply tolerances)
VIO
VSS
NC
= Output Buffer power
= Device Ground
= Pin Not Connected Internally
July 1, 2002
Am29LV128M
7
A D V A N C E I N F O R M A T I O N
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
Am29LV128M
H
94R
PC
I
TEMPERATURE RANGE
Industrial (–40°C to +85°C)
I
=
PACKAGE TYPE
E
=
=
=
56-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 056)
56-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR056)
F
PC
64-Ball Fortified Ball Grid Array (FBGA),
1.0 mm pitch, 13 x 11 mm package (LAA064)
SPEED OPTION
See Product Selector Guide and Valid Combinations
SECTOR ARCHITECTURE AND SECTOR WRITE PROTECTION (WP# = VIL)
H
L
=
=
Uniform sector device, highest address sector protected
Uniform sector device, lowest address sector protected
DEVICE NUMBER/DESCRIPTION
Am29LV128MH/L
128 Megabit (8 M x 16-Bit/16 M x 8-Bit) MirrorBit Uniform Sector Flash Memory with Enhanced VersatileIO
Control, 3.0 Volt-only Read, Program, and Erase
Valid Combinations for
TSOP Package
Speed
(ns)
VIO
Range
VCC
Range
Valid Combinations for
Fortified BGA Package
Speed
(ns)
VIO
VCC
Range Range
Am29LV128MH94R
Am29LV128ML94R
Order Number
Package Marking
3.0–3.6 V
1.65–1.95 V
2.7–3.6 V
Am29LV128MH94R
Am29LV128ML94R
L128MH94N
L128ML94N
90
3.0–3.6 V
Am29LV128MH99R
Am29LV128ML99R
3.0–
3.6 V
3.0–
3.6 V
90
Am29LV128MH99R
Am29LV128ML99R
L128MH99N
L128ML99N
Am29LV128MH104
Am29LV128ML104
Am29LV128MH104
Am29LV128ML104
L128MH104P
L128ML104P
2.7–
3.6 V
100
110
120
Am29LV128MH109
1.65–1.95 V
2.7–3.6 V
100
110
120
Am29LV128ML109
EI,
FI
Am29LV128MH109
Am29LV128ML109
L128MH109P
L128ML109P
1.65–
1.95 V
Am29LV128MH114
Am29LV128ML114
PCI
I
Am29LV128MH114
Am29LV128ML114
L128MH114P
L128ML114P
2.7–
3.6 V
2.7–3.6 V
Am29LV128MH119
Am29LV128ML119
2.7–
3.6 V
1.65–1.95 V
2.7–3.6 V
Am29LV128MH119
Am29LV128ML119
L128MH119P
L128ML119P
1.65–
1.95 V
Am29LV128MH124
Am29LV128ML124
Am29LV128MH124
Am29LV128ML124
L128MH124P
L128ML124P
2.7–
3.6 V
Am29LV128MH129
Am29LV128ML129
1.65–1.95 V
Am29LV128MH129
Am29LV128ML129
L128MH129P
L128ML129P
1.65–
1.95 V
Valid Combinations
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly re-
leased combinations.
8
Am29LV128M
July 1, 2002
A D V A N C E I N F O R M A T I O N
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Device Bus Operations
DQ8–DQ15
DQ0–
DQ7
BYTE#
= VIH
BYTE#
= VIL
Addresses
(Note 2)
Operation
CE# OE# WE# RESET#
WP#
X
ACC
X
Read
L
L
L
H
H
H
L
L
H
H
AIN
AIN
AIN
DOUT
DOUT
DQ8–DQ14
= High-Z,
DQ15 = A-1
Write (Program/Erase)
Accelerated Program
(Note 3)
(Note 3)
X
(Note 4) (Note 4)
(Note 4) (Note 4)
L
H
VHH
VCC
0.3 V
±
VCC ±
0.3 V
Standby
X
X
X
X
H
High-Z High-Z
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
X
X
X
X
X
X
High-Z High-Z
High-Z High-Z
High-Z
High-Z
X
SA, A6 =L,
A3=L, A2=L,
A1=H, A0=L
Sector Group Protect
(Note 2)
L
H
L
VID
H
X
(Note 4)
X
X
SA, A6=H,
A3=L, A2=L, (Note 4)
A1=H, A0=L
Sector Group Unprotect
(Note 2)
L
H
X
L
VID
VID
H
H
X
X
X
X
Temporary Sector Group
Unprotect
X
X
AIN
(Note 4) (Note 4)
High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address,
AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A22:A0 in word mode; A22:A-1 in byte mode. Sector addresses are A22:A15 in both modes.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection and Unprotection” section.
3. If WP# = VIL, the first or last sector remains protected. If WP# = VIH, the first or last sector will be protected or unprotected as
determined by the method described in “Sector Protection and Unprotection”. All sectors are unprotected when shipped from the
factory (The SecSi Sector may be factory protected depending on version ordered.)
4. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins operate in the byte or word configuration. If the
BYTE# pin is set at logic ‘1’, the device is in word con-
Enhanced VersatileIO (VIO) Control
The VersatileIO™ (VIO) control allows the host system
to set the voltage levels that the device generates and
tolerates on all I/Os and control inputs to the same
voltage level that is asserted on VIO. See Ordering In-
formation for VIO options on this device.
figuration, DQ0–DQ15 are active and controlled by
CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
July 1, 2002
Am29LV128M
9
A D V A N C E I N F O R M A T I O N
For example, a VI/O of 1.65–3.6 volts allows for I/O at
Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four. The
“Word/Byte Program Command Sequence” section
has details on programming data to the device using
both standard and Unlock Bypass command se-
quences.
the 1.8 or 3 volt levels, driving and receiving signals to
and from other 1.8 or 3 V devices on the same data
bus.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 2 indicates the address
space that each sector occupies.
Refer to the DC Characteristics table for the active
current specification for the write mode. The AC Char-
acteristics section contains timing specification tables
and timing diagrams for write operations.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
Write Buffer
Write Buffer Programming allows the system write to a
maximum of 16 words/32 bytes in one programming
operation. This results in faster effective programming
time than the standard programming algorithms. See
“Write Buffer” for more information.
Accelerated Program Operation
See “Reading Array Data” for more information. Refer
to the AC Read-Only Operations table for timing spec-
ifications and to Figure 13 for the timing diagram.
Refer to the DC Characteristics table for the active
current specification on reading array data.
The device offers accelerated program operations
through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is prima-
rily intended to allow faster manufacturing throughput
at the factory.
Page Mode Read
If the system asserts VHH on this pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read oper-
ation. This mode provides faster read access speed
for random locations within a page. The page size of
the device is 4 words/8 bytes. The appropriate page is
selected by the higher address bits A(max)–A2. Ad-
dress bits A1–A0 in word mode (A1–A-1 in byte mode)
determine the specific word within a page. This is an
asynchronous operation; the microprocessor supplies
the specific word location.
V
HH from the WP#/ACC pin returns the device to nor-
mal operation. Note that the WP#/ACC pin must not
be at VHH for operations other than accelerated pro-
gramming, or device damage may result. WP# has an
internal pullup; when unconnected, WP# is at VIH.
The random or initial page access is equal to tACC or
tCE and subsequent page read accesses (as long as
the locations specified by the microprocessor falls
within that page) is equivalent to tPACC. When CE# is
deasserted and reasserted for a subsequent access,
the access time is tACC or tCE. Fast page mode ac-
cesses are obtained by keeping the “read-page ad-
dresses” constant and changing the “intra-read page”
addresses.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the Autoselect Mode and Autose-
lect Command Sequence sections for more informa-
tion.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
The device features an Unlock Bypass mode to facil-
itate faster programming. Once the device enters the
10
Am29LV128M
July 1, 2002
A D V A N C E I N F O R M A T I O N
and the outputs are placed in the high impedance
state, independent of the OE# input.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VIO ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
VIO ± 0.3 V, the device will be in the standby mode, but
the standby current will be greater. The device re-
quires standard access time (tCE) for read access
when the device is in either of these standby modes,
before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS±0.3 V, the standby current will
be greater.
Refer to the DC Characteristics table for the standby
current specification.
Automatic Sleep Mode
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for tACC
+
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
Refer to the DC Characteristics table for the automatic
sleep mode current specification.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 15 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.
July 1, 2002
Am29LV128M
11
A D V A N C E I N F O R M A T I O N
Table 2. Sector Address Table
8-bit
16-bit
Sector Size
(Kbytes/Kwords)
Address Range
(in hexadecimal)
Address Range
(in hexadecimal)
Sector
SA0
A22–A15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1FFFFF
200000–20FFFF
210000–21FFFF
220000–22FFFF
230000–23FFFF
240000–24FFFF
250000–25FFFF
260000–26FFFF
270000–27FFFF
280000–28FFFF
290000–29FFFF
2A0000–2AFFFF
2B0000–2BFFFF
2C0000–2CFFFF
2D0000–2DFFFF
2E0000–2EFFFF
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
12
Am29LV128M
July 1, 2002
A D V A N C E I N F O R M A T I O N
Table 2. Sector Address Table (Continued)
8-bit
16-bit
Sector Size
(Kbytes/Kwords)
Address Range
(in hexadecimal)
Address Range
(in hexadecimal)
Sector
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
A22–A15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
2F0000–2FFFFF
300000–30FFFF
310000–31FFFF
320000–32FFFF
330000–33FFFF
340000–34FFFF
350000–35FFFF
360000–36FFFF
370000–37FFFF
380000–38FFFF
390000–39FFFF
3A0000–3AFFFF
3B0000–3BFFFF
3C0000–3CFFFF
3D0000–3DFFFF
3E0000–3EFFFF
3F0000–3FFFFF
400000–40FFFF
410000–41FFFF
420000–42FFFF
430000–43FFFF
440000–44FFFF
450000–45FFFF
460000–46FFFF
470000–47FFFF
480000–48FFFF
490000–49FFFF
4A0000–4AFFFF
4B0000–4BFFFF
4C0000–4CFFFF
4D0000–4DFFFF
4E0000–4EFFFF
4F0000–4FFFFF
500000–50FFFF
510000–51FFFF
520000–52FFFF
530000–53FFFF
540000–54FFFF
550000–55FFFF
560000–56FFFF
570000–57FFFF
580000–58FFFF
590000–59FFFF
5A0000–5AFFFF
5B0000–5BFFFF
5C0000–5CFFFF
5D0000–5DFFFF
5E0000–5EFFFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
200000–207FFF
208000–20FFFF
210000–217FFF
218000–21FFFF
220000–227FFF
228000–22FFFF
230000–237FFF
238000–23FFFF
240000–247FFF
248000–24FFFF
250000–257FFF
258000–25FFFF
260000–267FFF
268000–26FFFF
270000–277FFF
278000–27FFFF
280000–287FFF
288000–28FFFF
290000–297FFF
298000–29FFFF
2A0000–2A7FFF
2A8000–2AFFFF
2B0000–2B7FFF
2B8000–2BFFFF
2C0000–2C7FFF
2C8000–2CFFFF
2D0000–2D7FFF
2D8000–2DFFFF
2E0000–2E7FFF
2E8000–2EFFFF
2F0000–2F7FFF
July 1, 2002
Am29LV128M
13
A D V A N C E I N F O R M A T I O N
Table 2. Sector Address Table (Continued)
8-bit
16-bit
Sector Size
(Kbytes/Kwords)
Address Range
(in hexadecimal)
Address Range
(in hexadecimal)
Sector
SA95
A22–A15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
5F0000–5FFFFF
600000–60FFFF
610000–61FFFF
620000–62FFFF
630000–63FFFF
640000–64FFFF
650000–65FFFF
660000–66FFFF
670000–67FFFF
680000–68FFFF
690000–69FFFF
6A0000–6AFFFF
6B0000–6BFFFF
6C0000–6CFFFF
6D0000–6DFFFF
6E0000–6EFFFF
6F0000–6FFFFF
700000–70FFFF
710000–71FFFF
720000–72FFFF
730000–73FFFF
740000–74FFFF
750000–75FFFF
760000–76FFFF
770000–77FFFF
780000–78FFFF
790000–79FFFF
7A0000–7AFFFF
7B0000–7BFFFF
7C0000–7CFFFF
7D0000–7DFFFF
7E0000–7EFFFF
7F0000–7FFFFF
800000–80FFFF
810000–81FFFF
820000–82FFFF
830000–83FFFF
840000–84FFFF
850000–85FFFF
860000–86FFFF
870000–87FFFF
880000–88FFFF
890000–89FFFF
8A0000–8AFFFF
8B0000–8BFFFF
8C0000–8CFFFF
8D0000–8DFFFF
8E0000–8EFFFF
2F8000–2FFFFF
300000–307FFF
308000–30FFFF
310000–317FFF
318000–31FFFF
320000–327FFF
328000–32FFFF
330000–337FFF
338000–33FFFF
340000–347FFF
348000–34FFFF
350000–357FFF
358000–35FFFF
360000–367FFF
368000–36FFFF
370000–377FFF
378000–37FFFF
380000–387FFF
388000–38FFFF
390000–397FFF
398000–39FFFF
3A0000–3A7FFF
3A8000–3AFFFF
3B0000–3B7FFF
3B8000–3BFFFF
3C0000–3C7FFF
3C8000–3CFFFF
3D0000–3D7FFF
3D8000–3DFFFF
3E0000–3E7FFF
3E8000–3EFFFF
3F0000–3F7FFF
3F8000–3FFFFF
400000–407FFF
408000–40FFFF
410000–417FFF
418000–41FFFF
420000–427FFF
428000–42FFFF
430000–437FFF
438000–43FFFF
440000–447FFF
448000–44FFFF
450000–457FFF
458000–45FFFF
460000–467FFF
468000–46FFFF
470000–477FFF
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
SA142
14
Am29LV128M
July 1, 2002
A D V A N C E I N F O R M A T I O N
Table 2. Sector Address Table (Continued)
8-bit
16-bit
Sector Size
(Kbytes/Kwords)
Address Range
(in hexadecimal)
Address Range
(in hexadecimal)
Sector
SA143
SA144
SA145
SA146
SA147
SA148
SA149
SA150
SA151
SA152
SA153
SA154
SA155
SA156
SA157
SA158
SA159
SA160
SA161
SA162
SA163
SA164
SA165
SA166
SA167
SA168
SA169
SA170
SA171
SA172
SA173
SA174
SA175
SA176
SA177
SA178
SA179
SA180
SA181
SA182
SA183
SA184
SA185
SA186
SA187
SA188
SA189
SA190
A22–A15
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8F0000–8FFFFF
900000–90FFFF
910000–91FFFF
920000–92FFFF
930000–93FFFF
940000–94FFFF
950000–95FFFF
960000–96FFFF
970000–97FFFF
980000–98FFFF
990000–99FFFF
9A0000–9AFFFF
9B0000–9BFFFF
9C0000–9CFFFF
9D0000–9DFFFF
9E0000–9EFFFF
9F0000–9FFFFF
A00000–A0FFFF
A10000–A1FFFF
A20000–A2FFFF
A30000–A3FFFF
A40000–A4FFFF
A50000–A5FFFF
A60000–A6FFFF
A70000–A7FFFF
A80000–A8FFFF
A90000–A9FFFF
AA0000–AAFFFF
AB0000–ABFFFF
AC0000–ACFFFF
AD0000–ADFFFF
AE0000–AEFFFF
AF0000–AFFFFF
B00000–B0FFFF
B10000–B1FFFF
B20000–B2FFFF
B30000–B3FFFF
B40000–B4FFFF
B50000–B5FFFF
B60000–B6FFFF
B70000–B7FFFF
B80000–B8FFFF
B90000–B9FFFF
BA0000–BAFFFF
BB0000–BBFFFF
BC0000–BCFFFF
BD0000–BDFFFF
BE0000–BEFFFF
478000–47FFFF
480000–487FFF
488000–48FFFF
490000–497FFF
498000–49FFFF
4A0000–4A7FFF
4A8000–4AFFFF
4B0000–4B7FFF
4B8000–4BFFFF
4C0000–4C7FFF
4C8000–4CFFFF
4D0000–4D7FFF
4D8000–4DFFFF
4E0000–4E7FFF
4E8000–4EFFFF
4F0000–4F7FFF
4F8000–4FFFFF
500000–507FFF
508000–50FFFF
510000–517FFF
518000–51FFFF
520000–527FFF
528000–52FFFF
530000–537FFF
538000–53FFFF
540000–547FFF
548000–54FFFF
550000–557FFF
558000–55FFFF
560000–567FFF
568000–56FFFF
570000–577FFF
578000–57FFFF
580000–587FFF
588000–58FFFF
590000–597FFF
598000–59FFFF
5A0000–5A7FFF
5A8000–5AFFFF
5B0000–5B7FFF
5B8000–5BFFFF
5C0000–5C7FFF
5C8000–5CFFFF
5D0000–5D7FFF
5D8000–5DFFFF
5E0000–5E7FFF
5E8000–5EFFFF
5F0000–5F7FFF
July 1, 2002
Am29LV128M
15
A D V A N C E I N F O R M A T I O N
Table 2. Sector Address Table (Continued)
8-bit
16-bit
Sector Size
(Kbytes/Kwords)
Address Range
(in hexadecimal)
Address Range
(in hexadecimal)
Sector
SA191
SA192
SA193
SA194
SA195
SA196
SA197
SA198
SA199
SA200
SA201
SA202
SA203
SA204
SA205
SA206
SA207
SA208
SA209
SA210
SA211
SA212
SA213
SA214
SA215
SA216
SA217
SA218
SA219
SA220
SA221
SA222
SA223
SA224
SA225
SA226
SA227
SA228
SA229
SA230
SA231
SA232
SA233
SA234
SA235
SA236
SA237
SA238
A22–A15
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
BF0000–BFFFFF
C00000–C0FFFF
C10000–C1FFFF
C20000–C2FFFF
C30000–C3FFFF
C40000–C4FFFF
C50000–C5FFFF
C60000–C6FFFF
C70000–C7FFFF
C80000–C8FFFF
C90000–C9FFFF
CA0000–CAFFFF
CB0000–CBFFFF
CC0000–CCFFFF
CD0000–CDFFFF
CE0000–CEFFFF
CF0000–CFFFFF
D00000–D0FFFF
D10000–D1FFFF
D20000–D2FFFF
D30000–D3FFFF
D40000–D4FFFF
D50000–D5FFFF
D60000–D6FFFF
D70000–D7FFFF
D80000–D8FFFF
D90000–D9FFFF
DA0000–DAFFFF
DB0000–DBFFFF
DC0000–DCFFFF
DD0000–DDFFFF
DE0000–DEFFFF
DF0000–DFFFFF
E00000–E0FFFF
E10000–E1FFFF
E20000–E2FFFF
E30000–E3FFFF
E40000–E4FFFF
E50000–E5FFFF
E60000–E6FFFF
E70000–E7FFFF
E80000–E8FFFF
E90000–E9FFFF
EA0000–EAFFFF
EB0000–EBFFFF
EC0000–ECFFFF
ED0000–EDFFFF
EE0000–EEFFFF
5F8000–5FFFFF
600000–607FFF
608000–60FFFF
610000–617FFF
618000–61FFFF
620000–627FFF
628000–62FFFF
630000–637FFF
638000–63FFFF
640000–647FFF
648000–64FFFF
650000–657FFF
658000–65FFFF
660000–667FFF
668000–66FFFF
670000–677FFF
678000–67FFFF
680000–687FFF
688000–68FFFF
690000–697FFF
698000–69FFFF
6A0000–6A7FFF
6A8000–6AFFFF
6B0000–6B7FFF
6B8000–6BFFFF
6C0000–6C7FFF
6C8000–6CFFFF
6D0000–6D7FFF
6D8000–6DFFFF
6E0000–6E7FFF
6E8000–6EFFFF
6F0000–6F7FFF
6F8000–6FFFFF
700000–707FFF
708000–70FFFF
710000–717FFF
718000–71FFFF
720000–727FFF
728000–72FFFF
730000–737FFF
738000–73FFFF
740000–747FFF
748000–74FFFF
750000–757FFF
758000–75FFFF
760000–767FFF
768000–76FFFF
770000–777FFF
16
Am29LV128M
July 1, 2002
A D V A N C E I N F O R M A T I O N
Table 2. Sector Address Table (Continued)
8-bit
16-bit
Sector Size
(Kbytes/Kwords)
Address Range
(in hexadecimal)
Address Range
(in hexadecimal)
Sector
SA239
SA240
SA241
SA242
SA243
SA244
SA245
SA246
SA247
SA248
SA249
SA250
SA251
SA252
SA253
SA254
SA255
A22–A15
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
EF0000–EFFFFF
F00000–F0FFFF
F10000–F1FFFF
F20000–F2FFFF
F30000–F3FFFF
F40000–F4FFFF
F50000–F5FFFF
F60000–F6FFFF
F70000–F7FFFF
F80000–F8FFFF
F90000–F9FFFF
FA0000–FAFFFF
FB0000–FBFFFF
FC0000–FCFFFF
FD0000–FDFFFF
FE0000–FEFFFF
FF0000–FFFFFF
778000–77FFFF
780000–787FFF
788000–78FFFF
790000–797FFF
798000–79FFFF
7A0000–7A7FFF
7A8000–7AFFFF
7B0000–7B7FFF
7B8000–7BFFFF
7C0000–7C7FFF
7C8000–7CFFFF
7D0000–7D7FFF
7D8000–7DFFFF
7E0000–7E7FFF
7E8000–7EFFFF
7F0000–7F7FFF
7F8000–7FFFFF
July 1, 2002
Am29LV128M
17
A D V A N C E I N F O R M A T I O N
In addition, when verifying sector protection, the sector
Autoselect Mode
address must appear on the appropriate highest order
address bits (see Table 2). Table 3 shows the remain-
ing address bits that are don’t care. When all neces-
sary bits have been set as required, the programming
equipment may then read the corresponding identifier
code on DQ7–DQ0.
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equip-
ment to automatically match a device to be pro-
grammed with its corresponding programming
algorithm. However, the autoselect codes can also be
accessed in-system through the command register.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Tables 9 and 10. This
method does not require VID. Refer to the Autoselect
Command Sequence section for more information.
When using programming equipment, the autoselect
mode requires VID on address pin A9. Address pins
A6, A3, A2, A1, and A0 must be as shown in Table 3.
Table 3. Autoselect Codes, (High Voltage Method)
DQ8 to DQ15
A22 A14
A8
to A6
A7
A5
to
A4
A3
to
A2
Description
CE# OE# WE# to
to
A9
A1 A0
DQ7 to DQ0
BYTE# BYTE#
A15 A10
= VIH
= VIL
VID
Manufacturer ID: AMD
Cycle 1
L
L
L
L
H
H
X
X
X
X
X
L
X
X
L
L
L
L
L
H
L
00
X
01h
7Eh
12h
00h
22
X
VID
VID
VID
Cycle 2
X
L
H
H
H
H
22
X
Cycle 3
H
22
X
Sector Protection
Verification
01h (protected),
00h (unprotected)
L
L
L
L
H
H
SA
X
X
X
X
X
L
L
X
X
L
H
L
X
X
SecSi Sector Indicator
Bit (DQ7), WP#
protects highest
address sector
98h (factory locked),
18h (not factory locked)
L
H
H
X
X
SecSi Sector Indicator
Bit (DQ7), WP#
protects lowest
88h (factory locked),
08h (not factory locked)
VID
L
L
H
X
X
X
L
X
L
H
H
X
X
address sector
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
cycle timing. For sector unprotect, all unprotected sec-
tors must first be protected prior to the first sector un-
protect write cycle.
Sector Protection and Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both pro-
gram and erase operations in previously protected
sectors. Sector protection/unprotection can be imple-
mented via two methods.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
Sector protection/unprotection requires VID on the RE-
SET# pin only, and can be implemented either in-sys-
tem or via programming equipment. Figure 2 shows
the algorithms and Figure 23 shows the timing dia-
gram. This method uses standard microprocessor bus
It is possible to determine whether a sector is pro-
tected or unprotected. See the Autoselect Mode sec-
tion for details.
18
Am29LV128M
July 1, 2002
A D V A N C E I N F O R M A T I O N
Write Protect (WP#)
The Write Protect function provides a hardware
method of protecting the first or last sector without
using VID. Write Protect is one of two functions pro-
vided by the WP#/ACC input.
START
If the system asserts VIL on the WP#/ACC pin, the de-
vice disables program and erase functions in the first
or last sector independently of whether those sectors
were protected or unprotected using the method de-
scribed in “Sector Protection and Unprotection”. Note
that if WP#/ACC is at VIL when the device is in the
standby mode, the maximum input load current is in-
creased. See the table in “DC Characteristics”.
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
If the system asserts VIH on the WP#/ACC pin, the de-
vice reverts to whether the first or last sector was pre-
viously set to be protected or unprotected using the
method described in “Sector Protection and Unprotec-
tion”. Note that WP# has an internal pullup; when un-
connected, WP# is at VIH.
Temporary Sector
Unprotect Completed
(Note 2)
Temporary Sector Unprotect
Notes:
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RE-
SET# pin to VID. During this mode, formerly protected
sectors can be programmed or erased by selecting the
sector addresses. Once VID is removed from the RE-
SET# pin, all the previously protected sectors are
protected again. Figure 1 shows the algorithm, and
Figure 22 shows the timing diagrams, for this feature.
1. All protected sectors unprotected (If WP# = VIL, the first
or last sector will remain protected).
2. All previously protected sectors are protected once
again.
Figure 1. Temporary Sector Unprotect Operation
July 1, 2002
Am29LV128M
19
A D V A N C E I N F O R M A T I O N
START
START
Protect all sectors:
PLSCNT = 1
PLSCNT = 1
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
RESET# = VID
RESET# = VID
Wait 1 µs
Wait 1 µs
unprotect address
No
No
First Write
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
Cycle = 60h?
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
address
Sector Unprotect:
Wait 150 µs
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
Data = 01h?
Yes
A1 = 1, A0 = 0
No
Yes
Set up
next sector
address
Yes
No
PLSCNT
= 1000?
Protect another
sector?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
No
Last sector
verified?
Device failed
Write reset
command
Yes
Remove VID
Sector Unprotect
Algorithm
from RESET#
Sector Protect
Algorithm
Sector Protect
complete
Write reset
command
Sector Unprotect
complete
Figure 2. In-System Sector Group Protect/Unprotect Algorithms
Am29LV128M
20
July 1, 2002
A D V A N C E I N F O R M A T I O N
vices are then shipped from AMD’s factory with the
SecSi (Secured Silicon) Sector Flash
Memory Region
SecSi Sector permanently locked. Contact an AMD
representative for details on using AMD’s Express-
Flash service.
The SecSi (Secured Silicon) Sector feature provides a
Flash memory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The SecSi Sector is 128 words/256 bytes in
length, and uses a SecSi Sector Indicator Bit (DQ7) to
indicate whether or not the SecSi Sector is locked
when shipped from the factory. This bit is permanently
set at the factory and cannot be changed, which pre-
vents cloning of a factory locked part. This ensures the
security of the ESN once the product is shipped to the
field.
Customer Lockable: SecSi Sector NOT
Programmed or Protected At the Factory
As an alternative to the factory-locked version, the de-
vice may be ordered such that the customer may pro-
gram and protect the 128-word/256 bytes SecSi
sector.
The system may program the SecSi Sector using the
write-buffer, accelerated and/or unlock bypass meth-
ods, in addition to the standard programming com-
mand sequence. See Command Definitions.
AMD offers the device with the SecSi Sector either
factory locked or customer lockable. The fac-
tory-locked version is always protected when shipped
from the factory, and has the SecSi (Secured Silicon)
Sector Indicator Bit permanently set to a “1.” The cus-
tomer-lockable version is shipped with the SecSi Sec-
tor unprotected, allowing customers to program the
sector after receiving the device. The customer-lock-
able version also has the SecSi Sector Indicator Bit
permanently set to a “0.” Thus, the SecSi Sector Indi-
cator Bit prevents customer-lockable devices from
being used to replace devices that are factory locked.
Programming and protecting the SecSi Sector must be
used with caution since, once protected, there is no
procedure available for unprotecting the SecSi Sector
area and none of the bits in the SecSi Sector memory
space can be modified in any way.
The SecSi Sector area can be protected using one of
the following procedures:
■ Write the three-cycle Enter SecSi Sector Region
command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 2, ex-
cept that RESET# may be at either VIH or VID. This
allows in-system protection of the SecSi Sector
without raising any device pin to a high voltage.
Note that this method is only applicable to the SecSi
Sector.
The SecSi sector address space in this device is allo-
cated as follows:
Table 4. SecSi Sector Contents
SecSi Sector
Address Range
Standard
Factory Locked Factory Locked
ExpressFlash
Customer
Lockable
ESN or
000000h–000007h
000008h–00007Fh
ESN
determined by
customer
■ Write the three-cycle Enter SecSi Sector Region
command sequence, and then use the alternate
method of sector protection described in the “Sector
Protection and Unprotection” section.
Determined by
customer
Determined by
customer
Unavailable
The system accesses the SecSi Sector through a
command sequence (see “Enter SecSi Sector/Exit
SecSi Sector Command Sequence”). After the system
has written the Enter SecSi Sector command se-
quence, it may read the SecSi Sector by using the ad-
dresses normally occupied by the first sector (SA0).
This mode of operation continues until the system is-
sues the Exit SecSi Sector command sequence, or
until power is removed from the device. On power-up,
or following a hardware reset, the device reverts to
sending commands to sector SA0.
Once the SecSi Sector is programmed, locked and
verified, the system must write the Exit SecSi Sector
Region command sequence to return to reading and
writing within the remainder of the array.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Tables 9 and 10 for
command definitions). In addition, the following hard-
ware data protection measures prevent accidental
erasure or programming, which might otherwise be
caused by spurious system level signals during VCC
power-up and power-down transitions, or from system
noise.
Factory Locked: SecSi Sector Programmed and
Protected At the Factory
In devices with an ESN, the SecSi Sector is protected
when the device is shipped from the factory. The SecSi
Sector cannot be modified in any way. A factory locked
device has an 8-word/16-byte random ESN at ad-
dresses 000000h–000007h.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register
Customers may opt to have their code programmed by
AMD through the AMD ExpressFlash service. The de-
July 1, 2002
Am29LV128M
21
A D V A N C E I N F O R M A T I O N
and all internal program/erase circuits are disabled,
Logical Inhibit
and the device resets to the read mode. Subsequent
writes are ignored until VCC is greater than VLKO. The
system must provide the proper signals to the control
pins to prevent unintentional writes when VCC is
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
greater than VLKO
.
Power-Up Write Inhibit
Write Pulse “Glitch” Protection
If WE# = CE# = VIL and OE# = VIH during power up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to the read mode on power-up.
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
given in Tables 5–8. To terminate reading CFI data,
the system must write the reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 5–8. The
system must write the reset command to return the de-
vice to the autoselect mode.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the
World Wide Web at http://www.amd.com/prod-
ucts/nvd/overview/cfi.html. Alternatively, contact an
AMD representative for copies of these documents.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h, any time the device is ready to read array data.
The system can read CFI information at the addresses
Table 5. CFI Query Identification String
Addresses (x16)
Data
Description
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
22
Am29LV128M
July 1, 2002
A D V A N C E I N F O R M A T I O N
Table 6. System Interface String
Description
Addresses (x16)
Data
V
CC Min. (write/erase)
1Bh
0027h
D7–D4: volt, D3–D0: 100 millivolt
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
0036h
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
0000h
0000h
0007h
0007h
000Ah
0000h
0001h
0005h
0004h
0000h
VPP Min. voltage (00h = no VPP pin present)
VPP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 7. Device Geometry Definition
Addresses (x16)
Data
Description
27h
0018h
Device Size = 2N byte
28h
29h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
0005h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
Number of Erase Block Regions within device (01h = uniform device, 02h = boot
device)
2Ch
0001h
2Dh
2Eh
2Fh
30h
00FFh
0000h
0000h
0001h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
0000h
0000h
0000h
0000h
Erase Block Region 2 Information (refer to CFI publication 100)
Erase Block Region 3 Information (refer to CFI publication 100)
Erase Block Region 4 Information (refer to CFI publication 100)
35h
36h
37h
38h
0000h
0000h
0000h
0000h
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
July 1, 2002
Am29LV128M
23
A D V A N C E I N F O R M A T I O N
Table 8. Primary Vendor-Specific Extended Query
Addresses (x16)
Data
Description
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
0031h
0033h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
0008h
Process Technology (Bits 7-2) 0010b = 0.23 µm MirrorBit
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
46h
47h
48h
49h
4Ah
4Bh
4Ch
0002h
0001h
0001h
0004h
0000h
0000h
0001h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
04 = 29LV800 mode
Simultaneous Operation
00 = Not Supported, X = Number of Sectors in Bank
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
4Dh
4Eh
00B5h
00C5h
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
0004h/
0005h
00h = Uniform Device without WP# protect, 02h = Bottom Boot Device, 03h = Top
Boot Device, 04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top
WP# protect
4Fh
50h
Program Suspend
0001h
00h = Not Supported, 01h = Supported
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Tables 9 and 10 defines the valid register
command sequences. Writing incorrect address and
data values or writing them in the improper sequence
may place the device in an unknown state. A reset
command is then required to return the device to read-
ing array data.
first. Refer to the AC Characteristics section for timing
diagrams.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
All addresses are latched on the falling edge of WE#
or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
After the device accepts an Erase Suspend command,
the device enters the erase-suspend-read mode, after
which the system can read data from any
24
Am29LV128M
July 1, 2002
A D V A N C E I N F O R M A T I O N
non-erase-suspended sector. After completing a pro-
Tables 9 and 10 show the address and data require-
ments. This method is an alternative to that shown in
Table 3, which is intended for PROM programmers
and requires VID on address pin A9. The autoselect
command sequence may be written to an address that
is either in the read or erase-suspend-read mode. The
autoselect command may not be written while the de-
vice is actively programming or erasing.
gramming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See the Erase Suspend/Erase Resume
Commands section for more information.
The system must issue the reset command to return
the device to the read (or erase-suspend-read) mode
if DQ5 goes high during an active program or erase
operation, or if the device is in the autoselect mode.
See the next section, Reset Command, for more infor-
mation.
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the autoselect command. The
device then enters the autoselect mode. The system
may read at any address any number of times without
initiating another autoselect command sequence:
See also Requirements for Reading Array Data in the
Device Bus Operations section for more information.
The Read-Only Operations table provides the read pa-
rameters, and Figure 13 shows the timing diagram.
■ A read cycle at address XX00h returns the manu-
facturer code.
Reset Command
■ Three read cycles at addresses 01h, 0Eh, and 0Fh
Writing the reset command resets the device to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
return the device code.
■ A read cycle to an address containing a sector ad-
dress (SA), and the address 02h on A7–A0 in word
mode returns 01h if the sector is protected, or 00h if
it is unprotected.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to the read
mode. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the de-
vice was previously in Erase Suspend).
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
the read mode. If the program command sequence is
written while the device is in the Erase Suspend mode,
writing the reset command returns the device to the
erase-suspend-read mode. Once programming be-
gins, however, the device ignores reset commands
until the operation is complete.
Enter SecSi Sector/Exit SecSi Sector
Command Sequence
The SecSi Sector region provides a secured data area
containing an 8-word/16-byte random Electronic Serial
Number (ESN). The system can access the SecSi
Sector region by issuing the three-cycle Enter SecSi
Sector command sequence. The device continues to
access the SecSi Sector region until the system is-
sues the four-cycle Exit SecSi Sector command se-
quence. The Exit SecSi Sector command sequence
returns the device to normal operation. Tables 9 and
10 show the address and data requirements for both
command sequences. See also “SecSi (Secured Sili-
con) Sector Flash Memory Region” for further informa-
tion.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to the read mode. If the de-
vice entered the autoselect mode while in the Erase
Suspend mode, writing the reset command returns the
device to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to the
read mode (or erase-suspend-read mode if the device
was in Erase Suspend).
Word/Byte Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. Tables 9 and 10 show the
address and data requirements for the word program
command sequence.
Note that if DQ1 goes high during a Write Buffer Pro-
gramming operation, the system must write the
Write-to-Buffer-Abort Reset command sequence to
reset the device for the next operation.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and device codes,
and determine whether or not a sector is protected.
July 1, 2002
Am29LV128M
25
A D V A N C E I N F O R M A T I O N
When the Embedded Program algorithm is complete,
command written at the Sector Address in which pro-
gramming will occur. The fourth cycle writes the sector
address and the number of word locations, minus one,
to be programmed. For example, if the system will pro-
gram 6 unique address locations, then 05h should be
written to the device. This tells the device how many
write buffer addresses will be loaded with data and
therefore when to expect the Program Buffer to Flash
command. The number of locations to program cannot
exceed the size of the write buffer or the operation will
abort.
the device then returns to the read mode and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7 or DQ6. Refer to the Write Operation Status sec-
tion for information on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should
be reinitiated once the device has returned to the read
mode, to ensure data integrity.
The fifth cycle writes the first address location and
data to be programmed. The write-buffer-page is se-
lected by address bits AMAX–A4. All subsequent ad-
dress/data pairs must fall within the
selected-write-buffer-page. The system then writes the
remaining address/data pairs into the write buffer.
Write buffer locations may be loaded in any order.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause the device to set DQ5 = 1, or cause the DQ7
and DQ6 status bits to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0.” Only erase operations can convert a
“0” to a “1.”
The write-buffer-page address must be the same for
all address/data pairs loaded into the write buffer.
(This means Write Buffer Programming cannot be per-
formed across multiple write-buffer pages. This also
means that Write Buffer Programming cannot be per-
formed across multiple sectors. If the system attempts
to load programming data outside of the selected
write-buffer page, the operation will abort.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram words to the device faster than using the stan-
dard program command sequence. The unlock
bypass command sequence is initiated by first writing
two unlock cycles. This is followed by a third write
cycle containing the unlock bypass command, 20h.
The device then enters the unlock bypass mode. A
two-cycle unlock bypass program command sequence
is all that is required to program in this mode. The first
cycle in this sequence contains the unlock bypass pro-
gram command, A0h; the second cycle contains the
program address and data. Additional data is pro-
grammed in the same manner. This mode dispenses
with the initial two unlock cycles required in the stan-
dard program command sequence, resulting in faster
total programming time. Tables 9 and 10 show the re-
quirements for the command sequence.
Note that if a Write Buffer address location is loaded
multiple times, the address/data pair counter will be
decremented for every data load operation. The host
system must therefore account for loading a
write-buffer location more than once. The counter dec-
rements for each data load operation, not for each
unique write-buffer-address location. Note also that if
an address location is loaded more than once into the
buffer, the final data loaded for that address will be
programmed.
Once the specified number of write buffer locations
have been loaded, the system must then write the Pro-
gram Buffer to Flash command at the sector address.
Any other address and data combination aborts the
Write Buffer Programming operation. The device then
begins programming. Data polling should be used
while monitoring the last address location loaded into
the write buffer. DQ7, DQ6, DQ5, and DQ1 should be
monitored to determine the device status during Write
Buffer Programming.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h. The second cycle must contain the data 00h. The
device then returns to the read mode.
Write Buffer Programming
The write-buffer programming operation can be sus-
pended using the standard program suspend/resume
commands. Upon successful completion of the Write
Buffer Programming operation, the device is ready to
execute the next command.
Write Buffer Programming allows the system write to a
maximum of 16 words/32 bytes in one programming
operation. This results in faster effective programming
time than the standard programming algorithms. The
Write Buffer Programming command sequence is initi-
ated by first writing two unlock cycles. This is followed
by a third write cycle containing the Write Buffer Load
The Write Buffer Programming Sequence can be
aborted in the following ways:
26
Am29LV128M
July 1, 2002
A D V A N C E I N F O R M A T I O N
■ Load a value that is greater than the page buffer
from “0” back to a “1.” Attempting to do so may
cause the device to set DQ5 = 1, or cause the DQ7
and DQ6 status bits to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0.” Only erase operations can convert a
“0” to a “1.”
size during the Number of Locations to Program
step.
■ Write to an address in a sector different than the
one specified during the Write-Buffer-Load com-
mand.
■ Write an Address/Data pair to
a
different
Accelerated Program
write-buffer-page than the one selected by the
Starting Address during the write buffer data load-
ing stage of the operation.
The device offers accelerated program operations
through the WP#/ACC pin. When the system asserts
V
HH on the WP#/ACC pin, the device automatically en-
■ Write data other than the Confirm Command after
ters the Unlock Bypass mode. The system may then
write the two-cycle Unlock Bypass program command
sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation. Note that
the WP#/ACC pin must not be at VHH for operations
other than accelerated programming, or device dam-
age may result. WP# has an internal pullup; when un-
connected, WP# is at VIH.
the specified number of data load cycles.
The abort condition is indicated by DQ1 = 1, DQ7 =
DATA# (for the last address location loaded), DQ6 =
toggle, and DQ5=0. A Write-to-Buffer-Abort Reset
command sequence must be written to reset the de-
vice for the next operation. Note that the full 3-cycle
Write-to-Buffer-Abort Reset command sequence is re-
quired when using Write-Buffer-Programming features
in Unlock Bypass mode.
Figure 4 illustrates the algorithm for the program oper-
ation. Refer to the Erase and Program Operations
table in the AC Characteristics section for parameters,
and Figure 16 for timing diagrams.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
July 1, 2002
Am29LV128M
27
A D V A N C E I N F O R M A T I O N
Write “Write to Buffer”
command and
Sector Address
Part of “Write to Buffer”
Command Sequence
Write number of addresses
to program minus 1(WC)
and Sector Address
Write first address/data
Yes
WC = 0 ?
No
Write to a different
sector address
Abort Write to
Yes
Buffer Operation?
Write to buffer ABORTED.
Must write “Write-to-buffer
Abort Reset” command
sequence to return
No
(Note 1)
Write next address/data pair
to read mode.
WC = WC - 1
Write program buffer to
flash sector address
Notes:
1. When Sector Address is specified, any address in
the selected sector is acceptable. However, when
loading Write-Buffer address locations with data, all
addresses must fall within the selected Write-Buffer
Page.
Read DQ7 - DQ0 at
Last Loaded Address
2. DQ7 may change simultaneously with DQ5.
Therefore, DQ7 should be verified.
3. If this flowchart location was reached because
DQ5= “1”, then the device FAILED. If this
flowchart location was reached because DQ1=
“1”, then the Write to Buffer operation was
ABORTED. In either case, the proper reset
command must be written before the device can
begin another operation. If DQ1=1, write the
Write-Buffer-Programming-Abort-Reset
Yes
DQ7 = Data?
No
No
command. if DQ5=1, write the Reset command.
No
DQ1 = 1?
Yes
DQ5 = 1?
Yes
4. See Tables 9 and 10 for command sequences
required for write buffer programming.
Read DQ7 - DQ0 with
address = Last Loaded
Address
Yes
(Note 2)
DQ7 = Data?
No
(Note 3)
FAIL or ABORT
PASS
Figure 3. Write Buffer Programming Operation
Am29LV128M
28
July 1, 2002
A D V A N C E I N F O R M A T I O N
Program Suspend/Program Resume
Command Sequence
The Program Suspend command allows the system to
interrupt a programming operation or a Write to Buffer
programming operation so that data can be read from
any non-suspended sector. When the Program Sus-
pend command is written during a programming pro-
cess, the device halts the program operation within 1
ms and updates the status bits. Addresses are not re-
quired when writing the Program Suspend command.
START
Write Program
Command Sequence
Data Poll
from System
After the programming operation has been sus-
pended, the system can read array data from any
non-suspended sector. The Program Suspend com-
mand may also be issued during a programming oper-
ation while an erase is suspended. In this case, data
may be read from any addresses not in Erase Sus-
pend or Program Suspend. If a read is needed from
the SecSi Sector area (One-time Program area), then
user must use the proper command sequences to
enter and exit this region.
Embedded
Program
algorithm
in progress
Verify Data?
Yes
No
No
Increment Address
Last Address?
Yes
The system may also write the autoselect command
sequence when the device is in the Program Suspend
mode. The system can read as many autoselect
codes as required. When the device exits the autose-
lect mode, the device reverts to the Program Suspend
mode, and is ready for another valid operation. See
Autoselect Command Sequence for more information.
Programming
Completed
Note: See Tables 9 and 10 for program command
sequence.
After the Program Resume command is written, the
device reverts to programming. The system can deter-
mine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard pro-
gram operation. See Write Operation Status for more
information.
Figure 4. Program Operation
The system must write the Program Resume com-
mand (address bits are don’t care) to exit the Program
Suspend mode and continue the programming opera-
tion. Further writes of the Resume command are ig-
nored. Another Program Suspend command can be
written after the device has resume programming.
July 1, 2002
Am29LV128M
29
A D V A N C E I N F O R M A T I O N
When the Embedded Erase algorithm is complete, the
device returns to the read mode and addresses are no
longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, or DQ2.
Refer to the Write Operation Status section for infor-
mation on these status bits.
Program Operation
or Write-to-Buffer
Sequence in Progress
Write Program Suspend
Command Sequence
Write address/data
XXXh/B0h
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that oc-
curs, the chip erase command sequence should be
reinitiated once the device has returned to reading
array data, to ensure data integrity.
Command is also valid for
Erase-suspended-program
operations
Wait 1 ms
Autoselect and SecSi Sector
Read data as
required
read operations are also allowed
Figure 6 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations ta-
bles in the AC Characteristics section for parameters,
and Figure 18 section for timing diagrams.
Data cannot be read from erase- or
program-suspended sectors
Done
No
reading?
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command. Table 10 shows the ad-
dress and data requirements for the sector erase com-
mand sequence.
Yes
Write Program Resume
Command Sequence
Write address/data
XXXh/30h
Device reverts to
operation prior to
Program Suspend
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
Figure 5. Program Suspend/Program Resume
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Tables 9 and
10 show the address and data requirements for the
chip erase command sequence.
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise erasure may begin. Any sector erase
address and command following the exceeded
time-out may or may not be accepted. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector
Erase command is written. Any command other than
Sector Erase or Erase Suspend during the
time-out period resets the device to the read
mode. The system must rewrite the command se-
quence and any additional addresses and commands.
The system can monitor DQ3 to determine if the sec-
tor erase timer has timed out (See the section on DQ3:
Sector Erase Timer.). The time-out begins from the ris-
ing edge of the final WE# pulse in the command
sequence.
30
Am29LV128M
July 1, 2002
A D V A N C E I N F O R M A T I O N
When the Embedded Erase algorithm is complete, the
imum of 20 µs to suspend the erase operation. How-
ever, when the Erase Suspend command is written
during the sector erase time-out, the device immedi-
ately terminates the time-out period and suspends the
erase operation.
device returns to reading array data and addresses
are no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read
data from the non-erasing sector. The system can de-
termine the status of the erase operation by reading
DQ7, DQ6, or DQ2 in the erasing sector. Refer to the
Write Operation Status section for information on
these status bits.
After the erase operation has been suspended, the
device enters the erase-suspend-read mode. The sys-
tem can read data from or program data to any sector
not selected for erasure. (The device “erase sus-
pends” all sectors selected for erasure.) Reading at
any address within erase-suspended sectors pro-
duces status information on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
Refer to the Write Operation Status section for infor-
mation on these status bits.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other com-
mands are ignored. However, note that a hardware
reset immediately terminates the erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
Figure 6 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations ta-
bles in the AC Characteristics section for parameters,
and Figure 18 section for timing diagrams.
After an erase-suspended program operation is com-
plete, the device returns to the erase-suspend-read
mode. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits,
just as in the standard word program operation.
Refer to the Write Operation Status section for more
information.
Erase Suspend/Erase Resume
Commands
The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected
for erasure. This command is valid only during the
sector erase operation, including the 50 µs time-out
period during the sector erase command sequence.
The Erase Suspend command is ignored if written dur-
ing the chip erase operation or Embedded Program
algorithm.
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. Refer to the
Autoselect Mode and Autoselect Command Sequence
sections for details.
To resume the sector erase operation, the system
must write the Erase Resume command. The address
of the erase-suspended sector is required when writ-
ing this command. Further writes of the Resume com-
mand are ignored. Another Erase Suspend command
can be written after the chip has resumed erasing.
When the Erase Suspend command is written during
the sector erase operation, the device requires a max-
July 1, 2002
Am29LV128M
31
A D V A N C E I N F O R M A T I O N
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Tables 9 and 10 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
Figure 6. Erase Operation
32
Am29LV128M
July 1, 2002
A D V A N C E I N F O R M A T I O N
Command Definitions
Table 9. Command Definitions (x16 Mode, BYTE# = VIH)
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Second
Third
Fourth
Fifth
Sixth
Addr Data
Addr
Data
Addr
Data
Addr
Data
Addr Data Addr Data
Read (Note 6)
1
1
4
4
RA
XXX
555
555
RD
F0
Reset (Note 7)
Manufacturer ID
Device ID (Note 9)
AA
AA
2AA
2AA
55
55
555
555
90
90
X00
X01
0001
227E
X0E
2212 X0F 2200
SecSi Sector Factory Protect
(Note 10)
4
4
555
555
AA
AA
2AA
2AA
55
55
555
555
90
90
X03
(Note 10)
00/01
Sector Protect Verify (Note 12)
(SA)X02
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
3
4
4
3
1
3
3
2
2
6
6
1
1
1
555
555
555
555
SA
AA
AA
AA
AA
29
2AA
2AA
2AA
2AA
55
55
55
55
555
555
555
SA
88
90
A0
25
XXX
PA
00
PD
WC
Write to Buffer (Note 11)
Program Buffer to Flash
Write to Buffer Abort Reset (Note 13)
Unlock Bypass
SA
PA
PD
WBL
PD
555
555
XXX
XXX
555
555
BA
AA
AA
A0
90
2AA
2AA
PA
55
55
PD
00
55
55
555
555
F0
20
Unlock Bypass Program (Note 14)
Unlock Bypass Reset (Note 15)
Chip Erase
XXX
2AA
2AA
AA
AA
B0
30
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Program/Erase Suspend (Note 16)
Program/Erase Resume (Note 17)
CFI Query (Note 18)
BA
55
98
Legend:
X = Don’t care
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A22–A15 uniquely select any sector.
RA = Read Address of the memory location to be read.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on the falling edge of the WE#
or CE# pulse, whichever happens later.
BC = Word Count. Number of write buffer locations to load minus 1.
PD = Program Data for location PA. Data latches on the rising edge of
WE# or CE# pulse, whichever happens first.
Notes:
1. See Table 1 for description of bus operations.
lowest address sector, the data is 88h for factory locked and 08h
for not factor locked.
2. All values are in hexadecimal.
11. The total number of cycles in the command sequence is
determined by the number of words written to the write buffer. The
maximum number of cycles in the command sequence is 21.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
4. Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD and PD.
12. The data is 00h for an unprotected sector and 01h for a protected
sector.
5. Unless otherwise noted, address bits A22–A11 are don’t cares.
13. Command sequence resets device for next command after
aborted write-to-buffer operation.
6. No unlock or command cycles required when device is in read
mode.
14. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
7. The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when the device is in the autoselect mode, or if DQ5 goes high
while the device is providing status information.
15. The Unlock Bypass Reset command is required to return to the
read mode when the device is in the unlock bypass mode.
16. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
8. The fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care. See the Autoselect
Command Sequence section for more information.
9. The device ID must be read in three cycles.
17. The Erase Resume command is valid only during the Erase
Suspend mode.
10. If WP# protects the highest address sector, the data is 98h for
factory locked and 18h for not factory locked. If WP# protects the
18. Command is valid when device is ready to read array data or when
device is in autoselect mode.
July 1, 2002
Am29LV128M
33
A D V A N C E I N F O R M A T I O N
Table 10. Command Definitions (x8 Mode, BYTE# = VIL)
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Second
Third
Fourth
Fifth
Sixth
Addr Data
Addr
Data
Addr
Data
Addr
Data
Addr Data Addr Data
Read (Note 6)
Reset (Note 7)
Manufacturer ID
1
1
4
4
RA
RD
F0
XXX
AAA
AAA
AA
AA
555
555
55
55
AAA
AAA
90
90
X00
X02
01
7E
Device ID (Note 9)
X1C
12
X1E
00
SecSi Sector Factory Protect
(Note 10)
4
4
AAA
AAA
AA
AA
555
555
55
55
AAA
AAA
90
90
X06
(Note 10)
00/01
Sector Protect Verify (Note 12)
(SA)X04
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
3
4
4
3
1
3
3
2
2
6
6
1
1
1
AAA
AAA
AAA
AAA
SA
AA
AA
AA
AA
29
555
555
555
555
55
55
55
55
AAA
AAA
AAA
SA
88
90
A0
25
XXX
PA
00
PD
BC
Write to Buffer (Note 11)
Program Buffer to Flash
Write to Buffer Abort Reset (Note 13)
Unlock Bypass
SA
PA
PD
WBL
PD
AAA
AAA
XXX
XXX
AAA
AAA
BA
AA
AA
A0
90
555
555
PA
55
55
PD
00
55
55
AAA
AAA
F0
20
Unlock Bypass Program (Note 14)
Unlock Bypass Reset (Note 15)
Chip Erase
XXX
555
555
AA
AA
B0
30
AAA
AAA
80
80
AAA
AAA
AA
AA
555
555
55
55
AAA
SA
10
30
Sector Erase
Program/Erase Suspend (Note 16)
Program/Erase Resume (Note 17)
CFI Query (Note 18)
BA
AA
98
Legend:
X = Don’t care
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A22–A15 uniquely select any sector.
RA = Read Address of the memory location to be read.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on the falling edge of the WE#
or CE# pulse, whichever happens later.
BC = Byte Count. Number of write buffer locations to load minus 1.
PD = Program Data for location PA. Data latches on the rising edge of
WE# or CE# pulse, whichever happens first.
Notes:
1. See Table 1 for description of bus operations.
lowest address sector, the data is 88h for factory locked and 08h
for not factor locked.
2. All values are in hexadecimal.
11. The total number of cycles in the command sequence is
determined by the number of words written to the write buffer. The
maximum number of cycles in the command sequence is 37.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
4. Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD and PD.
12. The data is 00h for an unprotected sector group and 01h for a
protected sector group.
5. Unless otherwise noted, address bits A22–A11 are don’t cares.
13. Command sequence resets device for next command after
aborted write-to-buffer operation.
6. No unlock or command cycles required when device is in read
mode.
14. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
7. The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when the device is in the autoselect mode, or if DQ5 goes high
while the device is providing status information.
15. The Unlock Bypass Reset command is required to return to the
read mode when the device is in the unlock bypass mode.
16. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
8. The fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care. See the Autoselect
Command Sequence section for more information.
9. The device ID must be read in three cycles.
17. The Erase Resume command is valid only during the Erase
Suspend mode.
10. If WP# protects the highest address sector, the data is 98h for
factory locked and 18h for not factory locked. If WP# protects the
18. Command is valid when device is ready to read array data or when
device is in autoselect mode.
34
Am29LV128M
July 1, 2002
A D V A N C E I N F O R M A T I O N
WRITE OPERATION STATUS
The device provides several bits to determine the status of
a program or erase operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 11 and the following subsections describe the
function of these bits. DQ7 and DQ6 each offer a method
for determining whether a program or erase operation is
complete or in progress. The device also provides a
hardware-based output signal, RY/BY#, to determine
whether an Embedded Program or Erase operation is
in progress or has been completed.
valid data, the data outputs on DQ0–DQ6 may be still
invalid. Valid data on DQ0–DQ7 will appear on suc-
cessive read cycles.
Table 11 shows the outputs for Data# Polling on DQ7.
Figure 7 shows the Data# Polling algorithm. Figure 19
in the AC Characteristics section shows the Data#
Polling timing diagram.
DQ7: Data# Polling
START
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Program or Erase algorithm is in
progress or completed, or whether the device is in Erase
Suspend. Data# Polling is valid after the rising edge of the
final WE# pulse in the command sequence.
Read DQ7–DQ0
Addr = VA
During the Embedded Program algorithm, the device out-
puts on DQ7 the complement of the datum programmed to
DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to
DQ7. The system must provide the program address to
read valid status information on DQ7. If a program address
falls within a protected sector, Data# Polling on DQ7 is ac-
tive for approximately 1 µs, then the device returns to the
read mode.
Yes
DQ7 = Data?
No
No
DQ5 = 1?
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status infor-
mation on DQ7.
Yes
Read DQ7–DQ0
Addr = VA
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 is active for approximately 100 µs, then
the device returns to the read mode. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected. However, if the sys-
tem reads DQ7 at an address within a protected
sector, the status may not be valid.
Yes
DQ7 = Data?
No
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
Just prior to the completion of an Embedded Program
or Erase operation, DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the status or valid data. Even if the device has com-
pleted the program or erase operation and DQ7 has
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 7. Data# Polling Algorithm
July 1, 2002
Am29LV128M
35
A D V A N C E I N F O R M A T I O N
After an erase command sequence is written, if all sectors
RY/BY#: Ready/Busy#
selected for erasing are protected, DQ6 toggles for approxi-
mately 100 µs, then returns to reading array data. If not all
selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
The RY/BY# is a dedicated, open-drain output pin
which indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
The system can use DQ6 and DQ2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), DQ6 toggles. When the de-
vice enters the Erase Suspend mode, DQ6 stops toggling.
However, the system must also use DQ2 to determine
which sectors are erasing or erase-suspended. Alterna-
tively, the system can use DQ7 (see the subsection on
DQ7: Data# Polling).
pull-up resistor to VCC
.
If the output is low (Busy), the device is actively eras-
ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is in the read mode, the standby
mode, or in the erase-suspend-read mode. Table 11
shows the outputs for RY/BY#.
DQ6: Toggle Bit I
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any ad-
dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Table 11 shows the outputs for Toggle Bit I on DQ6.
Figure 8 shows the toggle bit algorithm. Figure 20 in
the “AC Characteristics” section shows the toggle bit
timing diagrams. Figure 21 shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE# to control the read cycles. When the operation is
complete, DQ6 stops toggling.
36
Am29LV128M
July 1, 2002
A D V A N C E I N F O R M A T I O N
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
START
Read DQ7–DQ0
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 11 to compare out-
puts for DQ2 and DQ6.
Read DQ7–DQ0
No
Toggle Bit
= Toggle?
Yes
Figure 8 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the RY/BY#: Ready/Busy# sub-
section. Figure 20 shows the toggle bit timing diagram.
Figure 21 shows the differences between DQ2 and
DQ6 in graphical form.
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
Reading Toggle Bits DQ6/DQ2
Refer to Figure 8 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the tog-
gle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is tog-
gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the de-
vice did not completed the operation successfully, and
the system must write the reset command to return to
reading array data.
Note: The system should recheck the toggle bit even if
DQ5 = “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
Figure 8. Toggle Bit Algorithm
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
the toggle bit and DQ5 through successive read cy-
cles, determining the status as described in the previ-
ous paragraph. Alternatively, it may choose to perform
July 1, 2002
Am29LV128M
37
A D V A N C E I N F O R M A T I O N
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 8).
mand. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between addi-
tional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sector Erase Command
Sequence section.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or
write-to-buffer time has exceeded a specified internal
pulse count limit. Under these conditions DQ5 produces a
“1,” indicating that the program or erase cycle was not suc-
cessfully completed.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all fur-
ther commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to
and following each subsequent sector erase com-
mand. If DQ3 is high on the second status check, the
last command might not have been accepted.
The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit
has been exceeded, DQ5 produces a “1.”
In all these cases, the system must write the reset
command to return the device to the reading the array
(or to erase-suspend-read if the device was previously
in the erase-suspend-program mode).
Table 11 shows the status of DQ3 relative to the other
status bits.
DQ3: Sector Erase Timer
DQ1: Write-to-Buffer Abort
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies after each additional sector erase com-
DQ1 indicates whether a Write-to-Buffer operation
was aborted. Under these conditions DQ1 produces a
“1”.
The
system
must
issue
the
Write-to-Buffer-Abort-Reset command sequence to re-
turn the device to reading array data. See Write Buffer
Table 11. Write Operation Status
DQ7
DQ5
DQ2
Status
(Note 2)
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
DQ1 RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
Program-Suspended
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
0
Standard
Mode
N/A
Invalid (not allowed)
Data
1
1
1
1
0
Program
Suspend
Mode
Program-
Sector
Suspend
Non-Program
Read
Suspended Sector
Erase-Suspended
1
No toggle
Toggle
0
N/A
Toggle
N/A
N/A
N/A
Erase-
Sector
Suspend
Erase
Suspend
Mode
Non-EraseSuspended
Read
Data
Sector
Erase-Suspend-Program
(Embedded Program)
DQ7#
0
N/A
Busy (Note 3)
Abort (Note 4)
DQ7#
DQ7#
Toggle
Toggle
0
0
N/A
N/A
N/A
N/A
0
1
0
0
Write-to-
Buffer
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the
maximum timing limits. Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
4. DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation.
38
Am29LV128M
July 1, 2002
A D V A N C E I N F O R M A T I O N
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
20 ns
20 ns
+0.8 V
Ambient Temperature
with Power Applied . . . . . . . . . . . . . –55°C to +125°C
–0.5 V
–2.0 V
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
VIO. . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
20 ns
A9, OE#, ACC, and RESET#
Figure 9. Maximum Negative
Overshoot Waveform
(Note 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V
All other pins (Note 1). . . . . . –0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O pins may
overshoot VSS to –2.0 V for periods of up to 20 ns.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
See Figure 9. During voltage transitions, input or I/O pins
may overshoot to VCC +2.0 V for periods up to 20 ns. See
Figure 10.
20 ns
VCC
+2.0 V
VCC
+0.5 V
2. Minimum DC input voltage on pins A9, OE#, ACC, and
RESET# is –0.5 V. During voltage transitions, A9, OE#,
ACC, and RESET# may overshoot VSS to –2.0 V for
periods of up to 20 ns. See Figure 9. Maximum DC input
voltage on pin A9, OE#, ACC, and RESET# is +12.5 V
which may overshoot to +14.0 V for periods up to 20 ns.
2.0 V
20 ns
20 ns
Figure 10. Maximum Positive
Overshoot Waveform
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Supply Voltages
VCC (regulated voltage range) . . . . . . . . . . . 3.0–3.6 V
VCC (full voltage range). . . . . . . . . . . . . . . . . 2.7–3.6 V
VIO (Note 2) . . . . . . . . . . . . . . 1.65–1.95 or 2.7–3.0 V
Notes:
1. Operating ranges define those limits between which the
functionality of the device is guaranteed.
2. See Ordering Information section for valid VCC/VIO range
combinations.
July 1, 2002
Am29LV128M
39
A D V A N C E I N F O R M A T I O N
DC CHARACTERISTICS
CMOS Compatible
Parameter
Symbol
Parameter Description
(Notes)
Test Conditions
Min
Typ
Max
Unit
VIN = VSS to VCC
,
ILI
Input Load Current (1)
±1.0
35
µA
µA
µA
VCC = VCC
max
ILIT
ILO
A9, ACC Input Load Current
Output Leakage Current
VCC = VCC max; A9 = 12.5 V
VOUT = VSS to VCC
CC = VCC max
,
±1.0
V
5 MHz
1 MHz
15
15
30
20
20
50
VCC Active Read Current
(2, 3)
ICC1
CE# = VIL, OE# = VIH
mA
ICC2
ICC3
ICC4
ICC5
ICC6
VCC Initial Page Read Current (2, 3)
VCC Intra-Page Read Current (2, 3)
VCC Active Write Current (3, 4)
VCC Standby Current (3)
CE# = VIL, OE# = VIH
mA
mA
mA
µA
CE# = VIL, OE# = VIH
10
50
1
20
60
5
CE# = VIL, OE# = VIH
CE#, RESET# = VCC ± 0.3 V, WP# = VIH
RESET# = VSS ± 0.3 V, WP# = VIH
VCC Reset Current (3)
1
5
µA
VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V,
WP# = VIH
ICC7
Automatic Sleep Mode (3, 5)
1
5
µA
ACC pin
VCC pin
10
30
20
60
mA
mA
V
IACC
ACC Accelerated Program Current (3)
CE# = VIL, OE# = VIH
3.0 V VIO
1.8 V VIO
3.0 V VIO
1.8 V VIO
–0.5
–0.4
0.8
VIL
Input Low Voltage (6)
0.4
V
VIO + 0.3
VIO + 0.4
2.0
V
VIH
Input High Voltage (6)
VIO – 0.4
V
VHH
VID
Voltage for ACC Program Acceleration
VCC = 2.7–3.6 V
VCC = 2.7–3.6 V
11.5
11.5
12.5
12.5
V
Voltage for Autoselect and Temporary Sector
Unprotect
V
3.0 V VIO
1.8 V VIO
3.0 V VIO
1.8 V VIO
I
OL = 4.0 mA, VCC = VCC min = VIO
OL = 100 µA, VCC = VCC min = VIO
0.4
0.1
V
V
V
VOL
Output Low Voltage
I
IOH = –2.0 mA, VCC = VCC min = VIO
OH = –100 µA, VCC = VCC min = VIO
2.4
VOH
Output High Voltage
VIO – 0.1
I
VLKO
Low VCC Lock-Out Voltage (7)
2.3
2.5
V
Notes:
1. On the WP#/ACC pin only, the maximum input load current when
WP# = VIL is ± 5.0 µA.
5. Automatic sleep mode enables the low power mode when
addresses remain stable for tACC + 30 ns. Typical sleep mode
current is 200 nA.
2. The ICC current listed is typically less than 2 mA/MHz, with OE# at
VIH.
6. VIO voltage requirements. VCC = 3 V and VIO = 3 V or 1.8 V.
7. Not 100% tested.
3. Maximum ICC specifications are tested with VCC = VCCmax.
4. ICC active while Embedded Erase or Embedded Program is in
progress.
40
Am29LV128M
July 1, 2002
A D V A N C E I N F O R M A T I O N
TEST CONDITIONS
Table 12. Test Specifications
3.3 V
Test Condition
Output Load
All Speeds
1 TTL gate
Unit
2.7 kΩ
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
C
L
6.2 kΩ
0.0–3.0
Input timing measurement
reference levels (See Note)
1.5
V
V
Output timing measurement
reference levels
0.5 VIO
Note: Diodes are IN3064 or equivalent
Figure 11. Test Setup
Note: If VIO < VCC, the reference level is 0.5 VIO.
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Changing, State Unknown
Don’t Care, Any Change Permitted
Does Not Apply
Center Line is High Impedance State (High Z)
3.0 V
1.5 V
0.5 VIO V
Input
Measurement Level
Output
0.0 V
Note: If VIO < VCC, the input measurement reference level is 0.5 VIO.
Figure 12. Input Waveforms and
Measurement Levels
July 1, 2002
Am29LV128M
41
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Read-Only Operations
Parameter
Speed Options
JEDEC Std. Description
Test Setup
90R
90
101
100
100
100
30
112
110
110
110
40
120
120
120
120
40
Unit
ns
tAVAV
tAVQV
tELQV
tRC Read Cycle Time (Note 1)
Min
CE#, OE# = VIL Max
tACC Address to Output Delay
90
ns
tCE Chip Enable to Output Delay
tPACC Page Access Time
OE# = VIL
Max
Max
Max
Max
Max
90
ns
25
ns
tGLQV
tEHQZ
tGHQZ
tOE Output Enable to Output Delay
tDF Chip Enable to Output High Z (Note 1)
tDF Output Enable to Output High Z (Note 1)
25
30
40
40
ns
25
25
ns
ns
Output Hold Time From Addresses, CE#
or OE#, Whichever Occurs First
tAXQX
tOH
Min
Min
Min
0
0
ns
ns
ns
Read
Output Enable Hold
tOEH
Toggle and
Data# Polling
Time (Note 1)
10
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 12 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
Output Valid
HIGH Z
HIGH Z
Outputs
RESET#
RY/BY#
0 V
Figure 13. Read Operation Timings
42
Am29LV128M
July 1, 2002
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Same Page
A22-A2
A1-A0*
Ad
Aa
tACC
Ab
tPACC
Ac
tPACC
tPACC
Data Bus
Qa
Qb
Qc
Qd
CE#
OE#
* Figure shows word mode. Addresses are A1–A-1 for byte mode.
Figure 14. Page Read Timings
July 1, 2002
Am29LV128M
43
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std.
Description
RESET# Pin Low (During Embedded Algorithms)
All Speed Options
Unit
tReady
Max
Max
20
µs
to Read Mode (See Note)
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
tReady
500
ns
tRP
tRH
RESET# Pulse Width
Min
Min
Min
500
50
ns
ns
µs
Reset High Time Before Read (See Note)
RESET# Low to Standby Mode
tRPD
20
Note: Not 100% tested.
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 15. Reset Timings
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Am29LV128M
July 1, 2002
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Erase and Program Operations
Parameter
Speed Options
JEDEC
tAVAV
Std.
tWC
tAS
Description
90R 101
90 100
112
120 Unit
Write Cycle Time (Note 1)
Address Setup Time
Min
Min
Min
Min
110
120
ns
ns
ns
ns
tAVWL
0
tASO
tAH
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
15
45
tWLAX
Address Hold Time From CE# or OE# high
during toggle bit polling
tAHT
Min
0
ns
tDVWH
tWHDX
tDS
tDH
Data Setup Time
Min
Min
Min
45
0
ns
ns
ns
Data Hold Time
tOEPH
Output Enable High during toggle bit polling
20
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHWL
tGHWL
Min
0
ns
tELWL
tWHEH
tWLWH
tWHDL
tCS
tCH
CE# Setup Time
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Min
Min
0
0
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs
µs
µs
µs
sec
ns
µs
CE# Hold Time
tWP
Write Pulse Width
35
30
tWPH
Write Pulse Width High
Write Buffer Program Operation (Notes 2, 3)
100
Per Byte
2.95
5.9
2.4
4.7
50
Effective Write Buffer Program Operation
(Notes 2, 4)
Per Word
Per Byte
Accelerated Effective Write Buffer
Program Operation (Notes 2, 4)
tWHWH1
tWHWH1
Per Word
Byte
Program Operation (Note 2)
Word
100
40
Byte
Accelerated Programming Operation
(Note 2)
Word
80
tWHWH2
tWHWH2 Sector Erase Operation (Note 2)
0.4
250
50
tVHH
tVCS
VHH Rise and Fall Time (Note 1)
VCC Setup Time (Note 1)
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
3. For 1–16 words/1–32 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
July 1, 2002
Am29LV128M
45
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#
OE#
tCH
tWHWH1
tWP
WE#
Data
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 16. Program Operation Timings
VHH
VIL or VIH
VIL or VIH
ACC
tVHH
tVHH
Figure 17. Accelerated Program Timing Diagram
46
Am29LV128M
July 1, 2002
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.
2. These waveforms are for the word mode.
Figure 18. Chip/Sector Erase Operation Timings
July 1, 2002
Am29LV128M
47
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
tRC
Addresses
VA
tACC
tCE
VA
VA
CE#
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ0–DQ6
Status Data
True
Valid Data
Status Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 19. Data# Polling Timings (During Embedded Algorithms)
48
Am29LV128M
July 1, 2002
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
tAHT
tAS
Addresses
tAHT
tASO
CE#
tOEH
WE#
tCEPH
tOEPH
OE#
tDH
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
DQ6/DQ2
RY/BY#
Valid Data
(first read)
(second read)
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle
Figure 20. Toggle Bit Timings (During Embedded Algorithms)
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle
DQ2 and DQ6.
Figure 21. DQ2 vs. DQ6
July 1, 2002
Am29LV128M
49
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
Min
500
ns
RESET# Setup Time for Temporary Sector
Unprotect
tRSP
4
µs
Note: Not 100% tested.
VID
VID
RESET#
VSS, VIL,
or VIH
VSS, VIL,
or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRRB
tRSP
RY/BY#
Figure 22. Temporary Sector Group Unprotect Timing Diagram
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Am29LV128M
July 1, 2002
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
VID
VIH
RESET#
SA, A6,
A1, A0
Valid*
Sector Group Protect or Unprotect
60h 60h
Valid*
Valid*
Status
Verify
40h
Data
Sector Group Protect: 150 µs,
Sector Group Unprotect: 15 ms
1 µs
CE#
WE#
OE#
* For sector group protect, A6 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 23. Sector Group Protect and Unprotect Timing Diagram
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Am29LV128M
51
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Alternate CE# Controlled Erase and Program Operations
Parameter
Speed Options
JEDEC
tAVAV
Std.
tWC
tAS
Description
90R 101R 112R 120
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Min
Min
Min
Min
Min
90
100
110
120
tAVWL
tELAX
tDVEH
tEHDX
0
ns
tAH
45
45
0
ns
tDS
ns
tDH
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHEL
tGHEL
Min
0
ns
tWLEL
tEHWH
tELEH
tEHEL
tWS
tWH
tCP
WE# Setup Time
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
0
0
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs
µs
µs
µs
sec
WE# Hold Time
CE# Pulse Width
45
30
100
tCPH
CE# Pulse Width High
Write Buffer Program Operation (Notes 2, 3)
Per Byte
2.95
5.9
2.4
4.7
50
Effective Write Buffer Program
Operation (Notes 2, 4)
Per Word
Per Byte
Per Word
Byte
Effective Accelerated Write Buffer
Program Operation (Notes 2, 4)
tWHWH1
tWHWH1
Program Operation (Note 2)
Word
100
40
Byte
Accelerated Programming
Operation (Note 2)
Word
80
tWHWH2
Notes:
tWHWH2 Sector Erase Operation (Note 2)
0.4
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
3. For 1–16 words/1–32 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
52
Am29LV128M
July 1, 2002
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.
Figure 24. Alternate CE# Controlled Write (Erase/Program)
Operation Timings
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
VCC Current
–1.0 V
VCC + 1.0 V
+100 mA
–100 mA
Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
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A D V A N C E I N F O R M A T I O N
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
Unit
sec
sec
µs
Comments
Sector Erase Time
Chip Erase Time
0.4
90
15
Excludes 00h programming
prior to erasure (Note 5)
Per Byte
Per Word
Byte
2.95
5.9
50
105
210
Effective Write Buffer Program
Time (Note 3)
µs
TBD
218
µs
Program Time
Word
100
2.4
4.7
40
µs
Excludes system level
overhead (Note 6)
Byte
TBD
TBD
TBD
TBD
TBD
µs
Effective Accelerated
Program Time (Note 3)
Word
µs
Byte
µs
Accelerated Program Time
Word
80
µs
Chip Program Time (Note 4)
TBD
sec
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 100,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 3.0 V, 100,000 cycles.
3. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
4. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words
program faster than the maximum program times listed.
5. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table
10 for further information on command definitions.
7. The device has a minimum erase and program cycle endurance of 100,000 cycles.
TSOP PIN AND BGA PACKAGE CAPACITANCE
Parameter Symbol
Parameter Description
Test Setup
Typ
6
Max
7.5
5
Unit
pF
pF
pF
pF
pF
pF
TSOP
BGA
CIN
Input Capacitance
VIN = 0
4.2
8.5
5.4
7.5
3.9
TSOP
BGA
12
6.5
9
COUT
Output Capacitance
VOUT = 0
VIN = 0
TSOP
BGA
CIN2
Control Pin Capacitance
4.7
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Description
Test Conditions
150°C
Min
Unit
Years
Years
10
20
Minimum Pattern Data Retention Time
125°C
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Am29LV128M
July 1, 2002
A D V A N C E I N F O R M A T I O N
PHYSICAL DIMENSIONS
TS056/TSR056—56-Pin Standard/Reverse Thin Small Outline Package (TSOP)
NOTES:
PACKAGE
TS/TSR 56
JEDEC
MO-142 (B) EC
1
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982.)
SYMBOL
MIN.
---
NOM.
---
MAX.
1.20
0.15
1.05
0.23
0.27
0.16
0.21
2
3
4
PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
A
A1
A2
b1
b
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.
0.05
0.95
0.17
0.17
0.10
0.10
---
1.00
0.20
0.22
---
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
5
6
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
MOLD PROTUSION IS 0.15 mm PER SIDE.
c1
c
---
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE
DAMBAR PROTUSION SHALL BE 0.08 mm TOTAL IN EXCESS OF b
DIMENSION AT MAX MATERIAL CONDITION. MINIMUM SPACE BETWEEN
PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 mm.
D
19.90
18.30
20.00
18.40
20.20
18.50
D1
E
e
13.90
14.00
14.10
7
THESE DIMESIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10 mm AND 0.25 mm FROM THE LEAD TIP.
0.50 BASIC
L
0.50
0˚
0.60
3˚
0.70
5˚
8. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE
SEATING PLANE.
O
R
N
0.08
---
0.20
9
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
56
3160\38.10A
July 1, 2002
Am29LV128M
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A D V A N C E I N F O R M A T I O N
PHYSICAL DIMENSIONS
LAA064—64-Ball Fortified Ball Grid Array
13 x 11 mm Package
56
Am29LV128M
July 1, 2002
A D V A N C E I N F O R M A T I O N
Ordering Information
REVISION SUMMARY
Revision A (October 3, 2001)
Corrected device density in device number/descrip-
tion.
Initial release as abbreviated Advance Information
data sheet.
Physical Dimensions
Revision A+1 (March 20, 2002)
Added drawing that shows both TS056 and TSR056
specifications.
Distinctive Characteristics
Clarified description of Enhanced VersatileIO control.
Revision B (July 1, 2002)
Expanded data sheet to full specification version.
Trademarks
Copyright © 2002 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
July 1, 2002
Am29LV128M
57
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