AM29F800T-120FEB [SPANSION]
Flash, 512KX16, 120ns, PDSO48, REVERSE, TSOP-48;
| 型号： | AM29F800T-120FEB |
| 厂家： | 
SPANSION |
| 描述： | Flash, 512KX16, 120ns, PDSO48, REVERSE, TSOP-48 光电二极管 内存集成电路 |
| 文件： | 总41页 (文件大小：250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
Am29F800T/Am29F800B
8 Megabit (1,048,576 x 8-Bit/524,288 x 16-Bit) CMOS
5.0 Volt-only, Sector Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
■ 5.0 V ± 10% for read and write operations
— Minimizes system level power requirements
■ Compatible with JEDEC standards
■ Embedded Program Algorithm
— Automatically programs and verifies data at
specified address
— Pinout and software compatible with
single-power-supply flash
■ Data Polling and Toggle Bit feature for detection
of program or erase cycle completion
— Superior inadvertent write protection
■ Ready/Busy output (RY/BY)
— Hardware method for detection of program or
erase cycle completion
■ Package options
— 44-pin SO
■ Erase Suspend/Resume
— 48-pin TSOP
— Supports reading data from or programming
data to a sector not being erased
■ Minimum 100,000 write/erase cycles guaranteed
■ High performance
■ Low power consumption
— 70 ns maximum access time
— 20 mA typical active read current for Byte Mode
— 28 mA typical active read current for Word Mode
— 30 mA typical program/erase current
■ Sector erase architecture
— One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and
fifteen 64 Kbytes
■ Enhanced power management for standby
— Any combination of sectors can be erased. Also
supports full chip erase.
mode
— 1 µA typical standby current
■ Sector protection
■ Boot Code Sector Architecture
— T = Top sector
— Hardware method that disables any combination
of sectors from write or erase operations.
Implemented using standard PROM
programming equipment.
— B = Bottom sector
■ Hardware RESET pin
■ Embedded Erase Algorithm
— Resets internal state machine to the read mode
— Automatically pre-programs and erases the chip
or any sector
GENERAL DESCRIPTION
The Am29F800 is an 8 Mbit, 5.0 Volt-only Flash mem-
ory organized as 1 Mbyte of 8 bits each or 512K words
of 16 bits each. For flexible erase capability, the 8 Mbits
of data are divided into 19 sectors as follows: one 16
Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64 Kbyte.
Eight bits of data appear on DQ0–DQ7 in byte mode; in
word mode 16 bits appear on DQ0–DQ15. The
Am29F800 is offered in 44-pin SO and 48-pin TSOP
packages. This device is designed to be programmed
in-system with the standard system 5.0 Volt VCC sup-
ply. A VPP of 12.0 volts is not required for program or
erase operations. The device can also be programmed
in standard EPROM programmers.
The standard Am29F800 offers access times of 70 ns, 90
ns, 120 ns, and 150 ns, allowing high-speed micropro-
cessors to operate without wait states. To eliminate bus
contention, the device has separate chip enable (CE),
write enable (WE), and output enable (OE) controls.
The Am29F800 is entirely command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine which
controls the erase and program circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
8/18/97
Publication# 20375 Rev: C Amendment/+1
Issue Date: August 1997
P R E L I M I N A R Y
of the device is similar to reading from 12.0 Volt Flash
The device features single 5.0 Volt power supply oper-
ation for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations. A low VCC detector au-
tomatically inhibits write operations during power tran-
sitions. The end of program or erase is detected by the
RY/BY pin. Data Polling of DQ7, or by the Toggle Bit
(DQ6). Once the end of a program or erase cycle has
been completed, the device automatically resets to the
read mode.
or EPROM devices.
The Am29F800 is programmed by executing the pro-
gram command sequence. This will invoke the Embed-
ded Program Algorithm which is an internal algorithm
that automatically times the program pulse widths and
verifies proper cell margin. Erase is accomplished by
executing the erase command sequence. This
will invoke the Embedded Erase Algorithm which is an
internal algorithm that automatically preprograms the
array if it is not already programmed before executing
the erase operation. During erase, the device automat-
ically times the erase pulse widths and verifies proper
cell margin.
The Am29F800 also has a hardware RESET pin.
When this pin is driven low, execution of any Embed-
ded Program Algorithm or Embedded Erase Algorithm
will be terminated. The internal state machine will then
be reset into the read mode. The RESET pin may be
tied to the system reset circuitry. Therefore, if a system
reset occurs during the Embedded Program Algorithm
or Embedded Erase Algorithm, the device will be auto-
matically reset to the read mode and will have errone-
ous data stored in the address locations being
operated on. These locations will need re-writing after
the Reset. Resetting the device will enable the sys-
tem’s microprocessor to read the boot-up firmware
from the Flash memory.
This device also features a sector erase architecture.
This allows for sectors of memory to be erased and re-
programmed without affecting the data contents of
other sectors. A sector is typically erased and verified
within 1.5 seconds. The Am29F800 is erased when
shipped from the factory.
The Am29F800 device also features hardware sector
protection. This feature will disable both program and
erase operations in any combination of nineteen sec-
tors of memory.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The Am29F800 memory electrically erases all
bits within a sector simultaneously via Fowler-Nor-
dhiem tunneling. The bytes/words are programmed
one byte/word at a time using the EPROM program-
ming mechanism of hot electron injection.
AMD has implemented an Erase Suspend feature that
enables the user to put erase on hold for any period of
time to read data from or program data to a sector that
was not being erased. Thus, true background erase
can be achieved.
2
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
PRODUCT SELECTOR GUIDE
Family Part No:
Am29F800
Ordering Part No: V = 5.0 V ± 10%
-70
70
70
30
-90
90
90
35
-120
120
120
50
-150
150
150
55
CC
Max Access Time (ns)
CE (E) Access (ns)
OE (G) Access (ns)
BLOCK DIAGRAM
DQ0–DQ15
RY/BY
Buffer
RY/BY
V
V
CC
Input/Output
Buffers
SS
Erase Voltage
Generator
State
Control
WE
BYTE
Command
Register
RESET
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE
OE
Y-Decoder
Y-Gating
STB
V
Detector
Timer
CC
X-Decoder
Cell Matrix
A0–A18
A–1
20375C-1
8/18/97
Am29F800T/Am29F800B
3
P R E L I M I N A R Y
CONNECTION DIAGRAMS
SO
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET
WE
RY/BY
A18
A17
A7
1
2
A8
3
A9
4
A10
A11
A12
A13
A14
A15
A16
BYTE
A6
5
A5
6
A4
7
A3
8
A2
9
A1
10
11
12
13
14
15
16
17
18
19
20
21
22
A0
CE
V
V
SS
SS
DQ15/A-1
DQ7
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
20375C-2
4
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
CONNECTION DIAGRAMS
1
2
3
4
5
6
7
A16
BYTE
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
8
9
10
11
12
13
14
15
16
17
18
19
20
WE
RESET
NC
NC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
21
22
23
24
OE
VSS
CE
A0
Standard TSOP
20375C-3
A16
BYTE
VSS
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE
RESET
NC
NC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
VSS
CE
A0
Reverse TSOP
20375C-4
8/18/97
Am29F800T/Am29F800B
5
P R E L I M I N A R Y
PIN CONFIGURATION
LOGIC SYMBOL
A0–A18
BYTE
CE
= 19 Addresses
= Selects 8-bit or 16-bit mode
= Chip Enable
A-1
19
16 or 8
A0–A18
DQ0–DQ14 = 15 Data Inputs/Outputs
DQ0–DQ15
DQ15/A-1 = DQ15 Data Input/Output,
A-1 Address Mux
CE (E)
OE (G)
NC
= Pin Not Connected Internally
= Output Enable
OE
WE (W)
RESET
RESET
RY/BY
VCC
= Hardware Reset Pin, Active Low
= Ready/Busy Output
BYTE
RY/BY
= +5.0 Volt Single-Power Supply
20375C-5
(±10% for -70, -90, -120, -150)
VSS
WE
= Device Ground
= Write Enable
6
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of:
AM29F800
T
-70
E
C
B
OPTIONAL PROCESSING
Blank = Standard Processing
B
= Burn-In
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I
= Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
E = 48-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 048)
F = 48-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR048)
S = 44-Pin Small Outline Package (SO 044)
SPEED OPTION
See Product Selector Guide and
Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
DEVICE NUMBER/DESCRIPTION
Am29F800
8 Megabit (1M x 8-Bit/512K x 16-Bit) CMOS Flash Memory
5.0 Volt-only Program and Erase
Valid Combinations
Valid Combinations
EC, EI, FC, FI, SC, SI
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
AM29F800T-70,
AM29F800B-70
AM29F800T-90,
AM29F800B-90
EC, EI, EE, EEB,
FC, FI, FE, FEB,
SC, SI, SE, SEB
AM29F800T-120,
AM29F800B-120
AM29F800T-150,
AM29F800B-150
8/18/97
Am29F800T/Am29F800B
7
P R E L I M I N A R Y
Table 1. Am29F800 User Bus Operations (BYTE = VIH)
Operation
Autoselect, AMD Manuf. Code (Note 1)
Autoselect Device Code (Note 1)
Read
CE
L
OE
L
WE
H
H
X
A0
L
A1
L
A6
L
A9
DQ0–DQ15
Code
RESET
V
V
H
H
H
H
H
H
H
ID
ID
L
L
H
L
L
Code
L
L
A0
X
A1
X
A6
X
A9
X
D
OUT
Standby
H
L
X
H
H
L
X
HIGH Z
HIGH Z
Output Disable
H
L
X
X
X
X
Write
L
A0
L
A1
H
A6
L
A9
D
IN
Verify Sector Protect (Note 2)
Temporary Sector Unprotect
Hardware Reset
L
H
X
V
Code
X
ID
X
X
X
X
X
X
X
X
V
ID
X
X
X
X
X
HIGH Z
L
Table 2. Am29F800 User Bus Operations (BYTE = VIL)
Operation
CE
OE
WE
A0
A1
A6
A9
DQ0–DQ7 DQ8–DQ15 RESET
Autoselect, AMD Manuf. Code
(Note 1)
L
L
H
L
L
L
V
Code
Code
HIGH Z
H
ID
Autoselect Device Code (Note 1)
L
L
H
L
L
L
L
H
X
X
H
L
H
A0
X
L
A1
X
L
A6
X
V
HIGH Z
HIGH Z
HIGH Z
HIGH Z
HIGH Z
H
H
H
H
H
ID
Read
A9
X
D
OUT
Standby
Output Disable
Write
X
H
H
HIGH Z
HIGH Z
X
X
X
X
A0
A1
A6
A9
D
IN
Verify
L
L
H
L
H
L
V
Code
HIGH Z
H
ID
Sector Protect (Note 2)
Temporary
X
X
X
X
X
X
X
X
X
X
X
X
X
X
HIGH Z
HIGH Z
V
ID
Sector Unprotect
Hardware Reset
X
HIGH Z
L
Legend:
L = logic 0, H = logic 1, X = Don’t Care. See Characteristics for voltage levels.
Notes:
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 7.
2. Refer to the section on Sector Protection.
Read Mode
The Am29F800 has two control functions which must
be satisfied in order to obtain data at the outputs. CE is
the power control and should be used for device selec-
tion. OE is the output control and should be used to
gate data to the output pins if a device is selected.
pins (assuming the addresses have been stable for at
least tACC–tOE time).
Standby Mode
There are two ways to implement the standby mode on
the Am29F800 device, both using the CE pin.
Address access time (tACC) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses
and stable CE to valid data at the output pins.
The output enable access time is the delay from the
falling edge of OE to valid data at the output
A CMOS standby mode is achieved with the CE input
held at VCC ± 0.3V. Under this condition the current is
typically reduced to less than 5 µA. A TTL standby
mode is achieved with the CE pin held at VIH. Under
this condition the current is typically reduced to 1 mA.
8
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
In the standby mode the outputs are in the high imped-
The manufacturer and device codes may also be read
via the command register, for instances when the
Am29F800 is erased or programmed in a system with-
out access to high voltage on the A9 pin. The command
sequence is illustrated in Table 4 (see Autoselect Com-
mand Sequence).
ance state, independent of the OE input.
Output Disable
With the OE input at a logic high level (VIH), output from
the device is disabled. This will cause the output pins
to be in a high impedance state.
Byte 0 (A0 = VIL) represents the manufacturer’s code
(AMD=01H) and byte 1 (A0 = VIH) the device identifier
code (Am29F800T = D6H and Am29F800B = 58H for
x8 mode; Am29F800T = 22D6H and Am29F800B =
2258H for x16 mode). These two bytes/words are
given in the table below. All identifiers for manufacturer
and device will exhibit odd parity with DQ7 defined as
the parity bit. In order to read the proper device codes
when executing the Autoselect, A1 must be VIL (see
Tables 3 and 4).
Autoselect
The autoselect mode allows the reading of a binary
code from the device and will identify its manufacturer
and type. This mode is intended for use by program-
ming equipment for the purpose of automatically
matching the device to be programmed with its corre-
sponding programming algorithm. This mode is func-
tional over the entire temperature range of the device.
To activate this mode, the programming equipment
must force VID (11.5 V to 12.5 V) on address pin A9.
Two identifier bytes may then be sequenced from the
device outputs by toggling address A0 from VIL to VIH.
All addresses are don’t cares except A0, A1, and A6
(see Table 3).
The autoselect mode also facilitates the determination
of sector protection in the system. By performing a read
operation at the address location XX02H with the
higher order address bits A12–A18 set to the desired
sector address, the device will return 01H for a pro-
tected sector and 00H for a non-protected sector.
Table 3. Am29F800 Sector Protection Verify Autoselect Codes
Type
A12–A18
A6
A1
A0
Code (HEX)
01H
Manufacturer Code—AMD
X
V
V
V
IL
IL
IL
Byte
Word
Byte
D6H
Am29F800T
Am29F800B
X
X
V
V
V
IL
IL
IH
IH
22D6H
58H
Am29F800 Device
V
V
V
V
IL
IL
IL
Word
2258H
Sector
Address
Sector Protection
V
V
01H*
IH
IL
*Outputs 01H at protected sector addresses
Table 4. Expanded Autoselect Code Table
DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ
Code
Type
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Manufacturer Code—AMD
01H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Am29F800T(B) D6H A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
(W) 22D6H
1
1
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1
0
0
0
1
0
Am29F800
Device
Am29F800B(B)
A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
0
0
1
1
0
0
1
1
1
1
0
0
0
0
0
0
58H
2258H
(W)
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
Sector Protection
01H
0
0
0
0
0
0
0
1
(B) – Byte mode
(W) – Word mode
8/18/97
Am29F800T/Am29F800B
9
P R E L I M I N A R Y
Table 5. Sector Address Tables (Am29F800T)
Sector
(x16)
Address Range
(x8)
A18
A17
A16
A15
A14
A13
A12
Size
Address Range
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
32 Kbytes
16 Kwords
8 Kbytes
SA0
SA1
0
0
0
0
X
X
X
00000h–07FFFh 00000h–0FFFFh
08000h–0FFFFh 10000h–1FFFFh
10000h–17FFFh 20000h–2FFFFh
18000h–1FFFFh 30000h–3FFFFh
20000h–27FFFh 40000h–4FFFFh
28000h–2FFFFh 50000h–5FFFFh
30000h–37FFFh 60000h–6FFFFh
38000h–3FFFFh 70000h–7FFFFh
40000h–47FFFh 80000h–8FFFFh
48000h–4FFFFh 90000h–9FFFFh
50000h–57FFFh A0000h–AFFFFh
58000h–5FFFFh B0000h–BFFFFh
60000h–67FFFh C0000h–CFFFFh
68000h–6FFFFh D0000h–DFFFFh
70000h–77FFFh E0000h–EFFFFh
78000h–7BFFFh F0000h–F7FFFh
7C000h–7CFFFh F8000h–F9FFFh
7D000h–7DFFFh FA000h–FBFFFh
7E000h–7FFFFh FC000h–FFFFFh
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
1
4 Kwords
8 Kbytes
1
0
1
4 Kwords
16 Kbytes
8 Kwords
1
1
X
Note: The address range is A18:A if in byte mode (BYTE = V ). The address range is A18:A0 if in word mode (BYTE = V ).
–1
IL
IH
10
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
Table 6. Sector Address Tables (Am29F800B)
Sector
(x16)
(x8)
A18
A17
A16
A15
A14
A13
A12
Size
Address Range
Address Range
16 Kbytes
8 Kwords
8 Kbytes
SA0
SA1
0
0
0
0
0
0
X
00000h–01FFFh
00000h–03FFFh
04000h–05FFFh
06000h–07FFFh
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
02000h–02FFFh
03000h–03FFFh
4 Kwords
8 Kbytes
SA2
4 Kwords
32 Kbytes
16 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
SA3
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
04000h–07FFFh 08000h–0FFFFh
08000h–0FFFFh 10000h–1FFFFh
10000h–17FFFh 20000h–2FFFFh
18000h–1FFFFh 30000h–3FFFFh
20000h–27FFFh 40000h–4FFFFh
28000h–2FFFFh 50000h–5FFFFh
30000h–37FFFh 60000h–6FFFFh
38000h–3FFFFh 70000h–7FFFFh
40000h–47FFFh 80000h–8FFFFh
48000h–4FFFFh 90000h–9FFFFh
50000h–57FFFh A0000h–AFFFFh
58000h–5FFFFh B0000h–BFFFFh
60000h–67FFFh C0000h–CFFFFh
68000h–6FFFFh D0000h–DFFFFh
70000h–77FFFh E0000h–EFFFFh
78000h–7FFFFh F0000h–FFFFFh
SA4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
Note: The address range is A18:A if in byte mode (BYTE = V ). The address range is A18:A0 if in word mode (BYTE = V ).
–1
IL
IH
8/18/97
Am29F800T/Am29F800B
11
P R E L I M I N A R Y
It is possible to determine if a sector is protected in the
Write
system by writing an Autoselect command. Performing
a read operation at the address location XX02H, where
the higher order address bits A12–A18 is the desired
sector address, will produce a logical “1” at DQ0 for a
protected sector. See Table 3 for Autoselect codes.
Device erasure and programming are accomplished
via the command register. The contents of the register
serve as inputs to the internal state machine. The state
machine outputs dictate the function of the device.
The command register itself does not occupy any ad-
dressable memory location. The register is a latch used
to store the commands, along with the address and
data information needed to execute the command. The
command register is written to by bringing WE to VIL,
while CE is at VIL and OE is at VIH. Addresses are
latched on the falling edge of WE or CE, whichever
happens later; while data is latched on the rising edge
of WE or CE, whichever happens first. Standard micro-
processor write timings are used.
Temporary Sector Unprotect
This feature allows temporary unprotection of previ-
ously protected sectors of the Am29F800 device in
order to change data in-system. The Sector Unprotect
mode is activated by setting the RESET pin to high volt-
age (12V). During this mode, formerly protected sec-
tors can be programmed or erased by selecting the
sector addresses. Once the 12 V is taken away from
the RESET pin, all the previously protected sectors will
be protected again. Refer to Figures 17 and 18.
Refer to AC Write Characteristics and the Erase/Pro-
gramming Waveforms for specific timing parameters.
Command Definitions
Device operations are selected by writing specific ad-
dress and data sequences into the command register.
Writing incorrect address and data values or writ-
ing them in the improper sequence will reset the
device to the read mode. Table 7 defines the valid
register command sequences. Note that the Erase
Suspend (B0H) and Erase Resume (30H) commands
are valid only while the Sector Erase operation is in
progress. Moreover, both Reset/Read commands are
functionally equivalent, resetting the device to the
read mode.
Sector Protection
The Am29F800 features hardware sector protection.
This feature will disable both program and erase oper-
ations in any combination of nineteen sectors of mem-
ory. The sector protect feature is enabled using
programming equipment at the user’s site. The device
is shipped with all sectors unprotected. Alternatively,
AMD may program and protect sectors in the factory
prior to shipping the device (AMD’s ExpressFlash™
Service).
12
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
Table 7. Am29F800 Command Definitions
Second Bus
Read/Write
Cycle
Fourth Bus
Read/Write
Cycle
Command
Sequence
Read/Reset
(Note 2)
Bus
Write
Cycles
First Bus
Write Cycle
Third Bus Write
Cycle
Fifth Bus
Write Cycle
Sixth Bus
Write Cycle
Req’d Addr
Data
XXF0
F0
Addr
Data
Addr
Data
Addr
Data
Addr
Data Addr Data
Word
Byte
Reset/Read
1
3
XXX
RA
RD
Word
Byte
555
AAA
555
XXAA
AA
2AA
555
2AA
XX55
55
555
AAA
555
XX90 XX00 XX01
90 00 01
XX90 XX01 22D6
Autoselect
Manufacturer ID
Autoselect
Word
XXAA
XX55
Device ID
(Top Boot Block)
3
3
Byte
AAA
555
AA
555
55
AAA
555
90
02
D6
Autoselect
Device ID
(Bottom Boot
Block)
Word
XXAA
2AA
XX55
XX90 XX01 2258
Byte
AAA
555
AA
555
55
AAA
555
90
02
58
XX00
XX01
00
(SA)
X02
Word
XXAA
2AA
XX55
XX90
Autoselect
Sector Protect
Verify (Note 3)
3
(SA)
X04
Byte
AAA
AA
555
55
AAA
90
01
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
555
AAA
555
AAA
555
AAA
XXAA
AA
2AA
555
2AA
555
2AA
555
XX55
55
555
AAA
555
AAA
555
AAA
XXA0
A0
Byte Program
Chip Erase
4
6
6
1
1
PA
PD
XXAA
AA
XX55
55
XX80
80
555
AAA
555
AAA
XXAA 2AA XX55 555 XX10
AA
XXAA 2AA XX55
AA 555 55
555
55
AAA
10
XX30
30
XXAA
AA
XX55
55
XX80
80
Sector Erase
SA
XXB0
B0
Erase Suspend
(Note 4)
XXX
XXX
XX30
30
Erase Resume
Legend:
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE or CE pulse.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE or CE pulse.
SA = Address of the sector to be erased. Address bits A18–A12 uniquely select any sector.
Notes:
1. All values are in hexadecimal.
2. See Tables 1 and 2 for description of bus operations.
3. The data is 00H for an unprotected sector group and 01H for a protected sector group. The complete bus address is
composed of the sector address (A18–A12), A1 = 1, and A0 = 0.
4. Read and program functions in non-erasing sectors are allowed in the Erase Suspend mode.
5. Address bits A18–A11 are don’t care for unlock and command cycles.
8/18/97
Am29F800T/Am29F800B
13
P R E L I M I N A R Y
the system is not required to provide further controls or
Read/Reset Command
timings. The device will automatically provide adequate
internally generated program pulses and verify the pro-
grammed cell margin.
The read or reset operation is initiated by writing the
read/reset command sequence into the command reg-
ister. Microprocessor read cycles retrieve array data
from the memory. The device remains enabled for
reads until the command register contents are altered.
The automatic programming operation is completed
when the data on DQ7 (also used as Data Polling) is
equivalent to the data written to this bit at which time
the device returns to the read mode and addresses are
no longer latched (see Table 8, Hardware Sequence
Flags). Therefore, the device requires that a valid ad-
dress to the device be supplied by the system at this
particular instance of time for Data Polling operations.
Data Polling must be performed at the memory location
which is being programmed.
The device will automatically power-up in the read/
reset state. In this case, a command sequence is not
required to read data. Standard microprocessor read
cycles will retrieve array data. This default value en-
sures that no spurious alteration of the memory content
occurs during the power transition. Refer to the AC
Read Characteristics and Waveforms for the specific
timing parameters.
Any commands written to the chip during the Embed-
ded Program Algorithm will be ignored. If a hardware
reset occurs during the programming operation, the
data at that particular location will be corrupted.
Autoselect Command
Flash memories are intended for use in applications
where the local CPU can alter memory contents. As
such, manufacture and device codes must be accessi-
ble while the device resides in the target system.
PROM programmers typically access the signature
codes by raising A9 to a high voltage. However, multi-
plexing high voltage onto the address lines is not gen-
erally a desirable system design practice.
Programming is allowed in any sequence and across
sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may
cause the device to exceed programming time limits
(DQ5 = 1) or result in an apparent success, according
to the data polling algorithm, but a read from reset/read
mode will show that the data is still “0”. Only erase op-
erations can convert “0”s to “1”s.
The device contains an autoselect command operation
to supplement traditional PROM programming method-
ology. The operation is initiated by writing the autose-
lect command sequence into the command register.
Following the command write, a read cycle from ad-
dress XX00H retrieves the manufacture code of 01H. A
read cycle from address XX01H returns the device
code (Am29F800T = D6H and Am29F800B = 58H for
x8 mode; Am29F800T = 22D6H and Am29F800B =
2258H for x16 mode) (see Tables 3 and 4).
Figure 1 illustrates the Embedded Programming Algo-
rithm using typical command strings and
bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two
“unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are
then followed by the chip erase command.
All manufacturer and device codes will exhibit odd par-
ity with DQ7 defined as the parity bit.
Chip erase does not require the user to program the
device prior to erase. Upon executing the Embedded
Erase Algorithm command sequence the device will
automatically program and verify the entire memory for
an all zero data pattern prior to electrical erase. The
erase is performed sequentially on all sectors at the
same time (see Table “Erase and Programming Perfor-
mance”). The system is not required to provide any
controls or timings during these operations.
Furthermore, the write protect status of sectors can be
read in this mode. Scanning the sector addresses
(A18, A17, A16, A15, A14, A13, and A12) while (A6,
A1, A0) = (0, 1, 0) will produce a logical “1” at device
output DQ0 for a protected sector.
To terminate the operation, it is necessary to write the
read/reset command sequence into the register.
Byte/Word Programming
The automatic erase begins on the rising edge of the
last WE pulse in the command sequence and termi-
nates when the data on DQ7 is “1” (see Write Opera-
tion Status section) at which time the device returns to
read the mode.
The device is programmed on a byte-by-byte (or
word-by-word) basis. Programming is a four bus cycle
operation. There are two “unlock” write cycles. These
are followed by the program set-up command and data
write cycles. Addresses are latched on the falling edge
of CE or WE, whichever happens later and the data is
latched on the rising edge of CE or WE, whichever hap-
pens first. The rising edge of CE or WE (whichever
happens first) begins programming using the Embed-
ded Program Algorithm. Upon executing the algorithm,
Figure 2 illustrates the Embedded Erase Algorithm
using typical command strings and bus operations.
14
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
reads or programs to a sector not being erased. This
Sector Erase
command is applicable ONLY during the Sector Erase
operation which includes the time-out period for sector
erase. The Erase Suspend command will be ignored if
written during the Chip Erase operation or Embedded
Program Algorithm. Writing the Erase Suspend com-
mand during the Sector Erase time-out results in imme-
diate termination of the time-out period and suspension
of the erase operation.
Sector erase is a six bus cycle operation. There are two
“unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are
then followed by the sector erase command. The sec-
tor address (any address location within the desired
sector) is latched on the falling edge of WE, while the
command (30H) is latched on the rising edge of WE.
After a time-out of 80 µs from the rising edge of the
last sector erase command, the sector erase operation
will begin.
Any other command written during the Erase Suspend
mode will be ignored except the Erase
Resume command. Writing the Erase Resume com-
mand resumes the erase operation. The addresses are
“don’t-cares” when writing the Erase Suspend or Erase
Resume command.
Multiple sectors may be erased sequentially by writing
the six bus cycle operations as described above. This
sequence is followed with writes of the Sector Erase
command to addresses in other sectors desired to be
sequentially erased. The time between writes must be
less than 80 µs otherwise that command will not be ac-
cepted and erasure will start. It is recommended that
processor interrupts be disabled during this time to
guarantee this condition. The interrupts can be re-en-
abled after the last Sector Erase command is written. A
time-out of 80 µs from the rising edge of the last WE will
initiate the execution of the Sector Erase command(s).
If another falling edge of the WE occurs within the 80
µs time-out window the timer is reset. (Monitor DQ3 to
determine if the sector erase timer window is still open.
See DQ3, Sector Erase Timer.) Any command other
than Sector Erase or Erase Suspend during this period
will reset the device to the read mode, ignoring the pre-
vious command string. In that case, restart the erase
on those sectors and allow them to complete.
When the Erase Suspend command is written during a
Sector Erase operation, the chip will take a maximum
of 20 µs to suspend the operation and go into erase
suspended mode, at which time the user can read or
program from a sector that is not being erased. Read-
ing data in this mode is the same as reading from the
standard read mode, except that the data must be read
from sectors that have not been erase suspended.
Successively reading from the erase-suspended sec-
tor while the device is in the erase-suspend-read mode
will cause DQ2 to toggle. After entering the erase-sus-
pend mode, the user can program the device by writing
the appropriate command sequence for Byte Program.
This program mode is known as the erase sus-
pend-program mode. Again, programming in this mode
is the same as programming in regular Byte Program
mode, except that the data must be programmed to
sectors that are not erase suspended. Successively
reading from the erase suspended sector while the de-
vice is in the erase suspend-program mode will cause
DQ2 to toggle. The end of the erase suspend-program
operation is detected by the RY/BY output pin, DATA
Polling of DQ7, or by the Toggle Bit (DQ6), which is the
same as the regular Byte Program operation. Note that
DQ7 must be read from the Byte Program address
while DQ6 can be read from any address.
Loading the sector erase buffer may be done in
any sequence and with any number of sectors (0 to18).
Refer to DQ3, Sector Erase Timer, in the Write Opera-
tion Status section.
Sector erase does not require the user to program the
device prior to erase. The device automatically pro-
grams all memory locations in the sector(s) to be
erased prior to electrical erase. When erasing a sector
or sectors the remaining unselected sectors are not af-
fected. The system is not required to provide any con-
trols or timings during these operations.
When the erase operation has been suspended, the de-
vice defaults to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the stan-
dard read mode except that the data must be read from
sectors that have not been erase-suspended.
The automatic sector erase begins after the 80 µs time
out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the
data on DQ7, Data Polling, is “1” (see Write Operation
Status section) at which time the device returns to the
read mode. Data Polling must be performed at an ad-
dress within any of the sectors being erased.
To resume the operation of Sector Erase, the Resume
command (30H) should be written. Any further writes of
the Resume command at this point will be ignored. An-
other Erase Suspend command can be written after the
chip has resumed erasing.
Figure 2 illustrates the Embedded Erase Algorithm
using typical command strings and bus operations.
Erase Suspend
The Erase Suspend command allows the user to inter-
rupt a Sector Erase operation and then perform data
8/18/97
Am29F800T/Am29F800B
15
P R E L I M I N A R Y
Write Operation Status
Table 8. Hardware Sequence Flags
Status
DQ7
DQ7
0
DQ6
DQ5
DQ3
DQ2
RDY/BSY
Byte Programming
Toggle
Toggle
No Tog
0
0
0
0
1
1
No Tog
(Note 1)
Toggle
0
0
1
Program/Erase in Auto-Erase
Erase sector address
1
Erase
In Progress
suspend
mode
Non-erase sector
address
Data
Data
Data
0
Data
1
Data
1
0
1
DQ7
(Note 2)
Program in erase suspend
Toggle
(Note 1)
Byte Programming
DQ7
0
Toggle
Toggle
Toggle
1
1
1
0
1
1
No Tog
(Note 3)
(Note 3)
0
0
0
Exceeded
Time
Program/Erase in Auto-Erase
Program in erase suspend
Limits
DQ7
Notes:
1. DQ2 can be toggled when sector address applied is that of an erasing sector. Conversely, DQ2 cannot be toggled when the
sector address applied is that of a non-erasing sector. DQ2 is therefore used to determine which sectors are erasing and
which are not.
2. These status flags apply when outputs are read from the address of a non-erase-suspended sector.
3. If DQ5 is high (exceeded timing limits), successive reads from a problem sector will cause DQ2 to toggle.
DQ7: Data Polling
the Embedded Algorithm operations and DQ7 has a
valid data, the data outputs on DQ0–DQ6 may be still
invalid. The valid data on DQ0–DQ7 will be read on the
successive read attempts.
The Am29F800 device features Data Polling as a
method to indicate to the host that the embedded algo-
rithms are in progress or completed. During the Em-
bedded Program Algorithm, an attempt to read the
device will produce the complement of the data last
written to DQ7. Upon completion of the Embedded Pro-
gram Algorithm, an attempt to read the device will pro-
duce the true data last written to DQ7. During the
Embedded Erase Algorithm, an attempt to read the de-
vice will produce a “0” at the DQ7 output.
Upon completion of the Embedded Erase Algorithm an
attempt to read the device will produce a “1” at the DQ7
output. The flowchart for Data Polling (DQ7) is shown
in Figure 3.
The Data Polling feature is only active during the Em-
bedded Programming Algorithm, Embedded Erase Al-
gorithm, or sector erase time-out (see Table 7).
See Figure 11 for the Data Polling timing specifications
and diagrams.
DQ6: Toggle Bit
The Am29F800 also features the “Toggle Bit” as a
method to indicate to the host system that the embed-
ded algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cy-
cle, successive attempts to read (OE toggling) data
from the device at any address will result in DQ6 tog-
gling between one and zero. Once the Embedded Pro-
gram or Erase Algorithm cycle is completed, DQ6 will
stop toggling and valid data will be read on the next
successive attempt. During programming, the Toggle
Bit is valid after the rising edge of the fourth WE pulse
in the four write pulse sequence. For chip erase, the
Toggle Bit is valid after the rising edge of the sixth WE
pulse in the six write pulse sequence. For Sector erase,
the Toggle Bit is valid after the last rising edge of the
sector erase WE pulse. The Toggle Bit is active during
the sector erase time-out.
For chip erase, the Data Polling is valid after the rising
edge of the sixth WE pulse in the six write pulse se-
quence. For sector erase, the Data Polling is valid after
the last rising edge of the sector erase WE pulse. Data
Polling must be performed at sector addresses within
any of the sectors being erased and not a protected
sector. Otherwise, the status may not be valid.
Just prior to the completion of Embedded Algorithm op-
erations DQ7 may change asynchronously while the
output enable (OE) is asserted low. This means that the
device is driving status information on DQ7 at
one instant of time and then that byte’s valid data at the
next instant of time. Depending on when the
system samples the DQ7 output, it may read the status
or valid data. Even if the device has completed
Either CE or OE toggling will cause DQ6 to toggle. In
addition, an Erase Suspend/Resume command will
16
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
cause DQ6 to toggle. See Figure 12 for the Toggle Bit
byte address of the non-erase suspend sector will indi-
cate a logic “1” at the DQ2 bit. Note that a sector which
is selected for erase is not available for read in Erase
Suspend mode. Other sectors which are not selected
for Erase can be read in Erase Suspend.
timing specifications and diagrams.
DQ5: Exceeded Timing Limits
DQ5 will indicate if the program or erase time has ex-
ceeded the specified limits (internal pulse count).
Under these conditions DQ5 will produce a “1”. This is
a failure condition which indicates that the program or
erase cycle was not successfully completed. Data Poll-
ing is the only operating function of the device under
this condition. The CE circuit will partially power down
the device under these conditions (to approximately 2
mA). The OE and WE pins will control the output dis-
able functions as described in Table 1.
DQ6 is different from DQ2 in that DQ6 toggles only
when the standard program or erase, or erase sus-
pend-program operation is in progress.
If the DQ5 failure condition is observed while in Sector
Erase mode (i.e., exceeded timing limits), the DQ2 tog-
gle bit can give extra information. In this case, the nor-
mal function of DQ2 is modified. If DQ5 is at logic “1”,
then DQ2 will toggle with consecutive reads only at the
sector address that caused the failure condition. DQ2
will toggle at the sector address where the failure oc-
curred and will not toggle at other sector addresses.
The DQ5 failure condition will also appear if a user tries
to program a 1 to a location that is previously pro-
grammed to 0. In this case the device locks out and
never completes the Embedded Program Algorithm.
Hence, the system never reads a valid data on DQ7 bit
and DQ6 never stops toggling. Once the device has ex-
ceeded timing limits, the DQ5 bit will indicate a “1”.
Please note that this is not a device failure condition
since the device was incorrectly used. If this occurs,
reset the device.
RY/BY: Ready/Busy
The Am29F800 provides a RY/BY open-drain output
pin as a way to indicate to the host system that the Em-
bedded Algorithms are either in progress or have been
completed. If the output is low, the device is busy with
either a program or erase operation. If the output is
high, the device is ready to accept any read/write or
erase operation. When the RY/BY pin is low, the device
will not accept any additional program or erase com-
mands with the exception of the Erase Suspend com-
mand. If the Am29F800 is placed in an Erase Suspend
mode, the RY/BY output will be high.
DQ3: Sector Erase Timer
After the completion of the initial sector erase com-
mand sequence the sector erase time-out will begin.
DQ3 will remain low until the time-out is complete. Data
Polling and Toggle Bit are valid after the initial sector
erase command sequence.
During programming, the RY/BY pin is driven low after
the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising
edge of the sixth WE pulse. The RY/BY pin should be
ignored while RESET is at VIL. Refer to Figure 13 for a
detailed timing diagram.
If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, DQ3 may be
used to determine if the sector erase timer window is
still open. If DQ3 is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent
commands (other than Erase Suspend) to the device
will be ignored until the erase operation is completed
as indicated by Data Polling or Toggle Bit. If DQ3 is low
(“0”), the device will accept additional sector erase
commands. To insure the command has been ac-
cepted, the system software should check the status of
DQ3 prior to and following each subsequent sector
erase command. If DQ3 were high on the second sta-
tus check, the command may not have been accepted.
Refer to Table 8, Hardware Sequence Flags.
Since this is an open-drain output, several RY/BY
pins can be tied together in parallel with a pull-up resis-
tor to VCC
.
RESET: Hardware Reset
The Am29F800 device may be reset by driving the
RESET pin to V . The RESET pin must be kept low
IL
(V ) for at least 500 ns. Any operation in progress will
IL
be terminated and the internal state machine will be
reset to the read mode 20 µs after the RESET pin is
driven low. Furthermore, once the RESET pin goes
high, the device requires an additional 50 ns before it
will allow read access. When the RESET pin is low, the
device will be in the standby mode for the duration of
the pulse and all the data output pins will be tri-stated.
If a hardware reset occurs during a program or erase
operation, the data at that particular location will
be indeterminate.
DQ2: Toggle Bit 2
This toggle bit, along with DQ6, can be used to deter-
mine whether the device is in the Embedded
Erase Algorithm or in Erase suspend.
Successive reads from the erasing sector will cause
DQ2 to toggle during the Embedded Erase Algorithm.
If the device is in the erase suspend-read mode, suc-
cessive reads from the erase-suspend sector will
cause DQ2 to toggle. When the device is in the erase
suspend-program mode, successive reads from the
The RESET pin may be tied to the system reset input.
Therefore, if a system reset occurs during
the Embedded Program or Erase Algorithm, the device
8/18/97
Am29F800T/Am29F800B
17
P R E L I M I N A R Y
will be automatically reset to read mode and this will
enable the system’s microprocessor to read the
boot-up firmware from the Flash memory.
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up
and power-down, the Am29F800 locks out write cycles
for VCC < VLKO (see DC Characteristics section for volt-
ages). When VCC < VLKO, the command register
is disabled, all internal program/erase circuits are dis-
abled, and the device resets to the read mode. The
Am29F800 ignores all writes until VCC > VLKO. The
user must ensure that the control pins are in the correct
logic state when VCC > VLKO to prevent unintentional
writes.
Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word
(16 bit) mode for the Am29F800 device. When this pin is
driven high, the device operates in the word (16 bit)
mode. The data is read and programmed at DQ0–
DQ15. When this pin is driven low, the device operates
in byte (8 bit) mode. Under this mode, the DQ15/A-1 pin
becomes the lowest address bit and DQ8–DQ14 bits are
tri-stated. However, the command bus cycle is always
an 8-bit operation and hence commands are written at
DQ0–DQ7 and the DQ8–DQ15 bits are ignored. Refer
to Figures 15 and 16 for the timing diagram.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or
WE will not initiate a write cycle.
Logical Inhibit
Data Protection
Writing is inhibited by holding any one of OE = VIL,
CE = VIH, or WE = VIH. To initiate a write cycle CE and
WE must be a logical zero while OE is a logical one.
The Am29F800 is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power tran-
sitions. During power up the device automatically re-
sets the internal state machine in the Read mode. Also,
with its control register architecture, alteration of the
memory contents only occurs after successful comple-
tion of specific multi-bus cycle command sequences.
Power-Up Write Inhibit
Power-up of the device with WE = CE = VIL and
OE = VIH will not accept commands on the rising edge
of WE. The internal state machine is automatically
reset to the read mode on power-up.
The device also incorporates several features to pre-
vent inadvertent write cycles resulting from VCC
power-up and power-down transitions or system noise.
18
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
EMBEDDED ALGORITHMS
Start
Write Program Command Sequence
(see below)
Data Poll Device
No
Increment Address
Last Address
?
Yes
Programming Completed
Program Command Sequence (Address/Command):
555H/AAH
2AAH/55H
555H/A0H
Program Address/Program Data
20375C-6
Figure 1. Embedded Programming Algorithm
8/18/97
Am29F800T/Am29F800B
19
P R E L I M I N A R Y
EMBEDDED ALGORITHMS
Start
Write Erase Command Sequence
(see below)
Data Polling or Toggle Bit
Successfully Completed
Erasure Completed
Individual Sector/Multiple Sector
Chip Erase Command Sequence
Erase Command Sequence
(Address/Command):
(Address/Command):
555H/AAH
2AAH/55H
555H/AAH
2AAH/55H
555H/80H
555H/AAH
2AAH/55H
555H/80H
555H/AAH
2AAH/55H
555H/10H
Sector Address/30H
Sector Address/30H
Additional sector
erase commands
are optional
Sector Address/30H
20375C-7
Note:
1. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each
subsequent sector erase command. If DQ3 were high on the second status check, the command may not have been ac-
cepted.
Figure 2. Embedded Erase Algorithm
20
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
Start
VA =Byte address for programming
Read Byte
(DQ0–DQ7)
Addr=VA
=any of the sector addresses within the
sector being erased during sector erase
operation
=Valid address equals any non-protected
sector group address during chip erase
Yes
DQ7=Data
?
No
No
DQ5=1
?
Yes
Read Byte
(DQ0–DQ7)
Addr=VA
Yes
DQ7=Data
?
Pass
No
Fail
20375C-8
Note:
1. DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Figure 3. Data Polling Algorithm
8/18/97
Am29F800T/Am29F800B
21
P R E L I M I N A R Y
Start
Read Byte
(DQ0–DQ7)
Addr=Don’t Care
No
DQ6=Toggle
?
Yes
No
DQ5=1
?
Yes
Read Byte
(DQ0–DQ7)
Addr=Don’t Care
No
DQ6=Toggle
?
Yes
Pass
Fail
20375C-9
Note:
1. DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as DQ5 changing to “1”.
Figure 4. Toggle Bit Algorithm
20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
20375C-10
20 ns
Figure 5. Maximum Negative Overshoot Waveform
20 ns
V
+ 2.0 V
CC
V
+ 0.5 V
2.0 V
CC
20375C-11
20 ns
20 ns
Figure 6. Maximum Positive Overshoot Waveform
22
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature
Commercial (C) Devices
Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C
Ambient Temperature (TA) . . . . . . . . . . .0°C to +70°C
Ambient Temperature
Industrial (I) Devices
with Power Applied . . . . . . . . . . . . . –55°C to +125°C
Ambient Temperature (TA) . . . . . . . . .–40°C to +85°C
Voltage with Respect to Ground
Extended (E) Devices
All pins except A9 (Note 1) . . . . . . . .–2.0 V to +7.0 V
Ambient Temperature (TA) . . . . . . . .–55°C to +125°C
VCC (Note 1). . . . . . . . . . . . . . . . . . . .–2.0 V to +7.0 V
A9 (Note 2). . . . . . . . . . . . . . . . . . . .–2.0 V to +13.0 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
VCC Supply Voltages
VCC for Am29F800T/B-70, 90,
120, 150 . . . . . . . . . . . . . . . . . . . . +4.50 V to +5.50 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, inputs may overshoot V to –2.0 V
SS
for periods of up to 20 ns. Maximum DC voltage on input
and I/O pins is V + 0.5 V. During voltage transitions,
CC
input and I/O pins may overshoot to V + 2.0 V for
CC
periods up to 20ns.
2. Minimum DC input voltage on A9 pin is –0.5 V. During
voltage transitions, A9 may overshoot V to –2.0 V for
SS
periods of up to 20 ns. Maximum DC input voltage on A9
is +12.5 V which may overshoot to 14.0 V for periods up
to 20 ns.
3. No more than one output shorted to ground at a time. Du-
ration of the short circuit should not be greater than one
second.
Stresses above those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these
or any other conditions above those indicated in the opera-
tional sections of this specification is not implied. Exposure of
the device to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
8/18/97
Am29F800T/Am29F800B
23
P R E L I M I N A R Y
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter
Symbol
Parameter Description
Test Conditions
= V to V , V = V Max
Min
Max
±1.0
35
Unit
µA
I
Input Load Current
V
V
V
LI
IN
SS
CC
CC
CC
I
A9 Input Load Current
Output Leakage Current
= V Max, A9 = 13.0 V
µA
LIT
CC
OUT
CC
I
= V to V , V = V Max
±1.0
40
µA
LO
SS
CC
CC
CC
Byte
I
V
Active Current (Note 1)
CE = V , OE = V
mA
CC1
CC
IL
IH
Word
50
I
I
V
V
Active Current (Notes 2, 3)
Standby Current
CE = V , OE = V
60
mA
mA
V
CC2
CC3
CC
IL
IH
V
= V Max, CE = V , OE = V
IL
1.0
0.8
CC
CC
CC
IH
V
Input Low Voltage
Input High Voltage
–0.5
2.0
IL
V
V
V
+ 0.5
CC
V
IH
Voltage for Autoselect and
Temporary Sector Unprotect
V
= 5.25 Volt
10.5
13.0
0.45
V
ID
CC
V
Output Low Voltage
Output High Voltage
I
I
= 5.8 mA, V = V Min
V
V
V
OL
OL
CC
CC
V
= –2.5 mA, V = V Min
2.4
3.2
OH
OH
CC
CC
V
Low V Lock-Out Voltage
4.2
LKO
CC
Notes:
1. The I current listed includes both the DC operating current and the frequency dependent component (at 6 MHz).
CC
The frequency component typically is less than 2 mA/MHz, with OE at V
.
IH
2. I active while Embedded Program or Erase Algorithm is in progress.
CC
3. Not 100% tested.
24
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
DC CHARACTERISTICS (Continued)
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Conditions
= V to V , V = V Max
Min
Typ
Max
±1.0
35
Unit
µA
I
Input Load Current
V
V
LI
IN
SS
CC CC
CC
I
A9 Input Load Current
= V Max, A9 = 13.0 V
µA
LIT
CC
CC
V
V
= V to V
,
OUT
SS
CC
I
Output Leakage Current
±1.0
µA
LO
= V Max
CC
CC
Byte
20
28
30
40
50
50
I
I
V
V
Active Current (Note 1)
CE = V , OE = V
IH
mA
mA
CC1
CC2
CC
IL
Word
Active Current (Notes 2, 3) CE = V , OE = V
CC
IL
IH
V
= V Max,
CC
CC
CE = V ± 0.3 V,
I
V
Standby Current (Note 4)
1
5
µA
CC
CC3
CC
OE = V RESET = V ± 0.3 V
IL,
CC
V
Input Low Voltage
Input High Voltage
–0.5
0.8
V
V
IL
V
V
0.7 x V
V
+ 0.3
CC
IH
CC
Voltage for Autoselect and
Temporary Sector Unprotect
V
= 5.25 Volt
10.5
13.0
0.45
V
ID
CC
V
Output Low Voltage
I
I
I
= 5.8 mA, V = V Min
V
V
V
V
OL
OL
OH
OH
CC
CC
V
V
V
= –2.5 mA, V = V Min
0.85 V
CC
OH1
OH2
LKO
CC
CC
Output Low Voltage
= –100 µA, V = V Min
V
–0.4
CC
CC
CC
Low V Lock-Out Voltage
3.2
4.2
CC
Notes:
1. The I current listed includes both the DC operating current and the frequency dependent component (at 6 MHz).
CC
The frequency component typically is less than 2 mA/MHz, with OE at V
.
IH
2. I active while Embedded Program or Erase Algorithm is in progress.
CC
3. Not 100% tested.
4. I
= 20 µA max at extended temperatures (>+85°C)
CC3
8/18/97
Am29F800T/Am29F800B
25
P R E L I M I N A R Y
AC CHARACTERISTICS
Read-only Operations Characteristics
Parameter
Symbols
Speed Options (Notes 1
and 2)
JEDEC Standard
Description
Test Setup
Min
-70
-90
-120 -150 Unit
t
t
Read Cycle Time (Note 4)
70
90
120
150
ns
AVAV
RC
CE = V
IL
IL
IL
t
t
t
Address to Output Delay
Max
70
90
120
150
ns
AVQV
ACC
OE = V
OE = V
t
t
Chip Enable to Output Delay
Max
Max
Max
Max
70
30
20
20
90
35
20
20
120
50
150
55
ns
ns
ns
ns
ELQV
GLQV
EHQZ
GHQZ
CE
t
t
Output Enable to Output Delay
OE
t
Chip Enable to Output High Z (Notes 3, 4)
Output Enable to Output High Z (Notes 3, 4)
30
35
DF
DF
t
t
30
35
Output Hold Time From Addresses, CE,
or OE, Whichever Occurs First
t
t
Min
0
0
0
0
ns
AXQX
OH
t
RESET Pin Low to Read Mode (Note 4)
Max
20
20
20
20
µs
Ready
t
ELFL
ELFH
CE to BYTE Switching Low or High
Max
Max
5
5
5
5
ns
ns
t
BYTE Switching Low to Output High Z
(Note 3)
t
20
30
30
30
FLQZ
Notes:
2. Test Conditions (for all others):
3. Output driver disable time.
4. Not 100% tested.
1. Test Conditions (for -70 only):
Output Load: 1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Output Load: 1 TTL gate and 100 pF
Input rise and fall times: 20 ns
Input pulse levels: 0.45 V to 2.4 V
Timing measurement reference
level, input and output voltages:
0.8 V and 2.0 V
Input pulse levels: 0.0 V to 3.0 V
Timing measurement reference level
input and output voltage: 1.5 V
5.0 V
IN3064
or Equivalent
2.7 kΩ
Device
Under
Test
C
6.2 kΩ
L
Diodes = IN3064
or Equivalent
Notes:
For -70: C = 30 pF including jig capacitance
L
For all others: C = 100 pF including jig capacitance
20375C-12
L
Figure 7. Test Conditions
26
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
AC CHARACTERISTICS
Write/Erase/Program Operations
Parameter
Symbols
JEDEC Standard Description
-70
70
0
-90
90
0
-120
120
0
-150
150
0
Unit
ns
t
t
Write Cycle Time (Note 2)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
Min
AVAV
WC
t
t
ns
AVWL
WLAX
AS
AH
DS
DH
t
t
45
30
0
45
45
0
50
50
0
50
50
0
ns
t
t
t
ns
DVWH
WHDX
t
Data Hold Time
ns
Output
Enable
Read (Note 2)
Toggle and Data Polling (Note 2)
0
0
0
0
ns
t
OEH
Min
Min
10
0
10
0
10
0
10
0
ns
ns
Hold Time
Read Recover Time Before Write
(OE High to WE Low)
t
t
GHWL
GHWL
t
t
t
CE Setup Time
Min
Min
Min
Min
Typ
Typ
Max
Min
Min
Min
Min
0
0
0
0
0
0
0
0
ns
ns
ELWL
WHEH
WLWH
WHWL
CS
CH
WP
t
t
CE Hold Time
t
Write Pulse Width
35
20
7
45
20
7
50
20
7
50
20
7
ns
t
t
Write Pulse Width High
Byte Programming Operation
ns
WPH
t
t
t
t
µs
sec
sec
µs
ns
WHWH1
WHWH2
WHWH1
1
1
1
1
Sector Erase Operation (Note 1)
WHWH2
8
8
8
8
t
V
Set Up Time (Note 2)
CC
50
500
500
30
50
500
500
35
50
500
500
50
50
500
500
55
VCS
t
Rise Time to V
ID
VIDR
t
RESET Pulse Width
ns
RP
t
Program/Erase Valid to RY/BY Delay (Note 2)
ns
BUSY
RESET Setup Time for Temporary Sector Unprotect
(Notes 2, 3)
t
Min
4
4
4
4
µs
RSP
Notes:
1. This does not include the preprogramming time.
2. Not 100% tested.
3. These timings are for Temporary Sector Unprotect operation.
4. Output Driver Disable Time.
8/18/97
Am29F800T/Am29F800B
27
P R E L I M I N A R Y
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
Will Be
Steady
May
Change
from H to L
Will Be
Changing
from H to L
May
Will Be
Change
from L to H
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is High-
Impedance
“Off” State
KS000010
SWITCHING WAVEFORMS
t
RC
Addresses
Addresses Stable
t
ACC
CE
OE
(t
)
DF
t
OE
t
OEH
WE
(t
)
CE
(t
)
OH
High Z
High Z
Output Valid
Outputs
20375C-13
Figure 8. AC Waveforms for Read Operations
28
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
SWITCHING WAVEFORMS
3rd Bus Cycle
Data Polling
PA
PA
555H
Addresses
t
t
RC
t
WC
AH
t
AS
CE
OE
t
GHWL
t
t
WHWH1
WP
WE
t
WPH
t
CS
t
DF
t
t
DH
OE
D
Data
A0H
PD
DQ7
OUT
t
DS
t
OH
5.0 V
t
CE
20375C-14
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. D is the output of the data written to the device.
OUT
5. Figure indicates last two bus cycles of four bus cycle sequence.
6. These waveforms are for the x16 mode.
Figure 9. Program Operation Timings
555 for chip erase
SA
t
AH
Addresses
2AAH
2AAH
555H
555H
555H
t
AS
CE
OE
t
GHWL
t
WP
WE
t
WPH
t
CS
t
DH
Data
t
55H
80H
55H
10H/30H
AAH
AAH
DS
V
t
CC
VCS
20375C-15
Notes:
1. SA is the sector address for Sector Erase.
2. These waveforms are for the x16 mode.
Figure 10. AC Waveforms Chip/Sector Erase Operations
Am29F800T/Am29F800B
8/18/97
29
P R E L I M I N A R Y
SWITCHING WAVEFORMS
t
CH
CE
t
DF
t
OE
OE
t
OEH
WE
t
CE
t
OH
*
High Z
DQ7=
DQ7
DQ7
Valid Data
t
WHWH 1 or 2
DQ0–DQ6
Valid Data
DQ0–DQ6=Invalid
DQ0–DQ6
20375C-16
Note:
*DQ7=Valid Data (The device has completed the Embedded operation).
Figure 11. AC Waveforms for Data Polling During Embedded Algorithm Operations
CE
t
OEH
WE
OE
*
DQ6=
Stop Toggling
DQ0–DQ7
Valid
Data
(DQ0–DQ7)
DQ6=Toggle
DQ6=Toggle
t
OE
20375C-17
Note:
*DQ6 stops toggling (The device has completed the Embedded operation).
Figure 12. AC Waveforms for Toggle Bit During Embedded Algorithm Operations
30
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
SWITCHING WAVEFORMS
CE
The rising edge of the last WE signal
WE
Entire programming
or erase operations
RY/BY
t
BUSY
20375C-18
Figure 13. RY/BY Timing Diagram During Program/Erase Operations
RESET
t
RP
t
Ready
20375C-19
Figure 14. RESET Timing Diagram
8/18/97
Am29F800T/Am29F800B
31
P R E L I M I N A R Y
SWITCHING WAVEFORMS
CE
OE
BYTE
t
t
ELFL
ELFH
Data Output
(DQ0–DQ7)
Data Output
(DQ0–DQ14)
DQ0–DQ14
DQ15/A–1
DQ15
Output
Address
Input
t
FLQZ
20375C-20
Figure 15. BYTE Timing Diagram for Read Operation
CE
The falling edge of the last WE signal
WE
BYTE
t
SET
(t
)
AS
t
(t
)
AH
HOLD
20375C-21
Figure 16. BYTE Timing Diagram for Write Operations
32
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
Start
RESET = V
(Note 1)
ID
Perform Erase or
Program Operations
RESET = V
IH
Temporary Sector Group
Unprotect Completed
(Note 2)
20375C-22
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.
Figure 17. Temporary Sector Unprotect Algorithm
t
VIDR
12 V
RESET
0 V or 5 V
CE
0 V or 5 V
WE
t
RSP
Program or Erase Command Sequence
20375C-23
Figure 18. Temporary Sector Unprotect Timing Diagram
8/18/97
Am29F800T/Am29F800B
33
P R E L I M I N A R Y
AC CHARACTERISTICS
Write/Erase/Program Operations
Alternate CE Controlled Writes
Parameter
Symbols
JEDEC Standard Description
-70
70
0
-90
90
0
-120
120
0
-150
150
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
sec
sec
ns
t
t
Write Cycle Time (Note 2)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
Typ
Max
Max
AVAV
AVEL
ELAX
WC
t
t
AS
AH
DS
DH
t
t
45
30
0
45
45
0
50
50
0
50
50
0
t
t
t
t
DVEH
EHDX
Data Hold Time
t
Output Enable Setup Time
0
0
0
0
OES
OEH
Read (Note 2)
0
0
0
0
Output Enable
Hold Time
t
Toggle and Data Polling (Note 2)
10
0
10
0
10
0
10
0
t
t
t
Read Recover Time Before Write
WE Setup Time
GHEL
WLEL
GHEL
t
0
0
0
0
WS
t
t
WE Hold Time
0
0
0
0
EHWH
WH
t
t
CE Pulse Width
35
20
7
45
20
7
50
20
7
50
20
7
ELEH
EHEL
CP
t
t
CE Pulse Width High
Byte Programming Operation
Word Programming Operation
CPH
t
t
t
t
WHWH1
WHWH2
WHWH1
14
1
14
1
14
1
14
1
Sector Erase Operation (Note 1)
WHWH2
8
8
8
8
t
BYTE Switching Low to Output High Z (Note 2)
20
30
30
30
FLQZ
Notes:
1. This does not include the preprogramming time.
2. Not 100% tested.
34
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
SWITCHING WAVEFORM
Data Polling
PA
Addresses
PA
555H
t
t
AH
WC
t
AS
WE
OE
t
GHEL
t
t
WHWH1
CP
CE
t
CPH
t
WS
t
DH
Data
D
A0H
P
DQ7
OUT
t
DS
5.0 Volt
20375C-24
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. D is the output of the data written to the device.
OUT
5. Figure indicates last two bus cycles of four bus cycle sequence.
6. These waveforms are for the x16 mode.
Figure 19. Alternate CE Controlled Program Operation Timings
8/18/97
Am29F800T/Am29F800B
35
P R E L I M I N A R Y
ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter
Sector Erase Time
Typ (Note 1)
Max (Note 2)
Unit
sec
sec
µs
Comments
1.0
8
Excludes 00H programming prior to
erasure
Chip Erase Time (Note 3)
19
152
300
600
21.6
Byte Programming Time (Note 5)
Word Programming Time (Note 5)
Chip Programming Time (Notes 3, 5)
Erase/Program Endurance
7
14
Excludes system-level overhead (Note 4)
µs
7.2
sec
1,000,000
cycles Minimum 100,000 cycles guaranteed
Notes:
1. The typical erase and programming times assume the following conditions: 25°C, 5.0 volt V , 100,000 cycles. These
CC
conditions do not apply to erase/program endurance. Programming typicals assume checkerboard pattern.
2. The maximum erase and programming times assume the following conditions: 90°C, 4.5 volt V , 100,000 cycles.
CC
3. Although Embedded Algorithms allow for longer chip program and erase time, the actual time will be considerably less since
bytes program or erase significantly faster than the worst case byte.
4. System-level overhead is defined as the time required to execute the four bus cycle command necessary to program each
byte. In the preprogramming step of the Embedded Erase algorithm, all bytes are programmed to 00H before erasure.
5. The Embedded Algorithms allow for 2.5 ms byte program time. DQ5 = “1” only after a byte takes the theoretical maximum
time to program. A minimal number of bytes may require significantly more programming pulses than the typical byte. The
majority of the bytes will program within one or two pulses. This is demonstrated by the Typical and Maximum Programming
Times listed above.
LATCHUP CHARACTERISTICS
Min
Max
+ 1.0 V
Input Voltage with respect to V on all I/O pins
–1.0 V
V
CC
SS
V
Current
–100 mA
+100 mA
CC
Includes all pins except V . Test conditions: V = 5.0 V, one pin at a time.
CC
CC
36
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
TSOP PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Test Setup
Typ
6
Max
7.5
12
Unit
pF
C
Input Capacitance
V
V
V
= 0
IN
IN
OUT
C
Output Capacitance
Control Pin Capacitance
= 0
= 0
8.5
8
pF
OUT
C
10
pF
IN2
IN
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
SO PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Input Capacitance
Test Setup
= 0
Typ
Max
Unit
pF
C
V
6
8.5
8
7.5
12
10
IN
IN
C
Output Capacitance
Control Pin Capacitance
V
= 0
= 0
pF
OUT
OUT
C
V
pF
IN2
PP
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
DATA RETENTION
Parameter
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
125°C
20
8/18/97
Am29F800T/Am29F800B
37
P R E L I M I N A R Y
PHYSICAL DIMENSIONS
TS 048
48-Pin Standard Thin Small Outline Package (measured in millimeters)
0.95
1.05
Pin 1 I.D.
1
48
11.90
12.10
0.50 BSC
24
25
0.05
0.15
18.30
18.50
19.80
20.20
16-038-TS48-2
TS 048
DA101
0.08
0.20
0.10
0.21
1.20
MAX
8-8-94 ae
0°
5°
0.25MM (0.0098") BSC
0.50
0.70
38
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
PHYSICAL DIMENSIONS (continued)
TSR048
48-Pin Reversed Thin Small Outline Package (measured in millimeters)
0.95
1.05
Pin 1 I.D.
1
48
11.90
12.10
0.50 BSC
24
25
0.05
0.15
18.30
18.50
19.80
20.20
SEATING PLANE
16-038-TS48
TSR048
DA104
0.08
0.20
8-8-94 ae
1.20
MAX
0.10
0.21
0°
5°
0.25MM (0.0098") BSC
0.50
0.70
8/18/97
Am29F800T/Am29F800B
39
P R E L I M I N A R Y
PHYISICAL DIMENSIONS (continued)
SO 044
44-Pin Small Outline Package (measured in millimeters)
44
23
13.10
13.50
15.70
16.30
1
22
1.27 NOM.
TOP VIEW
28.00
28.40
0.10
0.21
2.17
2.45
2.80
MAX.
0°
8°
SEATING
PLANE
0.60
1.00
0.35
0.50
0.10
0.35
END VIEW
SIDE VIEW
16-038-SO44-2
SO 044
DA82
11-9-95 lv
40
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
REVISION SUMMARY FOR Am29F800
Distinctive Characteristics:
High Performance: The fastest speed option available
is now 70 ns.
Enhanced power management for standby mode:
Changed typical standby current to 1µA.
In fact, software programs written using the previous
four-digit definitions do not require any changes; they
remain completely compatible with the new three-digit
definitions.
The addresses for the byte-mode read cycles (fourth
cycle) in the autoselect mode are corrected from 01h to
02h for device ID, and from SAX02h to SAX04h for
sector protect verification.
General Description:
Added 70 ns speed option.
Product Selector Guide:
Added -70 column.
Note 5 is clarified.
Pin Configuration:
Operating Ranges:
Added -70 speed option.
VCC Supply Voltages: Added -70 speed option to the
list.
Ordering Information, Standard Products:
The -70 speed option is now listed in the example.
DC Characteristics:
CMOS Compatible: Added column for typical ICC spec-
ifications. Revised max ICC specifications.
Valid Combinations: Added combinations for the -70
speed option.
AC Characteristics:
Read Only Operations Characteristics: Added the -70
column and test conditions.
Table 7, Command Definitions:
Corrected byte addresses for unlock and command cy-
cles from “2AA” to “AAA”.
Test Conditions, Figure 7:
Changed speed option in first CL statement to -70.
In the previous data sheet revision, the addresses for
command definitions were shortened from four hexa-
decimal digits to three. The more accurately represents
the actual address bits required, A10–A0. The remain-
ing upper address bits are don’t cares.
AC Characteristics:
Write/Erase/Program Operations, Alternate CE Con-
trolled Writes: Added the -70 column; revised word/
byte programming and sector erase specifications.
The new address is compatible with the previous four-
digit definition of “AAAA”; the only difference is that the
highest-order hexadecimal digit “A” is now “don’t care”.
Erase and Programming Performance:
Revised specifications.
Trademarks
Copyright © 1997 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof, and ExpressFlash are trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
8/18/97
Am29F800T/Am29F800B
41
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