AM29F400BT-45_技术文档

Am29F400B

Data Sheet

Am29F400B Cover Sheet

The following document contains information on Spansion memory products.

Continuity of Specifications

There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been

made are the result of normal data sheet improvement and are noted in the document revision summary.

For More Information

Please contact your local sales office for additional information about Spansion memory solutions.

Publication Number 21505

Revision E

Amendment 8

Issue Date November 11, 2009

D a t a S h e e t

This page left intentionally blank.

2

Am29F400B

21505_E8 November 11, 2009

DATA SHEET

Am29F400B

4 Megabit (512 K x 8-Bit/256 K x 16-Bit)

CMOS 5.0 Volt-only Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Single power supply operation

■ Embedded Algorithms

— 5.0 volt-only operation for read, erase, and

program operations

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any

combination of designated sectors

— Minimizes system level requirements

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

■ Manufactured on 0.32 µm process technology

— Compatible with 0.5 µm Am29F400 device

■ Minimum 1,000,000 program/erase cycles per

■ High performance

sector guaranteed

— Access times as fast as 45 ns

■ 20-year data retention at 125°C

— Reliable operation for the life of the system

■ Package option

■ Low power consumption (typical values at

5 MHz)

— 1 µA standby mode current

— 48-pin TSOP

— 20 mA read current (byte mode)

— 28 mA read current (word mode)

— 30 mA program/erase current

— 44-pin SO

— Known Good Die (KGD)

(see publication number 21258)

■ Flexible sector architecture

■ Compatibility with JEDEC standards

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

seven 64 Kbyte sectors (byte mode)

— Pinout and software compatible with single-

power-supply Flash

— One 8 Kword, two 4 Kword, one 16 Kword, and

seven 32 Kword sectors (word mode)

— Superior inadvertent write protection

■ Data# Polling and toggle bits

— Supports full chip erase

— Provides a software method of detecting

program or erase operation completion

— Sector Protection features:

A hardware method of locking a sector to

prevent any program or erase operations within

that sector

■ Ready/Busy# pin (RY/BY#)

— Provides a hardware method of detecting

program or erase cycle completion

Sectors can be locked via programming

equipment

■ Erase Suspend/Erase Resume

Temporary Sector Unprotect feature allows code

changes in previously locked sectors

— Suspends an erase operation to read data from,

or program data to, a sector that is not being

erased, then resumes the erase operation

■ Top or bottom boot block configurations available

■ Hardware reset pin (RESET#)

— Hardware method to reset the device to reading

array data

Publication# 21505 Rev: E Amendment: 8

Issue Date: November 11, 2009

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data

Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

D A T A S H E E T

GENERAL DESCRIPTION

The Am29F400B is a 4 Mbit, 5.0 volt-only Flash

memory organized as 524,288 bytes or 262,144 words.

The device is offered in 44-pin SO and 48-pin TSOP

packages. The device is also available in Known Good

Die (KGD) form. For more information, refer to publica-

tion number 21258. The word-wide data (x16) appears

on DQ15–DQ0; the byte-wide (x8) data appears on

DQ7–DQ0. This device is designed to be programmed in-

Device erasure occurs by executing the erase

command sequence. This initiates the Embedded

Erase algorithm—an internal algorithm that automatically

preprograms the array (if it is not already programmed)

before executing the erase operation. During erase, the

device automatically times the erase pulse widths and

verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6/

DQ2 (toggle) status bits. After a program or erase

cycle has been completed, the device is ready to read

array data or accept another command.

system with the standard system 5.0 volt V supply. A 12.0

CC

V V is not required for write or erase operations. The

PP

device can also be programmed in standard EPROM

programmers.

This device is manufactured using AMD’s 0.32 µm

process technology, and offers all the features and ben-

efits of the Am29F400, which was manufactured using

0.5 µm process technology.

The sector erase architecture allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

The standard device offers access times of 45, 50, 55,

70 and 90 ns, allowing high speed microprocessors to

operate without wait states. To eliminate bus contention

the device has separate chip enable (CE#), write

enable (WE#) and output enable (OE#) controls.

Hardware data protection measures include a low

V

detector that automatically inhibits write opera-

CC

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of memory.

This can be achieved via programming equipment.

The device requires only a single 5.0 volt power

supply for both read and write functions. Internally

generated and regulated voltages are provided for the

program and erase operations.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as input to an internal state-machine that

controls the erase and programming circuitry. Write

cycles also internally latch addresses and data needed

for the programming and erase operations. Reading

data out of the device is similar to reading from other

Flash or EPROM devices.

The hardware RESET# pin terminates any operation

in progress and resets the internal state machine to

reading array data. The RESET# pin may be tied to the

system reset circuitry. A system reset would thus also

reset the device, enabling the system microprocessor

to read the boot-up firmware from the Flash memory.

The system can place the device into the standby

mode. Power consumption is greatly reduced in this mode.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The device electrically erases all bits within a sector

simultaneously via Fowler-Nordheim tunneling. The data is

programmed using hot electron injection.

2

Am29F400B

21505E8 November 11, 2009

D A T A S H E E T

TABLE OF CONTENTS

Product Selector Guide. . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5

Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 6

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 7

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 8

Table 1. Am29F400B Device Bus Operations .................................. 8

Word/Byte Configuration .......................................................... 8

Requirements for Reading Array Data ..................................... 8

Writing Commands/Command Sequences .............................. 8

Program and Erase Operation Status ...................................... 9

Standby Mode .......................................................................... 9

RESET#: Hardware Reset Pin ................................................. 9

Output Disable Mode ................................................................ 9

Table 2. Am29F400BT Top Boot Block Sector Address Table....... 10

Table 3. Am29F400BB Bottom Boot Block Sector Address Table.. 10

Autoselect Mode ..................................................................... 10

Table 4. Am29F400B Autoselect Codes (High Voltage Method).... 11

Sector Protection/Unprotection ............................................... 11

Temporary Sector Unprotect .................................................. 11

Figure 1. Temporary Sector Unprotect Operation........................... 11

Hardware Data Protection ...................................................... 12

Low V_CCWrite Inhibit...................................................................... 12

Write Pulse “Glitch” Protection........................................................ 12

Logical Inhibit .................................................................................. 12

Power-Up Write Inhibit .................................................................... 12

Command Definitions . . . . . . . . . . . . . . . . . . . . . 13

Reading Array Data ................................................................ 13

Reset Command ..................................................................... 13

Autoselect Command Sequence ............................................ 13

Word/Byte Program Command Sequence ............................. 13

Figure 2. Program Operation .......................................................... 14

Chip Erase Command Sequence ........................................... 14

Sector Erase Command Sequence ........................................ 14

Erase Suspend/Erase Resume Commands ........................... 16

Figure 3. Erase Operation............................................................... 16

Table 5. Am29F400B Command Definitions................................... 17

Write Operation Status . . . . . . . . . . . . . . . . . . . . 18

DQ7: Data# Polling ................................................................. 18

Figure 4. Data# Polling Algorithm ................................................... 18

RY/BY#: Ready/Busy# ........................................................... 19

DQ6: Toggle Bit I .................................................................... 19

DQ2: Toggle Bit II ................................................................... 19

Reading Toggle Bits DQ6/DQ2 .............................................. 19

DQ5: Exceeded Timing Limits ................................................ 20

DQ3: Sector Erase Timer ....................................................... 20

Figure 5. Toggle Bit Algorithm......................................................... 20

Table 6. Write Operation Status...................................................... 21

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 22

Figure 6. Maximum Negative Overshoot Waveform ....................... 22

Figure 7. Maximum Positive Overshoot Waveform......................... 22

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 22

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23

TTL/NMOS Compatible .......................................................... 23

CMOS Compatible .................................................................. 24

Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 8. Test Setup....................................................................... 25

Table 7. Test Specifications........................................................... 25

Key to Switching Waveforms. . . . . . . . . . . . . . . . 25

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26

Read Operations .................................................................... 26

Figure 9. Read Operations Timings ............................................... 26

Hardware Reset (RESET#) .................................................... 27

Figure 10. RESET# Timings .......................................................... 27

Word/Byte Configuration (BYTE#) ...................................... 28

Figure 11. BYTE# Timings for Read Operations............................ 28

Figure 12. BYTE# Timings for Write Operations............................ 28

Erase/Program Operations ..................................................... 29

Figure 13. Program Operation Timings.......................................... 30

Figure 14. Chip/Sector Erase Operation Timings .......................... 31

Figure 15. Data# Polling Timings (During Embedded Algorithms). 32

Figure 16. Toggle Bit Timings (During Embedded Algorithms)...... 32

Figure 17. DQ2 vs. DQ6................................................................. 33

Temporary Sector Unprotect .................................................. 33

Figure 18. Temporary Sector Unprotect Timing Diagram .............. 33

Alternate CE# Controlled Erase/Program Operations ............ 34

Figure 19. Alternate CE# Controlled Write Operation Timings ...... 35

Erase and Programming Performance . . . . . . . . 36

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 36

TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 36

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 37

TS 048—48-Pin Standard Thin Small Outline Package ......... 37

SO 044—44-Pin Small Outline Package ................................ 38

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 39

Revision A (August 1997) ....................................................... 39

Revision B (October 1997) ..................................................... 39

Revision C (January 1998) ..................................................... 39

Revision C+1 (February 1998) ............................................... 39

Revision C+2 (April 1998) ....................................................... 39

Revision C+3 (June 1998) ...................................................... 39

Revision C+4 (August 1998) ................................................... 40

Revision D (January 1999) ..................................................... 40

Revision D+1 (July 2, 1999) ................................................... 40

Revision E (November 15, 1999) ............................................ 40

Revision E+1 (November 30, 2000) ....................................... 40

Revision E+2 (June 4, 2004) .................................................. 40

Revision E+3 (December 22, 2005) ....................................... 40

Revision E4 (May 18, 2006) ................................................... 40

Revision E5 (November 1, 2006) ............................................ 40

Revision E6 (March 3, 2009) .................................................. 40

Revision E7 (August 3, 2009) ................................................. 40

Revision E8 (November 11, 2009) .......................................... 40

November 11, 2009 21505E8

Am29F400B

3

D A T A S H E E T

PRODUCT SELECTOR GUIDE

Family Part Number

Am29F400B

V_CC= 5.0 V 5ꢀ

Speed Option

-45

-50

-55

55

V_CC= 5.0 V 10ꢀ

-70

70

30

-90

90

35

Max access time, ns (t_ACC

Max CE# access time, ns (t_CE

Max OE# access time, ns (t_OE

)

45

30

50

30

)

55

)

30

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

DQ0–DQ15 (A-1)

RY/BY#

V_CC

Sector Switches

V_SS

Erase Voltage

Generator

Input/Output

Buffers

RESET#

State

Control

WE#

BYTE#

Command

Register

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

Y-Gating

STB

V_CCDetector

Timer

Cell Matrix

X-Decoder

A0–A17

4

Am29F400B

21505E8 November 11, 2009

D A T A S H E E T

CONNECTION DIAGRAMS

This device is also available in Known Good Die (KGD) form. Refer to publication number 21258 for

more information.

A15

A14

A13

A12

A11

A10

A9

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE#

V_SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V_CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

V_SS

CE#

A0

A8

NC

WE#

RESET#

NC

RY/BY#

NC

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48-Pin TSOP—Standard Pinout

A17

A7

A6

A5

A4

A3

A2

A1

NC

RY/BY#

A17

A7

1

2

3

4

5

6

7

8

9

44 RESET#

43 WE#

42 A8

41 A9

A6

40 A10

A5

39 A11

A4

38 A12

A3

37 A13

A2

36 A14

A1 10

A0 11

35 A15

SO

34 A16

CE# 12

V_SS13

33 BYTE#

32 V_SS

OE# 14

DQ0 15

DQ8 16

DQ1 17

DQ9 18

DQ2 19

DQ10 20

DQ3 21

DQ11 22

31 DQ15/A-1

30 DQ7

29 DQ14

28 DQ6

27 DQ13

26 DQ5

25 DQ12

24 DQ4

23 V_CC

November 11, 2009 21505E8

Am29F400B

5

D A T A S H E E T

PIN CONFIGURATION

LOGIC SYMBOL

A0–A17

= 18 addresses

DQ0–DQ14 = 15 data inputs/outputs

18

DQ15/A-1

=

DQ15 (data input/output, word mode),

A-1 (LSB address input, byte mode)

A0–A17

16 or 8

DQ0–DQ15

(A-1)

BYTE#

CE#

=

Selects 8-bit or 16-bit mode

Chip enable

CE#

OE#

Output enable

WE#

Write enable

WE#

RESET#

RY/BY#

Hardware reset pin, active low

Ready/Busy# output

RESET#

BYTE#

RY/BY#

V

+5.0 V single power supply

(see Product Selector Guide for

device speed ratings and voltage

supply tolerances)

CC

V

=

Device ground

SS

NC

Pin not connected internally

6

Am29F400B

21505E8 November 11, 2009

D A T A S H E E T

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-

nation) is formed by a combination of the elements below.

Am29F400B

T

-45

E

F

OPTIONAL PROCESSING

Blank = Standard Processing

0

=

V

= 5.0 V 10ꢀ, 55 ns device only

CC

(Contact an AMD representative for more information)

TEMPERATURE RANGE

I

=

Industrial (–40°C to +85°C)

F

E

K

Industrial (–40°C to +85°C) with Pb-Free Package

Extended (–55°C to +125° C)

Extended (–55°C to +125° C) with Pb-free Package

PACKAGE TYPE

E

=

48-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 048)

S

=

44-Pin Small Outline Package (SO 044)

This device is also available in Known Good Die (KGD) form. See publication number

21258 for more information.

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T

B

=

Top sector

Bottom sector

DEVICE NUMBER/DESCRIPTION

Am29F400B

4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS Flash Memory

5.0 Volt-only Read, Program and Erase

Voltage

Valid Combinations

Range

AM29F400BT-45,

AM29F400BB-45,

EI, EF,

SI, SF

AM29F400BT-50,

AM29F400BB-50

5.0 V 5ꢀ

EI, EF, EE, EK

SI, SF, SE, SK

AM29F400BT-55,

AM29F400BB-55

EI0,

AM29F400BT-55,

AM29F400BB-55

EF0, EE0, EK0,

SI0,

SF0, SE0, SK0

5.0 V 10ꢀ

AM29F400BT-70,

AM29F400BB-70

EI,

EF, EE, EK

SI,

SF, SE, SK

AM29F400BT-90,

AM29F400BB-90

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

November 11, 2009 21505E8

Am29F400B

7

D A T A S H E E T

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is composed of latches that store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state

machine. The state machine outputs dictate the func-

tion of the device. Table 1 lists the device bus

operations, the inputs and control levels they require,

and the resulting output. The following subsections

describe each of these operations in further detail.

Table 1. Am29F400B Device Bus Operations

DQ8–DQ15

BYTE#

= V_IL

Operation

CE#

L

OE# WE# RESET# A0–A17 DQ0–DQ7

= V_IH

D_OUT

D_IN

Read

Write

L

H

L

H

A_IN

D_OUT

D_IN

High-Z

L

H

V_CC

0.5 V

V_CC

0.5 V

CMOS Standby

X

High-Z

TTL Standby

H

L

X

H

X

H

X

H

X

High-Z

D_IN

High-Z

D_IN

High-Z

X

Output Disable

Hardware Reset

X

L

X

Temporary Sector Unprotect (See Note)

V_ID

A_IN

Legend:

L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 12.0 ± ± 0.5 V, X = Don’t Care, D_IN= Data In, D_OUT= Data Out, A_IN= Address In

Note:See the sections onSector Group Protection and Temporary Sector Unprotect for more information.

valid addresses on the device address inputs produce

valid data on the device data outputs. The device

remains enabled for read access until the command

register contents are altered.

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins DQ15–DQ0 operate in the byte or word configura-

tion. If the BYTE# pin is set at logic ‘1’, the device is in

word configuration, DQ15–DQ0 are active and con-

trolled by CE# and OE#.

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specifica-

tions and to Figure 9 for the timing diagram. I

DC Characteristics table represents the active current

specification for reading array data.

in the

CC1

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ0–DQ7 are

active and controlled by CE# and OE#. The data I/O

pins DQ8–DQ14 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

Writing Commands/Command Sequences

To write a command or command sequence (which

includes programming data to the device and erasing

sectors of memory), the system must drive WE# and

Requirements for Reading Array Data

To read array data from the outputs, the system must

CE# to V , and OE# to V .

IL

IH

drive the CE# and OE# pins to V . CE# is the power

IL

control and selects the device. OE# is the output

control and gates array data to the output pins. WE#

For program operations, the BYTE# pin determines

whether the device accepts program data in bytes or

words. Refer to “Word/Byte Configuration” for more

information.

should remain at V . The BYTE# pin determines

IH

whether the device outputs array data in words or

bytes.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Tables 2 and 3 indicate the

address space that each sector occupies. A “sector

address” consists of the address bits required to

uniquely select a sector. The “Command Definitions”

section has details on erasing a sector or the entire

chip, or suspending/resuming the erase operation.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No

command is necessary in this mode to obtain array

data. Standard microprocessor read cycles that assert

8

Am29F400B

21505E8 November 11, 2009

D A T A S H E E T

After the system writes the autoselect command In the CMOS and TTL/NMOS-compatible DC Charac-

sequence, the device enters the autoselect mode. The

system can then read autoselect codes from the

internal register (which is separate from the memory

array) on DQ7–DQ0. Standard read cycle timings apply

in this mode. Refer to the “Autoselect Mode” and

“Autoselect Command Sequence” sections for more

information.

teristics tables, I

specification.

represents the standby current

CC3

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of reset-

ting the device to reading array data. When the

RESET# pin is driven low for at least a period of t the

RP,

device immediately terminates any operation in

progress, tristates all output pins, and ignores all read/

write commands for the duration of the RESET# pulse.

The device also resets the internal state machine to

reading array data. The operation that was interrupted

should be reinitiated once the device is ready to accept

another command sequence, to ensure data integrity.

I

in the DC Characteristics table represents the

CC2

active current specification for the write mode. The “AC

Characteristics” section contains timing specification

tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status

Current is reduced for the duration of the RESET#

bits on DQ7–DQ0. Standard read cycle timings and I

pulse. When RESET# is held at V , the device enters

CC

IL

read specifications apply. Refer to “The Erase Resume

command is valid only during the Erase Suspend

mode.” for more information, and to “AC Characteris-

tics” for timing diagrams.

the TTL standby mode; if RESET# is held at V

V, the device enters the CMOS standby mode.

0.5

SS

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

Standby Mode

When the system is not reading or writing to the device,

it can place the device in the standby mode. In this

mode, current consumption is greatly reduced, and the

outputs are placed in the high impedance state, inde-

pendent of the OE# input.

If RESET# is asserted during a program or erase oper-

ation, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of t

(during Embedded Algorithms). The

READY

system can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V ± 0.5 V.

CC

(Note that this is a more restricted voltage range than

V .) The device enters the TTL standby mode when

within a time of t

(not during Embedded Algo-

IH

READY

CE# and RESET# pins are both held at V . The device

rithms). The system can read data t

after the

IH

RH

requires standard access time (t ) for read access

RESET# pin returns to V .

CE

IH

when the device is in either of these standby modes,

before it is ready to read data.

Refer to the AC Characteristics tables for RESET#

parameters and to Figure 10 for the timing diagram.

The device also enters the standby mode when the

RESET# pin is driven low. Refer to the next section,

“RESET#: Hardware Reset Pin”.

Output Disable Mode

When the OE# input is at V , output from the device is

IH

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

disabled. The output pins are placed in the high imped-

ance state.

November 11, 2009 21505E8

Am29F400B

9

D A T A S H E E T

Table 2. Am29F400BT Top Boot Block Sector Address Table

Address Range (in hexadecimal)

Sector Size

(x8)

(x16)

Sector

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

A17

0

A16

0

A15

0

A14

X

0

A13

X

A12 (Kbytes/ Kwords)

Address Range

X

0

64/32

32/16

8/4

00000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–3FFFFh

40000h–4FFFFh

50000h–5FFFFh

60000h–6FFFFh

70000h–77FFFh

78000h–79FFFh

7A000h–7BFFFh

7C000h–7FFFFh

00000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3BFFFh

3C000h–3CFFFh

3D000h–3DFFFh

3E000h–3FFFFh

0

1

X

0

1

0

X

0

1

X

1

0

X

1

0

1

X

1

0

X

1

X

1

0

1

0

1

8/4

1

X

16/8

Table 3. Am29F400BB Bottom Boot Block Sector Address Table

Address Range (in hexadecimal)

Sector Size

(x8)

(x16)

Sector

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

A17

0

A16

0

A15

0

A14

0

A13

0

A12 (Kbytes/Kwords)

Address Range

X

0

16/8

8/4

00000h–03FFFh

04000h–05FFFh

06000h–07FFFh

08000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–3FFFFh

40000h–4FFFFh

50000h–5FFFFh

60000h–6FFFFh

70000h–7FFFFh

00000h–01FFFh

02000h–02FFFh

03000h–03FFFh

04000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

0

1

0

1

8/4

0

1

X

32/16

64/32

0

1

X

0

1

0

X

0

1

X

1

0

X

1

0

1

X

1

0

X

1

X

Note:

Address range is A17:A-1 in byte mode and A17:A0 in word mode.See the “Word/Byte Configuration” section for more

information.

Autoselect Mode

The autoselect mode provides manufacturer and

device identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equipment

to automatically match a device to be programmed with

its corresponding programming algorithm. However,

the autoselect codes can also be accessed in-system

through the command register.

the sector address must appear on the appropriate

highest order address bits (see Tables 2 and 3). Table

4 shows the remaining address bits that are don’t care.

When all necessary bits have been set as required, the

programming equipment may then read the corre-

sponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 5. This method

When using programming equipment, the autoselect

mode requires V (11.5 V to 12.5 V) on address pin

does not require V . See “Command Definitions” for

ID

A9. Address pins A6, A1, and A0 must be as shown in

Table 4. In addition, when verifying sector protection,

details on using the autoselect mode.

10

Am29F400B

21505E8 November 11, 2009

D A T A S H E E T

Table 4. Am29F400B Autoselect Codes (High Voltage Method)

A17 A11

to to

Mode CE# OE# WE# A12 A10 A9

A8

to

A7

A5

to

A2

DQ8

to

A0 DQ15

DQ7

to

DQ0

Description

A6

A1

Manufacturer ID: AMD

L

H

X

V_ID

X

L

X

L

X

01h

23h

Device ID:

Am29F400B

(Top Boot Block)

Word

Byte

Word

Byte

22h

X

V_ID

L

H

L

H

X

22h

X

23h

ABh

Device ID:

Am29F400B

(Bottom Boot Block)

X

V_ID

X

H

L

01h

(protected)

X

Sector Protection Verification

L

H

SA

V_ID

L

H

00h

(unprotected)

L = Logic Low = V_IL, H = Logic High = V_IH, SA = Sector Address, X = Don’t care.

rithm, and Figure 18 shows the timing diagrams, for this

feature.

Sector Protection/Unprotection

The hardware sector protection feature disables both

program and erase operations in any sector. The hard-

ware sector unprotection feature re-enables both

program and erase operations in previously protected

sectors.

START

Sector protection/unprotection must be implemented

using programming equipment. The procedure

RESET# = V_ID

(Note 1)

requires a high voltage (V ) on address pin A9 and

ID

OE#. Details on this method are provided in a supple-

ment, publication number 20185. Contact an AMD

representative to obtain a copy of this document.

Perform Erase or

Program Operations

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

RESET# = V_IH

Temporary Sector

Unprotect Completed

(Note 2)

It is possible to determine whether a sector is protected

or unprotected. See “Autoselect Mode” for details.

Temporary Sector Unprotect

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The

Sector Unprotect mode is activated by setting the

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once

again.

RESET# pin to V . During this mode, formerly pro-

ID

tected sectors can be programmed or erased by

selecting the sector addresses. Once V is removed

from the RESET# pin, all the previously protected

sectors are protected again. Figure 1 shows the algo-

ID

Figure 1. Temporary Sector Unprotect Operation

November 11, 2009 21505E8

Am29F400B

11

D A T A S H E E T

proper signals to the control pins to prevent uninten-

Hardware Data Protection

tional writes when V is greater than V

.

CC

LKO

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 5 for

command definitions). In addition, the following hard-

ware data protection measures prevent accidental

erasure or programming, which might otherwise be

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Logical Inhibit

caused by spurious system level signals during V

power-up and power-down transitions, or from system

noise.

Write cycles are inhibited by holding any one of OE# =

CC

V , CE# = V or WE# = V . To initiate a write cycle,

IL

IH

CE# and WE# must be a logical zero while OE# is a

logical one.

Low V

Write Inhibit

CC

Power-Up Write Inhibit

When V

is less than V

, the device does not

LKO

CC

accept any write cycles. This protects data during V

power-up and power-down. The command register and

all internal program/erase circuits are disabled, and the

If WE# = CE# = V and OE# = V during power up, the

CC

IL

IH

device does not accept commands on the rising edge

of WE#. The internal state machine is automatically

reset to reading array data on power-up.

device resets. Subsequent writes are ignored until V

CC

is greater than V

. The system must provide the

LKO

12

Am29F400B

21505E8 November 11, 2009

D A T A S H E E T

COMMAND DEFINITIONS

Writing specific address and data commands or

sequences into the command register initiates device

operations. Table 5 defines the valid register command

sequences. Writing incorrect address and data

values or writing them in the improper sequence

resets the device to reading array data.

however, the device ignores reset commands until the

operation is complete.

The reset command may be written between the

sequence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command must

be written to return to reading array data (also applies

to autoselect during Erase Suspend).

All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to

reading array data (also applies during Erase

Suspend).

Reading Array Data

Autoselect Command Sequence

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is also ready to read array

data after completing an Embedded Program or

Embedded Erase algorithm.

The autoselect command sequence allows the host

system to access the manufacturer and devices codes,

and determine whether or not a sector is protected.

Table 5 shows the address and data requirements. This

method is an alternative to that shown in Table 4, which

After the device accepts an Erase Suspend command,

the device enters the Erase Suspend mode. The

system can read array data using the standard read

timings, except that if it reads at an address within

erase-suspended sectors, the device outputs status

data. After completing a programming operation in the

Erase Suspend mode, the system may once again

read array data with the same exception. See “Erase

Suspend/Erase Resume Commands” for more infor-

mation on this mode.

is intended for PROM programmers and requires V

on address bit A9.

ID

The autoselect command sequence is initiated by

writing two unlock cycles, followed by the autoselect

command. The device then enters the autoselect

mode, and the system may read at any address any

number of times, without initiating another command

sequence.

A read cycle at address XX00h or retrieves the manu-

facturer code. A read cycle at address XX01h in word

mode (or 02h in byte mode) returns the device code. A

read cycle containing a sector address (SA) and the

address 02h in word mode (or 04h in byte mode)

returns 01h if that sector is protected, or 00h if it is

unprotected. Refer to Tables 2 and 3 for valid sector

addresses.

The system must issue the reset command to re-

enable the device for reading array data if DQ5 goes

high, or while in the autoselect mode. See the “Reset

Command” section, next.

See also “Requirements for Reading Array Data” in the

“Device Bus Operations” section for more information.

The Read Operations table provides the read parame-

ters, and Figure 9 shows the timing diagram.

The system must write the reset command to exit the

autoselect mode and return to reading array data.

Reset Command

Writing the reset command to the device resets the

device to reading array data. Address bits are don’t

care for this command.

Word/Byte Program Command Sequence

The system may program the device by word or byte,

depending on the state of the BYTE# pin. Program-

ming is a four-bus-cycle operation. The program

command sequence is initiated by writing two unlock

write cycles, followed by the program set-up command.

The program address and data are written next, which

in turn initiate the Embedded Program algorithm. The

system is not required to provide further controls or tim-

ings. The device automatically provides internally

generated program pulses and verify the programmed

cell margin. Table 5 shows the address and data

requirements for the byte program command

sequence.

The reset command may be written between the

sequence cycles in an erase command sequence

before erasing begins. This resets the device to reading

array data. Once erasure begins, however, the device

ignores reset commands until the operation is

complete.

The reset command may be written between the

sequence cycles in a program command sequence

before programming begins. This resets the device to

reading array data (also applies to programming in

Erase Suspend mode). Once programming begins,

When the Embedded Program algorithm is complete,

the device then returns to reading array data and

November 11, 2009 21505E8

Am29F400B

13

D A T A S H E E T

addresses are no longer latched. The system can

Chip Erase Command Sequence

determine the status of the program operation by using

DQ7, DQ6, or RY/BY#. See “The Erase Resume

command is valid only during the Erase Suspend

mode.” for information on these status bits.

Chip erase is a six-bus-cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 5 shows

the address and data requirements for the chip erase

command sequence.

Any commands written to the device during the

Embedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program-

ming operation. The Byte Program command

sequence should be reinitiated once the device has

reset to reading array data, to ensure data integrity.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may halt

the operation and set DQ5 to “1”, or cause the Data#

Polling algorithm to indicate the operation was suc-

cessful. However, a succeeding read will show that the

data is still “0”. Only erase operations can convert a “0”

to a “1”.

Any commands written to the chip during the

Embedded Erase algorithm are ignored. Note that a

hardware reset during the chip erase operation imme-

diately terminates the operation. The Chip Erase

command sequence should be reinitiated once the

device has returned to reading array data, to ensure

data integrity.

The system can determine the status of the erase oper-

ation by using DQ7, DQ6, DQ2, or RY/BY#. See “The

Erase Resume command is valid only during the Erase

Suspend mode.” for information on these status bits.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses are

no longer latched.

START

Write Program

Command Sequence

Figure 3 illustrates the algorithm for the erase opera-

tion. See the “Erase/Program Operations” tables in “AC

Characteristics” for parameters, and to Figure 14 for

timing diagrams.

Data Poll

from System

Embedded

Program

algorithm

Sector Erase Command Sequence

in progress

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two

additional unlock write cycles are then followed by the

address of the sector to be erased, and the sector

erase command. Table 5 shows the address and data

requirements for the sector erase command sequence.

Verify Data?

No

Yes

No

Increment Address

Last Address?

Yes

The device does not require the system to preprogram

the memory prior to erase. The Embedded Erase algo-

rithm automatically programs and verifies the sector for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or

timings during these operations.

Programming

Completed

After the command sequence is written, a sector erase

time-out of 50 µs begins. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of

sectors may be from one sector to all sectors. The time

between these additional cycles must be less than 50

Note:

See Table 5 for program command sequence.

Figure 2. Program Operation

14

Am29F400B

21505E8 November 11, 2009

D A T A S H E E T

µs, otherwise the last address and command might not

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other commands

are ignored. Note that a hardware reset during the

sector erase operation immediately terminates the

operation. The Sector Erase command sequence

should be reinitiated once the device has returned to

reading array data, to ensure data integrity.

be accepted, and erasure may begin. It is recom-

mended that processor interrupts be disabled during

this time to ensure all commands are accepted. The

interrupts can be re-enabled after the last Sector Erase

command is written. If the time between additional

sector erase commands can be assumed to be less

than 50 µs, the system need not monitor DQ3. Any

command other than Sector Erase or Erase

Suspend during the time-out period resets the

device to reading array data. The system must

rewrite the command sequence and any additional

sector addresses and commands.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses are

no longer latched. The system can determine the

status of the erase operation by using DQ7, DQ6, DQ2,

or RY/BY#. (Refer to “The Erase Resume command is

valid only during the Erase Suspend mode.” for infor-

mation on these status bits.)

The system can monitor DQ3 to determine if the sector

erase timer has timed out. (See the “DQ3: Sector Erase

Timer” section.) The time-out begins from the rising

edge of the final WE# pulse in the command sequence.

Figure 3 illustrates the algorithm for the erase opera-

tion. Refer to the “Erase/Program Operations” tables in

the “AC Characteristics” section for parameters, and to

Figure 14 for timing diagrams.

November 11, 2009 21505E8

Am29F400B

15

D A T A S H E E T

even at addresses within erasing sectors, since the

Erase Suspend/Erase Resume Commands

codes are not stored in the memory array. When the

device exits the autoselect mode, the device reverts to

the Erase Suspend mode, and is ready for another

valid operation. See “Autoselect Command Sequence”

for more information.

The Erase Suspend command allows the system to

interrupt a sector erase operation and then read data

from, or program data to, any sector not selected for

erasure. This command is valid only during the sector

erase operation, including the 50 µs time-out period

during the sector erase command sequence. The

Erase Suspend command is ignored if written during

the chip erase operation or Embedded Program algo-

rithm. Writing the Erase Suspend command during the

Sector Erase time-out immediately terminates the

time-out period and suspends the erase operation.

Addresses are “don’t-cares” when writing the Erase

Suspend command.

The system must write the Erase Resume command

(address bits are “don’t care”) to exit the erase suspend

mode and continue the sector erase operation. Further

writes of the Resume command are ignored. Another

Erase Suspend command can be written after the

device has resumed erasing.

When the Erase Suspend command is written during a

sector erase operation, the device requires a maximum

of 20 µs to suspend the erase operation. However,

when the Erase Suspend command is written during

the sector erase time-out, the device immediately ter-

minates the time-out period and suspends the erase

operation.

START

Write Erase

Command Sequence

After the erase operation has been suspended, the

system can read array data from or program data to

any sector not selected for erasure. (The device “erase

suspends” all sectors selected for erasure.) Normal

read and write timings and command definitions apply.

Reading at any address within erase-suspended

sectors produces status data on DQ7–DQ0. The

system can use DQ7, or DQ6 and DQ2 together, to

determine if a sector is actively erasing or is erase-sus-

pended. See “The Erase Resume command is valid

only during the Erase Suspend mode.” for information

on these status bits.

Data Poll

from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

Yes

Erasure Completed

After an erase-suspended program operation is com-

plete, the system can once again read array data within

non-suspended sectors. The system can determine

the status of the program operation using the DQ7 or

DQ6 status bits, just as in the standard program oper-

ation. See “The Erase Resume command is valid only

during the Erase Suspend mode.” for more information.

Notes:

1. See Table 5 for erase command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

The system may also write the autoselect command

sequence when the device is in the Erase Suspend

mode. The device allows reading autoselect codes

Figure 3. Erase Operation

16

Am29F400B

21505E8 November 11, 2009

D A T A S H E E T

Table 5. Am29F400B Command Definitions

Bus Cycles (Notes 2–5)

Command

Sequence

(Note 1)

First

Second

Third

Addr

Fourth

Fifth

Sixth

Addr Data Addr Data

Data Addr Data Addr Data Addr Data

Read (Note 6)

Reset (Note 7)

1

RA

XXX

555

RD

F0

Word

Byte

Word

Byte

Word

Byte

2AA

555

2AA

555

2AA

555

AAA

555

Manufacturer ID

4

AA

55

90

X00

01

AAA

555

X01

X02

2223

23

Device ID,

Top Boot Block

AAA

555

AAA

555

X01 22AB

Device ID,

Bottom Boot Block

AAA

X02

AB

XX00

XX01

00

(SA)

X02

Word

Byte

555

2AA

555

Sector Protect Verify

(Note 9)

4

AA

55

90

(SA)

X04

AAA

01

Word

Byte

Word

Byte

Word

Byte

555

AAA

555

2AA

555

2AA

555

2AA

555

AAA

555

Program

4

6

AA

55

A0

80

PA

PD

AA

555

AAA

555

2AA

555

2AA

555

Chip Erase

55

10

30

AAA

555

AAA

555

AAA

Sector Erase

SA

AAA

XXX

AAA

Erase Suspend (Note 10)

Erase Resume (Note 11)

1

B0

30

Legend:

X = Don’t care

PD = Data to be programmed at location PA. Data latches on the

rising edge of WE# or CE# pulse, whichever happens first.

RA = Address of the memory location to be read.

SA = Address of the sector to be verified (in autoselect mode) or

erased. Address bits A17–A12 uniquely select any sector.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed.

Addresses latch on the falling edge of the WE# or CE# pulse,

whichever happens later.

Notes:

1. See Table 1 for description of bus operations.

8. The fourth cycle of the autoselect command sequence is a

read cycle.

2. All values are in hexadecimal.

9. The data is 00h for an unprotected sector and 01h for a

protected sector. See“Autoselect Command Sequence” for

more information.

3. Except when reading array or autoselect data, all bus cycles

are write operations.

4. Data bits DQ15–DQ8 are don’t cares for unlock and

command cycles.

10. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend

mode. The Erase Suspend command is valid only during a

sector erase operation.

5. Address bits A17–A11 are don’t cares for unlock and

command cycles, unless PA or SA required.

6. No unlock or command cycles required when reading array

data.

11. The Erase Resume command is valid only during the Erase

Suspend mode.

7. The Reset command is required to return to reading array

data when device is in the autoselect mode, or if DQ5 goes

high (while the device is providing status data).

November 11, 2009 21505E8

Am29F400B

17

D A T A S H E E T

WRITE OPERATION STATUS

The device provides several bits to determine the

status of a write operation: DQ2, DQ3, DQ5, DQ6,

DQ7, and RY/BY#. Table 6 and the following subsec-

tions describe the functions of these bits. DQ7, RY/

BY#, and DQ6 each offer a method for determining

whether a program or erase operation is complete or in

progress. These three bits are discussed first.

Table 6 shows the outputs for Data# Polling on DQ7.

Figure 4 shows the Data# Polling algorithm.

START

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host

system whether an Embedded Algorithm is in progress

or completed, or whether the device is in Erase Sus-

pend. Data# Polling is valid after the rising edge of the

final WE# pulse in the program or erase command

sequence.

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to

programming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active for

approximately 2 µs, then the device returns to reading

array data.

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

This is analogous to the complement/true datum output

described for the Embedded Program algorithm: the

erase function changes all the bits in a sector to “1”;

prior to this, the device outputs the “complement,” or

“0.” The system must provide an address within any of

the sectors selected for erasure to read valid status

information on DQ7.

Yes

DQ7 = Data?

No

PASS

FAIL

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data#

Polling on DQ7 is active for approximately 100 µs, then

the device returns to reading array data. If not all

selected sectors are protected, the Embedded Erase

algorithm erases the unprotected sectors, and ignores

the selected sectors that are protected.

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at

DQ7–DQ0 on the following read cycles. This is

because DQ7 may change asynchronously with

DQ0–DQ6 while Output Enable (OE#) is asserted low.

Figure 15, Data# Polling Timings (During Embedded

Algorithms), in the “AC Characteristics” section illus-

trates this.

Figure 4. Data# Polling Algorithm

18

Am29F400B

21505E8 November 11, 2009

D A T A S H E E T

Table 6 shows the outputs for Toggle Bit I on DQ6.

RY/BY#: Ready/Busy#

Figure 5 shows the toggle bit algorithm. Figure 16 in the

“AC Characteristics” section shows the toggle bit timing

diagrams. Figure 17 shows the differences between

DQ2 and DQ6 in graphical form. See also the subsec-

tion on “DQ2: Toggle Bit II”.

The RY/BY# is a dedicated, open-drain output pin that

indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open-drain output,

several RY/BY# pins can be tied together in parallel

DQ2: Toggle Bit II

with a pull-up resistor to V

.

CC

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

If the output is low (Busy), the device is actively erasing

or programming. (This includes programming in the

Erase Suspend mode.) If the output is high (Ready),

the device is ready to read array data (including during

the Erase Suspend mode), or is in the standby mode.

Table 6 shows the outputs for RY/BY#. Figures 10,

Figure 13 and Figure 14 shows RY/BY# for reset, pro-

gram, and erase operations, respectively.

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. (The system may use either OE# or CE# to

control the read cycles.) But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-sus-

pended. DQ6, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but

cannot distinguish which sectors are selected for era-

sure. Thus, both status bits are required for sector and

mode information. Refer to Table 6 to compare outputs

for DQ2 and DQ6.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or complete,

or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address, and is

valid after the rising edge of the final WE# pulse in the

command sequence (prior to the program or erase

operation), and during the sector erase time-out.

Figure 5 shows the toggle bit algorithm in flowchart

form, and the section “DQ2: Toggle Bit II” explains the

algorithm. See also the “DQ6: Toggle Bit I” subsection.

Figure 16 shows the toggle bit timing diagram. Figure

17 shows the differences between DQ2 and DQ6 in

graphical form.

During an Embedded Program or Erase algorithm

operation, successive read cycles to any address

cause DQ6 to toggle. The system may use either OE#

or CE# to control the read cycles. When the operation

is complete, DQ6 stops toggling.

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6 toggles

for approximately 100 µs, then returns to reading array

data. If not all selected sectors are protected, the

Embedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are

protected.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 5 for the following discussion. When-

ever the system initially begins reading toggle bit

status, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically, the

system would note and store the value of the toggle bit

after the first read. After the second read, the system

would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has com-

pleted the program or erase operation. The system can

read array data on DQ7–DQ0 on the following read

cycle.

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is erase-

suspended. When the device is actively erasing (that is,

the Embedded Erase algorithm is in progress), DQ6

toggles. When the device enters the Erase Suspend

mode, DQ6 stops toggling. However, the system must

also use DQ2 to determine which sectors are erasing

or erase-suspended. Alternatively, the system can use

DQ7 (see the subsection on “DQ7: Data# Polling”).

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the

system also should note whether the value of DQ5 is

high (see the section on DQ5). If it is, the system

should then determine again whether the toggle bit is

toggling, since the toggle bit may have stopped tog-

gling just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the

device did not complete the operation successfully, and

the system must write the reset command to return to

reading array data.

If a program address falls within a protected sector,

DQ6 toggles for approximately 2 µs after the program

command sequence is written, then returns to reading

array data.

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded

Program algorithm is complete.

November 11, 2009 21505E8

Am29F400B

19

D A T A S H E E T

The remaining scenario is that the system initially

determines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor the

toggle bit and DQ5 through successive read cycles,

determining the status as described in the previous

paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to

determine the status of the operation (top of Figure 5).

START

Read DQ7–DQ0

(Note 1)

No

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure

condition that indicates the program or erase cycle was

not successfully completed.

Toggle Bit

= Toggle?

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is previously pro-

grammed to “0.” Only an erase operation can change

a “0” back to a “1.” Under this condition, the device

halts the operation, and when the operation has

exceeded the timing limits, DQ5 produces a “1.”

Yes

No

DQ5 = 1?

Yes

Under both these conditions, the system must issue the

reset command to return the device to reading array

data.

(Notes

1, 2)

Read DQ7–DQ0

Twice

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not an

erase operation has begun. (The sector erase timer

does not apply to the chip erase command.) If addi-

tional sectors are selected for erasure, the entire time-

out also applies after each additional sector erase com-

mand. When the time-out is complete, DQ3 switches

from “0” to “1.” If the time between additional sector

erase commands from the system can be assumed to

be less than 50 µs, the system need not monitor DQ3.

See also the “Sector Erase Command Sequence”

section.

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Notes:

1. Read toggle bit twice to determine whether or not it is

After the sector erase command sequence is written,

the system should read the status on DQ7 (Data#

Polling) or DQ6 (Toggle Bit I) to ensure the device has

accepted the command sequence, and then read DQ3.

If DQ3 is “1”, the internally controlled erase cycle has

begun; all further commands (other than Erase Sus-

pend) are ignored until the erase operation is complete.

If DQ3 is “0”, the device will accept additional sector

erase commands. To ensure the command has been

accepted, the system software should check the status

of DQ3 prior to and following each subsequent sector

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1”. See text.

Figure 5. Toggle Bit Algorithm

erase command. If DQ3 is high on the second status

check, the last command might not have been

accepted. Table 6 shows the outputs for DQ3.

20

Am29F400B

21505E8 November 11, 2009

D A T A S H E E T

Table 6. Write Operation Status

DQ7

DQ5

DQ2

Operation

(Note 2)

DQ6

(Note 1)

DQ3

N/A

1

(Note 2)

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

Reading within Erase

Suspended Sector

1

No toggle

0

N/A

Toggle

1

Erase

Suspend Reading within Non-Erase

Data

0

Data

N/A

Data

N/A

1

0

Mode

Suspended Sector

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

November 11, 2009 21505E8

Am29F400B

21

D A T A S H E E T

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . .–65° C to +150°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . .–55° C to +125°C

20 ns

Voltage with Respect to Ground

+0.8 V

V

(Note 1) . . . . . . . . . . . . . . . .–2.0 V to +7.0 V

CC

–0.5 V

–2.0 V

A9, OE#, and

RESET# (Note 2). . . . . . . . . . . .–2.0 V to +12.5 V

All other pins (Note 1) . . . . . . . . .–0.5 V to +7.0 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

20 ns

Notes:

Figure 6. Maximum Negative

Overshoot Waveform

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

voltage transitions, input or I/O pins may overshoot V_SSto

–2.0 V for periods of up to 20 ns. See Figure 6. Maximum

DC voltage on input or I/O pins is V_CC+0.5 V. During

voltage transitions, input or I/O pins may overshoot to V_CC

+2.0 V for periods up to 20 ns. See Figure 7.

20 ns

2. Minimum DC input voltage on pins A9, OE#, and RESET#

is –0.5 V. During voltage transitions, A9, OE#, and

RESET# may overshoot V_SSto –2.0 V for periods of up to

20 ns. See Figure 6. Maximum DC input voltage on pin A9

is +12.5 V which may overshoot to +13.5 V for periods up

to 20 ns.

V_CC

+2.0 V

V_CC

+0.5 V

2.0 V

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

20 ns

Note:Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is

a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

Figure 7. Maximum Positive

Overshoot Waveform

conditions for extended periods may affect device reliability.

OPERATING RANGES

Industrial (I) Devices

Ambient Temperature (T ) . . . . . . . . . –40°C to +85°C

A

Extended (E) Devices

Ambient Temperature (T ) . . . . . . . . –55°C to +125°C

A

V

Supply Voltages

CC

for 5ꢀ devices. . . . . . . . . . .+4.75 V to +5.25 V

for 10ꢀ devices. . . . . . . . . . . .+4.5 V to +5.5 V

Note:Operating ranges define those limits between which the

functionality of the device is guaranteed.

22

Am29F400B

21505E8 November 11, 2009

D A T A S H E E T

DC CHARACTERISTICS

TTL/NMOS Compatible

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

I_LI

Input Load Current

V_IN= V_SSto V_CC, V_CC= V_{CC max}

± 1.0

µA

A9, OE#, RESET# Input Load

Current

V_CC= V_{CC max};

A9, OE#, RESET# = 12.5 V

I_LIT

I_LO

50

± 1.0

40

µA

Output Leakage Current

V_OUT= V_SSto V_CC, V_CC= V_{CC max}

CE# = V_IL, OE# = V_IH,

f = 5 MHz, Byte Mode

19

mA

V_CCActive Read Current

(Notes 1, 2)

I_CC1

CE# = V_IL, OE# ₌V_IH,

f = 5 MHz, Word Mode

50

60

mA

V_CCActive Write Current

(Notes 2, 3, 4)

I_CC2

CE# = V_IL, OE# = V_IH

36

I_CC3

V_IL

V_CCStandby Current (Note 2)

Input Low Voltage

CE#, RESET#, and OE# = V_IH

0.4

1

mA

V

–0.5

2.0

0.8

V_CC

+0.5

V_IH

V_ID

Input High Voltage

V

Voltage for Autoselect and

Temporary Sector Unprotect

V_CC= 5.0 V

11.5

12.5

0.45

V_OL

V_OH

V_LKO

Output Low Voltage

I_OL= 5.8 mA, V_CC= V_{CC min}

I_OH= –2.5 mA, V_CC= V_{CC min}

V

Output High Voltage

Low V_CCLock-Out Voltage

2.4

3.2

4.2

Notes:

1. The I_CCcurrent listed is typically less than 2 mA/MHz, with OE# at V_IH..

2. Maximum I_CCspecifications are tested with V_CC= V_CCmax

.

3. I_CCactive while Embedded Erase or Embedded Program is in progress.

4. Not 100% tested.

November 11, 2009 21505E8

Am29F400B

23

D A T A S H E E T

DC CHARACTERISTICS

CMOS Compatible

Parameter

Description

Test Conditions

V_IN= V_SSto V_CC

Min

Typ

Max

Unit

,

I_LI

Input Load Current

± 1.0

µA

V_CC= V_{CC max}

A9, OE#, RESET#

Input Load Current

V_CC= V_{CC max};

A9, OE#, RESET# = 12.5 V

I_LIT

50

± 1.0

40

µA

V_OUT= V_SSto V_CC

V_CC= V_{CC max}

,

I_LO

Output Leakage Current

CE# = V_IL, OE# = V_IH,

f = 5 MHz, Byte Mode

20

28

30

0.3

V_CCActive Read Current

(Notes 1, 2)

I_CC1

mA

CE# = V_IL, OE# = V_IH,

f = 5 MHz, Word Mode

50

V_CCActive Write Current

(Notes 2, 3, 4)

I_CC2

CE# = V_IL, OE# ₌V_IH

50

V_CCStandby Current

(Notes 2, 5

I_CC3

V_IL

OE# = V_IH, CE# and RESET# = V_CC± 0.5 V

5

µA

V

Input Low Voltage

Input High Voltage

–0.5

0.8

0.7 x

V_CC

+

V_IH

V

0.3

Voltage for Autoselect and

Temporary Sector Unprotect

V_ID

V_OL

V_CC= 5.0 V

11.5

12.5

0.45

V

Output Low Voltage

I_OL= 5.8 mA, V_CC= V_{CC min}

I_OH= –2.5 mA, V_CC= V_{CC min}

0.85

V_CC

V_OH1

Output High Voltage

V_CC–0.

4

V_OH2

V_LKO

I_OH= –100 µA, V_CC= V_{CC min}

Low V_CCLock-Out Voltage

3.2

4.2

V

Notes:

1. The I_CCcurrent listed is typically less than 2 mA/MHz, with OE# at V_IH.

2. Maximum I_CCspecifications are tested with V_CC= V_CCmax

.

3. I_CCactive while Embedded Erase or Embedded Program is in progress.

4. Not 100% tested.

5. I_CC3= 20 µA max at extended temperature (>+85°±C).

24

Am29F400B

21505E8 November 11, 2009

D A T A S H E E T

TEST CONDITIONS

Table 7. Test Specifications

5.0 V

-45,

-50, -55

All

others Unit

Test Condition

2.7 kΩ

Output Load

1 TTL gate

Device

Under

Test

Output Load Capacitance, C_L

(including jig capacitance)

30

5

100

20

pF

C

L

6.2 kΩ

Input Rise and Fall Times

Input Pulse Levels

ns

V

0.0–3.0 0.45–2.4

Input timing measurement

reference levels

1.5

0.8, 2.0

V

Note:

Output timing measurement

reference levels

Diodes are IN3064 or equivalent.

Figure 8. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

November 11, 2009 21505E8

Am29F400B

25

D A T A S H E E T

AC CHARACTERISTICS

Read Operations

Parameter

Speed Options

JEDEC

Std

Description

Test Setup

-45

-50

-55

-70

-90

Unit

t_AVAV

t_RC

Read Cycle Time (Note 1)

Min

45

50

55

70

90

ns

CE# = V_IL

Max

t_AVQV

t_ACCAddress to Output Delay

45

55

90

ns

OE# = V_IL

t_ELQV

t_GLQV

t_CE

t_OE

Chip Enable to Output Delay

Output Enable to Output Delay

OE# = V_IL

Max

45

30

50

30

55

30

70

30

90

35

ns

Chip Enable to Output High Z

(Note 1)

t_EHQZ

t_DF

Max

15

20

ns

Output Enable to Output High Z

(Note 1)

t_GHQZ

t_DF

Max

Min

15

0

ns

Read

Output Enable

t_OEHHold Time

(Note 1)

Toggle and

Data# Polling

10

Output Hold Time From

Addresses, CE# or OE#,

Whichever Occurs First (Note 1)

t_AXQX

t_OH

Min

0

ns

Notes:

1. Not 100% tested.

2. See Figure 8 and Table 7 for test specifications.

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

Figure 9. Read Operations Timings

26

Am29F400B

21505E8 November 11, 2009

D A T A S H E E T

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std Description

Test Setup

All Speed Options

Unit

RESET# Pin Low (During Embedded

Algorithms) to Read or Write (See Note)

t_READY

Max

20

µs

RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (See Note)

t_READY

500

ns

t_RP

t_RH

t_RB

RESET# Pulse Width

Min

500

50

0

ns

RESET# High Time Before Read (See Note)

RY/BY# Recovery Time

Note:

Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

Figure 10. RESET# Timings

November 11, 2009 21505E8

Am29F400B

27

D A T A S H E E T

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

Speed Options

JEDEC

Std

Description

-45

-50

-55

5

-70

-90

Unit

ns

t

_ELFL/t_ELFHCE# to BYTE# Switching Low or High

Max

Min

t_FLQZ

t_FHQV

BYTE# Switching Low to Output HIGH Z

BYTE# Switching High to Output Active

15

45

15

50

15

55

20

70

20

90

ns

CE#

OE#

BYTE#

t_ELFL

Data Output

(DQ0–DQ14)

Data Output

(DQ0–DQ7)

BYTE#

Switching

from word

to byte

DQ0–DQ14

Address

Input

DQ15

Output

mode

DQ15/A-1

t_FLQZ

t_ELFH

BYTE#

Switching

from byte

to word

Data Output

(DQ0–DQ7)

Data Output

(DQ0–DQ14)

DQ0–DQ14

DQ15/A-1

mode

Address

Input

DQ15

Output

t_FHQV

Figure 11. BYTE# Timings for Read Operations

CE#

The falling edge of the last WE# signal

WE#

BYTE#

t_SET

(t_AS

)

t_HOLD(t_AH

)

Note:

Refer to the Erase/Program Operations table for t_ASand t_AHspecifications.

Figure 12. BYTE# Timings for Write Operations

28

Am29F400B

21505E8 November 11, 2009

D A T A S H E E T

AC CHARACTERISTICS

Erase/Program Operations

Parameter

Speed Options

JEDEC

t_AVAV

Std

t_WC

t_AS

Description

-45

-50

-55

55

0

-70

-90

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min

45

50

70

90

t_AVWL

t_WLAX

t_DVWH

t_WHDX

ns

t_AH

45

25

45

25

45

25

0

45

30

45

ns

t_DS

ns

t_DH

t_OES

Data Hold Time

ns

Output Enable Setup Time

0

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHWL

Min

0

ns

t_ELWL

t_WHEH

t_WLWH

t_WHWL

t_CS

t_CH

CE# Setup Time

Min

Typ

Min

Max

0

ns

CE# Hold Time

t_WP

Write Pulse Width

Write Pulse Width High

30

20

7

35

45

t_WPH

Byte

Programming Operation (Note

2)

t_WHWH1

t_WHWH2

t_WHWH1

µs

Word

12

1

t_WHWH2Sector Erase Operation (Note 2)

sec

µs

t_VCS

t_RB

V_CCSetup Time (Note 1)

50

0

Recovery Time from RY/BY#

ns

t_BUSY

Program/Erase Valid to RY/BY# Delay

30

35

ns

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

November 11, 2009 21505E8

Am29F400B

29

D A T A S H E E T

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D_OUTis the true data at the program address.

2. Illustration shows device in word mode.

Figure 13. Program Operation Timings

30

Am29F400B

21505E8 November 11, 2009

D A T A S H E E T

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

t_WC

VA

Addresses

CE#

2AAh

SA

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

2. Illustration shows device in word mode.

Figure 14. Chip/Sector Erase Operation Timings

November 11, 2009 21505E8

Am29F400B

31

D A T A S H E E T

AC CHARACTERISTICS

t_RC

VA

Addresses

VA

t_ACC

t_CE

CE#

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

Status Data

True

DQ0–DQ6

Valid Data

Status Data

True

t_BUSY

RY/BY#

Note:

VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

Figure 15. Data# Polling Timings (During Embedded Algorithms)

t_RC

Addresses

CE#

VA

t_ACC

t_CE

VA

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ6/DQ2

Valid Status

(first read)

Valid Status

Valid Data

(second read)

(stops toggling)

t_BUSY

RY/BY#

Note:

VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,

and array data read cycle.

Figure 16. Toggle Bit Timings (During Embedded Algorithms)

32

Am29F400B

21505E8 November 11, 2009

D A T A S H E E T

AC CHARACTERISTICS

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note:

The system may use either CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an

erase-suspended sector.

Figure 17. DQ2 vs. DQ6

Temporary Sector Unprotect

Parameter

JEDEC

Std

Description

All Speed Options

Unit

t_VIDR

V_IDRise and Fall Time (See Note)

Min

500

ns

RESET# Setup Time for Temporary Sector

Unprotect

t_RSP

4

µs

Note: Not 100% tested.

12 V

RESET#

0 or 5 V

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RSP

RY/BY#

Figure 18. Temporary Sector Unprotect Timing Diagram

November 11, 2009 21505E8

Am29F400B

33

D A T A S H E E T

AC CHARACTERISTICS

Alternate CE# Controlled Erase/Program Operations

Parameter

Speed Options

JEDEC

t_AVAV

Std

t_WC

t_AS

Description

-45

-50

-55

55

0

-70

-90

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min

45

50

70

90

t_AVEL

ns

t_ELAX

t_DVEH

t_EHDX

t_AH

45

25

45

25

45

25

0

45

30

45

ns

t_DS

ns

t_DH

t_OES

Data Hold Time

ns

Output Enable Setup Time

0

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

0

ns

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_WS

t_WH

t_CP

WE# Setup Time

WE# Hold Time

Min

Typ

0

ns

CE# Pulse Width

CE# Pulse Width High

30

20

7

35

45

t_CPH

Byte

Programming Operation

(Note 2)

t_WHWH1

t_WHWH2

t_WHWH1

t_WHWH2

µs

Word

12

1

Sector Erase Operation (Note 2)

sec

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

34

Am29F400B

21505E8 November 11, 2009

D A T A S H E E T

AC CHARACTERISTICS

555 for program

PA for program

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, D_OUT= Array Data.

2. Figure indicates the last two bus cycles of the command sequence, with the device in word mode.

Figure 19. Alternate CE# Controlled Write Operation Timings

November 11, 2009 21505E8

Am29F400B

35

D A T A S H E E T

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1)

Max (Note 2)

Unit

s

Comments

Sector Erase Time

Chip Erase Time

1.0

11

7

8

Excludes 00h programming

prior to erasure

s

Byte Programming Time

Word Programming Time

300

500

10.8

9.3

µs

s

12

3.6

3.1

Excludes system level

overhead (Note 5)

Byte Mode

Word Mode

Chip Programming Time

(Note 3)

s

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 5.0 V V_CC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V_CC= 4.5 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 5

for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V_SSon all pins except I/O pins

(including A9, OE#, and RESET#)

–1.0 V

12.5 V

Input voltage with respect to V_SSon all I/O pins

V_CCCurrent

–1.0 V

V_CC+ 1.0 V

+100 mA

–100 mA

Includes all pins except V_CC. Test conditions: V_CC= 5.0 V, one pin at a time.

TSOP AND SO PIN CAPACITANCE

Parameter

Symbol

Parameter Description

Input Capacitance

Test Setup

V_IN= 0

Typ

6

Max

7.5

12

Unit

pF

C_IN

C_OUT

C_IN2

Output Capacitance

Control Pin Capacitance

V_OUT= 0

V_IN= 0

8.5

7.5

pF

9

pF

Notes:

1. Sampled, not 100% tested.

2. Test conditions T_A= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter

Test Conditions

Min

10

Unit

Years

150°C

125°C

Minimum Pattern Data Retention Time

20

36

Am29F400B

21505E8 November 11, 2009

D A T A S H E E T

PHYSICAL DIMENSIONS

TS 048—48-Pin Standard Thin Small Outline Package

Dwg rev AA; 10/99

November 11, 2009 21505E8

Am29F400B

37

D A T A S H E E T

PHYSICAL DIMENSIONS

SO 044—44-Pin Small Outline Package

Dwg rev AC; 10/99

38

Am29F400B

21505E8 November 11, 2009

D A T A S H E E T

REVISION SUMMARY

Revision A (August 1997)

Revision C (January 1998)

Initial release.

Global

Formatted for consistency with other 5.0 volt-only

data sheets.

Revision B (October 1997)

Global

AC Characteristics

Added -55 and -60 speed options, deleted -65 speed

option. Changed data sheet designation from Advance

Information to Preliminary.

Changed t and T

to 15 ns for -55 speed option.

FLQZ

DF

Revision C+1 (February 1998)

Connection Diagrams

Table 2, Top Boot Block Sector Address Table

Corrected pinouts on all packages: deleted A18.

Corrected the sector size for SA10 to 16 Kbytes/

8 Kwords.

Table 1, Device Bus Operations

Revised to indicate inputs for both CE# and RESET#

are required for standby mode.

DC Characteristics—TTL/NMOS Compatible

Deleted Note 4.

Sector Protection/Unprotection

Revision C+2 (April 1998)

Corrected text to indicate that these functions can only

be implemented using programming equipment.

Distinctive Characteristics

Changed minimum 100K write/erase cycles guaran-

teed to 1,000,000.

Program Command Sequence

Changed to indicate Data# Polling is active for 2 µs

after a program command sequence if the sector spec-

ified is protected.

Product Selector Guide, Ordering Information

Added 55 ns 10ꢀ speed option.

Sector Erase Command Sequence and DQ3: Sector

Erase Timer

AC Characteristics

Word/Byte Configuration: Changed t

for 55 ns device.

specification

FHQV

Corrected sector erase timeout to 50 µs.

Erase Suspend Command

Erase/Program Operations: Changed t

word

WHWH1

mode specification to 12 µs. Corrected the notes refer-

ence for t and t . These parameters are

Changed to indicate that the device suspends the

erase operation a maximum of 20 µs after the rising

edge of WE#.

WHWH1

WHWH2

100ꢀ tested. Corrected the note reference for t

This parameter is not 100ꢀ tested.

.

VCS

DC Characteristics

Changed t and t specifications for 55 ns device.

DS

CP

Changed to indicate V min and max values are 11.5

ID

to 12.5 V,with a V test condition of 5.0 V. Revised I

Alternate CE# Controlled Erase/Program Operations:

Changed t word mode specification to 12 µs.

CC

LIT

to 50 µA. Added I

specification. Added typical

CC4

WHWH1

values to TTL/NMOS table. Revised CMOS typical

standby current (I ).

Corrected the notes reference for t

These parameters are 100ꢀ tested.

and t

.

WHWH1

WHWH2

CC3

Figure 14: Chip/Sector Erase Operation Timings;

Figure 19: Alternate CE# Controlled Write

Operation TImings

Changed t and t specifications for 55 ns device.

DS

CP

Temporary Sector Unprotect Table

Added note reference for t

100ꢀ tested.

. This parameter is not

VIDR

Corrected hexadecimal values in address and data

waveforms.

Erase and Programming Performance

AC Characteristics, Erase/Program Operations

Changed minimum 100K program and erase cycles

guaranteed to 1,000,000.

Corrected t specification for -90 speed option to 45

AH

ns.

Revision C+3 (June 1998)

Erase and Programming Performance

Corrected word and chip programming times.

Distinctive Characteristics

High Performance: Changed “Access times as fast as

55 ns” to “Access times as fast as 45 ns”.

November 11, 2009 21505E8

Am29F400B

39

D A T A S H E E T

General Description

Revision D+1 (July 2, 1999)

Third paragraph: Added 45 ns to access times.

Global

Product Selector Guide

Added references to availability of device in Known

Good Die (KGD) form.

Added the -45 speed option for V = 5.0 V 5ꢀ and

CC

the -55 speed option for V = 5.0 V 10ꢀ.

CC

Revision E (November 15, 1999)

Ordering Information

AC Characteristics—Figure 13. Program

Operations Timing and Figure 14. Chip/Sector

Erase Operations

Added “Special Designation” to “Optional Processing”

heading; added “0” for 55 ns 10ꢀ VCC, deleted burn-in.

Burn-in is available by contacting an AMD representative.

Deleted t

high.

and changed OE# waveform to start at

GHWL

Added -55 10ꢀ and -45 speed options to the list of

valid combinations. Added extended temperature

ratings to -55 5ꢀ valid combinations.

Physical Dimensions

Replaced figures with more detailed illustrations.

Table 1, Device Bus Operations

Changed the BYTE#=V input for DQ8–DQ15 during

temporary sector unprotect to “don’t care” (X).

IL

Revision E+1 (November 30, 2000)

Added table of contents. Reinserted revision summa-

ries for revisions A and B.

Figure 6. Maximum Negative Undershoot

Waveform

Revision E+2 (June 4, 2004)

Corrected figure title.

Ordering Information

Table 7, Test Specifications

Added Pb-Free OPNs

Test load capacitance: Removed 55 ns speed option

from and added -45 speed option to the 30 pF.

Revision E+3 (December 22, 2005)

DC Characteristics

Global

Removed V = V

test condition for I

– I

.

CC

CC max

CC1

CC3

Deleted 150 ns speed option and reverse TSOP pack-

age from document.

V

max is only valid for max specs.

CC

AC Characteristics

Revision E4 (May 18, 2006)

Added “Not recommended for new designs” note.

AC Characteristics

Added the -45 speed option.

Revision C+4 (August 1998)

Ordering Information

Changed t

specification to maximium value.

BUSY

Added extended temperature combinations to the -55,

10ꢀ speed option.

Revision E5 (November 1, 2006)

Deleted the -60 speed option.

Deleted “Not recommended for new designs” note and

Retired Product designation.

Revision D (January 1999)

Revision E6 (March 3, 2009)

Distinctive Characteristics

Global

Added:

Added obsolescence information.

■ 20-year data retention at 125°C

— Reliable operation for the life of the system

Revision E7 (August 3, 2009)

DC Characteristics—TTL/NMOS Compatible

Global

I

, I

: Added Note 2 “Maximum I

CC1 CC2 CC3 CC

Removed obsolescence information.

specifications are tested with V = V

”.

CC

CCmax

Revision E8 (November 11, 2009)

DC Characteristics—CMOS Compatible

, I , I : Added Note 2 “Maximum I

I

Global

CC1 CC2 CC3

CC

”.

specifications are tested with V = V

CC

CCmax

Removed 120 ns speed option.

Erase and Programming Performance

Removed all commercial temperature range options.

Deleted “(4.75 V for -45 and -55xx0)” from Note 2.

40

Am29F400B

21505E8 November 11, 2009

D A T A S H E E T

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as

contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the

public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,

aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for

any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to

you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor

devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design

measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal

operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under

the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,

the prior authorization by the respective government entity will be required for export of those products.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a Spansion product under

development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this

document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,

merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any

damages of any kind arising out of the use of the information in this document.

trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks

of their respective companies.

EcoRAM™ and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries.

Other names used are for informational purposes only and may be trademarks of their respective owners.

November 11, 2009 21505E8

Am29F400B

41


型号：	AM29F400BT-45
厂家：	SPANSION
描述：	4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory 4兆位（ 512K的×8位/ 256千×16位） CMOS 5.0伏只引导扇区闪存闪存
文件：	总43页 (文件大小：862K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM29F400BT-45 [SPANSION]

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