首页 |元器件品牌

AM29F032B-90FIB [SPANSION]

暂无描述;
AM29F032B-90FIB
型号： AM29F032B-90FIB
厂家： SPANSION    SPANSION
描述：

暂无描述
文件： 总40页 (文件大小：803K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
Am29F032B  
Data Sheet  
Am29F032B Cover Sheet  
The following document contains information on Spansion memory products.  
Continuity of Specifications  
There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been  
made are the result of normal data sheet improvement and are noted in the document revision summary.  
For More Information  
Please contact your local sales office for additional information about Spansion memory solutions.  
Publication Number 21610  
Revision D  
Amendment 8  
Issue Date November 11, 2009  
D a t a S h e e t  
This page left intentionally blank.  
2
Am29F032B  
21610_D8 November 11, 2009  
DATA SHEET  
Am29F032B  
32 Megabit (4 M x 8-Bit)  
CMOS 5.0 Volt-only, Uniform Sector Flash Memory  
DISTINCTIVE CHARACTERISTICS  
■ 5.0 V 10%, single power supply operation  
■ Minimum 1,000,000 write/erase cycles  
guaranteed  
— Minimizes system level power requirements  
■ 20-year data retention at 125°C  
— Reliable operation for the life of the system  
■ Package options  
■ Manufactured on 0.32 µm process technology  
■ High performance  
— Access times as fast as 70 ns  
— 40-pin TSOP  
■ Low power consumption  
— 44-pin SO  
— 30 mA typical active read current  
— 30 mA typical program/erase current  
■ Compatible with JEDEC standards  
— Pinout and software compatible with  
single-power-supply Flash standard  
— <1 µA typical standby current (standard access  
time to active mode)  
— Superior inadvertent write protection  
■ Flexible sector architecture  
— 64 uniform sectors of 64 Kbytes each  
— Any combination of sectors can be erased.  
— Supports full chip erase  
■ Data# Polling and toggle bits  
— Provides a software method of detecting  
program or erase cycle completion  
■ Ready/Busy output (RY/BY#)  
— Group sector protection:  
— Provides a hardware method for detecting  
program or erase cycle completion  
— A hardware method of locking sector groups to  
prevent any program or erase operations within  
that sector group  
■ Erase Suspend/Resume  
— Suspends a sector erase operation to read data  
from, or program data to, a non-erasing sector,  
then resumes the erase operation  
— Temporary Sector Group Unprotect allows code  
changes in previously locked sectors  
■ Embedded Algorithms  
■ Hardware reset pin (RESET#)  
— Embedded Erase algorithm automatically  
preprograms and erases the entire chip or any  
combination of designated sectors  
— Resets internal state machine to the read mode  
— Embedded Program algorithm automatically  
writes and verifies bytes at specified addresses  
Publication# 21610 Rev: D Amendment: 8  
Issue Date: November 11, 2009  
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data  
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.  
D A T A S H E E T  
GENERAL DESCRIPTION  
The Am29F032B is a 32 Mbit, 5.0 volt-only Flash  
memory organized as 4,194,304 bytes of 8 bits each.  
The 4 Mbytes of data are divided into 64 sectors of 64  
Kbytes each for flexible erase capability. The 8 bits of  
data appear on DQ0–DQ7. The Am29F032B is offered  
in 40-pin TSOP and 44-pin SO packages. The  
Am29F032B is manufactured using AMD’s 0.32 µm  
process technology. This device is designed to be pro-  
grammed in-system with the standard system 5.0 volt  
The sector erase architecture allows memory sectors  
to be erased and reprogrammed without affecting the  
data contents of other sectors. A sector is typically  
erased and verified within one second. The device is  
erased when shipped from the factory.  
The hardware sector group protection feature disables  
both program and erase operations in any combination  
of the eight sector groups of memory. A sector group  
consists of four adjacent sectors.  
V
supply. A 12.0 volt V is not required for program  
CC  
PP  
or erase operations. The device can also be pro-  
grammed in standard EPROM programmers.  
The Erase Suspend feature enables the system to put  
erase on hold for any period of time to read data from,  
or program data to, a sector that is not being erased.  
True background erase can thus be achieved.  
The standard device offers access times of 70 and 90  
ns, allowing high-speed microprocessors to operate  
without wait states. To eliminate bus contention, the  
device has separate chip enable (CE#), write enable  
(WE#), and output enable (OE#) controls.  
The device requires only a single 5.0 volt power supply  
for both read and write functions. Internally generated  
and regulated voltages are provided for the program  
and erase operations. A low V  
detector automati-  
CC  
The device is entirely command set compatible with  
the JEDEC single-power-supply Flash standard. Com-  
mands are written to the command register using stan-  
dard microprocessor write timings. Register contents  
serve as input to an internal state machine that con-  
trols the erase and programming circuitry. Write cycles  
also internally latch addresses and data needed for  
the programming and erase operations. Reading data  
out of the device is similar to reading from 12.0 volt  
Flash or EPROM devices.  
cally inhibits write operations during power transitions.  
The host system can detect whether a program or  
erase cycle is complete by using the RY/BY# pin, the  
DQ7 (Data# Polling) or DQ6 (toggle) status bits. After  
a program or erase cycle has been completed, the de-  
vice automatically returns to the read mode.  
A hardware RESET# pin terminates any operation in  
progress. The internal state machine is reset to the  
read mode. The RESET# pin may be tied to the sys-  
tem reset circuitry. Therefore, if a system reset occurs  
during either an Embedded Program or Embedded  
Erase algorithm, the device is automatically reset to the  
read mode. This enables the system’s microprocessor  
to read the boot-up firmware from the Flash memory.  
The device is programmed by executing the program  
command sequence. This invokes the Embedded Pro-  
gram algorithm—an internal algorithm that automati-  
cally times the program pulse widths and verifies  
proper cell margin. The device is erased by executing  
the erase command sequence. This invokes the Em-  
bedded Erase algorithm—an internal algorithm that  
automatically preprograms the array (if it is not already  
programmed) before executing the erase operation.  
During erase, the device automatically times the erase  
pulse widths and verifies proper cell margin.  
AMD’s Flash technology combines years of Flash  
memory manufacturing experience to produce the  
highest levels of quality, reliability, and cost  
effectiveness. The device electrically erases all bits  
within a sector simultaneously via Fowler-Nordheim  
tunneling. The bytes are programmed one byte at  
a time using the programming mechanism of hot  
electron injection.  
2
Am29F032B  
21610D8 November 11, 2009  
D A T A S H E E T  
TABLE OF CONTENTS  
Product Selector Guide. . . . . . . . . . . . . . . . . . . . . 4  
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5  
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 7  
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 8  
Table 1. Am29F032B Device Bus Operations .................................. 8  
Requirements for Reading Array Data ..................................... 8  
Writing Commands/Command Sequences .............................. 8  
Program and Erase Operation Status ...................................... 9  
Standby Mode .......................................................................... 9  
RESET#: Hardware Reset Pin ................................................. 9  
Output Disable Mode................................................................ 9  
Table 2. Am29F032B Sector Address Table................................... 10  
Autoselect Mode..................................................................... 11  
Table 3. Am29F032B Autoselect Codes......................................... 11  
Sector Group Protection/Unprotection.................................... 12  
Table 4. Sector Group Addresses................................................... 12  
Temporary Sector Group Unprotect ....................................... 12  
Figure 1. Temporary Sector Group Unprotect Operation................ 12  
Hardware Data Protection ...................................................... 13  
Low VCC Write Inhibit..................................................................... 13  
Write Pulse “Glitch” Protection........................................................ 13  
Logical Inhibit .................................................................................. 13  
Power-Up Write Inhibit .................................................................... 13  
Command Definitions . . . . . . . . . . . . . . . . . . . . . 13  
Reading Array Data................................................................ 13  
Reset Command..................................................................... 13  
Autoselect Command Sequence............................................ 14  
Byte Program Command Sequence....................................... 14  
Chip Erase Command Sequence........................................... 14  
Figure 2. Program Operation .......................................................... 15  
Sector Erase Command Sequence........................................ 15  
Erase Suspend/Erase Resume Commands........................... 15  
Figure 3. Erase Operation............................................................... 16  
Table 5. Am29F032B Command Definitions................................... 17  
Write Operation Status . . . . . . . . . . . . . . . . . . . . 18  
DQ7: Data# Polling................................................................. 18  
Figure 4. Data# Polling Algorithm ................................................... 18  
DQ6: Toggle Bit I.................................................................... 19  
DQ2: Toggle Bit II................................................................... 19  
Reading Toggle Bits DQ6/DQ2............................................... 19  
DQ5: Exceeded Timing Limits ................................................ 20  
DQ3: Sector Erase Timer ....................................................... 20  
Figure 5. Toggle Bit Algorithm........................................................ 20  
Table 6. Write Operation Status..................................................... 21  
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 22  
Figure 6. Maximum Negative Overshoot Waveform ...................... 22  
Figure 7. Maximum Positive Overshoot Waveform........................ 22  
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 22  
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23  
TTL/NMOS Compatible .......................................................... 23  
CMOS Compatible.................................................................. 23  
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Figure 8. Test Setup...................................................................... 24  
Table 7. Test Specifications........................................................... 24  
Key To Switching Waveforms . . . . . . . . . . . . . . . 24  
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25  
Read-only Operations............................................................. 25  
Figure 9. Read Operation Timings................................................. 25  
Hardware Reset (RESET#) .................................................... 26  
Figure 10. RESET# Timings .......................................................... 26  
Write (Erase/Program) Operations ......................................... 27  
Figure 11. Program Operation Timings.......................................... 28  
Figure 12. Chip/Sector Erase Operation Timings .......................... 29  
Figure 13. Data# Polling Timings (During Embedded Algorithms). 30  
Figure 14. Toggle Bit Timings (During Embedded Algorithms)...... 30  
Figure 15. DQ2 vs. DQ6................................................................. 31  
Temporary Sector Unprotect .................................................. 31  
Figure 16. Temporary Sector Group Unprotect Timings................ 31  
Write (Erase/Program) Operations—Alternate CE#  
Controlled Writes.................................................................... 32  
Figure 17. Alternate CE# Controlled Write Operation Timings ...... 33  
Erase And Programming Performance . . . . . . . 34  
Latchup Characteristic . . . . . . . . . . . . . . . . . . . . 34  
TSOP And SO Pin Capacitance . . . . . . . . . . . . . 34  
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 35  
SO 044–44-Pin Small Outline Package.................................. 35  
TS 040–40-Pin Standard Thin Small Outline Package........... 36  
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 37  
November 11, 2009 21610D8  
Am29F032B  
3
D A T A S H E E T  
PRODUCT SELECTOR GUIDE  
Family Part Number  
Am29F032B  
VCC = 5.0 V ± 5%  
VCC = 5.0 V ± 10%  
-75  
Speed Options  
-90  
90  
90  
40  
Max access time, ns (tACC  
)
70  
70  
40  
Max CE# access time, ns (tCE  
)
Max OE# access time, ns (tOE  
)
Note: See “AC Characteristics” for full specifications.  
BLOCK DIAGRAM  
DQ0–DQ7  
Sector Switches  
VCC  
VSS  
Erase Voltage  
Generator  
Input/Output  
Buffers  
RY/BY#  
RESET#  
State  
Control  
WE#  
Command  
Register  
PGM Voltage  
Generator  
Data  
Latch  
Chip Enable  
Output Enable  
STB  
CE#  
OE#  
Y-Decoder  
Y-Gating  
STB  
VCC Detector  
Timer  
Cell Matrix  
X-Decoder  
A0–A21  
4
Am29F032B  
21610D8 November 11, 2009  
D A T A S H E E T  
CONNECTION DIAGRAMS  
A19  
A18  
A17  
A16  
A15  
A14  
A13  
A12  
CE#  
VCC  
NC  
1
2
3
4
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
A20  
A21  
WE#  
OE#  
RY/BY#  
DQ7  
DQ6  
DQ5  
DQ4  
VCC  
5
6
7
8
9
40-Pin Standard TSOP  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
VSS  
RESET#  
A11  
A10  
A9  
VSS  
DQ3  
DQ2  
DQ1  
DQ0  
A0  
A8  
A7  
A6  
A1  
A5  
A2  
A4  
A3  
NC  
RESET#  
A11  
A10  
A9  
1
2
3
4
5
6
7
8
9
44 VCC  
43 CE#  
42 A12  
41 A13  
40 A14  
39 A15  
38 A16  
37 A17  
36 A18  
35 A19  
34 NC  
A8  
A7  
A6  
A5  
A4 10  
NC 11  
NC 12  
A3 13  
SO  
33 NC  
32 A20  
31 A21  
30 WE#  
29 OE#  
28 RY/BY#  
27 DQ7  
26 DQ6  
25 DQ5  
24 DQ4  
23 VCC  
A2 14  
A1 15  
A0 16  
DQ0 17  
DQ1 18  
DQ2 19  
DQ3 20  
VSS 21  
VSS 22  
November 11, 2009 21610D8  
Am29F032B  
5
D A T A S H E E T  
PIN CONFIGURATION  
LOGIC SYMBOL  
A0–A21  
=
22 Addresses  
22  
DQ0–DQ7 = 8 Data Inputs/Outputs  
A0–A21  
8
CE#  
=
=
=
=
=
=
Chip Enable  
DQ0–DQ7  
WE#  
Write Enable  
OE#  
Output Enable  
CE#  
OE#  
RESET#  
RY/BY#  
Hardware Reset Pin, Active Low  
Ready/Busy Output  
WE#  
V
+5.0 V single power supply  
(see Product Selector Guide for  
device speed ratings and voltage  
supply tolerances)  
CC  
RESET#  
RY/BY#  
V
=
=
Device Ground  
SS  
NC  
Pin Not Connected Internally  
6
Am29F032B  
21610D8 November 11, 2009  
D A T A S H E E T  
ORDERING INFORMATION  
Standard Products  
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is  
formed by a combination of the following:  
Am29F032B -75  
E
F
TEMPERATURE RANGE  
I
=
=
=
=
Industrial (–40° C to +85°C)  
E
F
K
Extended (–55°C to +125° C)  
Industrial (–40° C to +85°C) with Pb-free Package  
Extended (–55°C to +125° C) with Pb-free Package  
PACKAGE TYPE  
E
S
=
=
40-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 040)  
44-Pin Small Outline Package (SO 044)  
SPEED OPTION  
See Product Selector Guide and Valid Combinations  
DEVICE NUMBER/DESCRIPTION  
Am29F032B  
32 Megabit (4 M x 8-Bit) CMOS 5.0 Volt-only Sector Erase Flash Memory  
5.0 V Read, Program, and Erase  
Valid Combinations  
Valid Combinations  
Valid Combinations list configurations planned to be support-  
ed in volume for this device. Consult the local AMD sales of-  
fice to confirm availability of specific valid combinations and  
to check on newly released combinations.  
EI, EF,  
SI, SF  
AM29F032B-75  
AM29F032B-90  
EI, EE, EF, EK  
SI, SE, SF, SK  
November 11, 2009 21610D8  
Am29F032B  
7
D A T A S H E E T  
DEVICE BUS OPERATIONS  
This section describes the requirements and use of the  
device bus operations, which are initiated through the  
internal command register. The command register it-  
self does not occupy any addressable memory loca-  
tion. The register is composed of latches that store the  
commands, along with the address and data informa-  
tion needed to execute the command. The contents of  
the register serve as inputs to the internal state ma-  
chine. The state machine outputs dictate the function of  
the device. The appropriate device bus operations  
table lists the inputs and control levels required, and the  
resulting output. The following subsections describe  
each of these operations in further detail.  
Table 1. Am29F032B Device Bus Operations  
Operation  
CE#  
OE#  
L
WE#  
H
RESET#  
A0–A21  
DQ0–DQ7  
DOUT  
Read  
Write  
L
H
AIN  
AIN  
X
L
H
L
H
DIN  
CMOS Standby  
TTL Standby  
VCC 0.5 V  
X
X
VCC 0.5 V  
High-Z  
High-Z  
High-Z  
High-Z  
H
L
X
X
H
H
L
X
Output Disable  
Hardware Reset  
H
H
X
X
X
X
X
Temporary Sector Unprotect  
(See Note)  
X
X
X
VID  
AIN  
DIN  
Legend:  
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± ± 0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In  
Note: See the sections Sector Group Protection and Temporary Sector Unprotect for more information.  
sectors of memory), the system must drive WE# and  
Requirements for Reading Array Data  
To read array data from the outputs, the system must  
CE# to V , and OE# to V .  
IL  
IH  
drive the CE# and OE# pins to V . CE# is the power  
control and selects the device. OE# is the output con-  
trol and gates array data to the output pins. WE#  
An erase operation can erase one sector, multiple sec-  
tors, or the entire device. The Sector Address Tables  
indicate the address space that each sector occupies.  
A “sector address” consists of the address bits re-  
quired to uniquely select a sector. See the “Writing  
specific address and data commands or sequences  
into the command register initiates device operations.  
The Command Definitions table defines the valid reg-  
ister command sequences. Writing incorrect address  
and data values or writing them in the improper se-  
quence resets the device to reading array data.” sec-  
tion for details on erasing a sector or the entire chip, or  
suspending/resuming the erase operation.  
IL  
should remain at V .  
IH  
The internal state machine is set for reading array data  
upon device power-up, or after a hardware reset. This  
ensures that no spurious alteration of the memory  
content occurs during the power transition. No com-  
mand is necessary in this mode to obtain array data.  
Standard microprocessor read cycles that assert valid  
addresses on the device address inputs produce valid  
data on the device data outputs. The device remains  
enabled for read access until the command register  
contents are altered.  
After the system writes the autoselect command se-  
quence, the device enters the autoselect mode. The  
system can then read autoselect codes from the inter-  
nal register (which is separate from the memory array)  
on DQ7–DQ0. Standard read cycle timings apply in  
this mode. Refer to the “Autoselect Mode” on page 11  
and “Autoselect Command Sequence” on page 14  
sections for more information.  
See “Reading Array Data” on page 13 for more infor-  
mation. Refer to the AC Read Operations table for tim-  
ing specifications and to Figure 9, on page 25 for the  
timing waveforms. I  
in the DC Characteristics table  
CC1  
represents the active current specification for reading  
array data.  
Writing Commands/Command Sequences  
To write a command or command sequence (which in-  
cludes programming data to the device and erasing  
I
in the “DC Characteristics” on page 23 table rep-  
CC2  
resents the active current specification for the write  
mode. The ““AC Characteristics” on page 25 section  
8
Am29F032B  
21610D8 November 11, 2009  
D A T A S H E E T  
contains timing specification tables and timing dia-  
grams for write operations.  
RESET#: Hardware Reset Pin  
The RESET# pin provides a hardware method of reset-  
ting the device to reading array data. When the system  
Program and Erase Operation Status  
drives the RESET# pin low for at least a period of t ,  
RP  
During an erase or program operation, the system  
may check the status of the operation by reading the  
status bits on DQ7–DQ0. Standard read cycle timings  
the device immediately terminates any operation in  
progress, tristates all data output pins, and ignores all  
read/write attempts for the duration of the RESET#  
pulse. The device also resets the internal state ma-  
chine to reading array data. The operation that was in-  
terrupted should be reinitiated once the device is ready  
to accept another command sequence, to ensure data  
integrity.  
and I read specifications apply. The Erase Resume  
CC  
command is valid only during the Erase Suspend  
mode.Refer to “Erase Suspend/Erase Resume Com-  
mands” on page 15 for more information, and to each  
“AC Characteristics” on page 25 section for timing dia-  
grams.  
Current is reduced for the duration of the RESET#  
pulse. When RESET# is held at V , the device enters  
IL  
Standby Mode  
the TTL standby mode; if RESET# is held at V  
SS  
When the system is not reading or writing to the device,  
it can place the device in the standby mode. In this  
mode, current consumption is greatly reduced, and the  
outputs are placed in the high impedance state, inde-  
pendent of the OE# input.  
0.5 V, the device enters the CMOS standby mode.  
The RESET# pin may be tied to the system reset cir-  
cuitry. A system reset would thus also reset the Flash  
memory, enabling the system to read the boot-up firm-  
ware from the Flash memory.  
The device enters the CMOS standby mode when CE#  
If RESET# is asserted during a program or erase oper-  
ation, the RY/BY# pin remains a “0” (busy) until the in-  
ternal reset operation is complete, which requires a  
and RESET# pins are both held at V  
that this is a more restricted voltage range than V .)  
The device enters the TTL standby mode when CE#  
0.5 V. (Note  
CC  
IH  
time of t  
(during Embedded Algorithms). The  
and RESET# pins are both held at V . The device re-  
READY  
IH  
system can thus monitor RY/BY# to determine whether  
the reset operation is complete. If RESET# is asserted  
when a program or erase operation is not executing  
(RY/BY# pin is “1”), the reset operation is completed  
quires standard access time (t ) for read access when  
the device is in either of these standby modes, before it  
is ready to read data.  
CE  
The device also enters the standby mode when the RE-  
SET# pin is driven low. Refer to the next section, “RE-  
SET#: Hardware Reset Pin”.  
within a time of t  
(not during Embedded Algo-  
READY  
rithms). The system can read data t  
after the RE-  
RH  
SET# pin returns to V .  
IH  
If the device is deselected during erasure or program-  
ming, the device draws active current until the  
operation is completed.  
Refer to the “AC Characteristics” on page 25 tables for  
RESET# parameters and timing diagram.  
Output Disable Mode  
I
in DC Characteristics tables, represents the  
CC3  
standby current specification.  
When the OE# input is at V , output from the device is  
IH  
disabled. The output pins are placed in the high imped-  
ance state.  
November 11, 2009 21610D8  
Am29F032B  
9
D A T A S H E E T  
Table 2. Am29F032B Sector Address Table (Sheet 1 of 2)  
Sector  
SA0  
A21  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
A20  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
A19  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
A18  
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
A17  
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A16  
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Sector Size  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
Address Range  
000000h–00FFFFh  
010000h–01FFFFh  
020000h–02FFFFh  
030000h–03FFFFh  
040000h–04FFFFh  
050000h–05FFFFh  
060000h–06FFFFh  
070000h–07FFFFh  
080000h–08FFFFh  
090000h–09FFFFh  
0A0000h–0AFFFFh  
0B0000h–0BFFFFh  
0C0000h–0CFFFFh  
0D0000h–0DFFFFh  
0E0000h–0EFFFFh  
0F0000h–0FFFFFh  
100000h–10FFFFh  
110000h–11FFFFh  
120000h–12FFFFh  
130000h–13FFFFh  
140000h–14FFFFh  
150000h–15FFFFh  
160000h–16FFFFh  
170000h–17FFFFh  
180000h–18FFFFh  
190000h–19FFFFh  
1A0000h–1AFFFFh  
1B0000h–1BFFFFh  
1C0000h–1CFFFFh  
1D0000h–1DFFFFh  
1E0000h–1EFFFFh  
1F0000h–1FFFFFh  
200000h–20FFFFh  
210000h–21FFFFh  
220000h–22FFFFh  
230000h–23FFFFh  
240000h–24FFFFh  
250000h–25FFFFh  
260000h–26FFFFh  
270000h–27FFFFh  
280000h–28FFFFh  
290000h–29FFFFh  
2A0000h–2AFFFFh  
2B0000h–2BFFFFh  
SA1  
SA2  
SA3  
SA4  
SA5  
SA6  
SA7  
SA8  
SA9  
SA10  
SA11  
SA12  
SA13  
SA14  
SA15  
SA16  
SA17  
SA18  
SA19  
SA20  
SA21  
SA22  
SA23  
SA24  
SA25  
SA26  
SA27  
SA28  
SA29  
SA30  
SA31  
SA32  
SA33  
SA34  
SA35  
SA36  
SA37  
SA38  
SA39  
SA40  
SA41  
SA42  
SA43  
10  
Am29F032B  
21610D8 November 11, 2009  
D A T A S H E E T  
Table 2. Am29F032B Sector Address Table (Sheet 2 of 2)  
Sector  
SA44  
SA45  
SA46  
SA47  
SA48  
SA49  
SA50  
SA51  
SA52  
SA53  
SA54  
SA55  
SA56  
SA57  
SA58  
SA59  
SA60  
SA61  
SA62  
SA63  
A21  
1
A20  
0
A19  
1
A18  
1
A17  
0
A16  
0
Sector Size  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
Address Range  
2C0000h–2CFFFFh  
2D0000h–2DFFFFh  
2E0000h–2EFFFFh  
2F0000h–2FFFFFh  
300000h–30FFFFh  
310000h–31FFFFh  
320000h–32FFFFh  
330000h–33FFFFh  
340000h–34FFFFh  
350000h–35FFFFh  
360000h–36FFFFh  
370000h–37FFFFh  
380000h–38FFFFh  
390000h–39FFFFh  
3A0000h–3AFFFFh  
3B0000h–3BFFFFh  
3C0000h–3CFFFFh  
3D0000h–3DFFFFh  
3E0000h–3EFFFFh  
3F0000h–3FFFFFh  
1
0
1
1
0
1
1
0
1
1
1
0
1
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
1
1
1
0
0
1
0
1
1
0
0
1
1
1
1
0
1
0
0
1
1
0
1
0
1
1
1
0
1
1
0
1
1
0
1
1
1
1
1
1
0
0
0
1
1
1
0
0
1
1
1
1
0
1
0
1
1
1
0
1
1
1
1
1
1
0
0
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
Note: All sectors are 64 Kbytes in size.  
tection, the sector group address must appear on the  
appropriate highest order address bits (see Table 4 on  
page 12). Table 3 also shows the remaining address  
bits that are don’t care. When all necessary bits have  
been set as required, the programming equipment  
may then read the corresponding identifier code on  
DQ7-DQ0.  
Autoselect Mode  
The autoselect mode provides manufacturer and de-  
vice identification, and sector group protection verifica-  
tion, through identifier codes output on DQ7–DQ0.  
This mode is primarily intended for programming  
equipment to automatically match a device to be pro-  
grammed with its corresponding programming algo-  
rithm. However, the autoselect codes can also be  
accessed in-system through the command register.  
To access the autoselect codes in-system, the host  
system can issue the autoselect command via the  
command register, as shown in Table 5 on page 17.  
When using programming equipment, the autoselect  
This method does not require V on an address line.  
ID  
mode requires V (11.5 V to 12.5 V) on address pin  
ID  
Refer to the Autoselect Command Sequence section  
for more information.  
A9. Address pins A6, A1, and A0 must be as shown in  
Table 3. In addition, when verifying sector group pro-  
Table 3. Am29F032B Autoselect Codes  
Identifier Code on  
DQ7-DQ0  
Description  
A21-A18 A17-A10 A9 A8-A7 A6 A5-A2 A1  
A0  
VIL  
VIH  
Manufacturer ID: AMD  
Device ID: Am29F032B  
X
X
X
X
VID  
VID  
X
X
VIL  
VIL  
X
X
VIL  
VIL  
01h  
41h  
Sector  
Group  
Address  
01h (protected)  
Sector Group Protection  
Verification  
X
VID  
X
VIL  
X
VIH  
VIL  
00h (unprotected)  
Note: Identifier codes for manufacturer and device IDs exhibit odd parity with DQ7 defined as the parity bit.  
November 11, 2009 21610D8  
Am29F032B  
11  
D A T A S H E E T  
Sector Group Protection/Unprotection  
Temporary Sector Group Unprotect  
The hardware sector group protection feature disables  
both program and erase operations in any sector  
group. Each sector group consists of four adjacent  
sectors. Table 4 shows how the sectors are grouped,  
and the address range that each sector group con-  
tains. The hardware sector group unprotection feature  
re-enables both program and erase operations in pre-  
viously protected sector groups.  
This feature allows temporary unprotection of previ-  
ously protected sector groups to change data in-sys-  
tem. The Sector Group Unprotect mode is activated by  
setting the RESET# pin to V (11.5 V – 12.5 V). Dur-  
ID  
ing this mode, formerly protected sector groups can be  
programmed or erased by selecting the sector group  
addresses. Once V is removed from the RESET#  
ID  
pin, all the previously protected sector groups are  
protected again. Figure 1 shows the algorithm, and  
Figure 16 shows the timing diagrams, for this feature.  
Sector group protection/unprotection must be imple-  
mented using programming equipment. The proce-  
dure requires a high voltage (V ) on address pin A9  
ID  
and the control pins. Details on this method are pro-  
vided in a supplement, publication number 22184.  
Contact an AMD representative to obtain a copy of the  
appropriate document.  
START  
RESET# = VID  
(Note 1)  
The device is shipped with all sector groups unpro-  
tected. AMD offers the option of programming and pro-  
tecting sector groups at its factory prior to shipping the  
device through AMD’s ExpressFlash™ Service. Con-  
tact an AMD representative for details.  
Perform Erase or  
Program Operations  
It is possible to determine whether a sector group is  
protected or unprotected. See “Autoselect Mode” on  
page 11 for details.  
RESET# = VIH  
Temporary Sector Group  
Unprotect Completed  
(Note 2)  
Table 4. Sector Group Addresses  
Sector  
Group  
SGA0  
SGA1  
SGA2  
SGA3  
SGA4  
SGA5  
SGA6  
SGA7  
SGA8  
SGA9  
SGA10  
SGA11  
SGA12  
SGA13  
SGA14  
SGA15  
A21  
A20  
A19  
A18  
Sectors  
0
0
0
0
SA0–SA3  
0
0
0
1
SA4–SA7  
Notes:  
0
0
1
0
SA8–SA11  
SA12–SA15  
SA16–SA19  
SA20–SA23  
SA24–SA27  
SA28–SA31  
SA32–SA35  
SA36–SA39  
SA40–SA43  
SA44–SA47  
SA48–SA51  
SA52–SA55  
SA56–SA59  
SA60–SA63  
1. All protected sector groups unprotected.  
0
0
1
1
2. All previously protected sector groups are protected  
once again.  
0
1
0
0
0
1
0
1
Figure 1. Temporary Sector Group Unprotect  
Operation  
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
12  
Am29F032B  
21610D8 November 11, 2009  
D A T A S H E E T  
than V  
. The system must ensure that the control  
Hardware Data Protection  
LKO  
pins are logically correct to prevent unintentional  
writes when V is above V  
The command sequence requirement of unlock cycles  
for programming or erasing provides data protection.  
In addition, the following hardware data protection  
measures prevent accidental erasure or programming,  
which might otherwise be caused by spurious system  
.
LKO  
CC  
Write Pulse “Glitch” Protection  
Noise pulses of less than 5 ns (typical) on OE#, CE#  
or WE# do not initiate a write cycle.  
level signals during V  
power-up and power-down  
CC  
Logical Inhibit  
transitions, or from system noise.  
Write cycles are inhibited by holding any one of OE# =  
Low V Write Inhibit  
CC  
V , CE# = V or WE# = V . To initiate a write cycle,  
IL  
IH  
IH  
When V  
is less than V  
(see DC Characteristics  
LKO  
CC  
CE# and WE# must be at V while OE# is at V .  
IL  
IH  
for voltage levels), the device does not accept any  
write cycles. This protects data during V power-up  
and power-down. The command register and all inter-  
nal program/erase circuits are disabled. Under this  
condition the device resets to the read mode. Subse-  
Power-Up Write Inhibit  
If WE# = CE# = V and OE# = V during power up,  
CC  
IL  
IH  
the device does not accept commands on the rising  
edge of WE#. The internal state machine is automati-  
cally reset to the read mode on power-up.  
quent writes are ignored until the V  
level is greater  
CC  
COMMAND DEFINITIONS  
Writing specific address and data commands or se-  
quences into the command register initiates device op-  
erations. The Command Definitions table defines the  
valid register command sequences. Writing incorrect  
address and data values or writing them in the im-  
proper sequence resets the device to reading array  
data.  
See also “Requirements for Reading Array Data” in  
the “Device Bus Operations” section for more informa-  
tion. The Read Operations table provides the read pa-  
rameters, and Read Operation Timings diagram  
shows the timing diagram.  
Reset Command  
Writing the reset command to the device resets the  
device to reading array data. Address bits are don’t  
care for this command.  
All addresses are latched on the falling edge of WE# or  
CE#, whichever happens later. All data is latched on  
the rising edge of WE# or CE#, whichever happens  
first. Refer to the appropriate timing diagrams in “AC  
Characteristics” on page 25.  
The reset command may be written between the se-  
quence cycles in an erase command sequence before  
erasing begins. This resets the device to reading array  
data. Once erasure begins, however, the device ig-  
nores reset commands until the operation is complete.  
Reading Array Data  
The device is automatically set to reading array data  
after device power-up. No commands are required to  
retrieve data. The device is also ready to read array  
data after completing an Embedded Program or Em-  
bedded Erase algorithm.  
The reset command may be written between the se-  
quence cycles in a program command sequence be-  
fore programming begins. This resets the device to  
reading array data (also applies to programming in  
Erase Suspend mode). Once programming begins,  
however, the device ignores reset commands until the  
operation is complete.  
After the device accepts an Erase Suspend command,  
the device enters the Erase Suspend mode. The sys-  
tem can read array data using the standard read tim-  
ings, except that if it reads at an address within erase-  
suspended sectors, the device outputs status data.  
After completing a programming operation in the  
Erase Suspend mode, the system may once again  
read array data with the same exception. See “Erase  
Suspend/Erase Resume Commands” on page 15 for  
more information on this mode.  
The reset command may be written between the se-  
quence cycles in an autoselect command sequence.  
Once in the autoselect mode, the reset command  
must be written to return to reading array data (also  
applies to autoselect during Erase Suspend).  
If DQ5 goes high during a program or erase operation,  
writing the reset command returns the device to read-  
ing array data (also applies during Erase Suspend).  
The system must issue the reset command to re-en-  
able the device for reading array data if DQ5 goes  
high, or while in the autoselect mode. See “Reset  
Command”, next.  
November 11, 2009 21610D8  
Am29F032B  
13  
D A T A S H E E T  
hardware reset immediately terminates the program-  
Autoselect Command Sequence  
ming operation. The program command sequence  
should be reinitiated once the device has reset to read-  
ing array data, to ensure data integrity.  
The autoselect command sequence allows the host  
system to access the manufacturer and devices codes,  
and determine whether or not a sector is protected.  
The Command Definitions table shows the address  
and data requirements. This method is an alternative to  
that shown in the Autoselect Codes (High Voltage  
Method) table, which is intended for PROM program-  
Programming is allowed in any sequence and across  
sector boundaries. A bit cannot be programmed  
from a “0” back to a “1”. Attempting to do so may  
halt the operation and set DQ5 to “1”, or cause the  
Data# Polling algorithm to indicate the operation was  
successful. However, a succeeding read will show that  
the data is still “0”. Only erase operations can convert  
a “0” to a “1”.  
mers and requires V on address bit A9.  
ID  
The autoselect command sequence is initiated by  
writing two unlock cycles, followed by the autoselect  
command. The device then enters the autoselect  
mode, and the system may read at any address any  
number of times, without initiating another command  
sequence.  
Chip Erase Command Sequence  
Chip erase is a six-bus-cycle operation. The chip erase  
command sequence is initiated by writing two unlock  
cycles, followed by a set-up command. Two additional  
unlock write cycles are then followed by the chip erase  
command, which in turn invokes the Embedded Erase  
algorithm. The device does not require the system to  
preprogram prior to erase. The Embedded Erase algo-  
rithm automatically preprograms and verifies the entire  
memory for an all zero data pattern prior to electrical  
erase. The system is not required to provide any con-  
trols or timings during these operations. Table 5 on  
page 17 shows the address and data requirements for  
the chip erase command sequence.  
A read cycle at address XX00h retrieves the manufac-  
turer code. A read cycle at address XX01h returns the  
device code. A read cycle containing a sector address  
(SA) and the address 02h in returns 01h if that sector  
is protected, or 00h if it is unprotected. Refer to  
Table 2 on page 10 for valid sector addresses.  
The system must write the reset command to exit the  
autoselect mode and return to reading array data.  
Byte Program Command Sequence  
Programming is a four-bus-cycle operation. The pro-  
gram command sequence is initiated by writing two un-  
lock write cycles, followed by the program set-up  
command. The program address and data are written  
next, which in turn initiate the Embedded Program al-  
gorithm. The system is not required to provide further  
controls or timings. The device automatically provides  
internally generated program pulses and verify the pro-  
grammed cell margin. Table 5 on page 17 shows the  
address and data requirements for the byte program  
command sequence.  
Any commands written to the chip during the Embed-  
ded Erase algorithm are ignored. Note that a hardware  
reset during the chip erase operation immediately ter-  
minates the operation. The Chip Erase command se-  
quence should be reinitiated once the device has  
returned to reading array data, to ensure data integrity.  
The system can determine the status of the erase  
operation by using DQ7, DQ6, DQ2, or RY/BY#. The  
Erase Resume command is valid only during the  
Erase Suspend mode. See “Erase Suspend/Erase  
Resume Commands” on page 15 for information on  
these status bits. When the Embedded Erase algo-  
rithm is complete, the device returns to reading  
array data and addresses are no longer latched.  
When the Embedded Program algorithm is complete,  
the device then returns to reading array data and ad-  
dresses are no longer latched. The system can deter-  
mine the status of the program operation by using DQ7,  
DQ6, or RY/BY#. See Table 6 on page 21 for informa-  
tion on these status bits.  
Figure 3, on page 16 illustrates the algorithm for the  
erase operation. See Figure 3, on page 16 for parame-  
ters, and to the Figure 12, on page 29 for timing wave-  
forms.  
Any commands written to the device during the Em-  
bedded Program Algorithm are ignored. Note that a  
14  
Am29F032B  
21610D8 November 11, 2009  
D A T A S H E E T  
otherwise the last address and command might not be  
accepted, and erasure may begin. It is recommended  
that processor interrupts be disabled during this time to  
ensure all commands are accepted. The interrupts can  
be re-enabled after the last Sector Erase command is  
written. If the time between additional sector erase  
commands can be assumed to be less than 50 µs, the  
system need not monitor DQ3. Any command other  
than Sector Erase or Erase Suspend during the  
time-out period resets the device to reading array  
data. The system must rewrite the command sequence  
and any additional sector addresses and commands.  
START  
Write Program  
Command Sequence  
Data Poll  
from System  
Embedded  
Program  
algorithm  
in progress  
The system can monitor DQ3 to determine if the sector  
erase timer has timed out. (See “DQ3: Sector Erase  
Timer” on page 20.) The time-out begins from the rising  
edge of the final WE# pulse in the command sequence.  
Verify Data?  
Yes  
No  
Once the sector erase operation has begun, only the  
Erase Suspend command is valid. All other commands  
are ignored. Note that a hardware reset during the  
sector erase operation immediately terminates the op-  
eration. The Sector Erase command sequence should  
be reinitiated once the device has returned to reading  
array data, to ensure data integrity.  
No  
Increment Address  
Last Address?  
Yes  
When the Embedded Erase algorithm is complete, the  
device returns to reading array data and addresses are  
no longer latched. The system can determine the sta-  
tus of the erase operation by using DQ7, DQ6, DQ2, or  
RY/BY#. The Erase Resume command is valid only  
during the Erase Suspend mode. See “Erase Sus-  
pend/Erase Resume Commands” on page 15for infor-  
mation on these status bits.  
Programming  
Completed  
Note: See Table 5 for program command sequence.  
Figure 2. Program Operation  
Figure 3, on page 16 illustrates the algorithm for the  
erase operation. See Figure 3, on page 16 for parame-  
ters, and to the Figure 12, on page 29 for timing wave-  
forms.  
Sector Erase Command Sequence  
Sector erase is a six bus cycle operation. The sector  
erase command sequence is initiated by writing two un-  
lock cycles, followed by a set-up command. Two addi-  
tional unlock write cycles are then followed by the  
address of the sector to be erased, and the sector  
erase command. Table 5 on page 17 shows the ad-  
dress and data requirements for the sector erase com-  
mand sequence.  
Erase Suspend/Erase Resume Commands  
The Erase Suspend command allows the system to in-  
terrupt a sector erase operation and then read data  
from, or program data to, any sector not selected for  
erasure. This command is valid only during the sector  
erase operation, including the 50 µs time-out period  
during the sector erase command sequence. The  
Erase Suspend command is ignored if written during  
the chip erase operation or Embedded Program algo-  
rithm. Writing the Erase Suspend command during the  
Sector Erase time-out immediately terminates the  
time-out period and suspends the erase operation. Ad-  
dresses are “don’t-cares” when writing the Erase Sus-  
pend command.  
The device does not require the system to preprogram  
the memory prior to erase. The Embedded Erase algo-  
rithm automatically programs and verifies the sector for  
an all zero data pattern prior to electrical erase. The  
system is not required to provide any controls or tim-  
ings during these operations.  
After the command sequence is written, a sector erase  
time-out of 50 µs begins. During the time-out period,  
additional sector addresses and sector erase com-  
mands may be written. Loading the sector erase buffer  
may be done in any sequence, and the number of sec-  
tors may be from one sector to all sectors. The time be-  
tween these additional cycles must be less than 50 µs,  
When the Erase Suspend command is written during a  
sector erase operation, the device requires a maximum  
of 20 µs to suspend the erase operation. However,  
when the Erase Suspend command is written during  
the sector erase time-out, the device immediately ter-  
November 11, 2009 21610D8  
Am29F032B  
15  
D A T A S H E E T  
minates the time-out period and suspends the erase  
operation.  
writes of the Resume command are ignored. Another  
Erase Suspend command can be written after the de-  
vice has resumed erasing.  
After the erase operation has been suspended, the  
system can read array data from or program data to  
any sector not selected for erasure. (The device “erase  
suspends” all sectors selected for erasure.) Normal  
read and write timings and command definitions apply.  
Reading at any address within erase-suspended sec-  
tors produces status data on DQ7–DQ0. The system  
can use DQ7, or DQ6 and DQ2 together, to determine  
if a sector is actively erasing or is erase-suspended.  
The Erase Resume command is valid only during the  
Erase Suspend mode. See “Erase Suspend/Erase Re-  
sume Commands” on page 15 for information on these  
status bits.  
START  
Write Erase  
Command Sequence  
Data Poll  
from System  
Embedded  
Erase  
algorithm  
in progress  
After an erase-suspended program operation is com-  
plete, the system can once again read array data within  
non-suspended sectors. The system can determine  
the status of the program operation using the DQ7 or  
DQ6 status bits, just as in the standard program oper-  
ation. See “Erase Suspend/Erase Resume Com-  
mands” on page 15 for more information.  
No  
Data = FFh?  
Yes  
The system may also write the autoselect command  
sequence when the device is in the Erase Suspend  
mode. The device allows reading autoselect codes  
even at addresses within erasing sectors, since the  
codes are not stored in the memory array. When the  
device exits the autoselect mode, the device reverts to  
the Erase Suspend mode, and is ready for another  
valid operation. See “Autoselect Command Sequence”  
on page 14 for more information.  
Erasure Completed  
Notes:  
1. See the appropriate Command Definitions table for erase  
command sequence.  
2. See “DQ3: Sector Erase Timer” for more information.  
The system must write the Erase Resume command  
(address bits are “don’t care”) to exit the erase suspend  
mode and continue the sector erase operation. Further  
Figure 3. Erase Operation  
16  
Am29F032B  
21610D8 November 11, 2009  
D A T A S H E E T  
Command Definitions  
Table 5. Am29F032B Command Definitions  
Bus Cycles (Notes 2–4)  
Command  
Sequence  
(Note 1)  
First  
Second  
Third  
Addr  
Fourth  
Fifth  
Sixth  
Addr Data Addr Data  
Data Addr Data Addr Data Addr Data  
Read (Note 5)  
Reset (Note 6)  
Manufacturer ID  
1
1
4
4
RA  
XXX  
555  
555  
RD  
F0  
AA  
AA  
2AA  
2AA  
55  
55  
555  
555  
90  
90  
X00  
X01  
01  
41  
Autoselect  
Device ID  
(Note 7)  
XX00  
XX01  
PD  
Sector Group Protect  
Verify (Note 8)  
SGA  
X02  
4
555  
AA  
2AA  
55  
555  
90  
Program  
4
6
6
1
1
555  
555  
555  
XXX  
XXX  
AA  
AA  
AA  
B0  
30  
2AA  
2AA  
2AA  
55  
55  
55  
555  
555  
555  
A0  
80  
80  
PA  
555  
555  
Chip Erase  
AA  
2AA  
2AA  
55  
55  
555  
SA  
10  
30  
Sector Erase  
AA  
Erase Suspend (Note 9)  
Erase Resume (Note 10)  
Legend:  
X = Don’t care  
PD = Data to be programmed at location PA. Data latches on  
the rising edge of WE# or CE# pulse, whichever happens first.  
RA = Address of the memory location to be read.  
SA = Address of the sector to be verified (in autoselect mode)  
or erased. Address bits A21–A16 select a unique sector.  
RD = Data read from location RA during read operation.  
PA = Address of the memory location to be programmed.  
Addresses latch on the falling edge of the WE# or CE# pulse,  
whichever happens later.  
SGA = Address of the sector group to be verified. Address  
bits A21–A18 select a unique sector group.  
Notes:  
1. See Table 1 on page 8 for description of bus operations.  
7. The fourth cycle of the autoselect command sequence is  
a read cycle.  
2. All values are in hexadecimal.  
8. The data is 00h for an unprotected sector group and 01h  
for a protected sector group.See “Autoselect Command  
Sequence” for more information.  
3. Except when reading array or autoselect data, all bus  
cycles are write operations.  
4. Address bits A21–A11 are don’t cares for unlock and  
command cycles, unless SA or PA required.  
9. The system may read and program in non-erasing  
sectors, or enter the autoselect mode, when in the Erase  
Suspend mode. The Erase Suspend command is valid  
only during a sector erase operation.  
5. No unlock or command cycles required when reading  
array data.  
6. The Reset command is required to return to reading array  
data when device is in the autoselect mode, or if DQ5  
goes high (while the device is providing status data).  
10. The Erase Resume command is valid only during the  
Erase Suspend mode.  
November 11, 2009 21610D8  
Am29F032B  
17  
D A T A S H E E T  
WRITE OPERATION STATUS  
The device provides several bits to determine the sta-  
tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,  
and RY/BY#. Table 6 on page 21 and the following sub-  
sections describe the functions of these bits. DQ7,  
RY/BY#, and DQ6 each offer a method for determining  
whether a program or erase operation is complete or in  
progress. These three bits are discussed first.  
Table 6 on page 21 shows the outputs for Data# Polling  
on DQ7. Figure 4 shows the Data# Polling algorithm.  
START  
DQ7: Data# Polling  
Read DQ7–DQ0  
Addr = VA  
The Data# Polling bit, DQ7, indicates to the host  
system whether an Embedded Algorithm is in  
progress or completed, or whether the device is in  
Erase Suspend. Data# Polling is valid after the rising  
edge of the final WE# pulse in the program or erase  
command sequence.  
Yes  
DQ7 = Data?  
During the Embedded Program algorithm, the device  
outputs on DQ7 the complement of the datum pro-  
grammed to DQ7. This DQ7 status also applies to pro-  
gramming during Erase Suspend. When the  
Embedded Program algorithm is complete, the device  
outputs the datum programmed to DQ7. The system  
must provide the program address to read valid status  
information on DQ7. If a program address falls within a  
protected sector, Data# Polling on DQ7 is active for ap-  
proximately 2 µs, then the device returns to reading  
array data.  
No  
No  
DQ5 = 1?  
Yes  
Read DQ7–DQ0  
Addr = VA  
During the Embedded Erase algorithm, Data# Polling  
produces a “0” on DQ7. When the Embedded Erase al-  
gorithm is complete, or if the device enters the Erase  
Suspend mode, Data# Polling produces a “1” on DQ7.  
This is analogous to the complement/true datum output  
described for the Embedded Program algorithm: the  
erase function changes all the bits in a sector to “1”;  
prior to this, the device outputs the “complement,” or  
“0.” The system must provide an address within any of  
the sectors selected for erasure to read valid status in-  
formation on DQ7.  
Yes  
DQ7 = Data?  
No  
PASS  
FAIL  
After an erase command sequence is written, if all sec-  
tors selected for erasing are protected, Data# Polling  
on DQ7 is active for approximately 100 µs, then the de-  
vice returns to reading array data. If not all selected  
sectors are protected, the Embedded Erase algorithm  
erases the unprotected sectors, and ignores the se-  
lected sectors that are protected.  
Notes:  
1. VA = Valid address for programming. During a sector  
erase operation, a valid address is an address within  
any sector selected for erasure. During chip erase, a  
valid address is any non-protected sector address.  
2. DQ7 should be rechecked even if DQ5 = “1” because  
DQ7 may change simultaneously with DQ5.  
When the system detects DQ7 has changed from the  
complement to true data, it can read valid data at DQ7–  
DQ0 on the following read cycles. This is because DQ7  
may change asynchronously with DQ0–DQ6 while  
Output Enable (OE#) is asserted low. The Data# Poll-  
ing Timings (During Embedded Algorithms) figure in  
the “AC Characteristics” section illustrates this.  
Figure 4. Data# Polling Algorithm  
18  
Am29F032B  
21610D8 November 11, 2009  
D A T A S H E E T  
The Write Operation Status table shows the outputs for  
RY/BY#: Ready/Busy#  
Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit  
algorithm, and to the Toggle Bit Timings figure in the  
“AC Characteristics” section for the timing diagram.  
The DQ2 vs. DQ6 figure shows the differences be-  
tween DQ2 and DQ6 in graphical form. See also the  
subsection on “DQ2: Toggle Bit II”.  
The RY/BY# is a dedicated, open-drain output pin that  
indicates whether an Embedded Algorithm is in  
progress or complete. The RY/BY# status is valid after  
the rising edge of the final WE# pulse in the command  
sequence. Since RY/BY# is an open-drain output, sev-  
eral RY/BY# pins can be tied together in parallel with a  
pull-up resistor to V  
.
CC  
DQ2: Toggle Bit II  
If the output is low (Busy), the device is actively erasing  
or programming. (This includes programming in the  
Erase Suspend mode.) If the output is high (Ready),  
the device is ready to read array data (including during  
the Erase Suspend mode), or is in the standby mode.  
The “Toggle Bit II” on DQ2, when used with DQ6, indi-  
cates whether a particular sector is actively erasing  
(that is, the Embedded Erase algorithm is in progress),  
or whether that sector is erase-suspended. Toggle Bit  
II is valid after the rising edge of the final WE# pulse in  
the command sequence.  
Table 6 shows the outputs for RY/BY#. The timing dia-  
grams for read, reset, program, and erase shows the  
relationship of RY/BY# to other signals.  
DQ2 toggles when the system reads at addresses  
within those sectors that have been selected for era-  
sure. (The system may use either OE# or CE# to con-  
trol the read cycles.) But DQ2 cannot distinguish  
whether the sector is actively erasing or is erase-sus-  
pended. DQ6, by comparison, indicates whether the  
device is actively erasing, or is in Erase Suspend, but  
cannot distinguish which sectors are selected for era-  
sure. Thus, both status bits are required for sector and  
mode information. Refer to Table 6 on page 22 to com-  
pare outputs for DQ2 and DQ6.  
DQ6: Toggle Bit I  
Toggle Bit I on DQ6 indicates whether an Embedded  
Program or Erase algorithm is in progress or complete,  
or whether the device has entered the Erase Suspend  
mode. Toggle Bit I may be read at any address, and is  
valid after the rising edge of the final WE# pulse in the  
command sequence (prior to the program or erase op-  
eration), and during the sector erase time-out.  
During an Embedded Program or Erase algorithm op-  
eration, successive read cycles to any address cause  
DQ6 to toggle. (The system may use either OE# or  
CE# to control the read cycles.) When the operation is  
complete, DQ6 stops toggling.  
Figure 5, on page 20 shows the toggle bit algorithm in  
flowchart form, and the section “DQ2: Toggle Bit II” ex-  
plains the algorithm. See also the “DQ6: Toggle Bit I”  
subsection. Refer to the Toggle Bit Timings figure for  
the toggle bit timing diagram. The DQ2 vs. DQ6 figure  
shows the differences between DQ2 and DQ6 in graph-  
ical form.  
After an erase command sequence is written, if all  
sectors selected for erasing are protected, DQ6 tog-  
gles for approximately 100 µs, then returns to reading  
array data. If not all selected sectors are protected,  
the Embedded Erase algorithm erases the unpro-  
tected sectors, and ignores the selected sectors that  
are protected.  
Reading Toggle Bits DQ6/DQ2  
Refer to Figure 5, on page 20 for the following discus-  
sion. Whenever the system initially begins reading  
toggle bit status, it must read DQ7–DQ0 at least twice  
in a row to determine whether a toggle bit is toggling.  
Typically, a system would note and store the value of  
the toggle bit after the first read. After the second  
read, the system would compare the new value of the  
toggle bit with the first. If the toggle bit is not toggling,  
the device has completed the program or erase oper-  
ation. The system can read array data on DQ7–DQ0  
on the following read cycle.  
The system can use DQ6 and DQ2 together to deter-  
mine whether a sector is actively erasing or is erase-  
suspended. When the device is actively erasing (that is,  
the Embedded Erase algorithm is in progress), DQ6  
toggles. When the device enters the Erase Suspend  
mode, DQ6 stops toggling. However, the system must  
also use DQ2 to determine which sectors are erasing  
or erase-suspended. Alternatively, the system can use  
DQ7 (see the subsection on “DQ7: Data# Polling”).  
However, if after the initial two read cycles, the system  
determines that the toggle bit is still toggling, the  
system also should note whether the value of DQ5 is  
high (see the section on DQ5). If it is, the system  
should then determine again whether the toggle bit is  
toggling, since the toggle bit may have stopped tog-  
gling just as DQ5 went high. If the toggle bit is no longer  
toggling, the device has successfully completed the  
program or erase operation. If it is still toggling, the  
device did not complete the operation successfully, and  
If a program address falls within a protected sector,  
DQ6 toggles for approximately 2 µs after the program  
command sequence is written, then returns to reading  
array data.  
DQ6 also toggles during the erase-suspend-program  
mode, and stops toggling once the Embedded Pro-  
gram algorithm is complete.  
November 11, 2009 21610D8  
Am29F032B  
19  
D A T A S H E E T  
the system must write the reset command to return to  
reading array data.  
erase command. If DQ3 is high on the second status  
check, the last command might not have been ac-  
cepted. Table 6 on page 21 shows the outputs for DQ3.  
The remaining scenario is that the system initially de-  
termines that the toggle bit is toggling and DQ5 has not  
gone high. The system may continue to monitor the  
toggle bit and DQ5 through successive read cycles, de-  
termining the status as described in the previous para-  
graph. Alternatively, it may choose to perform other  
system tasks. In this case, the system must start at the  
beginning of the algorithm when it returns to determine  
the status of the operation (top of Figure 5).  
START  
Read DQ7–DQ0  
DQ5: Exceeded Timing Limits  
DQ5 indicates whether the program or erase time has  
exceeded a specified internal pulse count limit. Under  
these conditions DQ5 produces a “1.” This is a failure  
condition that indicates the program or erase cycle was  
not successfully completed.  
Read DQ7–DQ0  
(Note 1)  
No  
The DQ5 failure condition may appear if the system  
tries to program a “1” to a location that is previously pro-  
grammed to “0.” Only an erase operation can change  
a “0” back to a “1.” Under this condition, the device  
halts the operation, and when the operation has ex-  
ceeded the timing limits, DQ5 produces a “1.”  
Toggle Bit  
= Toggle?  
Yes  
No  
Under both these conditions, the system must issue the  
reset command to return the device to reading array  
data.  
DQ5 = 1?  
Yes  
DQ3: Sector Erase Timer  
After writing a sector erase command sequence, the  
system may read DQ3 to determine whether or not an  
erase operation has begun. (The sector erase timer  
does not apply to the chip erase command.) If addi-  
tional sectors are selected for erasure, the entire time-  
out also applies after each additional sector erase  
command. When the time-out is complete, DQ3  
switches from “0” to “1.” The system may ignore DQ3  
if the system can guarantee that the time between ad-  
ditional sector erase commands will always be less  
than 50 µs. See also “Sector Erase Command Se-  
quence” on page 15.  
(Notes  
1, 2)  
Read DQ7–DQ0  
Twice  
Toggle Bit  
= Toggle?  
No  
Yes  
Program/Erase  
Operation Not  
Complete, Write  
Reset Command  
Program/Erase  
Operation Complete  
After the sector erase command sequence is written,  
the system should read the status on DQ7 (Data# Poll-  
ing) or DQ6 (Toggle Bit I) to ensure the device has ac-  
cepted the command sequence, and then read DQ3. If  
DQ3 is “1”, the internally controlled erase cycle has be-  
gun; all further commands (other than Erase Suspend)  
are ignored until the erase operation is complete. If  
DQ3 is “0”, the device will accept additional sector  
erase commands. To ensure the command has been  
accepted, the system software should check the status  
of DQ3 prior to and following each subsequent sector  
Notes:  
1. Read toggle bit twice to determine whether or not it is  
toggling. See text.  
2. Recheck toggle bit because it may stop toggling as DQ5  
changes to “1”. See text.  
Figure 5. Toggle Bit Algorithm  
20  
Am29F032B  
21610D8 November 11, 2009  
D A T A S H E E T  
Table 6. Write Operation Status  
DQ7  
DQ5  
DQ2  
Operation  
(Note 1)  
DQ6  
(Note 2)  
DQ3  
N/A  
1
(Note 1)  
RY/BY#  
Embedded Program Algorithm  
Embedded Erase Algorithm  
DQ7#  
0
Toggle  
Toggle  
0
0
No toggle  
Toggle  
0
0
Standard  
Mode  
Reading within Erase  
Suspended Sector  
1
No toggle  
0
N/A  
Toggle  
1
Erase  
Suspend Reading within Non-Erase  
Data  
Data  
Data  
0
Data  
N/A  
Data  
N/A  
1
0
Mode  
Suspended Sector  
Erase-Suspend-Program  
DQ7#  
Toggle  
Notes:  
1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further  
details.  
2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.  
See “DQ5: Exceeded Timing Limits” for more information.  
November 11, 2009 21610D8  
Am29F032B  
21  
D A T A S H E E T  
ABSOLUTE MAXIMUM RATINGS  
Storage Temperature  
Plastic Packages . . . . . . . . . . . . . . .–65° C to +150°C  
20 ns  
20 ns  
Ambient Temperature  
with Power Applied. . . . . . . . . . . . . .–55° C to +125°C  
+0.8 V  
Voltage with Respect to Ground  
–0.5 V  
–2.0 V  
V
(Note 1) . . . . . . . . . . . . . . . . .–2.0 V to 7.0 V  
CC  
A9, OE#, RESET# (Note 2). . . . .–2.0 V to 13.0 V  
All other pins (Note 1) . . . . . . . . . .–2.0 V to 7.0 V  
Output Short Circuit Current (Note 3) . . . . . . 200 mA  
20 ns  
Notes:  
Figure 6. Maximum Negative  
Overshoot Waveform  
1. Minimum DC voltage on input or I/O pins is –0.5 V.  
During voltage transitions, inputs may overshoot VSS to –  
2.0 V for periods of up to 20 ns. See Figure 6. Maximum  
DC voltage on output and I/O pins is VCC + 0.5 V. During  
voltage transitions, outputs may overshoot to VCC + 2.0 V  
for periods up to 20 ns. See Figure 7.  
20 ns  
VCC  
2. Minimum DC input voltage on A9, OE#, RESET# pins is –  
0.5V. During voltage transitions, A9, OE#, RESET# pins  
may overshoot VSS to –2.0 V for periods of up to 20 ns. See  
Figure 6. Maximum DC input voltage on A9, OE#, and  
RESET# is 13.0 V which may overshoot to 13.5 V for  
periods up to 20 ns.  
+2.0 V  
VCC  
+0.5 V  
2.0 V  
20 ns  
20 ns  
3. No more than one output shorted at a time. Duration of  
the short circuit should not be greater than one second.  
Stresses greater than those listed in this section may cause  
permanent damage to the device. This is a stress rating only;  
functional operation of the device at these or any other condi-  
tions above those indicated in the operational sections of this  
specification is not implied. Exposure of the device to absolute  
maximum rating conditions for extended periods may affect de-  
vice reliability.  
Figure 7. Maximum Positive  
Overshoot Waveform  
OPERATING RANGES  
Industrial (I) Devices  
Ambient Temperature (T ) . . . . . . . . .–40°C to +85°C  
A
Extended (E) Devices  
Ambient Temperature (T ) . . . . . . . .–55° C to +125°C  
A
V
Supply Voltages  
CC  
V
V
for 5% devices. . . . . . . . . . .+4.75 V to +5.25 V  
for 10% devices . . . . . . . . . .+4.50 V to +5.50 V  
CC  
CC  
Operating ranges define those limits between which the  
functionality of the device is guaranteed.  
22  
Am29F032B  
21610D8 November 11, 2009  
D A T A S H E E T  
DC CHARACTERISTICS  
TTL/NMOS Compatible  
Parameter  
Symbol  
Parameter Description  
Test Description  
VIN = VSS to VCC, VCC = VCC Max  
VCC = VCC Max, A9 = 12.0 V  
VOUT = VSS to VCC, VCC = VCC Max  
CE# = VIL, OE# = VIH  
Min  
Typ  
Max  
± 1.0  
50  
Unit  
µA  
ILI  
Input Load Current  
ILIT  
A9 Input Load Current  
µA  
ILO  
Output Leakage Current  
VCC Read Current (Note 1)  
VCC Write Current (Notes 2, 3)  
± 1.0  
40  
µA  
ICC1  
ICC2  
30  
40  
mA  
mA  
CE# = VIL, OE# = VIH  
60  
VCC Standby Current  
(CE# Controlled)  
ICC3  
ICC4  
CE# = VIH, RESET# = VIH  
0.4  
0.4  
1.0  
1.0  
mA  
mA  
VCC Standby Current  
(RESET# Controlled)  
VCC = VCC Max, RESET# = VIL  
VIL  
Input Low Level  
Input High Level  
–0.5  
2.0  
0.8  
V
V
VIH  
VCC + 0.5  
Voltage for Autoselect and Sector  
Protect  
VID  
VCC = 5.0 V  
11.5  
12.5  
0.45  
V
VOL  
VOH  
VLKO  
Output Low Voltage  
Output High Level  
IOL = 12 mA, VCC = VCC Min  
IOH = –2.5 mA VCC = VCC Min  
V
V
V
2.4  
3.2  
Low VCC Lock-out Voltage  
4.2  
CMOS Compatible  
Parameter  
Symbol  
Parameter Description  
Test Description  
VIN = VSS to VCC, VCC = VCC Max  
VCC = VCC Max, A9 = 12.0 V  
VOUT = VSS to VCC, VCC = VCC Max  
CE# = VIL, OE# = VIH  
Min  
Typ  
Max  
± 1.0  
50  
Unit  
µA  
ILI  
Input Load Current  
ILIT  
A9 Input Load Current  
µA  
ILO  
Output Leakage Current  
VCC Read Current (Note 1)  
VCC Write Current (Notes 2, 3)  
± 1.0  
40  
µA  
ICC1  
ICC2  
30  
30  
mA  
mA  
CE# = VIL, OE# = VIH  
40  
VCC Standby Current  
(CE# Controlled)  
CE# = VCC ± 0.5 V,  
ICC3  
ICC4  
1
1
5
5
µA  
µA  
RESET# = VCC ± 0.5 V  
VCC Standby Current  
(RESET# Controlled)  
RESET# = VSS ± 0.5 V  
VIL  
VIH  
Input Low Level  
Input High Level  
–0.5  
0.8  
V
V
0.7x VCC  
VCC + 0.3  
Voltage for Autoselect  
and Sector Protect  
VID  
VCC = 5.0 V  
11.5  
12.5  
0.45  
V
VOL  
Output Low Voltage  
IOL = 12 mA, VCC = VCC Min  
IOH = –2.5 mA, VCC = VCC Min  
IOH = –100 µA, VCC = VCC Min  
V
V
V
V
VOH1  
VOH2  
VLKO  
0.85 VCC  
VCC – 0.4  
3.2  
Output High Voltage  
Low VCC Lock-out Voltage  
4.2  
Notes for DC Characteristics (both tables):  
1. The ICC current is typically less than 1 mA/MHz, with OE# at VIH.  
2. ICC active while Embedded Program or Embedded Erase algorithm is in progress.  
3. Not 100% tested.  
November 11, 2009 21610D8  
Am29F032B  
23  
D A T A S H E E T  
TEST CONDITIONS  
Table 7. Test Specifications  
5.0 V  
Test Condition  
-75  
All others Unit  
2.7 kΩ  
Output Load  
1 TTL gate  
100  
Device  
Under  
Test  
Output Load Capacitance, CL  
(including jig capacitance)  
30  
5
pF  
C
L
6.2 kΩ  
Input Rise and Fall Times  
Input Pulse Levels  
20  
ns  
V
0.0–3.0 0.45–2.4  
Input timing measurement  
reference levels  
1.5  
1.5  
0.8  
2.0  
V
V
Note: Diodes are IN3064 or equivalent  
Output timing measurement  
reference levels  
Figure 8. Test Setup  
KEY TO SWITCHING WAVEFORMS  
WAVEFORM  
INPUTS  
OUTPUTS  
Steady  
Changing from H to L  
Changing from L to H  
Don’t Care, Any Change Permitted  
Does Not Apply  
Changing, State Unknown  
Center Line is High Impedance State (High Z)  
24  
Am29F032B  
21610D8 November 11, 2009  
D A T A S H E E T  
AC CHARACTERISTICS  
Read-only Operations  
Parameter Symbol  
Speed Options  
JEDEC  
Std  
Parameter Description  
Read Cycle Time (Note 1)  
Test Setup  
-75  
-90  
Unit  
tAVAV  
tRC  
Min  
70  
90  
ns  
CE# = VIL  
OE# = VIL  
tAVQV  
tACC  
Address to Output Delay  
Max  
70  
90  
ns  
tELQV  
tGLQV  
tCE  
tOE  
Chip Enable to Output Delay  
Output Enable to Output Delay  
OE# = VIL  
Max  
Max  
Min  
70  
40  
90  
40  
ns  
ns  
ns  
Read  
0
Output Enable Hold Time  
(Note 1)  
tOEH  
Toggle and Data#  
Polling  
Min  
Max  
Max  
Min  
10  
ns  
ns  
ns  
ns  
µs  
Chip Enable to Output High Z  
(Note 1)  
tEHQZ  
tGHQZ  
tAXQX  
tDF  
20  
20  
20  
20  
Output Enable to Output High Z  
(Note 1)  
tDF  
Output Hold Time From Addresses CE# or OE#  
Whichever Occurs First  
tOH  
0
RESET# Pin Low to Read Mode  
(Note 1)  
tReady  
Max  
20  
Notes:  
1. Not 100% tested.  
2. Refer to Figure 8 and Table 7 for test specifications.  
tRC  
Addresses Stable  
tACC  
Addresses  
CE#  
tDF  
tOE  
OE#  
tOEH  
WE#  
tCE  
tOH  
HIGH Z  
HIGH Z  
Output Valid  
Outputs  
RESET#  
RY/BY#  
0 V  
Figure 9. Read Operation Timings  
November 11, 2009 21610D8  
Am29F032B  
25  
D A T A S H E E T  
AC CHARACTERISTICS  
Hardware Reset (RESET#)  
Parameter  
JEDEC  
Std Description  
Test Setup  
All Speed Options  
Unit  
RESET# Pin Low (During Embedded  
Algorithms) to Read or Write (See Note)  
tREADY  
Max  
Max  
20  
µs  
RESET# Pin Low (NOT During Embedded  
Algorithms) to Read or Write (See Note)  
tREADY  
500  
ns  
tRP  
tRH  
tRB  
RESET# Pulse Width  
Min  
Min  
Min  
500  
50  
0
ns  
ns  
ns  
RESET# High Time Before Read (See Note)  
RY/BY# Recovery Time  
Note: Not 100% tested.  
RY/BY#  
CE#, OE#  
RESET#  
tRH  
tRP  
tReady  
Reset Timings NOT during Embedded Algorithms  
Reset Timings during Embedded Algorithms  
tReady  
RY/BY#  
tRB  
CE#, OE#  
RESET#  
tRP  
Figure 10. RESET# Timings  
26  
Am29F032B  
21610D8 November 11, 2009  
D A T A S H E E T  
AC CHARACTERISTICS  
Write (Erase/Program) Operations  
Parameter  
Speed Options  
JEDEC  
tAVAV  
Std  
tWC  
tAS  
tAH  
tDS  
tDH  
Parameter Description  
Write Cycle Time (Note 1)  
-75  
-90  
Unit  
ns  
Min  
Min  
Min  
Min  
Min  
70  
90  
tAVWL  
tWLAX  
tDVWH  
tWHDX  
Address Setup Time  
Address Hold Time  
Data Setup Time  
Data Hold Time  
0
ns  
40  
40  
45  
45  
ns  
ns  
0
0
ns  
Read Recover Time Before Write  
(OE# high to WE# low)  
tGHWL  
tGHWL  
Min  
ns  
tELWL  
tWHEH  
tWLWH  
tWHWL  
tWHWH1  
tCS  
tCH  
CE# Setup Time  
Min  
Min  
Min  
Min  
Typ  
Typ  
Max  
Min  
Max  
0
0
ns  
ns  
CE# Hold Time  
tWP  
Write Pulse Width  
40  
45  
ns  
tWPH  
tWHWH1  
Write Pulse Width High  
Byte Programming Operation (Note 2)  
20  
7
ns  
µs  
1
sec  
sec  
µs  
tWHWH2  
tWHWH2  
Sector Erase Operation (Note 2)  
8
tVCS  
VCC Set Up Time (Note 1)  
WE# to RY/BY# Valid  
50  
tBUSY  
40  
40  
ns  
Notes:  
1. Not 100% tested.  
2. See the “Erase And Programming Performance” section for more information.  
November 11, 2009 21610D8  
Am29F032B  
27  
D A T A S H E E T  
AC CHARACTERISTICS  
Program Command Sequence (last two cycles)  
Read Status Data (last two cycles)  
tAS  
tWC  
Addresses  
555h  
PA  
PA  
PA  
tAH  
CE#  
OE#  
tCH  
tWHWH1  
tWP  
WE#  
Data  
tWPH  
tCS  
tDS  
tDH  
PD  
DOUT  
A0h  
Status  
tBUSY  
tRB  
RY/BY#  
VCC  
tVCS  
Note: PA = program address, PD = program data, DOUT is the true data at the program address.  
Figure 11. Program Operation Timings  
28  
Am29F032B  
21610D8 November 11, 2009  
D A T A S H E E T  
AC CHARACTERISTICS  
tAS  
SA  
tWC  
2AAh  
VA  
VA  
Addresses  
CE#  
555h for chip erase  
tAH  
tCH  
OE#  
tWP  
WE#  
tWPH  
tWHWH2  
tCS  
tDS  
tDH  
In  
Data  
Complete  
55h  
30h  
Progress  
10 for Chip Erase  
tBUSY  
tRB  
RY/BY#  
VCC  
tVCS  
Note: SA = Sector Address. VA = Valid Address for reading status data.  
Figure 12. Chip/Sector Erase Operation Timings  
November 11, 2009 21610D8  
Am29F032B  
29  
D A T A S H E E T  
AC CHARACTERISTICS  
tRC  
VA  
Addresses  
VA  
VA  
tACC  
tCE  
CE#  
tCH  
tOE  
OE#  
WE#  
tOEH  
tDF  
tOH  
Complement  
High Z  
High Z  
DQ7  
Valid Data  
Complement  
Status Data  
True  
DQ0–DQ6  
Status Data  
True  
Valid Data  
tBUSY  
RY/BY#  
Note:  
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.  
Figure 13. Data# Polling Timings (During Embedded Algorithms)  
tRC  
Addresses  
CE#  
VA  
tACC  
tCE  
VA  
VA  
VA  
tCH  
tOE  
OE#  
WE#  
tOEH  
tDF  
tOH  
High Z  
DQ6/DQ2  
RY/BY#  
Valid Status  
(first read)  
Valid Status  
Valid Status  
Valid Data  
(second read)  
(stops toggling)  
tBUSY  
Note:  
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,  
and array data read cycle.  
Figure 14. Toggle Bit Timings (During Embedded Algorithms)  
30  
Am29F032B  
21610D8 November 11, 2009  
D A T A S H E E T  
AC CHARACTERISTICS  
Enter  
Embedded  
Erasing  
Erase  
Suspend  
Enter Erase  
Suspend Program  
Erase  
Resume  
Erase  
Erase Suspend  
Read  
Erase  
Suspend  
Program  
Erase  
Complete  
WE#  
Erase  
Erase Suspend  
Read  
DQ6  
DQ2  
Note: The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the  
erase-suspended sector.  
Figure 15. DQ2 vs. DQ6  
Temporary Sector Unprotect  
Parameter  
JEDEC  
Std  
Description  
All Speed Options  
Unit  
tVIDR  
VID Rise and Fall Time (See Note)  
Min  
Min  
500  
ns  
RESET# Setup Time for Temporary Sector  
Unprotect  
tRSP  
4
µs  
Note: Not 100% tested.  
12 V  
RESET#  
0 or 5 V  
0 or 5 V  
tVIDR  
tVIDR  
Program or Erase Command Sequence  
CE#  
WE#  
tRSP  
RY/BY#  
Figure 16. Temporary Sector Group Unprotect Timings  
November 11, 2009 21610D8  
Am29F032B  
31  
D A T A S H E E T  
AC CHARACTERISTICS  
Write (Erase/Program) Operations—Alternate CE# Controlled Writes  
Parameter Symbol  
Speed Options  
JEDEC  
tAVAV  
Std  
tWC  
Parameter Description  
Write Cycle Time (Note 1)  
-75  
-90  
Unit  
ns  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Typ  
Typ  
Max  
70  
90  
tAVEL  
tAS  
Address Setup Time  
Address Hold Time  
0
ns  
tELAX  
tAH  
40  
40  
45  
45  
ns  
tDVEH  
tEHDX  
tGHEL  
tWLEL  
tEHWH  
tELEH  
tEHEL  
tWHWH1  
tDS  
Data Setup Time  
ns  
tDH  
Address Hold Time  
0
0
0
0
ns  
tGHEL  
tWS  
Read Recover Time Before Write  
CE# Setup Time  
ns  
ns  
tWH  
CE# Hold Time  
ns  
tCP  
Write Pulse Width  
40  
45  
ns  
tCPH  
tWHWH1  
Write Pulse Width High  
Byte Programming Operation (Note 2)  
20  
7
ns  
µs  
1
sec  
sec  
tWHWH2  
tWHWH2  
Sector Erase Operation (Note 2)  
8
Notes:  
1. Not 100% tested.  
2. See the “Erase And Programming Performance” section for more information.  
32  
Am29F032B  
21610D8 November 11, 2009  
D A T A S H E E T  
AC CHARACTERISTICS  
555 for program  
PA for program  
2AA for erase  
SA for sector erase  
555 for chip erase  
Data# Polling  
Addresses  
PA  
tWC  
tWH  
tAS  
tAH  
WE#  
OE#  
tGHEL  
tWHWH1 or 2  
tCP  
CE#  
Data  
tWS  
tCPH  
tDS  
tBUSY  
tDH  
DQ7#  
DOUT  
tRH  
A0 for program  
55 for erase  
PD for program  
30 for sector erase  
10 for chip erase  
RESET#  
RY/BY#  
Notes:  
1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data.  
2. Figure indicates the last two bus cycles of the command sequence.  
Figure 17. Alternate CE# Controlled Write Operation Timings  
November 11, 2009 21610D8  
Am29F032B  
33  
D A T A S H E E T  
ERASE AND PROGRAMMING PERFORMANCE  
Parameter  
Sector Erase Time  
Typ (Note 1)  
Max (Note 2)  
Unit  
sec  
sec  
µs  
Comments  
1
64  
7
8
Excludes 00h programming prior to  
erasure (Note 4)  
Chip Erase Time  
Byte Programming Time  
Chip Programming Time (Note 3)  
300  
Excludes system-level overhead  
(Note 5)  
28.8  
86.4  
sec  
Notes:  
1. Typical program and erase times assume the following conditions: 25°C, 5.0 V VCC, 1,000,000 cycles. Additionally,  
programming typicals assume checkerboard pattern.  
2. Under worst case conditions of 90°C, VCC = 4.5 V, 1,000,000 cycles (4.75 V for -75).  
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes  
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then does  
the device set DQ5 = 1. See the section on DQ5 for further information.  
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.  
5. System-level overhead is the time required to execute the four-bus-cycle sequence for programming. See Table 5 for further  
information on command definitions.  
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.  
LATCHUP CHARACTERISTIC  
Description  
Input Voltage with respect to VSS on I/O pins  
VCC Current  
Min  
Max  
–1.0 V  
VCC + 1.0 V  
+100 mA  
–100 mA  
Note: Includes all pins except VCC. Test conditions: VCC = 5.0 Volt, one pin at a time.  
TSOP AND SO PIN CAPACITANCE  
Parameter  
Symbol  
Parameter Description  
Input Capacitance  
Test Conditions  
Min  
6
Max  
7.5  
12  
Unit  
CIN  
VIN = 0  
VOUT = 0  
VIN = 0  
pF  
pF  
pF  
COUT  
CIN2  
Output Capacitance  
8.5  
7.5  
Control Pin Capacitance  
9
Notes:  
1. Sampled, not 100% tested.  
2. Test conditions TA = 25° C, f = 1.0 MHz.  
DATA RETENTION  
Parameter  
Test Conditions  
150°C  
Min  
10  
Unit  
Years  
Years  
Minimum Pattern Data Retention Time  
125°C  
20  
34  
Am29F032B  
21610D8 November 11, 2009  
D A T A S H E E T  
PHYSICAL DIMENSIONS  
SO 044–44-Pin Small Outline Package  
Dwg rev AC; 10/99  
November 11, 2009 21610D8  
Am29F032B  
35  
D A T A S H E E T  
PHYSICAL DIMENSIONS  
TS 040–40-Pin Standard Thin Small Outline Package  
Dwg rev AA; 10/99  
36  
Am29F032B  
21610D8 November 11, 2009  
D A T A S H E E T  
REVISION SUMMARY  
Revision A (June 1998)  
Initial release.  
Revision D+2 (November 8, 2004)  
Global  
Added cover page, colophon, and referenced links  
Revision B (July 1998)  
Updated Trademark.  
Distinctive Characteristics  
Changed typical active read current to 30 mA to match  
DC Characteristics table.  
Ordering Information  
Added temperature range for Pb-free Packages.  
Operating Ranges  
Valid Combinations  
Corrected temperature range descriptions to “ambient.”  
Added new combinations.  
Revision C (January 1999)  
Distinctive Characteristics  
Revision D3 (December 22, 2005)  
Global  
Added 20-year data retention subbullet.  
Revision C+1 (April 14, 1999)  
Deleted duplicate sections in the full data sheet.  
Deleted 120 and 150 ns speed options, and deleted re-  
verse TSOP package option.  
Revision D4 (May 19, 2006)  
Added “Not recommended for new designs” note.  
AC Characteristics  
Data Retention  
Added table.  
Revision D (November 17, 1999)  
Changed t  
specification to maximium value.  
BUSY  
AC Characteristics—Figure 11. Program  
Operations Timing and Figure 12. Chip/Sector  
Erase Operations  
Revision D5 (November 2, 2006)  
Deleted “Not recommended for new designs” note.  
Deleted t  
high.  
and changed OE# waveform to start at  
Revision D6 (March 5, 2009)  
Global  
GHWL  
Physical Dimensions  
Added obsolescence information.  
Replaced figures with more detailed illustrations.  
Revision D7 (August 3, 2009)  
Global  
Revision D+1 (December 5, 2000)  
Added table of contents.  
Removed obsolescence information.  
Ordering Information  
Revision D8 (November 11, 2009)  
Global  
Deleted burn-in option.  
Removed all commercial temperature range options.  
November 11, 2009 21610D8  
Am29F032B  
37  
D A T A S H E E T  
Colophon  
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-  
tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-  
templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the  
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,  
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for  
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable  
to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor  
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design  
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating  
conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign  
Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-  
thorization by the respective government entity will be required for export of those pr  
Trademarks  
Copyright © 1998–2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trade-  
marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are  
for identification purposes only and may be trademarks of their respective companies.  
Copyright © 2006-2009 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, Eco-  
RAM™ and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other  
names used are for informational purposes only and may be trademarks of their respective owners.  
38  
Am29F032B  
21610D8 November 11, 2009  

相关型号：

AM29F032B-90FK

 Flash, 4MX8, 90ns, PDSO40, REVERSE, MO-142CD, TSOP-40
SPANSION

AM29F032B-90FKB

 Flash, 4MX8, 90ns, PDSO40, REVERSE, TSOP-40
SPANSION

AM29F032B-90SC

 32 Megabit (4 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
AMD

AM29F032B-90SCB

 Flash, 4MX8, 90ns, PDSO44, SOP-44
SPANSION

AM29F032B-90SD

 32 Megabit (4 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
AMD

AM29F032B-90SDB

 Flash, 4MX8, 90ns, PDSO44, SOP-44
SPANSION

AM29F032B-90SE

 32 Megabit (4 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
AMD

AM29F032B-90SEB

 Flash, 4MX8, 90ns, PDSO44, SOP-44
SPANSION

AM29F032B-90SF

 32 Megabit (4 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
AMD

AM29F032B-90SFB

 Flash, 4MX8, 90ns, PDSO44, SOP-44
SPANSION

AM29F032B-90SI

 32 Megabit (4 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
AMD

AM29F032B-90SIB

 Flash, 4MX8, 90ns, PDSO44, SOP-44
SPANSION
©2020 ICPDF网 联系我们和版权申明