CXR704060GH [SONY]
Microcontroller, 32-Bit, MROM, ARM7 CPU, 22.579MHz, CMOS, PBGA208,;
| 型号： | CXR704060GH |
| 厂家： | 
SONY CORPORATION |
| 描述： | Microcontroller, 32-Bit, MROM, ARM7 CPU, 22.579MHz, CMOS, PBGA208, 微控制器和处理器 外围集成电路 时钟 |
| 文件： | 总45页 (文件大小：418K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXR704060
CMOS 32-bit Single Chip Microcomputer
Description
208 pin TFLGA (Plastic)
The CXR704060 is a CMOS 32-bit microcomputer
integrating on a single chip a micro processor unit
having a 32-bit RISC CPU as its core, and a signal
processing block having an accelerator circuit suited
for arithmetic signal processing. Adoption of this
arithmetic signal processing accelerator circuit
enables flexible support of various signal processing
systems.
The microcomputer block incorporates Memory Stick
interface, a MagicGate, FLASH memory interface,
USB interface, D/A converter for audio applications,
A/D converter, serial interface, I2C bus interface,
timer and PWM pulse generator as well as basic
configurations like a 32-bit RISC CPU, ROM, RAM,
and I/O ports. It also provides the idle/sleep/stop
functions that enable lower power consumption.
Features
• CPU
SR11 series 32-bit RISC CPU core (ARM7TDMI)
• Minimum instruction cycle
• Incorporated ROM
• Incorporated RAM
• Peripheral hardware
— Bus interface unit
— DMA controller
— A/D converter
44.29ns (fSRC: 22.5792MHz)
192K bytes
256K bytes
16-bit data bus, 24-bit address bus, 5 chip select outputs
4 channels
10-bit 8-analog input, successive approximation method
Clock synchronization, 1 channel (Incorporated 128-byte buffer RAM)
Clock synchronization, 1 channel (Incorporated 32-byte buffer RAM)
Asynchronization, 2 channels
— Serial interface
— 8-bit timer
8 channels (timer output)
— Time-base timer
— Prescaler
— Watchdog timer
— PWM pulse generator
16 bits × 1 channel
8 bits × 1 channel
— 16-bit D/A converter for audio applications
L channel, R channel
1 channel
— Memory Stick interface
— MagicGate
— Serial interface for EEPROM Serial interface for CXK2000, 1 channel
— USB interface
— Flash memory interface
— External interruption
Conforms to USB1.1, internal transceiver
1-bit error correction function
10 channels (polarity selection and both edge detection possible)
• Accelerator for arithmetic signal processing
• Standby mode
• Package
Idle/sleep/stop
208-pin plastic TFLGA
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E02655-PS
Block Diagram
7
8
AN0 to AN7
A/D CONVERTER
SCS0
SI0
SO0
SCK0
SERIAL INTERFACE
(CH0)
RAM
RAM
SCS1
SI1
SO1
SCK1
SERIAL INTERFACE
(CH1)
TxD0
RxD0
2
2
UART (CH0)
UART (CH1)
TxD1
RxD1
SDA
I2C BUS INTERFACE
RAM
SCL
EC0
8-BIT TIMER/COUNTER (CH0)
8-BIT TIMER (CH1)
8
T1
EC2
8-BIT TIMER/COUNTER (CH2)
8-BIT TIMER (CH3)
T3
8-BIT TIMER (CH4)
8-BIT TIMER (CH5)
BEEP
8-BIT TIMER (CH6)
8-BIT TIMER (CH7)
PWM
PWM PULSE GENERATOR
BUS INTERFACE UNIT
EXTERNAL BUS
AVDDA
AVSDA
VREFR
VREFL
2
2
8
5
16
24
CXR704060
Pin Assignment (Top View) 208-pin TFLGA package
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
V
U
T
101
105
107
93
103
106
89
91
87
97
85
99
83
92
81
88
77
79
75
80
71
73
70
69
67
65
64
58
63
56
61
57
53
55
59
52
V
U
T
100
112
51
47
R
P
N
M
L
R
P
N
M
L
113
110
104
102
98
95
96
94
90
86
84
82
78
76
74
72
68
66
62
60
54
49
45
118
120
116
121
108
114
100
115
111
50
48
44
40
46
43
41
39
123
128
122
126
117
124
119
125
42
35
38
37
36
32
26
18
30
27
21
16
34
31
28
25
33
29
24
23
K
J
129
134
135
131
133
139
127
132
137
130
136
138
K
J
H
G
F
H
G
F
140
142
146
148
141
144
147
151
143
149
154
157
145
155
165
164
14
8
10
6
22
17
13
12
20
19
15
11
E
D
C
B
A
E
D
C
B
A
173
171
177
175
180
179
187
185
191
189
193
194
195
197
199
205
1
4
203
207
150
152
153
158
160
156
159
161
3
7
2
9
5
163
162
166
167
169
168
174
170
178
172
183
176
182
181
184
186
192
188
196
190
200
198
202
201
208
204
206
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
– 3 –
CXR704060
• Pin Assignment Table
Pin Pin
No. position
Pin
No.
Pin
position
Pin
No.
Pin
position
Pin function
Pin function
VDIO1
Pin function
1
E5
B2
C3
E4
B1
F4
C2
F5
C1
G4
D1
D2
E2
G5
E1
H4
F2
H5
F1
G1
J4
VDIO0
PM4/A12
PM5/A13
PM6/A14
PM7/A15
PN0/A16
PN1/A17
PN2/A18
PN3/A19
PN4/A20
PN5/A21
PN6/A22
PN7/A23
DVSS7
FAD0
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
M1
M2
N1
N4
P1
M5
N2
P4
R1
P2
T1
N5
R2
P5
U1
T2
T3
R4
V2
U4
U3
U5
U2
R5
V3
P6
V4
V5
U6
R6
V6
P7
U7
V7
V8
R7
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
U8
PE4/SCK1
PE5/SO1
PE6/SI1
PE7/SCS1
TEST5
2
PO0/D0
PO1/D1
PO2/D2
PO3/D3
PO4/D4
PO5/D5
PO6/D6
PO7/D7
PB0/D8
PB1/D9
PB2/D10
PB3/D11
PB4/D12
PB5/D13
PB6/D14
PB7/D15
PA0/PWM
PA1/SDA
PA2/SCL
PC0/SCK0
PC1/SO0
PC2/SI0
PC3/SCS0
DVSS2
P8
3
V9
4
R8
5
V10
P9
6
DVDD1
7
U10
U9
DVSS3
8
VDIO3
9
V11
R9
PF0/EC0/INT3
PF1/T1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
V12
P10
V13
R10
V14
U11
V15
P11
U15
U12
V16
R11
R12
P12
U14
R13
U13
PF2/EC2/INT4
PF3/T3
PF4/BEEP
PG0/DACK0
PG1/DREQ0/INT5
PG2/DACK1/INT6
PG3/DREQ1/INT7
TEST2
FAD1
FAD2
FAD3
FAD4
TEST3
FAD5
TEST0
FAD6
TEST1
G2
H1
J1
FAD7
TEST6
FCLE
EVA
FALE
AVSAD
H2
J5
VDIODF
FWE
AVDAD
VDIO2
AN0
K4
J2
FRE
KDI
AN1
FWP
KRB
100 P14
101 V17
102 R14
103 U16
104 R15
105 U17
106 T16
107 T17
108 P15
AN2
K1
L4
K2
K5
L1
L2
M4
L5
FCE0
KCLK
AN3
FRB0
KCS
AN4
FCE1
KDO
AN5
FRB1
TEST4
AN6/INT8
AN7/INT9
RST
PP0
PE0/TxD0
PE1/RxD0
PE2/TXD1
PE3/RXD1
PP1
DVDD0
DVSS1
RAMBK
VDBK
– 4 –
CXR704060
Pin Pin
No. position
Pin
No.
Pin
position
Pin
No.
Pin
position
Pin function
TDI
Pin function
AVDUO
Pin function
109 U18
110 R17
111 P13
112 T18
113 R18
114 N15
115 N14
116 P17
117 M15
118 P18
119 M14
120 N18
121 N17
122 M17
123 M18
124 L15
125 L14
126 L17
127 K15
128 L18
129 K18
130 K14
131 K17
132 J15
133 J17
134 J18
135 H18
136 J14
137 H15
138 H14
139 H17
140 G18
141 G17
142 F18
143 G15
144 F17
145 G14
146 E18
147 E17
148 D18
149 F15
150 C18
151 D17
152 B18
153 C17
154 E15
155 F14
156 C16
157 D15
158 B17
159 B16
160 A17
161 A16
162 A15
163 B15
164 D14
165 E14
166 B14
167 A14
168 A13
169 B13
170 A12
171 D13
172 A11
173 E13
174 B12
175 D12
176 A10
177 E12
178 B11
179 D11
180 E11
181 A9
182 B9
183 B10
184 B8
185 D10
186 A8
187 E10
188 A7
189 D9
190 A6
191 E9
192 B7
193 E8
194 D8
195 E7
196 B6
197 D7
198 A5
199 E6
200 B5
201 A4
202 B4
203 D5
204 A3
205 D6
206 A2
207 D4
208 B3
PI6/MUTFGR
DVDD3
TMS
AVSPLL
AVDPLL
PQ0
TCK
DVSS5
TRST
VDIO5
TDO
PQ1
PJ0/WAIT
PJ1/RE
PJ2/LWR/LB
PJ3/UWR/UB
PJ4/WE
PK0/CS0
PK1/CS1
PK2
VDIOJT
DVDD2
PQ2
PQ3
DVSS4
PQ4
VDIO4
PQ5
PD0/CONNECT
PD1/XVDATA
PD2/DPLS
PD3/DMNS
PD4/TXDPLS
PD5/TXDMNS
PD6/TXENL
PD7/SUSPEND
VBUS
PQ6
PQ7
DVSS8
VDIO7
PR0
PK3
PK4
PR1
PK5/CS5
PK6/CS6
PK7/CS7
DVSS6
PR2
PR3
PR4
VDIOUS
UDM
PR5
VDIO6
PR6
PL0/A0
PL1/A1
PL2/A2
PL3/A3
PL4/A4
PL5/A5
PL6/A6
PL7/A7
PM0/A8
PM1/A9
PM2/A10
PM3/A11
DVSS0
UDP
PR7
TRON
DVSS9
VDIOMS
MSDIO
MSBS
MSSCLK
MSINS
PI7
AVSDA
VREFR
AOUTR
AOUTL
VREFL
AVDDA
XTAL
PI0/DADT
PI1/ADDT
PI2/LRCK
PI3/XBCK
PI4/FS2S6
PI5/MUTFGL
EXTAL
AVDMO
AVSOSC
TX
TEX
– 5 –
CXR704060
Pin Functions
Function
I/O power supply
Symbol
I/O
PJ0/WAIT
I/O / Input
Wait input for external bus.
Read signal output for external
bus.
PJ1/RE
I/O / Output
(Port J)
5-bit I/O port.
I/O can be specified in signal output
1-bit units.
Pull-up resistor can be
incorporated through
Strobe signal
Write strobe
PJ2/LWR/
LB
I/O / Output /
Output
output indicates
access to D0 to
D7.
for D0 to D7.
Strobe signal
output indicates
access to D8 to
D15.
Write strobe
signal output
for D8 to D15.
PJ3/UWR/
UB
I/O / Output / program in 1-bit units.
Output
(5 pins)
Write signal output for external
bus.
PJ4/WE
I/O / Output
I/O / Output
PK0/CS0,
PK1/CS1
(Port K)
8-bit I/O port.
Chip select output for external
bus. (2 pins)
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(8 pins)
PK2 to PK4
I/O
PK5/CS5 to
PK7/CS7
Chip select output for external
bus. (3 pins)
I/O / Output
VDIO0
VDIO5
VDIO6
(Port L)
8-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(8 pins)
PL0/A0 to
PL7/A7
I/O / Output
I/O / Output
I/O / Output
(Port M)
8-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be bus. (24 pins)
incorporated through
program in 1-bit units.
(8 pins)
PM0/A8 to
PM7/A15
Address bus output for external
(Port N)
8-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(8 pins)
PN0/A16 to
PN7/A23
– 6 –
CXR704060
Symbol
I/O
Function
I/O power supply
FAD0 to FAD7 I/O
Flash memory interface data I/O.
CLE output of flash memory interface.
ALE output of flash memory interface.
WE output of flash memory interface.
RE output of flash memory interface.
WP output of flash memory interface.
CE output of flash memory interface.
RB input of flash memory interface.
FCLE
Output
Output
FALE
FWE
Output
Output
Output
Output
Input
VDIODF
FRE
FWP
FCE0, FCE1
FRB0, FRB1
(Port P)
2-bit I/O port.
I/O can be specified in 1-bit units.
Pull-up resistor can be incorporated through program in
PP0, PP1
I/O
1-bit units.
(2 pins)
(Port O)
8-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
PO0/D0 to
PO7/D7
I/O / I/O
(8 pins)
Data bus I/O for external bus.
(16 pins)
(Port B)
8-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(8 pins)
PB0/D8 to
PB7/D15
I/O / I/O
VDIO1
VDIO2
VDIO3
(Port A)
3-bit I/O port.
PA0/PWM
PA1/SDA
I/O / Output
I/O / I/O
8-bit PWM output.
I/O can be specified in
1-bit units.
For Bit 0, pull-up resistor
I2C bus interface data I/O.
can be incorporated
through program.
I2C bus interface clock I/O.
(3 pins)
PA2/SCL
PC0/SCK0
PC1/SO0
PC2/SI0
I/O / I/O
I/O / I/O
Serial clock (CH0) I/O.
(Port C)
4-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(4 pins)
I/O / Output
I/O / Input
I/O / Input
Serial data (CH0) output.
Serial data (CH0) input.
Serial chip select (CH0) input.
PC3/SCS0
KDI
Input
Input
Serial interface data input for EEPROM.
KRB
Serial interface Ready/Busy input for EEPROM.
– 7 –
CXR704060
Symbol
KCLK
I/O
Output
Function
I/O power supply
Serial interface clock output for EEPROM.
Serial interface chip select output for EEPROM.
Serial interface data output for EEPROM.
KCS
KDO
Output
Output
UART (CH0) transmit data
output.
PE0/TxD0
PE1/RxD0
PE2/TxD1
PE3/RxD1
I/O / Output
I/O / Input
I/O / Output
I/O / Input
UART (CH0) receive data
input.
(Port E)
8-bit I/O port.
UART (CH1) transmit data
output.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(8 pins)
UART (CH1) receive data
input.
Serial clock (CH1) I/O.
PE4/SCK1
PE5/SO1
PE6/SI1
I/O / I/O
Serial data (CH1) output.
Serial data (CH1) input.
Serial chip select (CH1) input.
I/O / Output
I/O / Input
I/O / Input
PE7/SCS1
External event
input to 8-bit
timer (CH0).
External
interruption
request input.
PF0/EC0/
INT3
I/O / Input /
Input
(Port F)
Lower 4 bits are for I/O;
upper 1 bit is output-only
5-bit port.
For lower 4 bits, I/O can
be specified in 1-bit units.
For lower 4 bits, pull-up
resistor can be
VDIO1
VDIO2
VDIO3
8-bit timer (CH1) output.
PF1/T1
I/O / Output
External event
input to 8-bit
timer (CH2).
External
interruption
request input.
PF2/EC2/
INT4
I/O / Input /
Input
8-bit timer (CH3) output.
Beep output.
PF3/T3
I/O / Output
incorporated through
program in 1-bit.
(5 pins)
Output /
Output
PF4/BEEP
Transfer request acknowledge
signal output from DMA
controller (CH0).
PG0/DACK0
I/O / Output
Transfer request External
(Port G)
4-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
PG1/DREQ0/ I/O / Input /
input to DMA
interruption
INT5
Input
controller (CH0). request input.
Transfer request
acknowledge
signal output
from DMA
External
interruption
request input.
PG2/DACK1/
INT6
I/O / Output / incorporated through
Input
program in 1-bit units.
(4 pins)
controller (CH1).
Transfer request External
PG3/DREQ1/ I/O / Input /
input to DMA
interruption
INT7
Input
controller (CH1). request input.
AN0 to AN5
Input
Analog input to A/D converter. (6 pins)
AVDAD
External interruption request
input. (2 pins)
AN6/INT8,
AN7/INT9
Analog input to A/D
converter. (2 pins)
Input / Input
– 8 –
CXR704060
Symbol
PD0/
CONNECT
I/O
Function
I/O power supply
USB connection input.
(for external USB transceiver)
I/O / Input
USB receive data input.
(for external USB transceiver)
PD1/XVDATA I/O / Input
USB D+ data input.
(for external USB transceiver)
PD2/DPLS
PD3/DMNS
I/O / Input
I/O / Input
(Port D)
8-bit I/O port.
I/O can be specified in
1-bit units.
USB D– data input.
(for external USB transceiver)
Pull-up resistor can be
incorporated through
program in 1-bit units.
(8 pins)
USB D+ data output.
(for external USB transceiver)
PD4/TXDPLS I/O / Output
PD5/TXDMNS I/O / Output
VDIO4
USB D– data output.
(for external USB transceiver)
USB data control output.
(for external USB transceiver)
PD6/TXENL
I/O / Output
I/O / Output
PD7/
SUSPEND
USB suspend output.
(for external USB transceiver)
USB power signal input.
VBUS
Input
(USB connection detection signal input, for internal USB
transceiver)
UDM
I/O
USB D– data I/O. (for internal USB transceiver)
USB D+ data I/O. (for internal USB transceiver)
UDP pull-up resistor connection control output.
Internal DAC reference voltage output. (Lch)
Internal DAC Lch output.
UDP
I/O
VDIOUS
AVDDA
TRON
VREFL
AOUTL
AOUTR
VREFR
Output
Output
Output
Output
Output
Internal DAC Rch output.
Internal DAC reference voltage output. (Rch)
(Port Q)
8-bit I/O port.
PQ0 to PQ7
PR0 to PR7
I/O
I/O
I/O can be specified in 1-bit units.
Pull-up resistor can be incorporated through program in
1-bit units. (8 pins)
VDIO7
(Port R)
8-bit I/O port.
I/O can be specified in 1-bit units.
Pull-up resistor can be incorporated through program in
1-bit units. (8 pins)
– 9 –
CXR704060
Symbol
I/O
Function
I/O power supply
Audio data output to external
DAC. (for test output)
PI0/DADT
I/O / Output
Audio data input from external
ADC. (for test input)
PI1/ADDT
I/O / Input
I/O / I/O
I/O / I/O
L/R sampling clock I/O to
external DAC/ADC. (44.1kHz)
PI2/LRCK
(Port I)
8-bit I/O port.
VDIO0
VDIO5
VDIO6
I/O can be specified in Bit clock I/O to external
PI3/XBCK
1-bit units.
DAC/ADC. (2.822MHz)
Pull-up resistor can be
I/O / Output incorporated through
program in 1-bit units.
256fs clock output.
(11.2896MHz)
PI4/FS256
PI5/MUTFGL
PI6/MUTFGR
(8 pins)
Zero data detection signal
output. (Lch)
I/O / Output
Zero data detection signal
output. (Rch)
I/O / Output
I/O
PI7
MSDIO
MSBS
MSSCLK
MSINS
TEST4
I/O
Memory Stick interface data I/O.
Memory Stick interface bus state output.
Output
Output
Input
Input
VDIOMS
Memory Stick interface clock output.
Memory Stick interface card detection input. (INT0)
Test input.
TEST2, TEST3 Input
TEST0, TEST1 Input
Test input.
VDIO1
VDIO2
VDIO3
Test input.
TEST6
EVA
Output
Test output.
Input
Input
EVA mode switching input.
Data input for JTAG boundary scanning test.
TDI
Test mode control input for JTAG boundary scanning
test.
TMS
Input
VDIOJT
AVDMO
TCK
Input
Clock input for JTAG boundary scanning test.
Reset input for JTAG boundary scanning test.
Data output for JTAG boundary scanning test.
TRST
TDO
Input
Output
Oscillation connector for main oscillation.
(When a clock is supplied externally, input it to EXTAL;
opposite phase clock should be input to XTAL.)
EXTAL
XTAL
Input
Output
VDIO1
VDIO2
VDIO3
Test output.
TEST5
TEX
Output
Input
Oscillation connector for sub oscillation.
(When a clock is supplied externally, input it to TEX;
opposite phase clock should be input to TX.)
AVDUO
AVDAD
TX
Output
Input
System reset input.
RST
Control signal input for RAM backup.
RAMBK
Input
– 10 –
CXR704060
Symbol
VDBK
I/O
Function
Positive power supply for RAM backup.
Positive power supply for A/D converter.
GND for A/D converter.
I/O power supply
AVDAD
AVSAD
AVDDA
AVSDA
1
Positive power supply for internal DAC.
GND for internal DAC.
2
AVDPLL
AVSPLL
AVDMO
AVDUO
AVSOSC
VDIODF
VDIOMS
VDIOJT
VDIOUS
Positive power supply for PLL.
GND for PLL.
1
Positive power supply for main clock oscillator.
2
Positive power supply for sub clock oscillator.
Main clock and sub clock oscillator GND.
Positive power supply for flash memory interface.
Positive power supply for Memory Stick interface.
Positive power supply for JTAG.
Positive power supply for USB transceiver.
VDIO0 to
VDIO7
I/O interface positive power supply.
DVDD0 to
DVDD3
Positive power supply.
(Connect all four VDD pins to positive power supply.)
DVSS0 to
DVSS9
GND. (Connect all ten DVss pins to GND.)
1
AVDDA and AVDMO must be the same potential.
AVDPLL and AVDUO must be the same potential.
2
– 11 –
CXR704060
• I/O Power Supply and Pin Correspondence Table
I/O power supply
Digital/Analog
Symbol
PI0/DADT, PI1/ADDT, PI2/LRCK, PI3/XBCK, PI4/FS256,
VDIO0
VDIO5
VDIO6
PI5/MUTFGL, PI6/MUTFGR, PJ0/WAIT, PJ1/RE, PJ2/LWR/LB,
Digital power supply PJ3/UWR/UB, PJ4/WE, PK0/CS0, PK1/CS1, PK2, PK3, PK4,
PK5/CS5, PK6/CS6, PK7/CS7, PL0/A0 to PL7/A7,
PM0/A8 to PM7/A15, PN0/A16 to PN7/A23
FAD0 to FAD7, FCLE, FALE, FWE, FRE, FWP, FCE0, FRB0,
VDIODF
Digital power supply
FCE1, FRB1
PP0, PP1, PO0/D0 to PO7/D7, PB0/D8 to PB7/D15, PA0/PWM,
PA1/SDA, PA2/SCL, PC0/SCK0, PC1/SO0, PC2/SI0, PC3/SCS0,
KDI, KRB, KCLK, KCS, KDO, TEST4, PE0/TxD0, PE1/RxD0,
VDIO1
VDIO2
VDIO3
Digital power supply PE2/TxD1, PE3/RxD1, PE4/SCK1, PE5/SO1, PE6/SI1, PE7/SCS1,
TEST5, PF0/EC0/INT3, PF1/T1, PF2/EC2/INT4, PF3/T3,
PF4/BEEP, PG0/DACK0, PG1/DREQ0/INT5, PG2/DACK1/INT6,
PG3/DREQ1/INT7, TEST0 to TEST3, TEST6, EVA
1
AVDAD
VDIOJT
Analog power supply AN0 to AN5, AN6/INT8, AN7/INT9 (RST, RAMBK)
Digital power supply TDI, TMS, TCK, TRST, TDO
PD0/CONNECT, PD1/XVDATA, PD2/DPLS, PD3/DMNS,
Digital power supply PD4/TXDPLS, PD5/TXDMNS, PD6/TXENL, PD7/SUSPEND,
VBUS
VDIO4
VDIOUS
AVDDA
AVDMO
AVDUO
VDIO7
VDIOMS
1
Digital power supply UDM, UDP, TRON
Analog power supply VREFR, AOUTR, AOUTL, VREFL
Analog power supply XTAL, EXTAL
Analog power supply TX, TEX
Digital power supply PQ0 to PQ7, PR0 to PR7
Digital power supply MSDIO, MSBS, MSSCLK, MSINS, PI7
The H level input to RST and RAMBK must be the same potential as DVDD0 to DVDD3 and VDBK.
– 12 –
CXR704060
I/O Circuit Format for Pins
Pin
Circuit format
After a reset
VDIO
PWM
MPX
PA register
PASL register
"0" after a reset
PAD register
VDIO
PA0/PWM
Hi-Z
Hi-Z
Hi-Z
"0" after a reset
PAPUL register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
SDA, SCL
MPX
PA register
PASL register
"0" after a reset
PA1/SDA
PA2/SCL
PAD register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
SDA, SCL
D8 to D15
VDIO
MPX
MPX
PB register
PBSL register
"0" after a reset
DE
PB0/D8
to
PB7/D15
PBD register
VDIO
"0" after a reset
PBPUL register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
D8 to D15
– 13 –
CXR704060
Pin
Circuit format
After a reset
VDIO
SCK0
MPX
PC register
PCSL register
"0" after a reset
SCK0E
MPX
PCD register
PC0/SCK0
Hi-Z
VDIO
"0" after a reset
PCPUL register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
SCK0
SO0
VDIO
MPX
MPX
PC register
PCSL register
"0" after a reset
SO0E
PCD register
PC1/SO0
Hi-Z
VDIO
"0" after a reset
PCPUL register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
VDIO
PC register
PCD register
"0" after a reset
VDIO
PC2/SI0
PC3/SCS0
Hi-Z
PCPUL register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
SI0, SCS0
– 14 –
CXR704060
Pin
Circuit format
After a reset
VDIO
VDIO
PD register
PDD register
"0" after a reset
PDPUL register
"0" after a reset
PD0/CONNECT
PD1/XVDATA
PD2/DPLS
PDSL register
Hi-Z
PD3/DMNS
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
To USB interface
MPX
CONNECT, XVDATA, DPLS, DMNS
Signals from internal USB transceiver
CONNECT, XVDATA, DPLS, DMNS
TXDPLS, TXDMNS,
TXENL, SUSPEND
VDIO
MPX
PD register
PDSL register
"0" after a reset
PD4/TXDPLS
PD5/TXDMNS
PD6/TXENL
PDD register
VDIO
Hi-Z
"0" after a reset
PD7/SUSPEND
PDPUL register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
– 15 –
CXR704060
Pin
Circuit format
After a reset
VDIO
TXD0, TXD1
MPX
PE register
PESL register
"0" after a reset
PED register
PE0/TXD0
PE2/TXD1
VDIO
Hi-Z
"0" after a reset
PEPUL register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
VDIO
PE register
PED register
"0" after a reset
PE1/RXD0
PE3/RXD1
PE6/SI1
VDIO
Hi-Z
PEPUL register
"0" after a reset
PE7/SCS1
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
RXD0, RXD1, SI1, SCS1
VDIO
SCK1
MPX
MPX
PE register
PESL register
"0" after a reset
SCK1E
PED register
VDIO
PE4/SCK1
Hi-Z
"0" after a reset
PEPUL register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
SCK1
– 16 –
CXR704060
Pin
Circuit format
After a reset
VDIO
SO1
MPX
PE register
PESL register
"0" after a reset
SO1E
MPX
PED register
PE5/SO1
Hi-Z
Hi-Z
Hi-Z
VDIO
"0" after a reset
PEPUL register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
VDIO
PF register
PFD register
"0" after a reset
VDIO
PF0/EC0/INT3
PF2/EC2/INT4
PFPUL register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
EC0,EC2
INT3, INT4
VDIO
T1, T3
MPX
PF register
PFSL register
"0" after a reset
PFD register
VDIO
PF1/T1
PF3/T3
"0" after a reset
PFPUL register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
– 17 –
CXR704060
Pin
Circuit format
After a reset
VDIO
BEEP
MPX
PF register
"0" after a reset
PFSL register
PF4/BEEP
Hi-Z
BEEPE
Data bus
RD
VDIO
DACK0
MPX
PG register
PGSL register
"0" after a reset
PGD register
VDIO
PG0/DACK0
Hi-Z
"0" after a reset
PGPUL register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
VDIO
PG register
PGD register
"0" after a reset
VDIO
PG1/DREQ0/
INT5
Hi-Z
PGPUL register
"0" after a reset
PG3/DREQ1/
INT7
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
DREQ0, DREQ1
INT5, INT7
– 18 –
CXR704060
Pin
Circuit format
After a reset
VDIO
DACK1
MPX
PG register
PGSL register
"0" after a reset
PGD register
VDIO
PG2/DACK1/
INT6
"0" after a reset
Hi-Z
PGPUL register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
INT6
DADT, FS256,
MUTFGL, MUTFGR
VDIO
MPX
PI register
PISL register
"0" after a reset
PI0/DADT
PI4/FS256
PI5/MUTFGL
PI6/MUTFGR
PID register
VDIO
Hi-Z
"0" after a reset
PIPUL register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
VDIO
PI register
PID register
"0" after a reset
VDIO
PI1/ADDT
Hi-Z
PIPUL register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
ADDT
– 19 –
CXR704060
Pin
Circuit format
After a reset
VDIO
LRCK, XBCK
MPX
PI register
PISL register
"0" after a reset
LRCKE, XBCKE
MPX
PID register
PI2/LRCK
PI3/XBCK
Hi-Z
VDIO
"0" after a reset
PIPUL register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
LRCK, XBCK
VDIOMS
PI register
PID register
"0" after a reset
VDIOMS
PI7
Hi-Z
PIPUL register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
VDIO
VDIO
PJ register
PJD register
"0" after a reset
PJ0/WAIT
Hi-Z
PJPUL register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
WAIT
– 20 –
CXR704060
Pin
Circuit format
After a reset
VDIO
RE, LWR/LB, UWR/UB, WE
PJ register
MPX
PJSL register
"0" after a reset
PJ1/RE
PJD register
PJ2/LWR/LB
PJ3/UWR/UB
PJ4/WE
VDIO
Hi-Z
"0" after a reset
PJPUL register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
VDIO
CS0, CS1, CS5 to CS7
PK register
MPX
PKSL register
"0" after a reset
PK0/CS0
to
PK1/CS1
PKD register
VDIO
Hi-Z
"0" after a reset
PK5/CS5
to
PK7/CS7
PKPUL register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
VDIO
PK register
PKD register
"0" after a reset
VDIO
PK2 to PK4
Hi-Z
PKPUL register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
– 21 –
CXR704060
Pin
Circuit format
After a reset
VDIO
A0 to A7
MPX
PL register
PLSL register
"0" after a reset
AE
MPX
PL0/A0
to
PL7/A7
PLD register
Hi-Z
VDIO
"0" after a reset
PLPUL register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
VDIO
A8 to A15
MPX
MPX
PM register
PMSL register
"0" after a reset
AE
PM0/A8
to
PM7/A15
PMD register
Hi-Z
VDIO
"0" after a reset
PMPUL register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
– 22 –
CXR704060
Pin
Circuit format
After a reset
VDIO
A16 to A23
MPX
PN register
PNSL register
"0" after a reset
AE
MPX
PN0/A16
to
PN7/A23
PND register
Hi-Z
VDIO
"0" after a reset
PNPUL register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
VDIO
D0 to D7
MPX
MPX
PO register
POSL register
"0" after a reset
DE
PO0/D0
to
PO7/D7
POD register
Hi-Z
VDIO
"0" after a reset
POPUL register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
D0 to D7
VDIO
PP register
PPD register
"0" after a reset
VDIO
PP0
PP1
Hi-Z
PPPUL register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
– 23 –
CXR704060
Pin
Circuit format
After a reset
VDIO
VDIO
PQ register
PQD register
"0" after a reset
PQ0 to PQ7
Hi-Z
PQPUL register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
VDIO
PR register
PRD register
"0" after a reset
VDIO
PR0 to PR7
Hi-Z
PRPUL register
"0" after a reset
Data bus
MPX
Input data
latch
IP
RD
CMOS
Schmitt input
RST
To A/D converter
AN0 to AN5
AN0 to AN5
Hi-Z
Hi-Z
IP
RST
To A/D converter
AN6, AN7
IP
AN6/INT8
AN7/INT9
INT8, INT9
AVDAD × (0.7 ± 0.1)
– 24 –
CXR704060
Pin
Circuit format
After a reset
VDIODF
FAD0 to FAD7
output data
FAD0 to FAD7
output enable
VDIODF
FAD0 to FAD7
"L" output
FAD0 to FAD7
pull-up control
FAD0 to FAD7
input data
IP
CMOS
Schmitt input
VDIODF
FCLE
FALE
FWE
FRE, FWR,
FCE0, FCE1
FCL, FALE, FWE, FRE,
FWR, FCE0, FCE1
"L" output
FRB0, FRB1
FRB0
FRB1
"L" output
IP
CMOS
Schmitt input
KDI
KRB
IP
KDI, KRB
Hi-Z
VDIO
KDO
"L" output
KDO
VDIO
KCS
KCLK
"H" output
KCS, KCLK
IP
IP
EVA
EVA
Hi-Z
Hi-Z
VBUS
VBUS
– 25 –
CXR704060
Pin
Circuit format
After a reset
VDIOUS
TRON output data
TRON
Hi-Z
TRON output enable
VDIOMS
MSDIO output data
MSDIO output enable
MSDIO
Hi-Z
IP
MSDIO input data
CMOS
Schmitt input
VDIOMS
MSBS
MSSCLK
"L" output
MSBS, MSSCLK
MSINS
Hi-Z
IP
MSINS
AVDMO
• Diagram shows the circuit
configuration during
oscillation.
EXTAL
XTAL
IP
EXTAL
XTAL
Oscillation
• XTAL is "H" level when
oscillation is stopped.
AVDUO
• Diagram shows the circuit
configuration during
oscillation.
TEX
TX
IP
TEX
TX
Oscillation
• TX is "H" level when
oscillation is stopped.
– 26 –
CXR704060
Pin
Circuit format
After a reset
Hi-Z
RAMBK
IP
RAMBK
VDIOJT
TDI
TMS
TCK
Pull-up
IP
IP
TDI, TMS, TCK
TRST
TRST
TDO
Pull-down
VDIOJT
VDIOJT
TDO output data
Hi-Z
Hi-Z
TDO output enable
IP
RST
(to reset circuit)
RST
To AN0 to AN7
TEST0
IP
(to test circuit)
TEST0
Hi-Z
Hi-Z
CMOS
Schmitt input
TEST1
to
TEST3
IP
IP
TEST1 to TEST3
(to test circuit)
TEST4
(to test circuit)
VDIO
TEST4
Pull-down
"L" output
CMOS
Schmitt input
VDIO
TEST5
TEST6
TEST5, TEST6
(from test circuit)
– 27 –
CXR704060
Absolute Maximum Ratings
(DVSS = 0V reference)
Item
Symbol
DVDD
Rating
Unit
V
Remarks
–0.3 to +2.5
–0.3 to +2.5
–0.3 to +4.5
–0.3 to +4.5
–0.3 to +4.5
–0.3 to +4.5
–0.3 to +4.5
DVDD0, DVDD1, DVDD2, DVDD3
Power supply for backup RAM
VDBK
V
AVDAD
AVDDA
AVDMO
AVDUO
AVDPLL
V
V
V
V
Supply voltage
V
VDIO0, VDIO1, VDIO2, VDIO3,
VDIO4, VDIO5, VDIO6, VDIO7
VDIO
–0.3 to +4.5
V
VDIODF
VDIOJT
VDIOUS
VDIOMS
VIN
–0.3 to +4.5
–0.3 to +4.5
–0.3 to +4.5
–0.3 to +4.5
–0.3 to +4.5
–0.3 to +2.5
–0.3 to +4.5
–5
V
V
V
V
V
V
V
1
2
1
Excludes RST and RAMBK pins
RST and RAMBK pins
Input voltage
VINR
Output voltage
VOUT
IOH
High level output current
High level total output current
Low level output current
Low level total output current
Operating temperature
Storage temperature
mA Output (value per pin)
ΣIOH
–40
mA Total for all output pins
IOL
10
mA Output (value per pin)
ΣIOL
80
mA Total for all output pins
Topr
–20 to +70
–55 to +150
380
°C
°C
Tstg
Allowable power dissipation
PD
mW
1
VIN and VOUT must not exceed I/O supply voltage (VDIO, VDIODF, VDIOJT, VDIOUS and VDIOMS) + 0.3V.
VINR must not exceed DVDD + 0.3V.
2
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI.
Normal operation should be conducted under the recommended operating conditions. Exceeding these
conditions may adversely affect the reliability of the LSI.
– 28 –
CXR704060
Recommended Operating Conditions
(DVSS = 0V reference)
Item
Symbol
DVDD
Min.
1.1
Typ.
Max.
1.3
Unit
V
Remarks
Internal supply voltage
DVDD0, DVDD1, DVDD2, DVDD3
Supply voltage for
internal RAM backup
1
VDBK
1.1
1.3
V
AD converter supply voltage AVDAD
2.2
2.2
2.2
2.7
2.7
3.3
3.3
3.3
3.3
3.3
V
V
V
V
V
DAC supply voltage
AVDDA
Main oscillation voltage AVDMO
Sub oscillation voltage
PLL voltage
AVDUO
AVDPLL
VDIO0, VDIO1, VDIO2, VDIO3,
VDIO4, VDIO5, VDIO6, VDIO7
I/O voltage
VDIO
DVDD
3.6
V
JTAG voltage
VDIOJT
1.65
3.3
3.6
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
FLASH I/F voltage with ECC VDIODF
2.7
Memory Stick I/F voltage VDIOMS
2.7
3.6
USB transceiver voltage VDIOUS
3.0
3.3
3.45
VIHR
0.7DVDD
DVDD
RST pin
VIHBK
VIHS
0.7VDBK
VDBK
RAMBK pin
2
0.7VDIO
VDIO
CMOS Schmitt trigger input
3
VIHMSS
0.7VDIOMS
VDIOMS
VDIODF
VDIO
CMOS Schmitt trigger input
4
High level input voltage
VIHDFS
VIHC
0.7VDIODF
CMOS Schmitt trigger input
5
0.7VDIO
CMOS input
6
VIHJTC
VIHMSC
VIHKW
VILR
0.7VDIOJT
VDIOJT
VDIOMS
AVDAD
0.2DVDD
0.2VDBK
0.2VDIO
0.2VDIOMS
0.2VDIODF
0.2VDIO
0.2VDIOJT
0.2VDIOMS
0.6AVDAD
+70
CMOS input
7
0.7VDIOMS
CMOS input
8
0.8AVDAD
AN6 and AN7 pins
0
0
RST pin
VILBK
VILS
RAMBK pin
2
0
CMOS Schmitt trigger input
3
VILMSS
VILDFS
VILC
0
CMOS Schmitt trigger input
4
Low level input voltage
0
CMOS Schmitt trigger input
5
0
CMOS input
6
VILJTC
VILMSC
VILKW
Topr
0
CMOS input
7
0
CMOS input
8
0
AN6 and AN7 pins
Operating temperature
–20
1
VDBK should be the same voltage as DVDD (DVDD ± 0.1V or less).
2
3
4
5
6
7
8
Each pin of normal input ports (PA to PE, PF0 to PF3, PG, PI0 to PI6, PJ to PR, TEST0).
MSDIO and PI7 pins.
FAD0 to FAD7, FRB0 and FRB1 pins.
KDI, KRB, TEST1 to TEST4, EVA and VBUS pins.
TDI, TMS, TCK and TRST pins.
MSINS pins.
Do not set AN6 and AN7 to the center potential in the steady state.
(Low level input voltage: 0 to 0.4V, High level input voltage: (AVDAD – 0.4V) to AVDAD)
– 29 –
CXR704060
Electrical Characteristics
DC Characteristics
(DVDD = VDBK = 1.1 to 1.3V, AVDAD = AVDDA = AVDMO = 2.2 to 3.3V, AVDUO = AVDPLL = 2.7 to 3.3V)
(VDIO = VDIODF = VDIOMS = 2.7 to 3.6V, VDIOJT = 2.7 to 3.3V, VDIOUS = 3.0 to 3.45V)
(Topr = –20 to +70°C, DVSS = 0V reference)
Item
Symbol
Pins
Conditions
Min.
Typ.
Max.
Unit
V
PA0/PWM, PB, PD to PG,
PI0 to PI6, PJ to PR
VDIO = 2.7V,
IOH = –2.0mA
VDIO – 0.4
1
VDIOMS = 2.7V,
IOH = –2.0mA
PI7
VDIOMS – 0.4
V
V
D0 to D15, PC0/SCK0,
PC1/SO0, PC2, PC3,
TXDPLS, TXDMNS, TXENL,
SUSPEND, TXD0, TXD1,
SCK1, SO1, BEEP, DACK0,
DACK1, DADT, LRCK,
XBCK, FS256, MUTFGL,
MUTFGR, RE, LWR/LB,
UWR/UB, WE, CS0, CS1,
CS5 to CS7, A0 to A23,
VDIO = 2.7V,
IOH = –4.0mA
VDIO – 0.4
High level
output
VOH
voltage
2
KDO, KCLK, KCS
VDIOJT = 2.7V,
IOH = –4.0mA
TDO
VDIOJT – 0.4
VDIOUS – 0.4
VDIOMS – 0.4
V
V
V
VDIOUS = 3.0V,
IOH = –4.0mA
TRON
VDIOMS = 2.7V,
IOH = –4.0mA
MSDIO, MSBS, MSSCLK
FAD0 to FAD7, FCLE,
FALE, FWE, FRE, FWP,
FCE0, FCE1
VDIODF = 2.7V,
IOH = –4.0mA
VDIODF – 0.4
V
PA0/ PWM, PB, PD to PG,
PI0 to PI6, PJ to PR
VDIO = 2.7V,
IOL = 2.0mA
0.4
0.4
0.4
V
V
V
1
VDIOMS = 2.7V,
IOL = 2.0mA
PI7
VDIODF = 2.7V,
IOL = 2.0mA
FRB0, FRB1
PA1/ SDA, PA2/SCL,
D0 to D15, PC0/SCK0,
PC1/SO0, PC2, PC3,
TXDPLS, TXDMNS, TXENL,
SUSPEND, TXD0, TXD1,
Low level
output
voltage
VOL
SCK1, SO1, BEEP, DACK0, VDIO = 2.7V,
0.4
0.4
V
V
DACK1, DADT, LRCK,
XBCK, FS256, MUTFGL,
MUTFGR, RE, LWR/LB,
UWR/UB, WE, CS0, CS1,
CS5 to CS7, A0 to A23,
IOL = 4.0mA
2
KDO, KCLK, KCS
VDIOJT = 2.7V,
IOL = 4.0mA
TDO
– 30 –
CXR704060
Item
Symbol
Pins
Conditions
Min.
Typ.
Max. Unit
VDIOUS = 3.0V,
IOL = 4.0mA
TRON
0.4
0.4
V
V
Low level
output
VDIOMS = 2.7V,
IOL = 4.0mA
MSDIO, MSBS, MSSCLK
VOL
voltage
FAD0 to FAD7, FCLE,
FALE, FWE, FRE, FWP,
FCE0, FCE1
VDIODF = 2.7V,
IOL = 4.0mA
0.4
V
VDIO = 2.7V,
VIL = VSS
–30
–30
–30
µA
PA to PG, PI0 to PI6,
PJ to PR
VDIO = 3.6V,
VIL = VSS
–150 µA
µA
VDIOMS = 2.7V,
VIL = VSS
Input
current
3
IIL
PI7
VDIOMS = 3.6V,
VIL = VSS
–150 µA
µA
VDIODF = 2.7V,
VIL = VSS
FAD0 to FAD7
VDIODF = 3.6V,
VIL = VSS
–150 µA
PA to PG, PI0 to PI6,
PJ to PR, KDI, KRB, KDO,
KCLK, KCS,
TEST0 to TEST6, EVA,
VBUS
VDIO = 3.6V,
VI = 3.6V
10
µA
VDIOJT = 3.3V,
VI = 3.3V
TDO
10
10
10
µA
µA
µA
VDIOUS = 3.45V,
VI = 3.45V
TRON
3
IZH
PI7, MSDIO, MSBS,
MSSCLK, MSINS
VDIOMS = 3.6V,
VI = 3.6V
FAD0 to FAD7, FCLE,
FALE, FWE, FRE, FWP,
FCE0, FCE1, FRB0, FRB1
VDIODF = 3.6V,
VI = 3.6V
10
µA
I/O
leakage
current
AVDAD = 3.3V,
VI = 3.3V
AN0 to AN7
10
10
µA
µA
VDBK = 1.3V,
VI = 1.3V
RAMBK, RST
PA to PG, PI0 to PI6,
PJ to PR, KDI, KRB, KDO,
KCLK, KCS,
TEST0 to TEST6, EVA,
VBUS
VDIO = 3.6V,
VI = 0V
–10
µA
VDIOJT = 3.3V,
VI = 0V
IZL
TDO
–10
–10
–10
µA
µA
µA
VDIOUS = 3.45V,
VI = 0V
TRON
PI7, MSDIO, MSBS,
MSSCLK, MSINS
VDIOMS = 3.6V,
VI = 0V
– 31 –
CXR704060
Symbol
Pins
Conditions
Min.
Typ.
Max. Unit
Item
FAD0 to FAD7, FCLE,
FALE, FWE, FRE, FWP,
FCE0, FCE1, FRB0, FRB1
VDIODF = 3.6V,
VI = 0V
–10
µA
I/O
leakage
current
IZL
AVDAD = 3.3V,
VI = 0V
AN0 to AN7
–10
–10
µA
µA
VDBK = 1.3V,
VI = 0V
RAMBK, RST
PA to PG, PI to PR,
AN0 to AN7, FAD0 to FAD7,
FRB0, FRB1, MSDIO,
MSINS, KRB, KDI, EVA,
TEST0 to TEST4, RAMBK,
RST
Clock 1MHz
0V except the
measured pins
Input
capacitance
CIN
11
pF
1
2
3
When used as PA0/PWM, PB, PD to PG and PI to PO, specified at IOH = –2.0mA and IOL = 2.0mA.
When used as PA1/SDA, PA2/SCL, PC and dual function pins, specified at IOH = –4.0mA and IOL = 4.0mA.
The PA to PG, PI to PR and FAD0 to FAD7 pins specify the input current when the pull-up resistor is
selected, and specify the leakage current when non-resistor is selected.
(Topr = –20 to +70°C, DVDD = 1.1 to 1.3V, DVss = 0V reference)
Item
Pins
Symbol
IDD1
Conditions
Min.
Typ.
Max. Unit
2
Main execution mode
fSRC = 22.58MHz crystal oscillation
1/2 frequency division (11.29MHz)
—
4.5
7.5
mA
mA
4
(C1 = C2 = 10pF)
3
Main execution mode
IDD2
IDDI
fSRC = 22.58MHz crystal oscillation
—
—
29
Supply
current
4
DVDD/VDBK
(C1 = C2 = 10pF)
1
Main idle mode
fSRC = 22.58MHz crystal oscillation
—
—
3.5
6.5
mA
µA
4
(C1 = C2 = 10pF)
IDDS1
IDDS2
Ta = 25°C (DVDD = 1.2V)
Stop mode
100
—
300
Ta = –20 to +50°C
1500
1
2
3
4
When all output pins are left open, this indicates the current flowing to DVDD and VDBK.
During ATRAC3 decoding operation.
When the arithmetic accelerator circuit is always operating.
C1 and C2 indicate the external capacitors attached to the EXTAL and XTAL pins, respectively.
– 32 –
CXR704060
AC Characteristics
(1) EXTAL pins
1) Automatic oscillation
(Topr = –20 to +70°C, DVDD = VDBK = 1.1 to 1.3V, AVDMO = 2.2 to 3.3V, AVSOSC = DVss = 0V reference)
Item
Symbol
Conditions
Min.
22.4
Typ.
Max.
22.8
Unit
Oscillation frequency
fSRC
22.5792
MHz
2) When inputting pulses to EXTAL pin
(Topr = –20 to +70°C, DVDD = VDBK = 1.1 to 1.3V, AVDMO = 2.2 to 3.3V, AVSOSC = DVss = 0V reference)
Item
Symbol
tWHX
tWLX
Conditions
Min.
16
Typ.
Max.
Unit
ns
ns
ns
V
High level pulse width
Low level pulse width
Pulse period
16
tCX
43.9
44.6
Input high level
VIHX
VILX
0.7AVDMO
Input low level
0.2AVDMO
7
V
Rise time, fall time
tR, tF
ns
Note) When the clock is supplied externally, input to the EXTAL pin and input an opposite phase clock to
the XTAL pin.
t
CX
t
WHX
tWLX
V
V
IHX
IHX – (VIHX – VILX) × 0.1
AVDMO/2
EXTAL
V
V
ILX + (VIHX – VILX) × 0.1
ILX
t
R
tF
Fig. 1. Main Clock Timing
– 33 –
CXR704060
(2) TEX pin
1) Automatic oscillation
(Topr = –20 to +70°C, DVDD = VDBK = 1.1 to 1.3V, AVDUO = 2.7 to 3.3V, AVSOSC = DVss = 0V reference)
Item
Symbol
Conditions
Min.
8
Typ.
Max.
16
Unit
Oscillation frequency
fTEX
MHz
2) When inputting pulses to TEX pin
(Topr = –20 to +70°C, DVDD = VDBK = 1.1 to 1.3V, AVDUO = 2.7 to 3.3V, AVSOSC = DVss = 0V reference)
Item
Symbol
tWHTX
tWLTX
tCTX
Conditions
Min.
25
Typ.
Max.
Unit
ns
ns
ns
V
High level pulse width
Low level pulse width
Pulse period
25
62.5
125
Input high level
VIHTX
VILTX
tR, tF
0.7AVDUO
Input low level
0.2AVDUO
7
V
Rise time, fall time
ns
Note) When the clock is supplied externally, input to the TEX pin and input an opposite phase clock to the
TX pin.
t
CTX
t
WHTX
tWLTX
VIHTX
V
IHTX – (VIHTX – VILTX) × 0.1
AVDUO/2
TEX
V
V
ILTX + (VIHTX – VILTX) × 0.1
ILTX
t
R
tF
Fig. 2. Sub Clock Timing
– 34 –
CXR704060
3) Serial transfer (CH0, CH1)
(Topr = –20 to +70°C, DVDD = 1.1 to 1.3V, VDIO = 2.7 to 3.3V, DVSS = 0V reference)
Item
Symbol
tKCY
Pins
SCK0
Conditions
Input mode
Min.
6/fPS2
1/fSCK
3/fPS2
0.5/fSCK – 5
–2/fPS2 + 5
35
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
SCK cycle time
SCK1
SCK0
SCK1
SI0
Output mode
—
tKH
tKL
Input mode
—
SCK high, low pulse
width
Output mode
—
SCLK input mode
SCLK output mode
SCLK input mode
SCLK output mode
SCLK input mode
SCLK output mode
—
SI input setup time
(for SCK↑)
tSIK
tKSI
tKSO
SI1
—
SI0
2/fPS2 + 5
0
—
SI input hold time
(for SCK↑)
SI1
—
3/fPS2 + 40
5
SO0
SO1
—
SCK↓ → SO delay time
—
Note 1) The load capacitance of the measurement pin is 75pF.
Note 2) fSCK: Serial clock
Note 3) fPS2: PS2 clock (fPS2 = fSRC/4)
Note 4) fSCK = fPS2/{2 × (Register setting value + 1)}: Register setting value (01h to FFh)
tKCY
tKL
tKH
SCK0
SCK1
tSIK
tKSI
SI0
SI1
Input data
tKSO
SO0
SO1
Output data
Fig. 3. Serial CH0 and CH1 Transfer Timing
– 35 –
CXR704060
4) Serial transfer (Memory Stick)
(Topr = –20 to +70°C, DVDD = 1.1 to 1.3V, VDIOMS = 2.7 to 3.6V, DVSS = 0V reference)
Item
Symbol
tKCY
Pins
Conditions
Min.
Max.
—
Unit
ns
ns
ns
ns
ns
ns
MSSCLK cycle time
MSSCLK
MSSCLK
MSBS
1000/fMSCK
tKH, tKL
tBSD
MSSCLK high, low pulse width
MSBS output delay time
MSDIO output delay time
MSDIO input setup time
MSDIO input hold time
500/fMSCK – 5
—
For MSSCLK↓
For MSSCLK↓
For MSSCLK↑
For MSSCLK↑
—
—
14
5
10
10
—
tDIOD
MSDIO
MSDIO
MSDIO
tDIOS
tDIOH
—
Note 1) The load capacitance is 26pF.
Note 2) The oscillation of the TEX pin is at 50% duty.
Note 3) fMSCK is as follows for fSRC from the main oscillation circuit or fTEX from the sub oscillation circuit.
Shift clock frequency division ratio
Main oscillation 1/2 frequency division
Main oscillation 1/4 frequency division
Sub oscillation
fMSCK [MHz]
fSRC/2
fSRC/4
fTEX
t
KCY
0.7VDIOMS
0.2VDIOMS
MSSCLK
t
KL
tKH
Bus state output
MSBS
t
BSD
MSDIO (output)
Output data
t
DIOD
MSDIO (input)
Input data
t
DIOS
tDIOH
Fig. 4. Memory Stick Transfer Timing
– 36 –
CXR704060
5) Flash memory interface characteristics
(Topr = –20 to +70°C, DVDD = 1.1 to 1.3V, VDIODF = 2.7 to 3.3V, DVSS = 0V reference)
Item
Symbol
tRECY
tRSFA
Pins
FRE
Conditions
Min.
Max.
—
Unit
ns
FRE low pulse width
FRE↑ setup time
FRE↑ hold time
T × (RSTB setting value) – 10
FAD[7:0]
FAD[7:0]
FWE
35
—
ns
tRHFA
0
—
ns
FEW low pulse width
tWECY
T × (WSTB setting value) – 10
—
ns
T × (WSTP setting value +
WSTB setting value) – 10
FWE↑ setup time
FWE↑ hold time
tWSFA
tWHFA
FAD[7:0]
FAD[7:0]
—
—
ns
ns
T × (WHLD setting value) – 10
Note 1) "T" indicates the 1 cycle (1/fSRC) of the system clock.
Note 2) RSTB, WSTB, WSTP and WHLD indicate the register set to the flash memory interface WE/RE
timing register (FIWERETR).
See the table below for allowable setting values.
Note 3) The load capacitance of the measurement pin is 75pF.
RSTB, WSTB, WSTP and WHLD setting value
Item
Bits within FIWERETR register Allowable setting values
WSTP
WSTB
WHLD
RSTB
[27:24]
[23:20]
[19:16]
[7:4]
0h to Fh
0h to Fh
0h to Fh
0h to Fh
– 37 –
CXR704060
• During Read
t
RECY
FRE
VDIODF/2
t
RSFA
tRHFA
FAD[7:0]
• During Write
t
WECY
FWE
VDIODF/2
t
WSFA
tWHFA
FAD[7:0]
Fig. 5. Flash Memory Interface Transfer Timing with ECC
– 38 –
CXR704060
6) Bus interface unit (BIU) characteristics
• 2-cycle access AC characteristics parameter in write operation
(Topr = –20 to +70°C, DVDD = 1.1 to 1.3V, VDIO = 2.7 to 3.3V, DVSS = 0V reference)
Item
Symbol
tADULD1
Min.
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
Address setup time for UWR (UB) and LWR (LB) ↓
CS↓ and WE↓ setup time for UWR (UB) and LWR (LB) ↓
Address hold time for UWR (UB) and LWR (LB) ↑
CS↑ and WE↑ hold time for UWR (UB) and LWR (LB) ↑
UWR (UB) and LWR (LB) low pulse width
3/2fSRC – 5
tCWULD1 3/2fSRC – 5
1/2fSRC – 5
tULCWD1 1/2fSRC – 5
—
tULADD1
—
—
tWUL1
tDULD1
tDD1
1/fSRC
1/2fSRC – 5
0
—
Data setup time for UWR (UB) and LWR (LB) ↓
Data hold time for CS↑ and WE↑
—
—
Note) The load capacitance of the measurement pin is 75pF.
Tw
T1
T2
Address
CS, WE
t
ADULD1
tULADD1
t
CWULD1
tULCWD1
t
WUL1
UWR, UB,
LWR, LB
RD
t
DULD1
tDD1
D15 to D0
Valid
Fig. 6. 2-cycle Access Basic Timing in Write Operation
– 39 –
CXR704060
• 3-cycle access AC characteristics parameter in write operation
(Topr = –20 to +70°C, DVDD = 1.1 to 1.3V, VDIO = 2.7 to 3.3V, DVSS = 0V reference)
Item
Symbol
tADULD2
tCWULD2
tULADD2
tULCWD2
tWUL2
Min.
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
2/fSRC – 5
2/fSRC – 5
1/fSRC – 5
1/fSRC – 5
1/fSRC
Address setup time for UWR (UB) and LWR (LB) ↓
CS↓ and WE↓ setup time for UWR (UB) and LWR (LB) ↓
Address hold time for UWR (UB) and LWR (LB) ↑
CS↑ and WE↑ hold delay time for UWR (UB) and LWR (LB) ↑
UWR (UB) and LWR (LB) low pulse width
—
—
—
—
tDULD2
tDD2
1/fSRC – 5
0
—
Data setup time for UWR (UB) and LWR (LB) ↓
Data hold time for CS↑ and WE↑
—
Note) The load capacitance of the measurement pin is 75pF.
Tw
T1
T2
T3
Address
CS, WE
t
ADULD2
tULADD2
t
CWULD2
tULCWD2
t
WUL2
UWR, UB,
LWR, LB
RD
t
DULD2
tDD2
D15 to D0
Valid
Fig. 7. 3-cycle Access Basic Timing in Write Operation
– 40 –
CXR704060
• 2-cycle access AC characteristics parameter in read operation
(Topr = –20 to +70°C, DVDD = 1.1 to 1.3V, VDIO = 2.7 to 3.3V, DVSS = 0V reference)
Item
Symbol
Min.
Max. Unit
Address, CS and WE setup time for UWR (UB) and LWR (LB) ↓
UWR (UB) and LWR (LB) low pulse width
tADULD3 1/2fSRC – 5
tWUL3 1/fSRC
—
—
—
—
—
ns
ns
ns
ns
ns
Address, CS and WE hold time for UWR (UB), LWR (LB) ↓ and RD↓ tULADD3 1/2fSRC – 5
Data setup time for UWR (UB), LWR (LB) ↑ and RD↑
Data hold time for UWR (UB), LWR (LB) ↑ and RD↑
tRDS1
tRDH1
1/2fSRC + 23
0
Note) The load capacitance of the measurement pin is 75pF.
T1
T2
Address
CS, WE
tADULD3
tWUL3
tULADD3
UWR, UB,
LWR, LB, RD
tRDS1
tRDH1
D15 to D0
Valid data in
Fig. 8. 2-cycle Access Basic Timing in Read Operation
– 41 –
CXR704060
• 3-cycle access AC characteristics parameter in read operation
(Topr = –20 to +70°C, DVDD = 1.1 to 1.3V, VDIO = 2.7 to 3.3V, DVSS = 0V reference)
Item
Symbol
Min.
Max.
—
Unit
ns
Address, CS and WE setup time for UWR (UB), LWR (LB) ↓ and RD↓ tADULD4 1/fSRC – 5
UWR (UB) and LWR (LB) low pulse width
tWUL4
1/fSRC
—
ns
Address, CS and WE hold time for UWR (UB), LWR (LB) ↓ and RD↓
Data setup time for UWR (UB), LWR (LB) ↑ and RD↑
Data hold time for UWR (UB), LWR (LB) ↑ and RD↑
tULADD4 1/fSRC – 5
—
ns
tRDS2
tRDH2
24
0
—
ns
—
ns
Note) The load capacitance of the measurement pin is 75pF.
T1
T2
T3
Address
CS, WE
t
ADULD4
t
WUL4
tULADD4
UWR, UB,
LWR, LB, RD
t
RDS2
tRDH2
Valid data in
D15 to D0
Fig. 9. 3-cycle Access Basic Timing in Read Operation
– 42 –
CXR704060
7) A/D converter characteristics
(Topr = –20 to +70°C, DVDD = 1.1 to 1.3V, AVDAD = 2.2 to 3.0V, DVss = 0V, AVSAD = 0V reference)
Item
Symbol
Pins
Min.
—
Typ.
—
Max.
10
Unit
Bits
LSB
LSB
LSB
µs
Resolution
—
Absolute error
—
—
—
±7
Differential linearity error
Integral linearity error
Conversion time
—
—
—
±1
—
—
—
±3
tCONV
tSAMP
VIAN
—
—
19/fPS4
—
—
20/fPS4
—
Sampling time
3/fPS4
—
µs
Analog input voltage
AN0 to AN7
0
AVDAD
V
Note) fPS4 is fSRC/16 [MHz] relative to the main oscillation circuit output fSRC.
Conversion time indicates the time required from the start of conversion when one channel is selected
until the ADC interrupt request is generated, and also includes the sampling time.
Differential linearity error
(Code center interval offset)
A/D conversion
line
3FFh
3FEh
A/D conversion
results
Absolute error
Integral linearity error
(Code center offset from AD conversion line)
001h
000h
AVDAD
Analog input voltage
Analog input voltage
Fig. 10. Definition of A/D Converter Terms
– 43 –
CXR704060
Internal DAC Specifications
1) Digital filter characteristics
Pass band
Stop band
0 [Hz] to 20 [kHz]
24.1 to 328.7 [kHz]
±0.03 [dB] or less
54 [dB] or more
Pass band ripple
Stop band attenuation
2) Analog characteristics
(AVDDA = 2.4V, Ta = 25°C)
Item
Min.
—
Typ.
92
Max.
—
Unit
dB
S/N
THD + N
—
0.015
93
—
%
Dynamic range
—
—
dB
Gain difference between channels
—
—
10
—
0.1
0.15
—
dB or less
Vrms
kΩ or more
kHz
1
Output voltage
666.2
—
Output load resistor
—
Analog filter cutoff frequency
90
—
1
The output voltage is approximately 0.8AVDDA [Vp-p].
– 44 –
CXR704060
Package Outline
Unit: mm
208PIN TFLGA
0.20
S A
13.0
X
PIN 1 INDEX
1.1MAX
0.1 MAX
x4
0.15
3- 1.0
(0.55)
1.075
0.65
DETAIL X
A
208– φ0.35 ± 0.05
V
U
T
M
φ0.08
AB
S
R
P
N
M
B
L
K
J
H
G
F
E
D
C
B
A
1
1 1
1
11 12 3 4 5 16 7 8
4 5 6 7 8 9 10
1
1 2
3
0.325
0.975
1.0
PACKAGE STRUCTURE
C0.3
ORGANIC SUBSTRATE
PACKAGE MATERIAL
TERMINAL TREATMENT
TERMINAL MATERIAL
PACKAGE MASS
(0.55)
1.075
TFLGA-208P-01
NICKEL & GOLD PLATING
SONY CODE
EIAJ CODE
COPPER
0.39g
P-TFLGA-208-13.0x13.0-0.65
JEDEC CODE
Sony Corporation
– 45 –
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