CXA3236N [SONY]

All Band TV Tuner IC with On-chip PLL; 全波段电视调谐器IC具有片上PLL


型号：	CXA3236N
厂家：	SONY CORPORATION
描述：	All Band TV Tuner IC with On-chip PLL 全波段电视调谐器IC具有片上PLL 电视
文件：	总23页 (文件大小：313K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CXA3235/3236N

All Band TV Tuner IC with On-chip PLL

Description

30 pin SSOP (Plastic)

The CXA3235/3236N is a monolithic TV tuner IC

which integrates local oscillator and mixer circuits for

VHF band, local oscillator and mixer circuits for UHF

band, an IF amplifier and a tuning PLL onto a single

chip, enabling further miniaturization of the tuner.

The PLL on this IC supports the I²C bus format.

Features

• Low noise figure

Absolute Maximum Ratings (Ta = 25 °C)

• Low power consumption (5 V, 54 mA typ.)

• On-chip tuning PLL (I²C bus format)

• Selection of frequency steps 31.25 kHz, 50 kHz

and 62.5 kHz

• Supply voltage VCC1,VCC2

–0.3 to +5.5

VCC3

–0.3 to +10.0

• Storage temperature

Tstg

• Allowable power dissipation

–55 to +150

880

°C

• On-chip 4-output band switch

Applications

• TV tuners

(when mounted on a substrate)

• VCR tuners

• CATV tuners

Operating Conditions

• Supply voltage VCC1, VCC2 4.75 to 5.30

VCC3

4.75 to 9.45

Structure

• Operating temperature

Topr

Bipolar silicon monolithic IC

–25 to +75

°C

Note) Electrostatic discharge strength is weak, and care should be taken in handling this IC.

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by

any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the

operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

—1—

E97943A81-TE

CXA3235/3236N

Block Diagram and Pin Configuration

30 VCC3

SCL

I²C BUS

Receiver

Shift

Divider

1/512,640,1024

REF

OSC

SDA

REFOSC

ADSW

FMT

BVL

BVH

CPO

CPE

Phase

Detector

Charge

Pump

Band

Driver

LOCK

Det

LOCK

Divider

14/15bit

IF OUT

GND

USW

Prescaler

1/8

Bias

VCC1

V.REG

VCC2

IF AMP

Buffer

MIXout1

MIXout2

UOSCB2

UOSCE2

UOSCE1

UHF

OSC

GND1

Buffer

UOSCB1

VHF

MIX

VHFin

VOSC2

GND

VHF

OSC

UHFin1 14

16 VOSC1

UHF

MIX

UHFin2

—2—

CXA3235/3236N

Pin Description

Pin voltage

(V)

Symbol

No.

Equivalent circuit

Description

VCC2

100k

SCL

—

Clock input.

VCC2

100k

SDA

—

Data I/O.

VCC2

150k

50k

Address selection.

1.25

ADSW

This pin controls bits 2 and 1 of

the address byte.

(when open)

4 : Output for FM TRAP.

5 : Power supply output for

VL band.

FMT

BVL

VCC3

20k

6 : Power supply pin for VH

band.

ON : VCC3

OFF : 0

7 : Power supply output for

UHF band.

BVH

The pin corresponding to the

selected band goes High.

V^CC1

Analog circuit power supply.

Mixer outputs.

MIXout1

MIXout2

GND1

—

Analog circuit GND.

—3—

CXA3235/3236N

No.

Pin voltage

(V)

Symbol

Equivalent circuit

Description

Pin used for selecting a

frequency step mode.

Any of the five modes can be

selected by applying an input

voltage.

VCC2

1.5

(when open)

120k

2.3

(VHF)

50k

VHF input.

VHFin

The input format is unbalanced

input.

(UHF)

(VHF)

2.3

UHFin1

UHFin2

VOSC1

UHF inputs.

(UHF)

The input method can be

selected from balanced input

or unbalanced input.

(VHF)

2.3

(UHF)

600

(VHF)

3.1

VCC1

(UHF)

3.5

External resonance circuit

connection for VHF oscillator.

(VHF)

5.0

15p

VOSC2

GND

(UHF)

—

GND

3.2

(VHF)

2.9

UOSCB1

(UHF)

—

(VHF)

2.4

VCC1

UOSCE1

UOSCE2

UOSCB2

(UHF)

—

External resonance circuit

connection for UHF oscillator.

(VHF)

2.4

(UHF)

3.2

(VHF)

2.9

(UHF)

—4—

CXA3235/3236N

No.

Pin voltage

Symbol

Equivalent circuit

Description

(V)

—

VCC2

—

PLL circuit power supply.

PLL circuit GND.

GND2

—

VCC1

IFOUT

2.3

IF output.

VCC2

5.0

40k

(Lock)

LOCK detection.

LOCK

High when locked, Low when

unlocked.

0.2

(UNLock)

VCC2

NPN transistor connection for

varicap diode drive.

CPE

CPO

0.6

2.0

200

500

20k

Charge pump output.

Connect a loop filter.

60k

30p

Crystal connection for

reference oscillator.

REFOSC

4.3

—

Power supply for external

supply.

V^CC3

—5—

CXA3235/3236N

Electrical Characteristics

See the Electrical Characteristics Measurement Circuit.

Circuit Current

(VCC=5 V, Ta=25 °C)

Item

Symbol

Measurement conditions

VCC1 current, Band switch output

open during VHF operation

VCC1 current, Band switch output

open during UHF operation

VCC2 current

Min.

Typ.

Max.

Unit

Circuit current A

AICCV

AICCU

DICC

Circuit current D

OSC/MIX/IF Amplifier Block

Item

Symbol

Measurement conditions

VHF operation fRF = 55 MHz

VHF operation fRF = 360 MHz

UHF operation fRF = 360 MHz

UHF operation fRF = 800 MHz

VHF operation fRF = 55 MHz

VHF operation fRF = 360 MHz

UHF operation f^RF= 360 MHz

UHF operation fRF = 800 MHz

VHF operation

Min.

Typ.

Max.

Unit

Conversion gain

CG1

CG2

CG3

CG4

NF1

NF2

NF3

NF4

Noise figure

8.5

9.5

12.5

13.5

1 % cross

CM1

CM2

CM3

CM4

101

100

dBµ

modulation

fD = 55 MHz, fUD = ±12 MHz

VHF operation

fD = 360 MHz, fUD = ±12 MHz

UHF operation

fD = 360 MHz, fUD = ±12 MHz

UHF operation

dBµ

dBm

kHz

fD = 800 MHz, fUD = ±12 MHz

50 Ω load saturation output

VHF operation fOSC = 100 MHz

∆f from 3 s to 3 min after switch ON

VHF operation fOSC = 405 MHz

∆f from 3 s to 3 min after switch ON

UHF operation fOSC = 405 MHz

∆f from 3 s to 3 min after switch ON

UHF operation fOSC = 845 MHz

∆f from 3 s to 3 min after switch ON

VHF operation fOSC = 100 MHz

∆f when VCC 5 V changes ±5 %

VHF operation fOSC = 405 MHz

∆f when VCC 5 V changes ±5 %

UHF operation fOSC = 405 MHz

∆f when VCC 5 V changes ±5 %

UHF operation fOSC = 845 MHz

∆f when VCC 5 V changes ±5 %

Maximum output power Pomax

+10

Switch ON drift

∆fsw1

∆fsw2

∆fsw3

±300

±400

±500

±150

±250

±200

±250

kHz

∆fsw4

Supply voltage drift

∆fst1

∆fst2

∆fst3

∆fst4

—6—

CXA3235/3236N

Measured value for untuned inputs.

Noise figure is the direct-reading value of NF meter in DSB.

Desired signal (fD) input level is –30 dBm. Undesired signal (fUD) is 100 kHz, 30 % AM at ±12 MHz.

The measurement value is undesired signal level, it measured with a spectrum analyzer at S/I=46 dB.

Value when the PLL is not operating.

PLL Block

Item

SDA, SCL

Symbol

Measurement conditions

Min.

Typ.

Max.

Unit

“H” level input voltage VIH

“L” level input voltage VIL

“H” level input current IIH

“L” level input current IIL

SDA “L” output voltage LSDA

Clock input hysteresis CIHYS

VCC

1.5

GND

VIH = VCC

–0.1

–2

µA

VIL = GND

–1

Sink current = 3 mA

0.4

0.25

0.4

0.65

0.5

Clock rate

CIRATE

MHz

CPO (charge pump)

Output current 1

Output current 2

Leak current 1

Leak current 2

REFOSC

ICPO1

Byte4/Bit6 = 0

Byte4/Bit6 = 1

±35

±50

±75

±300

µA

I^CPO2

±140

±200

LeakCP1 Byte4/Bit6 = 0

LeakCP2 Byte4/Bit6 = 1

100

Oscillator

FXTOSC

MHz

frequency range

Input capacitance

Drive level

CXTOSC

VXTOSC

17.5

200

20.5

400

mVp-p

BVL, BVH, BU (Band SW)

Output current

Saturation voltage

Leak current

IBS1

When ON

–25

200

µA

VSAT1

When ON Sink current = 20 mA

100

0.5

LeakBS1 When OFF

FMT (Band SW)

Output current

Saturation voltage

Leak current

IBS2

When ON

–7

150

0.1

µA

VSAT2

When ON Sink current = 5 mA

LeakBS2 When OFF

0.03

Bus timing

SCL clock frequency fSCL

400

kHz

Start waiting time

Start hold time

Low hold time

High hold time

Start setup time

Data hold time

Data setup time

Rise time

tWSTA

See Timing Chart on Page 15.

—7—

1300

600

tHSTA

tLOW

tHIGH

tSSTA

tHDAT

tSDAT

1300

600

1300

600

300

Fall time

Start setup time

tSSTO

600

CXA3235/3236N

Electrical Characteristics Measurement Circuit

+30V

22k

8200p

1.2k

47k 0.047µ

33p

BVL

BVH

3.2ø

5.5t

47k

+5V

47k

2SC2785

47k

3.3µ

3.0ø

2.5t

2.5ø2.5t

0.5p

LOCK IF OUT

150p

1T363

47k

1T363

47k

XTAL

4MHz

1T362

16p

47k

56p

100p

47k

CXA3235/3236N

4.5t

100

4.5t

SCL

SDA ADSW

56p 56p

FMT

BVL

BVH BU

VHF IN

UHF IN

3.3µ

+5V

—8—

CXA3235/3236N

Description of Functions

The CXA3235/3236N is a terrestrial wave broadcast tuner IC which converts frequencies to IF in order to

tune and detect only the desired reception frequency of VHF, CATV and UHF band signals.

In addition to the mixer, local oscillator and IF amplifier circuits required for frequency conversion to IF, this

IC also integrates a PLL circuit for local oscillator frequency control onto a single chip.

The functions of the various circuits are described below.

1. Mixer circuit

This circuit outputs the frequency difference between the signal input to VHFIN or UHFIN and the local

oscillation signal.

2. Local oscillator circuit

A VCO is formed by externally connecting an LC resonance circuit composed of a varicap diode and

inductance.

3. IF amplifier circuit

This circuit amplifies the mixer IF output, and consists of an amplifier stage and low impedance output

stage.

4. PLL circuit

This PLL circuit fixes the local oscillator frequency to the desired frequency. It consists of a prescaler, main

divider, reference divider, phase comparator, charge pump and reference oscillator. The control format

supports the I²C bus format. The following five modes can be selected according to the combination of the

frequency division values of the main and reference dividers.

Mode

B-0

Main divider

15 bit

Reference divider

1024 fixed

B-1

14 bit

512 fixed

B-2

15 bit

640 fixed

B-3

15 bit

512 fixed

B-4

15 bit

512/1024 switching

—9—

CXA3235/3236N

Description of Analog Block Operation

VHF oscillator circuit

(See the Electrical Characteristics Measurement Circuit.)

• This circuit is a differential amplifier type oscillator circuit.

Pin 18 is the output and Pin 16 is the input.

Oscillation is performed by connecting an LC resonance circuit including a varicap to Pin 18 via coupled

capacitance, inputting to Pin 16 with feedback capacitance, and applying positive feedback.

• The amplifier between Pins 16 and 18 has an extremely high gain. Therefore, care should be taken to

avoid creating parasitic capacitance, resistance or other feedback loops as this may produce abnormal

oscillation.

VHF mixer circuit

• The mixer circuit employs a double balance mixer with little local oscillation signal leakage.

The input format is base input type, with Pin 12 grounded and the RF signal input to Pin 13.

• The RF signal is inserted from the oscillator, converted to IF frequency and output from Pins 9 and 10.

• Pins 9 and 10 are open collectors, so power must be supplied externally. The electric potential of Pins 9

and 10 at this time must be DC 4.0 V or more.

UHF oscillator circuit

• This oscillator circuit is designed so that two collector ground type Colpitts oscillators perform differential

oscillation operation via an LC resonance circuit including a varicap. Connect resonator capacitance

composing colpitts oscillators between Pins 19 and 20, Pins 20 and 21, and Pins 21 and 22.

• Then, LC resonance circuit comprising a varicap diode is connected across Pins 19 and 22.

UHF mixer circuit

• This circuit employs a double balance mixer like the VHF mixer circuit.

The input format is base input type, with Pins 14 and 15 as the RF input pins. The input method can be

selected from balanced input consisting of differential input to Pins 14 and 15 or unbalanced input

consisting of grounding Pin 14 via a capacitor and input to Pin 15.

• Pins 9 and 10 are the mixer outputs.

• Pins 9 and 10 are open collectors, so power must be supplied externally. The electric potential of Pins 9

and 10 at this time must be DC 4.0 V or more.

IF amplifier circuit

• The signals frequency converted by the mixer are output from Pins 9 and 10, and at the same time are

AC coupled inside the IC and input to the IF amplifier.

• Single-tuned filters are connected to Pins 9 and 10 in order to improve the interference characteristics of

the IF amplifier.

• The signal amplified by the IF amplifier is output from Pin 25.

The output impedance is approximately 75 Ω.

—10—

CXA3235/3236N

Description of PLL Block

The PLL on this IC supports the I²C bus control format. The control pins are as shown in the table below.

Symbol

ADSW

SCL

Description

Address selection

SCL input

SDA

SDA I/O

1) Mode Setting Method

The modes for each frequency step are set according to the MS pin voltage.

Main

divider

15 bit

14 bit

15 bit

Reference

divider

1024

512

Frequency

step

Mode

MS pin voltage

Reference frequency

B-0

B-1

B-2

B-3

0 to 0.15 VCC

OPEN

3.90625 kHz

7.8125 kHz

6.25 kHz

31.25 kHz

62.5 kHz

50 kHz

0.45 VCC to 0.55 VCC

0.65 VCC to 0.75 VCC

640

512

7.8125 kHz

7.8125 kHz/

6.25 kHz/

62.5 kHz

62.5 kHz/

50 kHz/

512/

B-4

0.85 VCC to VCC

15 bit

640/

1024

3.90625 kHz

31.25 kHz

Frequency step is for when X’tal OSC = 4 MHz.

2) Address Setting

The responding address can be changed according to the ADSW pin voltage, so that multiple PLL can

exist within one system.

Address

ADSW pin voltage

0 to 0.1 VCC

MA1

MA0

OPEN or 0.2 VCC to 0.3 VCC

0.4 VCC to 0.6 VCC

0.9 VCC to VCC

—11—

CXA3235/3236N

3) Programming

The VCO lock frequency is obtained according to the following formula.

fosc = fref × 8 × (32 M + S)

fosc: local oscillator frequency

fref : reference frequency

: prescaler fixed frequency division ratio

: main divider frequency division ratio

: swallow counter frequency division ratio

The variable frequency division ranges of M and S are as follows, and are set as binary.

32 ≤ M ≤ 1023 (32 ≤ M ≤ 511 for B-1 mode)

0 ≤ S ≤ 31

3-1) The CXA3235N control format is as follows.

3-1-1 : B-0/B-1/B-2/B-3 Modes

Write-mode : Slave Receiver

MSB

LSB

MODE

bit7

bit6

bit5

bit4

bit3

bit2

MA1

bit1

MA0

bit0

Address byte

Divider byte 1

Divider byte 2

Control byte

Band SW byte

BVL

FMT

BVH

X : Don’t care

M9 is “0” for B-1 mode.

3-1-2 : B-4 Mode

Write-mode : Slave Receiver

MSB

bit7

LSB

bit0

MODE

bit6

bit5

bit4

bit3

bit2

MA1

bit1

MA0

Address byte

Divider byte 1

Divider byte 2

Control byte

Band SW byte

BVL

FMT

BVH

X : Don’t care

—12—

CXA3235/3236N

3-2) The CXA3236N control format is as follows.

The BU and FMT data order is switched for the CXA3235N.

3-2-1 : B-0/B-1/B-2/B-3 Modes

Write-mode

: Slave Receiver

MSB

LSB

MODE

bit7

bit6

bit5

bit4

bit3

bit2

MA1

bit1

MA0

bit0

Address byte

Divider byte 1

Divider byte 2

Control byte

BVL

Band SW byte

FMT

BVH

X : Don’t care

M9 is “0” for B-1 mode.

3-2-2 : B-4 Mode

Write-mode

: Slave Receiver

MSB

bit7

LSB

bit0

MODE

bit6

bit5

bit4

bit3

bit2

MA1

bit1

MA0

Address byte

Divider byte 1

Divider byte 2

Control byte

BVL

Band SW byte

FMT

BVH

X : Don’t care

: Acknowledge bit

MA0, MA1 : address setting

M0 to

S0 to

: main divider frequency division ratio setting

: swallow counter frequency division ratio setting

: test mode selection

(when “1”)

: charge pump OFF

: varicap output OFF

: charge pump current switching

: VL band switch control

(200 µA when “1”, 50 µA when “0”)

(output PNP Tr ON when “1”)

BVL

BVH

FMT

: VH band switch control

: FM trap switch control

: UHF band switch control

R0, R1

: Reference divider frequency division ratio setting

—13—

CXA3235/3236N

Reference Divider Frequency Division Ratio Table

Reference divider

1024

512

640

X : Don’t care

3-3) The read data format is as shown below.

Read-mode

MODE

Address byte

Status byte

: Slave Transmitter

bit7

bit6

bit5

bit4

bit3

bit2

MA1

bit1

MA0

bit0

: acknowledge bit

: power-on reset

: lock detection signal

MA0, MA1 : address setting

—14—

CXA3235/3236N

I²C Bus Timing Chart

tWSTA

SDA

tSSTO

tSSTA

SCL

tHSTA

tLOW

tHIGH

tSDAT

tHDAT

START

CLOCK

DATACHANGE

STOP

tSSTA =Start setup time

tWSTA =Start waiting time

tHSTA =Start hold time

tSDAT =Data setup time

tHDAT =Data hold time

tSSTO =Stop setup time

tLOW =LOW clock pulse width

tHIGH =HIGH clock pulse width

=Rise time

=Fall time

—15—

CXA3235/3236N

Circuit current vs. Supply voltage 1

Circuit current vs. Supply voltage 2

UHF

VHF

4.7

4.8 4.9 5.0

5.1 5.2 5.3

5.4

4.7 4.8 4.9 5.0

5.1 5.2 5.3

5.4

VCC1 - Supply voltage [V]

VCC2 - Supply voltage [V]

Band SW output voltage vs. Output current (BU, BVH, BVL)

9.2

Band SW output voltage vs. Output current (FMT)

9.2

9.0

8.8

8.6

9.0

VCC3=9V

8.8

8.6

5.0

4.8

4.6

4.4

VCC3=5V

4.8

VCC3=5V

4.6

4.4

Output current [mA]

I/O characteristics (Untuned input)

–20

–40

–60

fRF=100MHz (VHF)

fRF=450MHz (UHF)

fIF is both f=45MHz

–60

–50

–40

–30

–20

–10

RF input level [dBm]

—16—

CXA3235/3236N

Conversion gain vs. Reception frequency (Untuned input)

Noise figure vs. Reception frequency (Untuned input, in DSB)

fIF=45MHz

UHF

VHF (Low)

VHF (Low) VHF (High)

VHF (High)

UHF

100 200 300 400 500 600 700 800 900

Reception frequency [MHz]

100 200 300 400 500 600 700 800 900

Reception frequency [MHz]

Next adjacent cross modulation vs. Reception frequency

(Untuned input)

Oscillation frequency power supply fluctuation (PLL off)

120

100

400

V^CC+5%

V^CC–5%

(V^CC=5V)

300

200

100

VHF (High)

VHF (Low)

UHF

fIF=45MHz

fUD=fD+12MHz

f^UD=fD–12MHz

(100kHz, 30% AM)

–100

–200

–300

–400

100 200 300 400 500 600 700 800 900

Reception frequency [MHz]

100 200 300 400 500 600 700 800 900

Oscillation frequency [MHz]

PCS beat characteristics

+20

+10

fIF

–10

–20

–30

–40

–50

–60

–70

–80

fLocal=129MHz

fP=83.25MHz

fC=86.83MHz, (fP–12dB)

fS=87.75MHz, (fP–1.7dB)

fIF=45.75MHz

fBeat

fBeat=fIF±920kHz

–30

–20

–10

+10

+20

SG output level [dBm]

(fP level)

—17—

CXA3235/3236N

Tuning Response Time

VHF (Low) 95MHz → VHF (High) 395MHz

T=70ms

5.0V/div

offset 10.0V

10,0000ms

20.0ms/div

–90,0000ms

110,000ms

UHF 413MHz → UHF 847MHz

T=70ms

5.0V/div

offset 10.0V

–90,0000ms

110,000ms

10,0000ms

20.0ms/div

—18—

CXA3235/3236N

RL=0dBm

10dB/div

IF output spectrum

VHF (Low)

fRF=55MHz

fLO=100MHz

RF input level : –40dBm

CENTER 45.0MHz

RES BW 1.0kHz

SPAN 100.0kHz

SWP 30.0s

VBW 10Hz

RL=0dBm

10dB/div

IF output spectrum

VHF (High)

fRF=350MHz

fLO=395MHz

RF input level : –40dBm

CENTER 45.0MHz

RES BW 1.0kHz

SPAN 100.0kHz

SWP 30.0s

VBW 10Hz

—19—

CXA3235/3236N

RL=0dBm

10dB/div

IF output spectrum

UHF (Low)

fRF=800MHz

fLO=845MHz

RF input level : –40dBm

CENTER 45.0MHz

RES BW 1.0kHz

SPAN 100.0kHz

SWP 30.0s

VBW 10Hz

—20—

CXA3235/3236N

VHF Input Impedance

j50

j25

j100

50MHz

1000p

S11

350MHz

–j25

–j100

–j50

j50

UHF Input Impedance

j25

j100

1000p

S11

350MHz

800MHz

–j25

–j100

–j50

—21—

CXA3235/3236N

IF output Impedance

j50

j25

j100

45MHz

–j25

–j100

–j50

—22—

CXA3235/3236N

Package Outline Unit : mm

30PIN SSOP (PLASTIC)

+ 0.2

1.25 – 0.1

9.7 ± 0.1

0.10

+ 0.1

0.22 – 0.05

+ 0.05

– 0.02

0.65

0.15

0.13

0.1 ± 0.1

0° to 10°

NOTE: Dimension “ ” does not include mold protrusion.

DETAIL A

PACKAGE STRUCTURE

PACKAGE MATERIAL

EPOXY RESIN

SOLDER/PALLADIUM

PLATING

LEAD TREATMENT

LEAD MATERIAL

PACKAGE MASS

SONY CODE

EIAJ CODE

SSOP-30P-L01

42/COPPER ALLOY

SSOP030-P-0056

JEDEC CODE

0.1g

NOTE : PALLADIUM PLATING

This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).

—23—

CXA3236N [SONY]

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SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E