CXA3202N [SONY]
TX Gain Control Amplifier; TX增益控制放大器
| 型号： | CXA3202N |
| 厂家： | 
SONY CORPORATION |
| 描述： | TX Gain Control Amplifier |
| 文件： | 总10页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXA3202N
TX Gain Control Amplifier
For the availability of this product, please contact the sales office.
Description
16 pin SSOP (Plastic)
CXA3202N is a TX gain control amplifier suitable
for CDMA cellular/PCS phone.
Features
• Wide gain control range
• Linear gain slope
• Wideband operation (50MHz to 300MHz)
• Very small package (16 Pin SSOP)
• Low voltage operation
• High output IP3
• Power save function included
Absolute Maximum Ratings
• Supply voltage
VCC
6
V
• Operating temperature
• Storage temperature
Topr –55 to +125 °C
Tstg –65 to +150 °C
• Allowable Power dissipation PD
• Supply voltage range
• Logic input voltage
330
mW
V
–0.3 to 6
–0.3 to VCC + 0.3 V
–0.3 to VCC + 0.3 V
• Signal input voltage
•
Differental signal input voltage
0 to 2.5
V
Operating Condition
Supply voltage
VCC
2.7 to 3.8
V
Applications
CDMA cellular/PCS phone
Structure
Bipolar silicon monolithic IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E97808-PS
CXA3202N
Block Diagram
CDMA IN
OUT
IF Input
IF Output
CDMA INX
OUTX
Gain control
GCTL
Supply Voltage
VCC1, 2
Bias
Driver
Ground
GND1, 2
PSV
Power Save
Pin Configuration
CDMA IN
1
2
3
4
5
6
7
8
16 GCTL
CDMA INX
NC
15 NC
14 VCC1
13
GND1
GND2
NC
VCC2
12 GND1
11 GND2
OUT
10
9
NC
OUTX
PSV
– 2 –
CXA3202N
Pin Description
Pin
Pin voltage
TYP (V)
Symbol
No.
Equivalent circuit
Description
1
2
CDMA IN
1.1
1.1
40k
40k
Differential input pins for CDMA
transmit IF signal.
GND
CDMA INX
1
2
3
6
7
No connection.
NC
15
4
12
GND1
GND2
0
0
Ground
Ground
5
11
VCC1
Power save function pin.
High: Active
Low: Power save
8
PSV
—
8
135k
GND
9
10
510
VCC2
510
9
OUTX
OUT
—
—
12.25k
12.25k
Differential output pins for transmit
IF signal.
Open collector output.
10
GND
Positive power supply for output
stage.
13
14
3.0
3.0
VCC2
VCC1
Positive power supply.
– 3 –
CXA3202N
Pin
No.
Pin voltage
TYP (V)
Equivalent circuit
Description
Symbol
VCC1
8k
8k
16 GCTL
—
Gain control pin.
16
6k
6k
GND
– 4 –
CXA3202N
Electrical Characteristics
(VCC = 3.0V, Ta = 27°C)
Min. Typ. Max. Unit
DC Characteristics
Parameter
Symbol
Conditions
15.7
18
10
5
21.5 mA
Current consumption 1
Current consumption 2
Input current pin 8H
Input current pin 8L
Input current pin 16H
Input current pin 16L
PSV high voltage
ICC1
Vpsv = 3.0V, Vgctl = 1.5V, Pin 13, 14
40
1
ICC2
Vpsv = 0 V, Vgctl = 1.5V, Pin 13, 14
IpsvH
IpsvL
IgctlH
IgctlL
VpsH
VpsL
Vpsv = 3.0V
Vpsv = 0 V
Vgctl = 3.0V
Vgctl = 0.5V
Pin 8
–15
µA
1
–1
2.5
V
0.5
PSV low voltage
Pin 8
AC Characteristics
(VCC = 3.0V, Ta = 27°C)
Unit
Min. Typ. Max.
Parameter
Symbol
Fr
Conditions
Operating frequency
range
50
13
300 MHz
21
f = 130.38MHz, level = –22.5dBm,
Vgctl = 2.3V
17
Gain 2.3
G2.3
–28 –24 –20
–58 –54 –50
–75 –70 –65
Gain 1.5
G1.5
G1.0
G0.7
GCLIN
Vgctl = 1.5V
dB
Gain 1.0
Vgctl = 1.0V
Gain 0.7
Vgctl = 0.7V
56
59
62 dB/V
CDMA Gain slope
Gain at Vgctl = 2.0V – Gain at Vgctl = 1.0V
1
G = 15dB
Input level 3rd order
intercept point
–8.5 –4.5
28
dBm
IIP3
NF
f1= 129.38MHz, f2 = 131.38MHz
Measure of 130.38MHz
1
G = 15dB
32
dB
Noise Figure
Measure of 130.38MHz
1 Adjust GCTL voltage, and set the overall gain to 15dB.
– 5 –
CXA3202N
Measurement Circuit
V16
V14
1k
1µ 2k
1
1
2
3
4
5
6
7
8
CDMA IN
CDMA INX
NC
GCTL 16
A16
A14
1000p
1000p
CDMA
INPUT
0.01µ
NC
15
2
VCC1 14
0.01µ
13
VCC2
GND1
GND2
NC
GND1 12
GND2 11
OUT 10
3
3
820n
820n
2.4k
1
NC
OUTPUT
V8
PSV
OUTX
9
A8
1 TOKO, Inc. B5FL 616DS-1135
2 Coilcraft, Inc. 1008HS-102TKBC
3 Coilcraft, Inc. 1008HS-821TKBC
– 6 –
CXA3202N
Application Circuit
VCC
Gain Control
Voltage
1000p
1000p
1k
1
2
3
4
5
6
7
8
CDMA IN
CDMA INX
NC
GCTL 16
CDMA
RX IF
INPUT
0.01µ
100p
0.01µ
NC
15
VCC1 14
13
VCC2
GND1
GND2
NC
GND1 12
GND2 11
OUT 10
1000p
NC
RX IF
OUTPUT
Active
Sleep
PSV
OUTX
9
1000p
Must be adjusting values to result a best impedance matching between BPF filter and this IC.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 7 –
CXA3202N
Design Reference Values
Single ended measurement
(VCC = 3.0V, Ta = 27°C)
Conditions
Typ.
10
Unit
kΩ
pF
Symbol
Item
Input resistance
Input capacitance
Output resistance
Output capacitance
Rin
0.98
6.0
Cin
f = 130.38MHz, Vgctl = 1.5V
kΩ
pF
Rout
Cout
0.92
Notes on Operation
1) This IC is a wideband amplifier with wide gain control range. The decouping capacitors between GND Pin
and VCC Pin should be as close to the IC as possible.
2) The resistors connected to Pins 9 and 10 should be as close to the IC as possible.
3) This IC assumes the excellent characteristics when the differential input impedance between Pins 1 and 2 is
500Ω. Refer to the Measurement Circuit for the external element settings, etc.
4) Pay attention to handling this IC because its electrostatic discharge strength is weak.
– 8 –
CXA3202N
IIP3
Sensitivity
15
10
5
40
20
VCC = 3.0V
VCC = 3.0V
0
–20
–40
–60
0
–5
–10
–15
T = –40°C
T = 27°C
T = 85°C
T = –40°C
T = 27°C
T = 85°C
–80
–100
–60
–40
–20
0
20
40
0
0.5
1
1.5
2
2.5
3
3.5
Power gain [dB]
Vgctl [V]
Noise Figure
Gain Error from Room Temp
100
90
80
70
60
50
40
30
20
6
4
VCC = 3.0V
VCC = 3.0V
2
0
–2
–4
–6
T = –40°C
T = 27°C
T = 85°C
T = –40°C
T = 85°C
–80
–60
–40
–20
0
20
–80
–60
–40
–20
0
20
40
Power gain [dB]
Power gain [dB]
– 9 –
CXA3202N
Package Outline
Unit: mm
16PIN SSOP (PLASTIC)
+ 0.2
1.25 – 0.1
5.0 ± 0.1
0.1
9
16
A
8
1
+ 0.05
0.15 – 0.02
0.65
+ 0.1
0.22 – 0.05
0.13
M
0.1 ± 0.1
0° to 10°
DETAIL A
NOTE: Dimension “ ” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SOLDER / PALLADIUM
PLATING
SONY CODE
EIAJ CODE
SSOP-16P-L01
SSOP016-P-0044
42/COPPER ALLOY
0.1g
JEDEC CODE
PACKAGE MASS
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
– 10 –
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