LAN8710A [SMSC]
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR Technology; 小尺寸MII / RMII 10/100以太网收发器， HP Auto-MDIX的和flexPWR技术
| 型号： | LAN8710A |
| 厂家： | 
SMSC CORPORATION |
| 描述： | Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR Technology |
| 文件： | 总82页 (文件大小：1172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LAN8710A/LAN8710Ai
Small Footprint MII/RMII 10/100 Ethernet
Transceiver with HP Auto-MDIX and
flexPWR® Technology
Datasheet
PRODUCT FEATURES
Highlights
Key Benefits
High-Performance 10/100 Ethernet Transceiver
Single-Chip Ethernet Physical Layer Transceiver
(PHY)
—
—
—
—
—
—
—
—
Compliant with IEEE802.3/802.3u (Fast Ethernet)
Compliant with ISO 802-3/IEEE 802.3 (10BASE-T)
Loop-back modes
Comprehensive flexPWR® Technology
—
—
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Flexible Power Management Architecture
LVCMOS Variable I/O voltage range: +1.6V to +3.6V
Integrated 1.2V regulator with disable feature
Auto-negotiation
Automatic polarity detection and correction
Link status change wake-up detection
Vendor specific register functions
Supports both MII and the reduced pin count RMII
interfaces
HP Auto-MDIX support
Small footprint 32-pin QFN lead-free RoHS compliant
package (5 x 5 x 0.9mm height)
Power and I/Os
—
—
—
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Various low power modes
Integrated power-on reset circuit
Two status LED outputs
Latch-Up Performance Exceeds 150mA per EIA/JESD
78, Class II
May be used with a single 3.3V supply
Target Applications
Set-Top Boxes
Networked Printers and Servers
Test Instrumentation
—
Additional Features
—
LAN on Motherboard
Ability to use a low cost 25Mhz crystal for reduced BOM
Embedded Telecom Applications
Video Record/Playback Systems
Cable Modems/Routers
DSL Modems/Routers
Packaging
—
32-pin QFN (5x5 mm) Lead-Free RoHS Compliant
package with MII and RMII
Environmental
—
Extended commercial temperature range
(0°C to +85°C)
Industrial temperature range version available
(-40°C to +85°C)
Digital Video Recorders
IP and Video Phones
—
Wireless Access Points
Digital Televisions
Digital Media Adaptors/Servers
Gaming Consoles
POE Applications (Refer to SMSC Application Note 17.18)
SMSC LAN8710A/LAN8710Ai
Revision 1.4 (08-23-12)
DATASHEET
®
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR Technology
Datasheet
Order Numbers:
LAN8710Ai-EZK for 32-pin QFN lead-free RoHS compliant package (-40 to +85°C temp)
LAN8710Ai-EZK-TR for 32-pin QFN lead-free RoHS compliant package (-40 to +85°C temp)
LAN8710A-EZC for 32-pin QFN lead-free RoHS compliant package (0 to +85°C temp)
LAN8710A-EZC-TR for 32-pin QFN lead-free RoHS compliant package (0 to +85°C temp)
TR indicates tape & reel option. Reel size is 4,000.
This product meets the halogen maximum concentration values per IEC61249-2-21
For RoHS compliance and environmental information, please visit www.smsc.com/rohs
Please contact your SMSC sales representative for additional documentation related to this product
such as application notes, anomaly sheets, and design guidelines.
Copyright © 2012 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for
construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC
reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications
before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent
rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated
version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not
designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property
damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of
this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered
trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
The Microchip name and logo, and the Microchip logo are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE
OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL
DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT;
TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD
TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Revision 1.4 (08-23-12)
2
SMSC LAN8710A/LAN8710Ai
DATASHEET
®
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR Technology
Datasheet
Table of Contents
Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1
1.2
General Terms and Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 2 Pin Description and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
2.2
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Chapter 3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1
Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.1
3.1.2
3.1.3
3.1.4
100BASE-TX Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
100BASE-TX Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
10BASE-T Transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
10BASE-T Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2
Auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.1
3.2.2
3.2.3
3.2.4
Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Restarting Auto-negotiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Disabling Auto-negotiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Half vs. Full Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.3
3.4
HP Auto-MDIX Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MAC Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.4.1
3.4.2
3.4.3
MII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
RMII. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
MII vs. RMII Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.5
3.6
Serial Management Interface (SMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Interrupt Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.6.1
3.6.2
Primary Interrupt System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Alternate Interrupt System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.7
Configuration Straps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
PHYAD[2:0]: PHY Address Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
MODE[2:0]: Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
RMIISEL: MII/RMII Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
REGOFF: Internal +1.2V Regulator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
nINTSEL: nINT/TXER/TXD4 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.8
Miscellaneous Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.8.1
3.8.2
3.8.3
3.8.4
3.8.5
3.8.6
3.8.7
3.8.8
3.8.9
LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Variable Voltage I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Isolate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Collision Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Link Integrity Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Loopback Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.9
Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.9.1
3.9.2
3.9.3
3.9.4
3.9.5
Simplified System Level Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Power Supply Diagram (1.2V Supplied by Internal Regulator) . . . . . . . . . . . . . . . . . . . . 46
Power Supply Diagram (1.2V Supplied by External Source). . . . . . . . . . . . . . . . . . . . . . 47
Twisted-Pair Interface Diagram (Single Power Supply). . . . . . . . . . . . . . . . . . . . . . . . . . 48
Twisted-Pair Interface Diagram (Dual Power Supplies) . . . . . . . . . . . . . . . . . . . . . . . . . 49
SMSC LAN8710A/LAN8710Ai
3
Revision 1.4 (08-23-12)
DATASHEET
®
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR Technology
Datasheet
Chapter 4 Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.1
4.2
Register Nomenclature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
Basic Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Basic Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
PHY Identifier 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
PHY Identifier 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Auto Negotiation Advertisement Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Auto Negotiation Link Partner Ability Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Auto Negotiation Expansion Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Mode Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Special Modes Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.2.10 Symbol Error Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.2.11 Special Control/Status Indications Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.2.12 Interrupt Source Flag Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.2.13 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.2.14 PHY Special Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Chapter 5 Operational Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.1
5.2
5.3
5.4
5.5
Absolute Maximum Ratings*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Operating Conditions** . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.5.6
Equivalent Test Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Power Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Power-On nRST & Configuration Strap Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
MII Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
RMII Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SMI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.6
Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Chapter 6 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Chapter 7 Datasheet Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Revision 1.4 (08-23-12)
4
SMSC LAN8710A/LAN8710Ai
DATASHEET
®
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR Technology
Datasheet
List of Figures
Figure 1.1 System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 1.2 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2.1 32-QFN Pin Assignments (TOP VIEW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3.1 100BASE-TX Transmit Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 3.2 100BASE-TX Receive Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 3.3 Relationship Between Received Data and Specific MII Signals . . . . . . . . . . . . . . . . . . . . . . 24
Figure 3.4 Direct Cable Connection vs. Cross-over Cable Connection . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 3.5 MDIO Timing and Frame Structure - READ Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 3.6 MDIO Timing and Frame Structure - WRITE Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 3.7 LED1/REGOFF Polarity Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 3.8 LED2/nINTSEL Polarity Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 3.9 Near-end Loopback Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 3.10 Far Loopback Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 3.11 Connector Loopback Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 3.12 Simplified System Level Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 3.13 Power Supply Diagram (1.2V Supplied by Internal Regulator) . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 3.14 Power Supply Diagram (1.2V Supplied by External Source) . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 3.15 Twisted-Pair Interface Diagram (Single Power Supply). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 3.16 Twisted-Pair Interface Diagram (Dual Power Supplies). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 5.1 Output Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 5.2 Power Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 5.3 Power-On nRST & Configuration Strap Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 5.4 MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 5.5 MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 5.6 RMII Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 5.7 SMI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 6.1 32-QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 6.2 Recommended PCB Land Pattern. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 6.3 Taping Dimensions and Part Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 6.4 Reel Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 6.5 Tape Length and Part Quantity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
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Datasheet
List of Tables
Table 2.1 MII/RMII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2.2 LED Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 2.3 Serial Management Interface (SMI) Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 2.4 Ethernet Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 2.5 Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 2.6 Analog Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 2.7 Power Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2.8 32-QFN Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 2.9 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3.1 4B/5B Code Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 3.2 MII/RMII Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 3.3 Interrupt Management Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 3.4 Alternative Interrupt System Management Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 3.5 Pin Names for Address Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 3.6 MODE[2:0] Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 3.7 Pin Names for Mode Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 4.1 Register Bit Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 4.2 SMI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 5.1 Device Only Current Consumption and Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 5.2 Non-Variable I/O Buffer Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 5.3 Variable I/O Buffer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 5.4 100BASE-TX Transceiver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 5.5 10BASE-T Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 5.6 Power Sequence Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 5.7 Power-On nRST & Configuration Strap Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 5.8 MII Receive Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 5.9 MII Transmit Timing Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 5.10 RMII Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 5.11 RMII CLKIN (REF_CLK) Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 5.12 SMI Timing Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 5.13 Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 6.1 32-QFN Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 7.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
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Datasheet
Chapter 1 Introduction
1.1
General Terms and Conventions
The following is list of the general terms used throughout this document:
BYTE
FIFO
MAC
MII
8-bits
First In First Out buffer; often used for elasticity buffer
Media Access Controller
Media Independent Interface
RMIITM
N/A
Reduced Media Independent InterfaceTM
Not Applicable
X
Indicates that a logic state is “don’t care” or undefined.
RESERVED
Refers to a reserved bit field or address. Unless otherwise
noted, reserved bits must always be zero for write
operations. Unless otherwise noted, values are not
guaranteed when reading reserved bits. Unless otherwise
noted, do not read or write to reserved addresses.
SMI
Serial Management Interface
1.2
General Description
The LAN8710A/LAN8710Ai is a low-power 10BASE-T/100BASE-TX physical layer (PHY) transceiver
with variable I/O voltage that is compliant with the IEEE 802.3-2005 standards.
The LAN8710A/LAN8710Ai supports communication with an Ethernet MAC via a standard MII (IEEE
802.3u)/RMII interface. It contains a full-duplex 10-BASE-T/100BASE-TX transceiver and supports
10Mbps (10BASE-T) and 100Mbps (100BASE-TX) operation. The LAN8710A/LAN8710Ai implements
auto-negotiation to automatically determine the best possible speed and duplex mode of operation. HP
Auto-MDIX support allows the use of direct connect or cross-over LAN cables.
The LAN8710A/LAN8710Ai supports both IEEE 802.3-2005 compliant and vendor-specific register
functions. However, no register access is required for operation. The initial configuration may be
selected via the configuration pins as described in Section 3.7, "Configuration Straps," on page 36.
Register-selectable configuration options may be used to further define the functionality of the
transceiver.
Per IEEE 802.3-2005 standards, all digital interface pins are tolerant to 3.6V. The device can be
configured to operate on a single 3.3V supply utilizing an integrated 3.3V to 1.2V linear regulator. The
linear regulator may be optionally disabled, allowing usage of a high efficiency external regulator for
lower system power dissipation.
The LAN8710A/LAN8710Ai is available in both extended commercial and industrial temperature range
versions. A typical system application is shown in Figure 1.1.
SMSC LAN8710A/LAN8710Ai
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MII/
RMII
10/100
Ethernet
MAC
LAN8710A/
LAN8710Ai
MDI
Transformer
RJ45
Mode
LED
Crystal or
Clock
Oscillator
Figure 1.1 System Block Diagram
MODE[0:2]
nRST
Mode Control
Reset Control
HP Auto-MDIX
Auto-
Negotiation
100M TX
Logic
100M
Transmitter
TXP/TXN
RXP/RXN
RMIISEL
TXD[0:3]
Transmitter
10M TX
Logic
10M
Transmitter
SMI
Management
Control
MDIX
Control
TXEN
TXER
XTAL1/CLKIN
XTAL2
TXCLK
PLL
RXD[0:3]
100M RX
Logic
Analog-to-
Digital
DSP System:
Clock
Data Recovery
Equalizer
RXDV
RXER
Interrupt
Generator
nINT
LED1
LED2
RXCLK
CRS
100M PLL
LEDs
Receiver
COL/CRS_DV
MDC
10M RX
Logic
Squeltch
& Filters
RBIAS
Central Bias
10M PLL
MDIO
PHY Address
Latches
PHYAD[0:2]
LAN8710A/LAN8710Ai
Figure 1.2 Architectural Overview
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Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR Technology
Datasheet
Chapter 2 Pin Description and Configuration
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
TXD3
RXDV
VDD1A
TXN
MDIO
SMSC
LAN8710A/LAN8710Ai
COL/CRS_DV/MODE2
CRS
32 PIN QFN
(TOP VIEW)
RXER/RXD4/PHYAD0
VDDIO
VSS
TXP
RXN
RXD0/MODE0
RXD1/MODE1
RXD2/RMIISEL
RXP
RBIAS
NOTE: Exposed pad (VSS) on bottom of package must be connected to ground
Figure 2.1 32-QFN Pin Assignments (TOP VIEW)
Note: When a lower case “n” is used at the beginning of the signal name, it indicates that the signal
is active low. For example, nRST indicates that the reset signal is active low.
Note: The buffer type for each signal is indicated in the BUFFER TYPE column. A description of the
buffer types is provided in Section 2.2.
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Table 2.1 MII/RMII Signals
BUFFER
NUM PINS
NAME
SYMBOL
TYPE
DESCRIPTION
Transmit
Data 0
TXD0
VIS
The MAC transmits data to the transceiver using
this signal in all modes.
1
Transmit
Data 1
TXD1
TXD2
VIS
VIS
The MAC transmits data to the transceiver using
this signal in all modes.
1
1
Transmit
Data 2
(MII Mode)
The MAC transmits data to the transceiver using
this signal in MII Mode.
Note:
This signal must be grounded in RMII
Mode.
Transmit
Data 3
(MII Mode)
TXD3
nINT
VIS
The MAC transmits data to the transceiver using
this signal in MII Mode.
1
Note:
This signal must be grounded in RMII
Mode.
Interrupt
Output
VO8
Active low interrupt output. Place an external
resistor pull-up to VDDIO.
Note:
Refer to Section 3.6, "Interrupt
Management," on page 34 for additional
details on device interrupts.
Note:
Refer to Section 3.8.1.2, "nINTSEL and
LED2 Polarity Selection," on page 39 for
details on how the nINTSEL
configuration strap is used to determine
the function of this pin.
1
Transmit
Error
(MII Mode)
TXER
TXD4
VIS
(PU)
When driven high, the 4B/5B encode process
substitutes the Transmit Error code-group (/H/)
for the encoded data word. This input is ignored
in the 10BASE-T mode of operation.
Transmit
Data 4
(MII Mode)
VIS
(PU)
In Symbol Interface (5B Decoding) mode, this
signal becomes the MII Transmit Data 4 line (the
MSB of the 5-bit symbol code-group).
Note:
This signal is not used in RMII Mode.
Transmit
Enable
TXEN
VIS
(PD)
Indicates that valid transmission data is present
on TXD[3:0]. In RMII Mode, only TXD[1:0]
provide valid data.
1
1
Transmit
Clock
(MII Mode)
TXCLK
VO8
Used to latch data from the MAC into the
transceiver.
MII (100BASE-TX): 25MHz
MII (10BASE-T): 2.5MHz
Note:
This signal is not used in RMII Mode.
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Datasheet
Table 2.1 MII/RMII Signals (continued)
BUFFER
TYPE
NUM PINS
NAME
SYMBOL
DESCRIPTION
Receive
Data 0
RXD0
VO8
Bit 0 of the 4 (2 in RMII Mode) data bits that are
sent by the transceiver on the receive path.
PHY
Operating
Mode 0
Configuration
Strap
MODE0
VIS
(PU)
Combined with MODE1 and MODE2, this
configuration strap sets the default PHY mode.
1
See Note 2.1 for more information on
configuration straps.
Note:
Refer to Section 3.7.2, "MODE[2:0]:
Mode Configuration," on page 36 for
additional details.
Receive
Data 1
RXD1
VO8
Bit 1 of the 4 (2 in RMII Mode) data bits that are
sent by the transceiver on the receive path.
PHY
Operating
Mode 1
MODE1
VIS
(PU)
Combined with MODE0 and MODE2, this
configuration strap sets the default PHY mode.
1
See Note 2.1 for more information on
configuration straps.
Configuration
Strap
Note:
Refer to Section 3.7.2, "MODE[2:0]:
Mode Configuration," on page 36 for
additional details.
Receive
Data 2
RXD2
VO8
Bit 2 of the 4 (in MII Mode) data bits that are sent
by the transceiver on the receive path.
(MII Mode)
Note:
This signal is not used in RMII Mode.
MII/RMII
Mode Select
Configuration
Strap
RMIISEL
VIS
(PD)
This configuration strap selects the MII or RMII
mode of operation. When strapped low to VSS,
MII Mode is selected. When strapped high to
VDDIO RMII Mode is selected.
1
See Note 2.1 for more information on
configuration straps.
Note:
Refer to Section 3.7.3, "RMIISEL:
MII/RMII Mode Configuration," on
page 37 for additional details.
Receive
Data 3
RXD3
VO8
Bit 3 of the 4 (in MII Mode) data bits that are sent
by the transceiver on the receive path.
(MII Mode)
Note:
This signal is not used in RMII Mode.
PHY Address
2
Configuration
Strap
PHYAD2
VIS
(PD)
Combined with PHYAD0 and PHYAD1, this
configuration strap sets the transceiver’s SMI
address.
1
See Note 2.1 for more information on
configuration straps.
Note:
Refer to Section 3.7.1, "PHYAD[2:0]:
PHY Address Configuration," on
page 36 for additional information.
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Table 2.1 MII/RMII Signals (continued)
BUFFER
TYPE
NUM PINS
NAME
SYMBOL
DESCRIPTION
Receive Error
RXER
VO8
VO8
This signal is asserted to indicate that an error
was detected somewhere in the frame presently
being transferred from the transceiver.
Note:
This signal is optional in RMII Mode.
Receive
Data 4
(MII Mode)
RXD4
In Symbol Interface (5B Decoding) mode, this
signal is the MII Receive Data 4 signal, the MSB
of the received 5-bit symbol code-group.
Note:
Unless configured to the Symbol
Interface mode, this pin functions as
RXER.
1
PHY Address
0
Configuration
Strap
PHYAD0
VIS
(PD)
Combined with PHYAD1 and PHYAD2, this
configuration strap sets the transceiver’s SMI
address.
See Note 2.1 for more information on
configuration straps.
Note:
Refer to Section 3.7.1, "PHYAD[2:0]:
PHY Address Configuration," on
page 36 for additional information.
Receive
Clock
(MII Mode)
RXCLK
VO8
In MII mode, this pin is the receive clock output.
MII (100BASE-TX): 25MHz
MII (10BASE-T): 2.5MHz
PHY Address
1
Configuration
PHYAD1
VIS
(PD)
Combined with PHYAD0 and PHYAD2, this
configuration strap sets the transceiver’s SMI
address.
1
Strap
See Note 2.1 for more information on
configuration straps.
Note:
Refer to Section 3.7.1, "PHYAD[2:0]:
PHY Address Configuration," on
page 36 for additional information.
Receive Data
Valid
RXDV
VO8
Indicates that recovered and decoded data is
available on the RXD pins.
1
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Datasheet
Table 2.1 MII/RMII Signals (continued)
BUFFER
TYPE
NUM PINS
NAME
SYMBOL
DESCRIPTION
Carrier Sense
/ Receive
Data Valid
CRS_DV
VO8
This signal is asserted to indicate the receive
medium is non-idle in RMII Mode. When a
10BASE-T packet is received, CRS_DV is
asserted, but RXD[1:0] is held low until the SFD
byte (10101011) is received.
(RMII Mode)
Note:
Per the RMII standard, transmitted data
is not looped back onto the receive data
pins in 10BASE-T half-duplex mode.
Collision
Detect
COL
VO8
This signal is asserted to indicate detection of a
collision condition in MII Mode.
1
(MII Mode)
PHY
Operating
Mode 2
Configuration
Strap
MODE2
VIS
(PU)
Combined with MODE0 and MODE1, this
configuration strap sets the default PHY mode.
See Note 2.1 for more information on
configuration straps.
Note:
Refer to Section 3.7.2, "MODE[2:0]:
Mode Configuration," on page 36 for
additional details.
Carrier Sense
(MII Mode)
CRS
VO8
(PD)
This signal indicates detection of a carrier in MII
Mode.
1
Note 2.1 Configuration strap values are latched on power-on reset and system reset. Configuration
straps are identified by an underlined symbol name. Signals that function as configuration
straps must be augmented with an external resistor when connected to a load. Refer to
Section 3.7, "Configuration Straps," on page 36 for additional information.
Table 2.2 LED Pins
BUFFER
TYPE
NUM PINS
NAME
SYMBOL
DESCRIPTION
LED 1
LED1
O12
Link activity LED Indication. This pin is driven
active when a valid link is detected and blinks
when activity is detected.
Note:
Refer to Section 3.8.1, "LEDs," on
page 39 for additional LED information.
Regulator Off
Configuration
Strap
REGOFF
IS
(PD)
This configuration strap is used to disable the
internal 1.2V regulator. When the regulator is
disabled, external 1.2V must be supplied to
VDDCR.
When REGOFF is pulled high to VDD2A with
an external resistor, the internal regulator is
disabled.
1
When REGOFF is floating or pulled low, the
internal regulator is enabled (default).
See Note 2.2 for more information on
configuration straps.
Note:
Refer to Section 3.7.4, "REGOFF:
Internal +1.2V Regulator Configuration,"
on page 38 for additional details.
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Datasheet
Table 2.2 LED Pins (continued)
BUFFER
NUM PINS
NAME
SYMBOL
TYPE
DESCRIPTION
LED 2
LED2
O12
Link Speed LED Indication. This pin is driven
active when the operating speed is 100Mbps. It
is inactive when the operating speed is 10Mbps
or during line isolation.
Note:
Refer to Section 3.8.1, "LEDs," on
page 39 for additional LED information.
nINT/TXER/
TXD4
nINTSEL
IS
(PU)
This configuration strap selects the mode of the
nINT/TXER/TXD4 pin.
Function
Select
Configuration
Strap
When nINTSEL is floated or pulled to VDD2A,
nINT is selected for operation on the
nINT/TXER/TXD4 pin (default).
1
When nINTSEL is pulled low to VSS,
TXER/TXD4 is selected for operation on the
nINT/TXER/TXD4 pin.
See Note 2.2 for more information on
configuration straps.
Note:
Refer to See Section 3.8.1.2, "nINTSEL
and LED2 Polarity Selection," on
page 39 for additional information.
Note 2.2 Configuration strap values are latched on power-on reset and system reset. Configuration
straps are identified by an underlined symbol name. Signals that function as configuration
straps must be augmented with an external resistor when connected to a load. Refer to
Section 3.7, "Configuration Straps," on page 36 for additional information.
Table 2.3 Serial Management Interface (SMI) Pins
BUFFER
NUM PINS
NAME
SYMBOL
TYPE
DESCRIPTION
SMI Data
Input/Output
MDIO
VIS/
VOD8
Serial Management Interface data input/output
1
1
SMI Clock
MDC
VIS
Serial Management Interface clock
Table 2.4 Ethernet Pins
BUFFER
TYPE
NUM PINS
NAME
SYMBOL
DESCRIPTION
Ethernet
TX/RX
Positive
Channel 1
TXP
AIO
Transmit/Receive Positive Channel 1
1
Ethernet
TX/RX
Negative
TXN
AIO
Transmit/Receive Negative Channel 1
1
Channel 1
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Table 2.4 Ethernet Pins (continued)
BUFFER
TYPE
NUM PINS
NAME
SYMBOL
DESCRIPTION
Ethernet
TX/RX
Positive
Channel 2
RXP
AIO
Transmit/Receive Positive Channel 2
1
Ethernet
TX/RX
Negative
Channel 2
RXN
AIO
Transmit/Receive Negative Channel 2
1
Table 2.5 Miscellaneous Pins
BUFFER
NUM PINS
NAME
SYMBOL
TYPE
DESCRIPTION
External
Crystal
Input
XTAL1
CLKIN
ICLK
External crystal input
1
External
ICLK
Single-ended clock oscillator input.
Clock Input
Note:
When using a single ended clock
oscillator, XTAL2 should be left
unconnected.
External
Crystal
Output
XTAL2
nRST
OCLK
External crystal output
1
1
External
Reset
VIS
(PU)
System reset. This signal is active low.
Table 2.6 Analog Reference Pins
BUFFER
NUM PINS
NAME
SYMBOL
TYPE
DESCRIPTION
External 1%
Bias Resistor
Input
RBIAS
AI
This pin requires connection of a 12.1k ohm (1%)
resistor to ground.
Refer to the LAN8710A/LAN8710Ai reference
schematic for connection information.
1
Note:
The nominal voltage is 1.2V and the
resistor will dissipate approximately
1mW of power.
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Table 2.7 Power Pins
BUFFER
NUM PINS
NAME
SYMBOL
TYPE
DESCRIPTION
+1.6V to
+3.6V
Variable I/O
Power
VDDIO
P
+1.6V to +3.6V variable I/O power
1
Refer to the LAN8710A/LAN8710Ai reference
schematic for connection information.
+1.2V Digital
Core Power
Supply
VDDCR
P
Supplied by the on-chip regulator unless
configured for regulator off mode via the
REGOFF configuration strap.
Refer to the LAN8710A/LAN8710Ai reference
schematic for connection information.
1
1
Note:
1 uF and 470 pF decoupling capacitors
in parallel to ground should be used on
this pin.
+3.3V
Channel 1
Analog Port
Power
VDD1A
VDD2A
P
P
+3.3V Analog Port Power to Channel 1
Refer to the LAN8710A/LAN8710Ai reference
schematic for connection information.
+3.3V
Channel 2
Analog Port
Power
+3.3V Analog Port Power to Channel 2 and the
internal regulator.
1
1
Refer to the LAN8710A/LAN8710Ai reference
schematic for connection information.
Ground
VSS
P
Common ground. This exposed pad must be
connected to the ground plane with a via array.
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2.1
Pin Assignments
Table 2.8 32-QFN Package Pin Assignments
PIN NUM
PIN NAME
PIN NUM
PIN NAME
1
2
VDD2A
LED2/nINTSEL
LED1/REGOFF
XTAL2
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
MDC
nINT/TXER/TXD4
nRST
3
4
TXCLK
TXEN
5
XTAL1/CLKIN
VDDCR
6
TXD0
7
RXCLK/PHYAD1
RXD3/PHYAD2
RXD2/RMIISEL
RXD1/MODE1
RXD0/MODE0
VDDIO
TXD1
8
TXD2
9
TXD3
10
11
12
13
14
15
16
RXDV
VDD1A
TXN
RXER/RXD4/PHYAD0
CRS
TXP
RXN
COL/CRS_DV/MODE2
MDIO
RXP
RBIAS
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2.2
Buffer Types
Table 2.9 Buffer Types
DESCRIPTION
BUFFER TYPE
IS
O12
VIS
Schmitt-triggered input
Output with 12mA sink and 12mA source
Variable voltage Schmitt-triggered input
VO8
VOD8
PU
Variable voltage output with 8mA sink and 8mA source
Variable voltage open-drain output with 8mA sink
50uA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pull-
ups are always enabled.
Note:
Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on
internal resistors to drive signals external to the device. When connected to a load
that must be pulled high, an external resistor must be added.
PD
50uA (typical) internal pull-down. Unless otherwise noted in the pin description, internal
pull-downs are always enabled.
Note:
Internal pull-down resistors prevent unconnected inputs from floating. Do not rely
on internal resistors to drive signals external to the device. When connected to a
load that must be pulled low, an external resistor must be added.
AI
AIO
ICLK
OCLK
P
Analog input
Analog bi-directional
Crystal oscillator input pin
Crystal oscillator output pin
Power pin
Note: The digital signals are not 5V tolerant. Refer to Section 5.1, "Absolute Maximum Ratings*," on
page 66 for additional buffer information.
Note 2.3 Sink and source capabilities are dependant on the VDDIO voltage. Refer to Section 5.1,
"Absolute Maximum Ratings*," on page 66 for additional information.
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Chapter 3 Functional Description
This chapter provides functional descriptions of the various device features. These features have been
categorized into the following sections:
Transceiver
Auto-negotiation
HP Auto-MDIX Support
MAC Interface
Serial Management Interface (SMI)
Interrupt Management
Configuration Straps
Miscellaneous Functions
Application Diagrams
3.1
Transceiver
3.1.1
100BASE-TX Transmit
The 100BASE-TX transmit data path is shown in Figure 3.1. Each major block is explained in the
following subsections.
TX_CLK
(for MII only)
PLL
MAC
Ext Ref_CLK (for RMII only)
MII 25 Mhz by 4 bits
4B/5B
Encoder
Scrambler
and PISO
25MHz
by 4 bits
25MHz by
5 bits
or
MII/RMII
RMII 50Mhz by 2 bits
NRZI
Converter
MLT-3
Converter
Tx
Driver
125 Mbps Serial
NRZI
MLT-3
MLT-3
MLT-3
MLT-3
Magnetics
RJ45
CAT-5
Figure 3.1 100BASE-TX Transmit Data Path
3.1.1.1
100BASE-TX Transmit Data Across the MII/RMII Interface
For MII, the MAC controller drives the transmit data onto the TXD bus and asserts TXEN to indicate
valid data. The data is latched by the transceiver’s MII block on the rising edge of TXCLK. The data
is in the form of 4-bit wide 25MHz data.
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For RMII, the MAC controller drives the transmit data onto the TXD bus and asserts TXEN to indicate
valid data. The data is latched by the transceiver’s RMII block on the rising edge of REF_CLK. The
data is in the form of 2-bit wide 50MHz data.
3.1.1.2
4B/5B Encoding
The transmit data passes from the MII/RMII block to the 4B/5B encoder. This block encodes the data
from 4-bit nibbles to 5-bit symbols (known as “code-groups”) according to Table 3.1. Each 4-bit data-
nibble is mapped to 16 of the 32 possible code-groups. The remaining 16 code-groups are either used
for control information or are not valid.
The first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles,
0 through F. The remaining code-groups are given letter designations with slashes on either side. For
example, an IDLE code-group is /I/, a transmit error code-group is /H/, etc.
Table 3.1 4B/5B Code Table
CODE
GROUP
RECEIVER
INTERPRETATION
TRANSMITTER
INTERPRETATION
SYM
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101
11111
11000
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
I
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
DATA
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
DATA
IDLE
Sent after /T/R until TXEN
Sent for rising TXEN
J
First nibble of SSD, translated to “0101”
following IDLE, else RXER
10001
01101
K
T
Second nibble of SSD, translated to
“0101” following J, else RXER
Sent for rising TXEN
Sent for falling TXEN
First nibble of ESD, causes de-assertion
of CRS if followed by /R/, else assertion
of RXER
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Table 3.1 4B/5B Code Table (continued)
CODE
GROUP
RECEIVER
INTERPRETATION
TRANSMITTER
INTERPRETATION
SYM
00111
R
Second nibble of ESD, causes
deassertion of CRS if following /T/, else
assertion of RXER
Sent for falling TXEN
00100
00110
11001
00000
00001
00010
00011
00101
01000
01100
10000
H
V
V
V
V
V
V
V
V
V
V
Transmit Error Symbol
Sent for rising TXER
INVALID
INVALID, RXER if during RXDV
INVALID, RXER if during RXDV
INVALID, RXER if during RXDV
INVALID, RXER if during RXDV
INVALID, RXER if during RXDV
INVALID, RXER if during RXDV
INVALID, RXER if during RXDV
INVALID, RXER if during RXDV
INVALID, RXER if during RXDV
INVALID, RXER if during RXDV
INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
3.1.1.3
Scrambling
Repeated data patterns (especially the IDLE code-group) can have power spectral densities with large
narrow-band peaks. Scrambling the data helps eliminate these peaks and spread the signal power
more uniformly over the entire channel bandwidth. This uniform spectral density is required by FCC
regulations to prevent excessive EMI from being radiated by the physical wiring.
The seed for the scrambler is generated from the transceiver address, PHYAD, ensuring that in
multiple-transceiver applications, such as repeaters or switches, each transceiver will have its own
scrambler sequence.
The scrambler also performs the Parallel In Serial Out conversion (PISO) of the data.
3.1.1.4
3.1.1.5
NRZI and MLT-3 Encoding
The scrambler block passes the 5-bit wide parallel data to the NRZI converter where it becomes a
serial 125MHz NRZI data stream. The NRZI is encoded to MLT-3. MLT-3 is a tri-level code where a
change in the logic level represents a code bit “1” and the logic output remaining at the same level
represents a code bit “0”.
100M Transmit Driver
The MLT3 data is then passed to the analog transmitter, which drives the differential MLT-3 signal, on
outputs TXP and TXN, to the twisted pair media across a 1:1 ratio isolation transformer. The 10BASE-
T and 100BASE-TX signals pass through the same transformer so that common “magnetics” can be
used for both. The transmitter drives into the 100Ω impedance of the CAT-5 cable. Cable termination
and impedance matching require external components.
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3.1.1.6
100M Phase Lock Loop (PLL)
The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125 MHz
logic and the 100BASE-TX transmitter.
3.1.2
100BASE-TX Receive
The 100BASE-TX receive data path is shown in Figure 3.2. Each major block is explained in the
following subsections.
RX_CLK
(for MII only)
PLL
MAC
Ext Ref_CLK (for RMII only)
25MHz
by 4 bits
25MHz by
5 bits
MII 25Mhz by 4 bits
or
RMII 50Mhz by 2 bits
4B/5B
Decoder
Descrambler
and SIPO
MII/RMII
125 Mbps Serial
DSP: Timing
recovery, Equalizer
and BLW Correction
NRZI
MLT-3
NRZI
Converter
MLT-3
Converter
MLT-3
MLT-3
MLT-3
A/D
Converter
Magnetics
RJ45
CAT-5
6 bit Data
Figure 3.2 100BASE-TX Receive Data Path
100M Receive Input
3.1.2.1
3.1.2.2
The MLT-3 from the cable is fed into the transceiver (on inputs RXP and RXN) via a 1:1 ratio
transformer. The ADC samples the incoming differential signal at a rate of 125M samples per second.
Using a 64-level quanitizer, it generates 6 digital bits to represent each sample. The DSP adjusts the
gain of the ADC according to the observed signal levels such that the full dynamic range of the ADC
can be used.
Equalizer, Baseline Wander Correction and Clock and Data Recovery
The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates
for phase and amplitude distortion caused by the physical channel consisting of magnetics, connectors,
and CAT- 5 cable. The equalizer can restore the signal for any good-quality CAT-5 cable between 1m
and 150m.
If the DC content of the signal is such that the low-frequency components fall below the low frequency
pole of the isolation transformer, then the droop characteristics of the transformer will become
significant and Baseline Wander (BLW) on the received signal will result. To prevent corruption of the
received data, the transceiver corrects for BLW and can receive the ANSI X3.263-1995 FDDI TP-PMD
defined “killer packet” with no bit errors.
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The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the timing
unit of the DSP, selects the optimum phase for sampling the data. This is used as the received
recovered clock. This clock is used to extract the serial data from the received signal.
3.1.2.3
3.1.2.4
NRZI and MLT-3 Decoding
The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then
converted to an NRZI data stream.
Descrambling
The descrambler performs an inverse function to the scrambler in the transmitter and also performs
the Serial In Parallel Out (SIPO) conversion of the data.
During reception of IDLE (/I/) symbols. the descrambler synchronizes its descrambler key to the
incoming stream. Once synchronization is achieved, the descrambler locks on this key and is able to
descramble incoming data.
Special logic in the descrambler ensures synchronization with the remote transceiver by searching for
IDLE symbols within a window of 4000 bytes (40us). This window ensures that a maximum packet size
of 1514 bytes, allowed by the IEEE 802.3 standard, can be received with no interference. If no IDLE-
symbols are detected within this time-period, receive operation is aborted and the descrambler re-starts
the synchronization process.
3.1.2.5
3.1.2.6
Alignment
The de-scrambled signal is then aligned into 5-bit code-groups by recognizing the /J/K/ Start-of-Stream
Delimiter (SSD) pair at the start of a packet. Once the code-word alignment is determined, it is stored
and utilized until the next start of frame.
5B/4B Decoding
The 5-bit code-groups are translated into 4-bit data nibbles according to the 4B/5B table. The
translated data is presented on the RXD[3:0] signal lines. The SSD, /J/K/, is translated to “0101 0101”
as the first 2 nibbles of the MAC preamble. Reception of the SSD causes the transceiver to assert the
receive data valid signal, indicating that valid data is available on the RXD bus. Successive valid code-
groups are translated to data nibbles. Reception of either the End of Stream Delimiter (ESD) consisting
of the /T/R/ symbols, or at least two /I/ symbols causes the transceiver to de-assert the carrier sense
and receive data valid signals.
Note: These symbols are not translated into data.
3.1.2.7
Receive Data Valid Signal
The Receive Data Valid signal (RXDV) indicates that recovered and decoded nibbles are being
presented on the RXD[3:0] outputs synchronous to RXCLK. RXDV becomes active after the /J/K/
delimiter has been recognized and RXD is aligned to nibble boundaries. It remains active until either
the /T/R/ delimiter is recognized or link test indicates failure or SIGDET becomes false.
RXDV is asserted when the first nibble of translated /J/K/ is ready for transfer over the Media
Independent Interface (MII mode).
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J
K
5
5
5
D
Idle
data data data data
T
R
CLEAR-TEXT
RX_CLK
RX_DV
5
Figure 3.3 Relationship Between Received Data and Specific MII Signals
Receiver Errors
5
5
5
5
D
data data data data
RXD
3.1.2.8
3.1.2.9
During a frame, unexpected code-groups are considered receive errors. Expected code groups are the
DATA set (0 through F), and the /T/R/ (ESD) symbol pair. When a receive error occurs, the RXER
signal is asserted and arbitrary data is driven onto the RXD[3:0] lines. Should an error be detected
during the time that the /J/K/ delimiter is being decoded (bad SSD error), RXER is asserted true and
the value ‘1110’ is driven onto the RXD[3:0] lines. Note that the Valid Data signal is not yet asserted
when the bad SSD error occurs.
100M Receive Data Across the MII/RMII Interface
In MII mode, the 4-bit data nibbles are sent to the MII block. These data nibbles are clocked to the
controller at a rate of 25MHz. The controller samples the data on the rising edge of RXCLK. To ensure
that the setup and hold requirements are met, the nibbles are clocked out of the transceiver on the
falling edge of RXCLK. RXCLK is the 25MHz output clock for the MII bus. It is recovered from the
received data to clock the RXD bus. If there is no received signal, it is derived from the system
reference clock (XTAL1/CLKIN).
When tracking the received data, RXCLK has a maximum jitter of 0.8ns (provided that the jitter of the
input clock, XTAL1/CLKIN, is below 100ps).
In RMII mode, the 2-bit data nibbles are sent to the RMII block. These data nibbles are clocked to the
controller at a rate of 50MHz. The controller samples the data on the rising edge of XTAL1/CLKIN
(REF_CLK). To ensure that the setup and hold requirements are met, the nibbles are clocked out of
the transceiver on the falling edge of XTAL1/CLKIN (REF_CLK).
3.1.3
10BASE-T Transmit
Data to be transmitted comes from the MAC layer controller. The 10BASE-T transmitter receives 4-bit
nibbles from the MII at a rate of 2.5MHz and converts them to a 10Mbps serial data stream. The data
stream is then Manchester-encoded and sent to the analog transmitter, which drives a signal onto the
twisted pair via the external magnetics.
The 10M transmitter uses the following blocks:
MII (digital)
TX 10M (digital)
10M Transmitter (analog)
10M PLL (analog)
3.1.3.1
10M Transmit Data Across the MII/RMII Interface
The MAC controller drives the transmit data onto the TXD bus. For MII, when the controller has driven
TXEN high to indicate valid data, the data is latched by the MII block on the rising edge of TXCLK.
The data is in the form of 4-bit wide 2.5MHz data. For RMII, TXD[1:0] shall transition synchronously
with respect to REF_CLK. When TXEN is asserted, TXD[1:0] are accepted for transmission by the
device. TXD[1:0] shall be “00” to indicate idle when TXEN is deasserted. Values of TXD[1:0] other than
“00” when TXEN is deasserted are reserved for out-of-band signalling (to be defined). Values other
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than “00” on TXD[1:0] while TXEN is deasserted shall be ignored by the device.TXD[1:0] shall provide
valid data for each REF_CLK period while TXEN is asserted.
In order to comply with legacy 10BASE-T MAC/Controllers, in half-duplex mode the transceiver loops
back the transmitted data, on the receive path. This does not confuse the MAC/Controller since the
COL signal is not asserted during this time. The transceiver also supports the SQE (Heartbeat) signal.
See Section 3.8.7, "Collision Detect," on page 42, for more details.
3.1.3.2
Manchester Encoding
The 4-bit wide data is sent to the 10M TX block. The nibbles are converted to a 10Mbps serial NRZI
data stream. The 10M PLL locks onto the external clock or internal oscillator and produces a 20MHz
clock. This is used to Manchester encode the NRZ data stream. When no data is being transmitted
(TXEN is low), the 10M TX block outputs Normal Link Pulses (NLPs) to maintain communications with
the remote link partner.
3.1.3.3
10M Transmit Drivers
The Manchester encoded data is sent to the analog transmitter where it is shaped and filtered before
being driven out as a differential signal across the TXP and TXN outputs.
3.1.4
10BASE-T Receive
The 10BASE-T receiver gets the Manchester- encoded analog signal from the cable via the magnetics.
It recovers the receive clock from the signal and uses this clock to recover the NRZI data stream. This
10M serial data is converted to 4-bit data nibbles which are passed to the controller via MII at a rate
of 2.5MHz.
This 10M receiver uses the following blocks:
Filter and SQUELCH (analog)
10M PLL (analog)
RX 10M (digital)
MII (digital)
3.1.4.1
3.1.4.2
10M Receive Input and Squelch
The Manchester signal from the cable is fed into the transceiver (on inputs RXP and RXN) via 1:1 ratio
magnetics. It is first filtered to reduce any out-of-band noise. It then passes through a SQUELCH
circuit. The SQUELCH is a set of amplitude and timing comparators that normally reject differential
voltage levels below 300mV and detect and recognize differential voltages above 585mV.
Manchester Decoding
The output of the SQUELCH goes to the 10M RX block where it is validated as Manchester encoded
data. The polarity of the signal is also checked. If the polarity is reversed (local RXP is connected to
RXN of the remote partner and vice versa), the condition is identified and corrected. The reversed
condition is indicated by the XPOL bit of the Special Control/Status Indications Register. The 10M PLL
is locked onto the received Manchester signal, from which the 20MHz cock is generated. Using this
clock, the Manchester encoded data is extracted and converted to a 10MHz NRZI data stream. It is
then converted from serial to 4-bit wide parallel data.
The 10M RX block also detects valid 10Base-T IDLE signals - Normal Link Pulses (NLPs) - to maintain
the link.
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3.1.4.3
10M Receive Data Across the MII/RMII Interface
For MII, the 4-bit data nibbles are sent to the MII block. In MII mode, these data nibbles are valid on
the rising edge of the 2.5 MHz RXCLK.
For RMII, the 2-bit data nibbles are sent to the RMII block. In RMII mode, these data nibbles are valid
on the rising edge of the RMII REF_CLK.
3.1.4.4
Jabber Detection
Jabber is a condition in which a station transmits for a period of time longer than the maximum
permissible packet length, usually due to a fault condition, which results in holding the TXEN input for
a long period. Special logic is used to detect the jabber state and abort the transmission to the line
within 45ms. Once TXEN is deasserted, the logic resets the jabber condition.
As shown in Section 4.2.2, "Basic Status Register," on page 53, the Jabber Detect bit indicates that a
jabber condition was detected.
3.2
Auto-negotiation
The purpose of the auto-negotiation function is to automatically configure the transceiver to the
optimum link parameters based on the capabilities of its link partner. Auto-negotiation is a mechanism
for exchanging configuration information between two link-partners and automatically selecting the
highest performance mode of operation supported by both sides. Auto-negotiation is fully defined in
clause 28 of the IEEE 802.3 specification.
Once auto-negotiation has completed, information about the resolved link can be passed back to the
controller via the Serial Management Interface (SMI). The results of the negotiation process are
reflected in the Speed Indication bits of the PHY Special Control/Status Register, as well as in the Auto
Negotiation Link Partner Ability Register. The auto-negotiation protocol is a purely physical layer
activity and proceeds independently of the MAC controller.
The advertised capabilities of the transceiver are stored in the Auto Negotiation Advertisement
Register. The default advertised by the transceiver is determined by user-defined on-chip signal
options.
The following blocks are activated during an Auto-negotiation session:
Auto-negotiation (digital)
100M ADC (analog)
100M PLL (analog)
100M equalizer/BLW/clock recovery (DSP)
10M SQUELCH (analog)
10M PLL (analog)
10M Transmitter (analog)
When enabled, auto-negotiation is started by the occurrence of one of the following events:
Hardware reset
Software reset
Power-down reset
Link status down
Setting the Restart Auto-Negotiate bit of the Basic Control Register
On detection of one of these events, the transceiver begins auto-negotiation by transmitting bursts of
Fast Link Pulses (FLP), which are bursts of link pulses from the 10M transmitter. They are shaped as
Normal Link Pulses and can pass uncorrupted down CAT-3 or CAT-5 cable. A Fast Link Pulse Burst
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consists of up to 33 pulses. The 17 odd-numbered pulses, which are always present, frame the FLP
burst. The 16 even-numbered pulses, which may be present or absent, contain the data word being
transmitted. Presence of a data pulse represents a “1”, while absence represents a “0”.
The data transmitted by an FLP burst is known as a “Link Code Word.” These are defined fully in IEEE
802.3 clause 28. In summary, the transceiver advertises 802.3 compliance in its selector field (the first
5 bits of the Link Code Word). It advertises its technology ability according to the bits set in the Auto
Negotiation Advertisement Register.
There are 4 possible matches of the technology abilities. In the order of priority these are:
100M Full Duplex (Highest Priority)
100M Half Duplex
10M Full Duplex
10M Half Duplex (Lowest Priority)
If the full capabilities of the transceiver are advertised (100M, Full Duplex), and if the link partner is
capable of 10M and 100M, then auto-negotiation selects 100M as the highest performance mode. If
the link partner is capable of half and full duplex modes, then auto-negotiation selects full duplex as
the highest performance operation.
Once a capability match has been determined, the link code words are repeated with the acknowledge
bit set. Any difference in the main content of the link code words at this time will cause auto-negotiation
to re-start. Auto-negotiation will also re-start if not all of the required FLP bursts are received.
The capabilities advertised during auto-negotiation by the transceiver are initially determined by the
logic levels latched on the MODE[2:0] configuration straps after reset completes. These configuration
straps can also be used to disable auto-negotiation on power-up. Refer to Section 3.7.2, "MODE[2:0]:
Mode Configuration," on page 36 for additional information.
Writing the bits 8 through 5 of the Auto Negotiation Advertisement Register allows software control of
the capabilities advertised by the transceiver. Writing the Auto Negotiation Advertisement Register
does not automatically re-start auto-negotiation. The Restart Auto-Negotiate bit of the Basic Control
Register must be set before the new abilities will be advertised. Auto-negotiation can also be disabled
via software by clearing the Auto-Negotiation Enable bit of the Basic Control Register.
Note: The device does not support “Next Page” capability.
3.2.1
Parallel Detection
If the LAN8710A/LAN8710Ai is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs
are detected), it is able to determine the speed of the link based on either 100M MLT-3 symbols or
10M Normal Link Pulses. In this case the link is presumed to be half duplex per the IEEE standard.
This ability is known as “Parallel Detection.” This feature ensures interoperability with legacy link
partners. If a link is formed via parallel detection, then the Link Partner Auto-Negotiation Able bit of the
Auto Negotiation Expansion Register is cleared to indicate that the Link Partner is not capable of auto-
negotiation. The controller has access to this information via the management interface. If a fault
occurs during parallel detection, the Parallel Detection Fault bit of Link Partner Auto-Negotiation Able
is set.
Auto Negotiation Link Partner Ability Register is used to store the link partner ability information, which
is coded in the received FLPs. If the link partner is not auto-negotiation capable, then the Auto
Negotiation Link Partner Ability Register is updated after completion of parallel detection to reflect the
speed capability of the link partner.
3.2.2
Restarting Auto-negotiation
Auto-negotiation can be restarted at any time by setting the Restart Auto-Negotiate bit of the Basic
Control Register. Auto-negotiation will also restart if the link is broken at any time. A broken link is
caused by signal loss. This may occur because of a cable break, or because of an interruption in the
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signal transmitted by the link partner. Auto-negotiation resumes in an attempt to determine the new
link configuration.
If the management entity re-starts auto-negotiation by setting the Restart Auto-Negotiate bit of the
Basic Control Register, the LAN8710A/LAN8710Ai will respond by stopping all transmission/receiving
operations. Once the break_link_timer is completed in the Auto-negotiation state-machine
(approximately 1200ms), auto-negotiation will re-start. In this case, the link partner will have also
dropped the link due to lack of a received signal, so it too will resume auto-negotiation.
3.2.3
3.2.4
Disabling Auto-negotiation
Auto-negotiation can be disabled by setting the Auto-Negotiation Enable bit of the Basic Control
Register to zero. The device will then force its speed of operation to reflect the information in the Basic
Control Register (Speed Select bit and Duplex Mode bit). These bits should be ignored when auto-
negotiation is enabled.
Half vs. Full Duplex
Half duplex operation relies on the CSMA/CD (Carrier Sense Multiple Access / Collision Detect)
protocol to handle network traffic and collisions. In this mode, the carrier sense signal, CRS, responds
to both transmit and receive activity. If data is received while the transceiver is transmitting, a collision
results.
In full duplex mode, the transceiver is able to transmit and receive data simultaneously. In this mode,
CRS responds only to receive activity. The CSMA/CD protocol does not apply and collision detection
is disabled.
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3.3
HP Auto-MDIX Support
HP Auto-MDIX facilitates the use of CAT-3 (10BASE-T) or CAT-5 (100BASE-T) media UTP
interconnect cable without consideration of interface wiring scheme. If a user plugs in either a direct
connect LAN cable, or a cross-over patch cable, as shown in Figure 3.4, the device’s Auto-MDIX
transceiver is capable of configuring the TXP/TXN and RXP/RXN pins for correct transceiver operation.
The internal logic of the device detects the TX and RX pins of the connecting device. Since the RX
and TX line pairs are interchangeable, special PCB design considerations are needed to accommodate
the symmetrical magnetics and termination of an Auto-MDIX design.
The Auto-MDIX function can be disabled via the AMDIXCTRL bit in the Special Control/Status
Indications Register.
RJ-45 8-pin straight-through
for 10BASE-T/100BASE-TX
signaling
RJ-45 8-pin cross-over for
10BASE-T/100BASE-TX
signaling
TXP
TXN
TXP
TXP
TXN
TXP
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
1
2
3
4
5
6
7
8
TXN
TXN
2
3
4
5
6
7
8
RXP
RXP
RXP
RXP
Not Used
Not Used
RXN
Not Used
Not Used
RXN
Not Used
Not Used
RXN
Not Used
Not Used
RXN
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Direct Connect Cable
Cross-Over Cable
Figure 3.4 Direct Cable Connection vs. Cross-over Cable Connection
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3.4
MAC Interface
The MII/RMII block is responsible for communication with the MAC controller. Special sets of hand-
shake signals are used to indicate that valid received/transmitted data is present on the 4 bit
receive/transmit bus.
The device must be configured in MII or RMII mode. This is done by specific pin strapping
configurations. Refer to Section 3.4.3, "MII vs. RMII Configuration," on page 31 for information on pin
strapping and how the pins are mapped differently.
3.4.1
MII
The MII includes 16 interface signals:
transmit data - TXD[3:0]
transmit strobe - TXEN
transmit clock - TXCLK
transmit error - TXER/TXD4
receive data - RXD[3:0]
receive strobe - RXDV
receive clock - RXCLK
receive error - RXER/RXD4/PHYAD0
collision indication - COL
carrier sense - CRS
In MII mode, on the transmit path, the transceiver drives the transmit clock, TXCLK, to the controller.
The controller synchronizes the transmit data to the rising edge of TXCLK. The controller drives TXEN
high to indicate valid transmit data. The controller drives TXER high when a transmit error is detected.
On the receive path, the transceiver drives both the receive data, RXD[3:0], and the RXCLK signal.
The controller clocks in the receive data on the rising edge of RXCLK when the transceiver drives
RXDV high. The transceiver drives RXER high when a receive error is detected.
3.4.2
RMII
The device supports the low pin count Reduced Media Independent Interface (RMII) intended for use
between Ethernet transceivers and switch ASICs. Under IEEE 802.3, an MII comprised of 16 pins for
data and control is defined. In devices incorporating many MACs or transceiver interfaces such as
switches, the number of pins can add significant cost as the port counts increase. RMII reduces this
pin count while retaining a management interface (MDIO/MDC) that is identical to MII.
The RMII interface has the following characteristics:
It is capable of supporting 10Mbps and 100Mbps data rates
A single clock reference is used for both transmit and receive
It provides independent 2-bit (di-bit) wide transmit and receive data paths
It uses LVCMOS signal levels, compatible with common digital CMOS ASIC processes
The RMII includes the following interface signals (1 optional):
transmit data - TXD[1:0]
transmit strobe - TXEN
receive data - RXD[1:0]
receive error - RXER (Optional)
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carrier sense - CRS_DV
Reference Clock - (RMII references usually define this signal as REF_CLK)
3.4.2.1
CRS_DV - Carrier Sense/Receive Data Valid
The CRS_DV is asserted by the device when the receive medium is non-idle. CRS_DV is asserted
asynchronously on detection of carrier due to the criteria relevant to the operating mode. In 10BASE-
T mode when squelch is passed, or in 100BASE-X mode when 2 non-contiguous zeroes in 10 bits are
detected, the carrier is said to be detected.
Loss of carrier shall result in the deassertion of CRS_DV synchronous to the cycle of REF_CLK which
presents the first di-bit of a nibble onto RXD[1:0] (i.e. CRS_DV is deasserted only on nibble
boundaries). If the device has additional bits to be presented on RXD[1:0] following the initial
deassertion of CRS_DV, then the device shall assert CRS_DV on cycles of REF_CLK which present
the second di-bit of each nibble and de-assert CRS_DV on cycles of REF_CLK which present the first
di-bit of a nibble. The result is, starting on nibble boundaries, CRS_DV toggles at 25 MHz in 100Mbps
mode and 2.5 MHz in 10Mbps mode when CRS ends before RXDV (i.e. the FIFO still has bits to
transfer when the carrier event ends). Therefore, the MAC can accurately recover RXDV and CRS.
During a false carrier event, CRS_DV shall remain asserted for the duration of carrier activity. The data
on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV
is asynchronous relative to REF_CLK, the data on RXD[1:0] shall be “00” until proper receive signal
decoding takes place.
3.4.2.2
Reference Clock (REF_CLK)
The RMII REF_CLK is a continuous clock that provides the timing reference for CRS_DV, RXD[1:0],
TXEN, TXD[1:0] and RXER. The device uses REF_CLK as the network clock such that no buffering
is required on the transmit data path. However, on the receive data path, the receiver recovers the
clock from the incoming data stream, and the device uses elasticity buffering to accommodate for
differences between the recovered clock and the local REF_CLK.
3.4.3
MII vs. RMII Configuration
The device must be configured to support the MII or RMII bus for connectivity to the MAC. This
configuration is done via the RMIISEL configuration strap. MII or RMII mode selection is configured
based on the strapping of the RMIISEL configuration strap as described in Section 3.7.3, "RMIISEL:
MII/RMII Mode Configuration," on page 37.
Most of the MII and RMII pins are multiplexed. Table 3.2, "MII/RMII Signal Mapping" describes the
relationship of the related device pins to the MII and RMII mode signal names.
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Table 3.2 MII/RMII Signal Mapping
PIN NAME
MII MODE
RMII MODE
TXD0
TXD1
TXEN
TXD0
TXD1
TXEN
RXER
TXD0
TXD1
TXEN
RXER/
RXER
RXD4/PHYAD0
Note 3.2
COL/CRS_DV/MODE2
RXD0/MODE0
RXD1/MODE1
TXD2
COL
RXD0
RXD1
TXD2
TXD3
CRS_DV
RXD0
RXD1
Note 3.1
Note 3.1
TXD3
nINT/TXER/TXD4
TXER/
TXD4
CRS
CRS
RXDV
RXDV
RXD2/RMIISEL
RXD3/PHYAD2
TXCLK
RXD2
RXD3
TXCLK
RXCLK/PHYAD1
XTAL1/CLKIN
RXCLK
XTAL1/CLKIN
REF_CLK
Note 3.1 In RMII mode, this pin needs to tied to VSS.
Note 3.2 The RXER signal is optional on the RMII bus. This signal is required by the transceiver,
but it is optional for the MAC. The MAC can choose to ignore or not use this signal.
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3.5
Serial Management Interface (SMI)
The Serial Management Interface is used to control the device and obtain its status. This interface
supports registers 0 through 6 as required by Clause 22 of the 802.3 standard, as well as “vendor-
specific” registers 16 to 31 allowed by the specification. Non-supported registers (such as 7 to 15) will
be read as hexadecimal “FFFF”. Device registers are detailed in Chapter 4, "Register Descriptions,"
on page 50.
At the system level, SMI provides 2 signals: MDIO and MDC. The MDC signal is an aperiodic clock
provided by the station management controller (SMC). MDIO is a bi-directional data SMI input/output
signal that receives serial data (commands) from the controller SMC and sends serial data (status) to
the SMC. The minimum time between edges of the MDC is 160 ns. There is no maximum time
between edges. The minimum cycle time (time between two consecutive rising or two consecutive
falling edges) is 400 ns. These modest timing requirements allow this interface to be easily driven by
the I/O port of a microcontroller.
The data on the MDIO line is latched on the rising edge of the MDC. The frame structure and timing
of the data is shown in Figure 3.5 and Figure 3.6. The timing relationships of the MDIO signals are
further described in Section 5.5.6, "SMI Timing," on page 76.
Read Cycle
MDC
...
D1
D15 D14
D0
32 1's
0
1
1
0
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
...
MDIO
Start of
Frame
OP
Code
Turn
Around
Preamble
PHY Address
Register Address
Data
Data To Phy
Data From Phy
Figure 3.5 MDIO Timing and Frame Structure - READ Cycle
Write Cycle
MDC
...
D15 D14
D1
D0
32 1's
0
1
0
1
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
PHY Address Register Address
...
MDIO
Start of
Frame
OP
Code
Turn
Around
Preamble
Data
Data To Phy
Figure 3.6 MDIO Timing and Frame Structure - WRITE Cycle
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3.6
Interrupt Management
The device management interface supports an interrupt capability that is not a part of the IEEE 802.3
specification. This interrupt capability generates an active low asynchronous interrupt signal on the
nINT output whenever certain events are detected as setup by the Interrupt Mask Register.
The device’s interrupt system provides two modes, a Primary Interrupt mode and an Alternative
interrupt mode. Both systems will assert the nINT pin low when the corresponding mask bit is set.
These modes differ only in how they de-assert the nINT interrupt output. These modes are detailed in
the following subsections.
Note: The Primary interrupt mode is the default interrupt mode after a power-up or hard reset. The
Alternative interrupt mode requires setup after a power-up or hard reset.
3.6.1
Primary Interrupt System
The Primary interrupt system is the default interrupt mode (ALTINT bit of the Mode Control/Status
Register is “0”). The Primary interrupt system is always selected after power-up or hard reset. In this
mode, to set an interrupt, set the corresponding mask bit in the Interrupt Mask Register (see Table 3.3).
Then when the event to assert nINT is true, the nINT output will be asserted. When the corresponding
event to deassert nINT is true, then the nINT will be de-asserted.
Table 3.3 Interrupt Management Table
INTERRUPT SOURCE
FLAG
EVENT TO
ASSERT nINT
EVENT TO
DE-ASSERT nINT
MASK
INTERRUPT SOURCE
30.7
29.7
ENERGYON
17.1
ENERGYON
Rising 17.1
(Note 3.3)
Falling 17.1 or
Reading register 29
30.6
30.5
29.6
29.5
Auto-Negotiation
complete
1.5
1.4
Auto-Negotiate
Complete
Rising 1.5
Falling 1.5 or
Reading register 29
Remote Fault
Detected
Remote Fault
Rising 1.4
Falling 1.4, or
Reading register 1 or
Reading register 29
30.4
30.3
30.2
29.4
29.3
29.2
Link Down
1.2
Link Status
Falling 1.2
Rising 5.14
Rising 6.4
Reading register 1 or
Reading register 29
Auto-Negotiation
LP Acknowledge
5.14
6.4
Acknowledge
Falling 5.14 or
Read register 29
Parallel Detection
Fault
Parallel
Detection Fault
Falling 6.4 or
Reading register 6, or
Reading register 29
or
Re-Auto Negotiate or
Link down
30.1
29.1
Auto-Negotiation
Page Received
6.1
Page Received
Rising 6.1
Falling of 6.1 or
Reading register 6, or
Reading register 29
Re-Auto Negotiate, or
Link Down.
Note 3.3 If the mask bit is enabled and nINT has been de-asserted while ENERGYON is still high,
nINT will assert for 256 ms, approximately one second after ENERGYON goes low when
the Cable is unplugged. To prevent an unexpected assertion of nINT, the ENERGYON
interrupt mask should always be cleared as part of the ENERGYON interrupt service
routine.
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Note: The ENERGYON bit in the Mode Control/Status Register is defaulted to a ‘1’ at the start of the
signal acquisition process, therefore the INT7 bit in the Interrupt Mask Register will also read
as a ‘1’ at power-up. If no signal is present, then both ENERGYON and INT7 will clear within
a few milliseconds.
3.6.2
Alternate Interrupt System
The Alternate interrupt system is enabled by setting the ALTINT bit of the Mode Control/Status Register
to “1”. In this mode, to set an interrupt, set the corresponding bit of the in the Mask Register 30, (see
Table 3.4). To Clear an interrupt, either clear the corresponding bit in the Interrupt Mask Register to
deassert the nINT output, or clear the interrupt source, and write a ‘1’ to the corresponding Interrupt
Source Flag. Writing a ‘1’ to the Interrupt Source Flag will cause the state machine to check the
Interrupt Source to determine if the Interrupt Source Flag should clear or stay as a ‘1’. If the Condition
to deassert is true, then the Interrupt Source Flag is cleared and nINT is also deasserted. If the
Condition to deassert is false, then the Interrupt Source Flag remains set, and the nINT remains
asserted.
For example, setting the INT7 bit in the Interrupt Mask Register will enable the ENERGYON interrupt.
After a cable is plugged in, the ENERGYON bit in the Mode Control/Status Register goes active and
nINT will be asserted low. To de-assert the nINT interrupt output, either clear the ENERGYON bit in
the Mode Control/Status Register by removing the cable and then writing a ‘1’ to the INT7 bit in the
Interrupt Mask Register, OR clear the INT7 mask (bit 7 of the Interrupt Mask Register).
Table 3.4 Alternative Interrupt System Management Table
CONDITION
TO
DE-ASSERT
BIT TO
CLEAR
nINT
INTERRUPT SOURCE
FLAG
EVENT TO
ASSERT nINT
MASK
INTERRUPT SOURCE
30.7
30.6
29.7
29.6
ENERGYON
17.1 ENERGYON
Rising 17.1
Rising 1.5
17.1 low
1.5 low
29.7
Auto-Negotiation
complete
1.5
1.4
1.2
Auto-Negotiate
Complete
29.6
29.5
30.5
29.5
Remote Fault
Detected
Remote Fault
Rising 1.4
1.4 low
30.4
30.3
29.4
29.3
Link Down
Link Status
Falling 1.2
Rising 5.14
1.2 high
5.14 low
29.4
29.3
Auto-Negotiation
LP Acknowledge
5.14 Acknowledge
30.2
30.1
29.2
29.1
Parallel
6.4
6.1
Parallel Detection
Fault
Rising 6.4
Rising 6.1
6.4 low
6.1 low
29.2
29.1
Detection Fault
Auto-Negotiation
Page Received
Page Received
Note: The ENERGYON bit in the Mode Control/Status Register is defaulted to a ‘1’ at the start of the
signal acquisition process, therefore the INT7 bit in the Interrupt Mask Register will also read
as a ‘1’ at power-up. If no signal is present, then both ENERGYON and INT7 will clear within
a few milliseconds.
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3.7
Configuration Straps
Configuration straps allow various features of the device to be automatically configured to user defined
values. Configuration straps are latched upon Power-On Reset (POR) and pin reset (nRST).
Configuration straps include internal resistors in order to prevent the signal from floating when
unconnected. If a particular configuration strap is connected to a load, an external pull-up or pull-down
resistor should be used to augment the internal resistor to ensure that it reaches the required voltage
level prior to latching. The internal resistor can also be overridden by the addition of an external
resistor.
Note: The system designer must guarantee that configuration strap pins meet the timing
requirements specified in Section 5.5.3, "Power-On nRST & Configuration Strap Timing," on
page 72. If configuration strap pins are not at the correct voltage level prior to being latched,
the device may capture incorrect strap values.
Note: When externally pulling configuration straps high, the strap should be tied to VDDIO, except
for REGOFF and nINTSEL which should be tied to VDD2A.
3.7.1
PHYAD[2:0]: PHY Address Configuration
The PHYAD[2:0] configuration straps are driven high or low to give each PHY a unique address. This
address is latched into an internal register at the end of a hardware reset (default = 000b). In a multi-
transceiver application (such as a repeater), the controller is able to manage each transceiver via the
unique address. Each transceiver checks each management data frame for a matching address in the
relevant bits. When a match is recognized, the transceiver responds to that particular frame. The PHY
address is also used to seed the scrambler. In a multi-transceiver application, this ensures that the
scramblers are out of synchronization and disperses the electromagnetic radiation across the
frequency spectrum.
The device’s SMI address may be configured using hardware configuration to any value between 0
and 7. The user can configure the PHY address using Software Configuration if an address greater
than 7 is required. The PHY address can be written (after SMI communication at some address is
established) using the PHYAD bits of the Special Modes Register. The PHYAD[2:0] configuration straps
are multiplexed with other signals as shown in Table 3.5.
Table 3.5 Pin Names for Address Bits
ADDRESS BIT
PIN NAME
PHYAD[0]
PHYAD[1]
PHYAD[2]
RXER/RXD4/PHYAD0
RXCLK/PHYAD1
RXD3/PHYAD2
3.7.2
MODE[2:0]: Mode Configuration
The MODE[2:0] configuration straps control the configuration of the 10/100 digital block. When the
nRST pin is deasserted, the register bit values are loaded according to the MODE[2:0] configuration
straps. The 10/100 digital block is then configured by the register bit values. When a soft reset occurs
via the Soft Reset bit of the Basic Control Register, the configuration of the 10/100 digital block is
controlled by the register bit values and the MODE[2:0] configuration straps have no affect.
The device’s mode may be configured using the hardware configuration straps as summarized in
Table 3.6. The user may configure the transceiver mode by writing the SMI registers.
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Table 3.6 MODE[2:0] Bus
DEFAULT REGISTER BIT VALUES
MODE[2:0]
MODE DEFINITIONS
REGISTER 0
[13,12,10,8]
REGISTER 4
[8,7,6,5]
000
001
010
10Base-T Half Duplex. Auto-negotiation disabled.
10Base-T Full Duplex. Auto-negotiation disabled.
0000
0001
1000
N/A
N/A
N/A
100Base-TX Half Duplex. Auto-negotiation
disabled.
CRS is active during Transmit & Receive.
011
100
100Base-TX Full Duplex. Auto-negotiation disabled.
CRS is active during Receive.
1001
1100
N/A
100Base-TX Half Duplex is advertised. Auto-
negotiation enabled.
CRS is active during Transmit & Receive.
0100
101
110
Repeater mode. Auto-negotiation enabled.
100Base-TX Half Duplex is advertised.
CRS is active during Receive.
1100
N/A
0100
N/A
Power Down mode. In this mode the transceiver will
wake-up in Power-Down mode. The transceiver
cannot be used when the MODE[2:0] bits are set to
this mode. To exit this mode, the MODE bits in
Register 18.7:5(see Section 4.2.9, "Special Modes
Register," on page 60) must be configured to some
other value and a soft reset must be issued.
111
All capable. Auto-negotiation enabled.
X10X
1111
The MODE[2:0] hardware configuration pins are multiplexed with other signals as shown in Table 3.7.
Table 3.7 Pin Names for Mode Bits
MODE BIT
PIN NAME
MODE[0]
MODE[1]
MODE[2]
RXD0/MODE0
RXD1/MODE1
COL/CRS_DV/MODE2
3.7.3
RMIISEL: MII/RMII Mode Configuration
MII or RMII mode selection is latched on the rising edge of the internal reset (nRST) based on the
strapping of the RMIISEL configuration strap. The default mode is MII (via the internal pull-down
resistor). To select RMII mode, pull the RMIISEL configuration strap high with an external resistor to
VDDIO.
When the nRST pin is deasserted, the MIIMODE bit of the Special Modes Register is loaded according
to the RMIISEL configuration strap. The mode is reflected in the MIIMODE bit of the Special Modes
Register.
Refer to Section 3.4, "MAC Interface," on page 30 for additional information on MII and RMII modes.
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3.7.4
REGOFF: Internal +1.2V Regulator Configuration
The incorporation of flexPWR technology provides the ability to disable the internal +1.2V regulator.
When the regulator is disabled, an external +1.2V must be supplied to the VDDCR pin. Disabling the
internal +1.2V regulator makes it possible to reduce total system power, since an external switching
regulator with greater efficiency (versus the internal linear regulator) can be used to provide +1.2V to
the transceiver circuitry.
Note: Because the REGOFF configuration strap shares functionality with the LED1 pin, proper
consideration must also be given to the LED polarity. Refer to Section 3.8.1.1, "REGOFF and
LED1 Polarity Selection," on page 39 for additional information on the relation between
REGOFF and the LED1 polarity.
3.7.4.1
Disabling the Internal +1.2V Regulator
To disable the +1.2V internal regulator, a pull-up strapping resistor should be connected from the
REGOFF configuration strap to VDD2A. At power-on, after both VDDIO and VDD2A are within
specification, the transceiver will sample REGOFF to determine whether the internal regulator should
turn on. If the pin is sampled at a voltage greater than VIH, then the internal regulator is disabled and
the system must supply +1.2V to the VDDCR pin. The VDDIO voltage must be at least 80% of the
operating voltage level (1.44V when operating at 1.8V, 2.0V when operating at 2.5V, 2.64V when
operating at 3.3V) before voltage is applied to VDDCR. As described in Section 3.7.4.2, when
REGOFF is left floating or connected to VSS, the internal regulator is enabled and the system is not
required to supply +1.2V to the VDDCR pin.
3.7.4.2
Enabling the Internal +1.2V Regulator
The +1.2V for VDDCR is supplied by the on-chip regulator unless the transceiver is configured for the
regulator off mode using the REGOFF configuration strap as described in Section 3.7.4.1. By default,
the internal +1.2V regulator is enabled when REGOFF is floating (due to the internal pull-down
resistor). During power-on, if REGOFF is sampled below VIL, then the internal +1.2V regulator will turn
on and operate with power from the VDD2A pin.
3.7.5
nINTSEL: nINT/TXER/TXD4 Configuration
The nINT, TXER, and TXD4 functions share a common pin. There are two functional modes for this
pin, the TXER/TXD4 mode and nINT (interrupt) mode. The nINTSEL configuration strap is latched at
POR and on the rising edge of the nRST. By default, nINTSEL is configured for nINT mode via the
internal pull-up resistor.
Note: Because the nINTSEL configuration strap shares functionality with the LED2 pin, proper
consideration must also be given to the LED polarity. Refer to Section 3.8.1.2, "nINTSEL and
LED2 Polarity Selection," on page 39 for additional information on the relation between
nINTSEL and the LED2 polarity.
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3.8
Miscellaneous Functions
3.8.1
LEDs
Two LED signals are provided as a convenient means to determine the transceiver's mode of
operation. All LED signals are either active high or active low as described in Section 3.8.1.2,
"nINTSEL and LED2 Polarity Selection" and Section 3.8.1.1, "REGOFF and LED1 Polarity Selection,"
on page 39.
The LED1 output is driven active whenever the device detects a valid link, and blinks when CRS is
active (high) indicating activity.
The LED2 output is driven active when the operating speed is 100Mbps. This LED will go inactive
when the operating speed is 10Mbps or during line isolation.
Note: When pulling the LED1 and LED2 pins high, they must be tied to VDD2A, NOT VDDIO.
3.8.1.1
REGOFF and LED1 Polarity Selection
The REGOFF configuration strap is shared with the LED1 pin. The LED1 output will automatically
change polarity based on the presence of an external pull-up resistor. If the LED1 pin is pulled high to
VDD2A by an external pull-up resistor to select a logical high for REGOFF, then the LED1 output will
be active low. If the LED1 pin is pulled low by the internal pull-down resistor to select a logical low for
REGOFF, the LED1 output will then be an active high output. Figure 3.7 details the LED1 polarity for
each REGOFF configuration.
REGOFF = 1 (Regulator OFF)
LED output = Active Low
REGOFF = 0 (Regulator ON)
LED output = Active High
VDD2A
LED1/REGOFF
10K
~270 ohms
~270 ohms
LED1/REGOFF
Figure 3.7 LED1/REGOFF Polarity Configuration
Note: Refer to Section 3.7.4, "REGOFF: Internal +1.2V Regulator Configuration," on page 38 for
additional information on the REGOFF configuration strap.
3.8.1.2
nINTSEL and LED2 Polarity Selection
The nINTSEL configuration strap is shared with the LED2 pin. The LED2 output will automatically
change polarity based on the presence of an external pull-down resistor. If the LED2 pin is pulled high
to VDD2A to select a logical high for nINTSEL, then the LED2 output will be active low. If the LED2
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pin is pulled low by an external pull-down resistor to select a logical low for nINTSEL, the LED2 output
will then be an active high output. Figure 3.8 details the LED2 polarity for each nINTSEL configuration.
nINTSEL = 1
nINTSEL = 0
LED output = Active Low
LED output = Active High
VDD2A
LED2/nINTSEL
10K
~270 ohms
~270 ohms
LED2/nINTSEL
Figure 3.8 LED2/nINTSEL Polarity Configuration
Note: Refer to Section 3.7.5, "nINTSEL: nINT/TXER/TXD4 Configuration," on page 38 for additional
information on the nINTSEL configuration strap.
3.8.2
Variable Voltage I/O
The device’s digital I/O pins are variable voltage, allowing them to take advantage of low power savings
from shrinking technologies. These pins can operate from a low I/O voltage of +1.62V up to +3.6V.
The applied I/O voltage must maintain its value with a tolerance of ± 10%. Varying the voltage up or
down after the transceiver has completed power-on reset can cause errors in the transceiver operation.
Refer to Chapter 5, "Operational Characteristics," on page 66 for additional information.
Note: Input signals must not be driven high before power is applied to the device.
3.8.3
Power-Down Modes
There are two device power-down modes: General Power-Down Mode and Energy Detect Power-
Down Mode. These modes are described in the following subsections.
3.8.3.1
General Power-Down
This power-down mode is controlled via the Power Down bit of the Basic Control Register. In this
mode, the entire transceiver (except the management interface) is powered-down and remains in this
mode as long as the Power Down bit is “1”. When the Power Down bit is cleared, the transceiver
powers up and is automatically reset.
3.8.3.2
Energy Detect Power-Down
This power-down mode is activated by setting the EDPWRDOWN bit of the Mode Control/Status
Register. In this mode, when no energy is present on the line the transceiver is powered down (except
for the management interface, the SQUELCH circuit, and the ENERGYON logic). The ENERGYON
logic is used to detect the presence of valid energy from 100BASE-TX, 10BASE-T, or Auto-negotiation
signals.
In this mode, when the ENERGYON bit of the Mode Control/Status Register is low, the transceiver is
powered-down and nothing is transmitted. When energy is received via link pulses or packets, the
ENERGYON bit goes high and the transceiver powers-up. The device automatically resets into the
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state prior to power-down and asserts the nINT interrupt if the ENERGYON interrupt is enabled in the
Interrupt Mask Register. The first and possibly the second packet to activate ENERGYON may be lost.
When the EDPWRDOWN bit of the Mode Control/Status Register is low, energy detect power-down is
disabled.
3.8.4
3.8.5
Isolate Mode
The device data paths may be electrically isolated from the MII/RMII interface by setting the Isolate bit
of the Basic Control Register to “1”. In isolation mode, the transceiver does not respond to the TXD,
TXEN and TXER inputs, but does respond to management transactions.
Isolation provides a means for multiple transceivers to be connected to the same MII/RMII interface
without contention. By default, the transceiver is not isolated (on power-up (Isolate=0).
Resets
The device provides two forms of reset: Hardware and Software. The device registers are reset by
both Hardware and Software resets. Select register bits, indicated as “NASR” in the register definitions,
are not cleared by a Software reset. The registers are not reset by the power-down modes described
in Section 3.8.3.
Note: For the first 16us after coming out of reset, the MII/RMII interface will run at 2.5 MHz. After this
time, it will switch to 25 MHz if auto-negotiation is enabled.
3.8.5.1
Hardware Reset
A Hardware reset is asserted by driving the nRST input pin low. When driven, nRST should be held
low for the minimum time detailed in Section 5.5.3, "Power-On nRST & Configuration Strap Timing,"
on page 72 to ensure a proper transceiver reset. During a Hardware reset, an external clock must be
supplied to the XTAL1/CLKIN signal.
Note: A hardware reset (nRST assertion) is required following power-up. Refer to Section 5.5.3,
"Power-On nRST & Configuration Strap Timing," on page 72 for additional information.
3.8.5.2
Software Reset
A Software reset is activated by setting the Soft Reset bit of the Basic Control Register to “1”. All
registers bits, except those indicated as “NASR” in the register definitions, are cleared by a Software
reset. The Soft Reset bit is self-clearing. Per the IEEE 802.3u standard, clause 22 (22.2.4.1.1) the reset
process will be completed within 0.5s from the setting of this bit.
3.8.6
Carrier Sense
The carrier sense (CRS) is output on the CRS pin in MII mode, and the CRS_DV pin in RMII mode.
CRS is a signal defined by the MII specification in the IEEE 802.3u standard. The device asserts CRS
based only on receive activity whenever the transceiver is either in repeater mode or full-duplex mode.
Otherwise the transceiver asserts CRS based on either transmit or receive activity.
The carrier sense logic uses the encoded, unscrambled data to determine carrier activity status. It
activates carrier sense with the detection of 2 non-contiguous zeros within any 10 bit span. Carrier
sense terminates if a span of 10 consecutive ones is detected before a /J/K/ Start-of Stream Delimiter
pair. If an SSD pair is detected, carrier sense is asserted until either /T/R/ End–of-Stream Delimiter
pair or a pair of IDLE symbols is detected. Carrier is negated after the /T/ symbol or the first IDLE. If
/T/ is not followed by /R/, then carrier is maintained. Carrier is treated similarly for IDLE followed by
some non-IDLE symbol.
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3.8.7
Collision Detect
A collision is the occurrence of simultaneous transmit and receive operations. The COL output is
asserted to indicate that a collision has been detected. COL remains active for the duration of the
collision. COL is changed asynchronously to both RXCLK and TXCLK. The COL output becomes
inactive during full duplex mode.
The COL may be tested by setting the Collision Test bit of the Basic Control Register to “1”. This
enables the collision test. COL will be asserted within 512 bit times of TXEN rising and will be de-
asserted within 4 bit times of TXEN falling.
3.8.8
Link Integrity Test
The device performs the link integrity test as outlined in the IEEE 802.3u (Clause 24-15) Link Monitor
state diagram. The link status is multiplexed with the 10Mbps link status to form the Link Status bit in
the Basic Status Register and to drive the LINK LED (LED1).
The DSP indicates a valid MLT-3 waveform present on the RXP and RXN signals as defined by the
ANSI X3.263 TP-PMD standard, to the Link Monitor state-machine, using the internal DATA_VALID
signal. When DATA_VALID is asserted, the control logic moves into a Link-Ready state and waits for
an enable from the auto-negotiation block. When received, the Link-Up state is entered, and the
Transmit and Receive logic blocks become active. Should auto-negotiation be disabled, the link
integrity logic moves immediately to the Link-Up state when the DATA_VALID is asserted.
To allow the line to stabilize, the link integrity logic will wait a minimum of 330 μsec from the time
DATA_VALID is asserted until the Link-Ready state is entered. Should the DATA_VALID input be
negated at any time, this logic will immediately negate the Link signal and enter the Link-Down state.
When the 10/100 digital block is in 10BASE-T mode, the link status is derived from the 10BASE-T
receiver logic.
3.8.9
Loopback Operation
The device may be configured for near-end loopback and far loopback. These loopback modes are
detailed in the following subsections.
3.8.9.1
Near-end Loopback
Near-end loopback mode sends the digital transmit data back out the receive data signals for testing
purposes, as indicated by the blue arrows in Figure 3.9. The near-end loopback mode is enabled by
setting the Loopback bit of the Basic Control Register to “1”. A large percentage of the digital circuitry
is operational in near-end loopback mode because data is routed through the PCS and PMA layers
into the PMD sublayer before it is looped back. The COL signal will be inactive in this mode, unless
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Collision Test is enabled in the Basic Control Register. The transmitters are powered down regardless
of the state of TXEN.
TXD
RXD
TX
RX
10/100
Ethernet
MAC
X
X
CAT-5
XFMR
Digital
Analog
SMSC
Ethernet Transceiver
Figure 3.9 Near-end Loopback Block Diagram
3.8.9.2
Far Loopback
Far loopback is a special test mode for MDI (analog) loopback as indicated by the blue arrows in
Figure 3.11. The far loopback mode is enabled by setting the FARLOOPBACK bit of the Mode
Control/Status Register to “1”. In this mode, data that is received from the link partner on the MDI is
looped back out to the link partner. The digital interface signals on the local MAC interface are isolated.
Note: This special test mode is only available when operating in RMII mode.
Far-end system
TXD
TX
RX
10/100
Ethernet
MAC
X
Link
Partner
CAT-5
XFMR
RXDX
Digital
Analog
SMSC
Ethernet Transceiver
Figure 3.10 Far Loopback Block Diagram
Connector Loopback
3.8.9.3
The device maintains reliable transmission over very short cables, and can be tested in a connector
loopback as shown in Figure 3.11. An RJ45 loopback cable can be used to route the transmit signals
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an the output of the transformer back to the receiver inputs, and this loopback will work at both 10 and
100.
1
2
TXD
RXD
TX
RX
10/100
Ethernet
MAC
3
4
5
6
7
8
XFMR
Digital
Analog
RJ45 Loopback Cable.
Created by connecting pin 1 to pin 3
and connecting pin 2 to pin 6.
SMSC
Ethernet Transceiver
Figure 3.11 Connector Loopback Block Diagram
3.9
Application Diagrams
This section provides typical application diagrams for the following:
Simplified System Level Application Diagram
Power Supply Diagram (1.2V Supplied by Internal Regulator)
Power Supply Diagram (1.2V Supplied by External Source)
Twisted-Pair Interface Diagram (Single Power Supply)
Twisted-Pair Interface Diagram (Dual Power Supplies)
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3.9.1
Simplified System Level Application Diagram
LAN8710A/LAN8710Ai
10/100 PHY
32-QFN
MII
MII
MDIO
MDC
nINT
Mag
RJ45
TXP
TXN
TXD[3:0]
4
4
TXCLK
TXER
TXEN
RXP
RXN
RXD[3:0]
RXCLK
RXDV
XTAL1/CLKIN
XTAL2
25MHz
LED[2:1]
nRST
2
Interface
Figure 3.12 Simplified System Level Application Diagram
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3.9.2
Power Supply Diagram (1.2V Supplied by Internal Regulator)
LAN8710A/LAN8710Ai
Power
Supply
3.3V
32-QFN
Ch.2 3.3V
Core Logic
Circuitry
VDDCR
VDDIO
Internal
Regulator
VDD2A
OUT
IN
1 uF
470 pF
CBYPASS
VDDDIO
Supply
1.8 - 3.3V
VDD1A
RBIAS
Ch.1 3.3V
Circuitry
CBYPASS
CF
CBYPASS
LED1/
REGOFF
12.1k
VSS
~270 Ohm
Figure 3.13 Power Supply Diagram (1.2V Supplied by Internal Regulator)
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3.9.3
Power Supply Diagram (1.2V Supplied by External Source)
LAN8710A/LAN8710Ai
Power
Supply
3.3V
32-QFN
Ch.2 3.3V
Core Logic
Circuitry
VDDCR
Supply
1.2V
Internal
Regulator
(Disabled)
VDDCR
VDDIO
VDD2A
OUT
IN
1 uF
470 pF
CBYPASS
VDDDIO
Supply
1.8 - 3.3V
VDD1A
RBIAS
Ch.1 3.3V
Circuitry
CBYPASS
CF
CBYPASS
LED1/
REGOFF
12.1k
VSS
~270 Ohm
10k
Figure 3.14 Power Supply Diagram (1.2V Supplied by External Source)
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3.9.4
Twisted-Pair Interface Diagram (Single Power Supply)
Ferrite
bead
LAN8710A/LAN8710Ai
32-QFN
Power
Supply
3.3V
49.9 Ohm Resistors
VDD2A
VDD1A
TXP
CBYPASS
CBYPASS
Magnetics
RJ45
1
2
3
4
5
6
7
8
75
75
TXN
RXP
RXN
1000 pF
3 kV
CBYPASS
Figure 3.15 Twisted-Pair Interface Diagram (Single Power Supply)
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3.9.5
Twisted-Pair Interface Diagram (Dual Power Supplies)
LAN8710A/LAN8710Ai
32-QFN
Power
Supply
3.3V
Power
Supply
2.5V - 3.3V
49.9 Ohm Resistors
VDD2A
VDD1A
TXP
CBYPASS
CBYPASS
Magnetics
RJ45
1
2
3
4
5
6
7
8
75
75
TXN
RXP
RXN
1000 pF
3 kV
CBYPASS
Figure 3.16 Twisted-Pair Interface Diagram (Dual Power Supplies)
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Chapter 4 Register Descriptions
This chapter describes the various control and status registers (CSR’s). All registers follow the IEEE
802.3 (clause 22.2.4) management register set. All functionality and bit definitions comply with these
standards. The IEEE 802.3 specified register index (in decimal) is included with each register definition,
allowing for addressing of these registers via the Serial Management Interface (SMI) protocol.
4.1
Register Nomenclature
Table 4.1 describes the register bit attribute notation used throughout this document.
Table 4.1 Register Bit Types
REGISTER BIT TYPE
NOTATION
REGISTER BIT DESCRIPTION
R
W
Read: A register or bit with this attribute can be read.
Read: A register or bit with this attribute can be written.
Read only: Read only. Writes have no effect.
RO
WO
WC
WAC
RC
LL
Write only: If a register or bit is write-only, reads will return unspecified data.
Write One to Clear: writing a one clears the value. Writing a zero has no effect
Write Anything to Clear: writing anything clears the value.
Read to Clear: Contents is cleared after the read. Writes have no effect.
Latch Low: Clear on read of register.
LH
Latch High: Clear on read of register.
SC
Self-Clearing: Contents are self-cleared after the being set. Writes of zero have no
effect. Contents can be read.
SS
Self-Setting: Contents are self-setting after being cleared. Writes of one have no
effect. Contents can be read.
RO/LH
Read Only, Latch High: Bits with this attribute will stay high until the bit is read. After
it is read, the bit will either remain high if the high condition remains, or will go low if
the high condition has been removed. If the bit has not been read, the bit will remain
high regardless of a change to the high condition. This mode is used in some Ethernet
PHY registers.
NASR
Not Affected by Software Reset. The state of NASR bits do not change on assertion
of a software reset.
RESERVED
Reserved Field: Reserved fields must be written with zeros to ensure future
compatibility. The value of reserved bits is not guaranteed on a read.
Many of these register bit notations can be combined. Some examples of this are shown below:
R/W: Can be written. Will return current setting on a read.
R/WAC: Will return current setting on a read. Writing anything clears the bit.
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4.2
Control and Status Registers
Table 4.2 provides a list of supported registers. Register details, including bit definitions, are provided
in the proceeding subsections.
Table 4.2 SMI Register Map
REGISTER INDEX
(DECIMAL)
REGISTER NAME
Basic Control Register
GROUP
0
1
Basic
Basic Status Register
Basic
2
PHY Identifier 1
Extended
3
PHY Identifier 2
Extended
4
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Ability Register
Auto-Negotiation Expansion Register
Mode Control/Status Register
Special Modes
Extended
5
Extended
6
Extended
17
18
26
27
29
30
31
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Symbol Error Counter Register
Control / Status Indication Register
Interrupt Source Register
Interrupt Mask Register
PHY Special Control/Status Register
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4.2.1
Basic Control Register
Index (In Decimal):
0
Size:
16 bits
BITS
DESCRIPTION
TYPE
DEFAULT
15
Soft Reset
R/W
SC
0b
1 = software reset. Bit is self-clearing. When setting this bit do not set other
bits in this register. The configuration (as described in Section 3.7.2,
"MODE[2:0]: Mode Configuration," on page 36) is set from the register bit
values, and not from the mode pins.
14
13
Loopback
R/W
R/W
0b
0 = normal operation
1 = loopback mode
Speed Select
0 = 10Mbps
1 = 100Mbps
Note 4.1
Note:
Ignored if Auto-negotiation is enabled (0.12 = 1).
12
11
Auto-Negotiation Enable
R/W
R/W
Note 4.1
0b
0 = disable auto-negotiate process
1 = enable auto-negotiate process (overrides 0.13 and 0.8)
Power Down
0 = normal operation
1 = General power down mode
Note:
The Auto-Negotiation Enable must be cleared before setting the
Power Down.
10
9
Isolate
R/W
0b
0b
0 = normal operation
1 = electrical isolation of PHY from the MII/RMII
Restart Auto-Negotiate
0 = normal operation
1 = restart auto-negotiate process
R/W
SC
Note:
Bit is self-clearing.
8
Duplex Mode
0 = half duplex
1 = full duplex
R/W
Note 4.1
Note:
Ignored if Auto-Negotiation is enabled (0.12 = 1).
7
Collision Test
R/W
RO
0b
-
0 = disable COL test
1 = enable COL test
6:0
RESERVED
Note 4.1 The default value of this bit is determined by the MODE[2:0] configuration straps. Refer to
Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 36 for additional information.
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4.2.2
Basic Status Register
Index (In Decimal):
1
Size:
16 bits
BITS
DESCRIPTION
TYPE
DEFAULT
15
100BASE-T4
0 = no T4 ability
1 = T4 able
RO
0b
14
13
12
11
10
9
100BASE-TX Full Duplex
0 = no TX full duplex ability
1 = TX with full duplex
RO
RO
RO
RO
RO
RO
RO
1b
1b
1b
1b
0b
0b
0b
100BASE-TX Half Duplex
0 = no TX half duplex ability
1 = TX with half duplex
10BASE-T Full Duplex
0 = no 10Mbps with full duplex ability
1 = 10Mbps with full duplex
10BASE-T Half Duplex
0 = no 10Mbps with half duplex ability
1 = 10Mbps with half duplex
100BASE-T2 Full Duplex
0 = PHY not able to perform full duplex 100BASE-T2
1 = PHY able to perform full duplex 100BASE-T2
100BASE-T2 Half Duplex
0 = PHY not able to perform half duplex 100BASE-T2
1 = PHY able to perform half duplex 100BASE-T2
8
Extended Status
0 = no extended status information in register 15
1 = extended status information in register 15
7:6
5
RESERVED
RO
RO
-
Auto-Negotiate Complete
0 = auto-negotiate process not completed
1 = auto-negotiate process completed
0b
4
3
2
1
0
Remote Fault
RO/LH
RO
0b
1b
0b
0b
1b
1 = remote fault condition detected
0 = no remote fault
Auto-Negotiate Ability
0 = unable to perform auto-negotiation function
1 = able to perform auto-negotiation function
Link Status
0 = link is down
1 = link is up
RO/LL
RO/LH
RO
Jabber Detect
0 = no jabber condition detected
1 = jabber condition detected
Extended Capabilities
0 = does not support extended capabilities registers
1 = supports extended capabilities registers
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Datasheet
4.2.3
PHY Identifier 1 Register
Index (In Decimal):
2
Size:
16 bits
BITS
DESCRIPTION
TYPE
DEFAULT
15:0
PHY ID Number
R/W
0007h
Assigned to the 3rd through 18th bits of the Organizationally Unique
Identifier (OUI), respectively.
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4.2.4
PHY Identifier 2 Register
Index (In Decimal):
3
Size:
16 bits
BITS
DESCRIPTION
TYPE
DEFAULT
15:10
PHY ID Number
R/W
110000b
001111b
Assigned to the 19th through 24th bits of the OUI.
9:4
3:0
Model Number
Six-bit manufacturer’s model number.
R/W
R/W
Revision Number
Four-bit manufacturer’s revision number.
Note 4.2
Note 4.2 The default value of this field will vary dependant on the silicon revision number.
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Datasheet
4.2.5
Auto Negotiation Advertisement Register
Index (In Decimal):
4
Size:
16 bits
BITS
DESCRIPTION
TYPE
DEFAULT
15:14
13
RESERVED
RO
-
Remote Fault
0 = no remote fault
1 = remote fault detected
R/W
0b
12
RESERVED
RO
-
11:10
Pause Operation
00 = No PAUSE
R/W
00b
01 = Symmetric PAUSE
10 = Asymmetric PAUSE toward link partner
11 = Advertise support for both Symmetric PAUSE and Asymmetric PAUSE
toward local device
Note:
When both Symmetric PAUSE and Asymmetric PAUSE are set, the
device will only be configured to, at most, one of the two settings
upon auto-negotiation completion.
9
8
RESERVED
RO
-
100BASE-TX Full Duplex
0 = no TX full duplex ability
1 = TX with full duplex
R/W
Note 4.3
7
6
100BASE-TX
0 = no TX ability
1 = TX able
R/W
R/W
R/W
R/W
1b
10BASE-T Full Duplex
0 = no 10Mbps with full duplex ability
1 = 10Mbps with full duplex
Note 4.3
Note 4.3
00001b
5
10BASE-T
0 = no 10Mbps ability
1 = 10Mbps able
4:0
Selector Field
00001 = IEEE 802.3
Note 4.3 The default value of this bit is determined by the MODE[2:0] configuration straps. Refer to
Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 36 for additional information.
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Datasheet
4.2.6
Auto Negotiation Link Partner Ability Register
Index (In Decimal):
5
Size:
16 bits
BITS
DESCRIPTION
TYPE
DEFAULT
15
Next Page
0 = no next page ability
1 = next page capable
RO
0b
Note:
This device does not support next page ability.
14
13
Acknowledge
RO
RO
0b
0b
0 = link code word not yet received
1 = link code word received from partner
Remote Fault
0 = no remote fault
1 = remote fault detected
12:11
10
RESERVED
RO
RO
-
Pause Operation
0 = No PAUSE supported by partner station
1 = PAUSE supported by partner station
0b
9
100BASE-T4
0 = no T4 ability
1 = T4 able
RO
0b
Note:
This device does not support T4 ability.
8
7
100BASE-TX Full Duplex
0 = no TX full duplex ability
1 = TX with full duplex
RO
RO
RO
RO
RO
0b
0b
100BASE-TX
0 = no TX ability
1 = TX able
6
10BASE-T Full Duplex
0 = no 10Mbps with full duplex ability
1 = 10Mbps with full duplex
0b
5
10BASE-T
0 = no 10Mbps ability
1 = 10Mbps able
0b
4:0
Selector Field
00001 = IEEE 802.3
00001b
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Datasheet
4.2.7
Auto Negotiation Expansion Register
Index (In Decimal):
6
Size:
16 bits
BITS
DESCRIPTION
TYPE
DEFAULT
15:5
4
RESERVED
Parallel Detection Fault
0 = no fault detected by parallel detection logic
1 = fault detected by parallel detection logic
RO
-
RO/LH
0b
3
2
1
0
Link Partner Next Page Able
RO
RO
0b
0b
0b
0b
0 = link partner does not have next page ability
1 = link partner has next page ability
Next Page Able
0 = local device does not have next page ability
1 = local device has next page ability
Page Received
0 = new page not yet received
1 = new page received
RO/LH
RO
Link Partner Auto-Negotiation Able
0 = link partner does not have auto-negotiation ability
1 = link partner has auto-negotiation ability
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Datasheet
4.2.8
Mode Control/Status Register
Index (In Decimal): 17
Size:
16 bits
BITS
DESCRIPTION
TYPE
DEFAULT
15:14
13
RESERVED
EDPWRDOWN
Enable the Energy Detect Power-Down mode:
0 = Energy Detect Power-Down is disabled
1 = Energy Detect Power-Down is enabled
RO
-
R/W
0b
12:10
9
RESERVED
RO
-
FARLOOPBACK
R/W
0b
Enables far loopback mode (i.e., all the received packets are sent back
simultaneously (in 100BASE-TX only)). This bit is only active in RMII mode.
This mode works even if the Isolate bit (0.10) is set.
0 = Far loopback mode is disabled
1 = Far loopback mode is enabled
Refer to Section 3.8.9.2, "Far Loopback," on page 43 for additional
information.
8:7
6
RESERVED
RO
-
ALTINT
Alternate Interrupt Mode:
R/W
0b
0 = Primary interrupt system enabled (Default)
1 = Alternate interrupt system enabled
Refer to Section 3.6, "Interrupt Management," on page 34 for additional
information.
5:2
1
RESERVED
RO
RO
-
ENERGYON
1b
Indicates whether energy is detected. This bit transitions to “0” if no valid
energy is detected within 256ms. It is reset to “1” by a hardware reset and
is unaffected by a software reset. Refer to Section 3.8.3.2, "Energy Detect
Power-Down," on page 40 for additional information.
0
RESERVED
R/W
0b
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Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology
Datasheet
4.2.9
Special Modes Register
Index (In Decimal): 18
Size:
16 bits
BITS
DESCRIPTION
TYPE
DEFAULT
15
14
RESERVED
RO
-
MIIMODE
R/W
NASR
Note 4.4
Reflects the mode of the digital interface:
0 = MII Mode
1 = RMII Mode
Note:
When writing to this register, the default value of this bit must
always be written back.
13:8
7:5
RESERVED
RO
-
MODE
R/W
NASR
Note 4.5
Transceiver mode of operation. Refer to Section 3.7.2, "MODE[2:0]: Mode
Configuration," on page 36 for additional details.
4:0
PHYAD
R/W
NASR
Note 4.6
PHY Address. The PHY Address is used for the SMI address and for
initialization of the Cipher (Scrambler) key. Refer to Section 3.7.1,
"PHYAD[2:0]: PHY Address Configuration," on page 36 for additional details.
Note 4.4 The default value of this field is determined by the RMIISEL configuration strap. Refer to
Section 3.7.3, "RMIISEL: MII/RMII Mode Configuration," on page 37 for additional
information.
Note 4.5 The default value of this field is determined by the MODE[2:0] configuration straps. Refer
to Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 36 for additional information.
Note 4.6 The default value of this field is determined by the PHYAD[2:0] configuration straps. Refer
to Section 3.7.1, "PHYAD[2:0]: PHY Address Configuration," on page 36 for additional
information.
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Datasheet
4.2.10
Symbol Error Counter Register
Index (In Decimal): 26
Size:
16 bits
BITS
DESCRIPTION
TYPE
DEFAULT
15:0
SYM_ERR_CNT
RO
0000h
The symbol error counter increments whenever an invalid code symbol is
received (including IDLE symbols) in 100BASE-TX mode. The counter is
incremented only once per packet, even when the received packet contains
more than one symbol error. This counter increments up to 65,536 (216) and
rolls over to 0 after reaching the maximum value.
Note:
This register is cleared on reset, but is not cleared by reading the
register. This register does not increment in 10BASE-T mode.
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4.2.11
Special Control/Status Indications Register
Index (In Decimal): 27
Size:
16 bits
BITS
DESCRIPTION
TYPE
DEFAULT
15
AMDIXCTRL
R/W
0b
HP Auto-MDIX control:
0 = Enable Auto-MDIX
1 = Disable Auto-MDIX (use 27.13 to control channel)
14
13
RESERVED
RO
-
CH_SELECT
Manual channel select:
0 = MDI (TX transmits, RX receives)
1 = MDIX (TX receives, RX transmits)
R/W
0b
12
11
RESERVED
RO
-
SQEOFF
R/W
NASR
0b
Disable the SQE test (Heartbeat):
0 = SQE test is enabled
1 = SQE test is disabled
10:5
4
RESERVED
RO
RO
-
XPOL
0b
Polarity state of the 10BASE-T:
0 = Normal polarity
1 = Reversed polarity
3:0
RESERVED
RO
-
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Datasheet
4.2.12
Interrupt Source Flag Register
Index (In Decimal): 29
Size:
16 bits
BITS
DESCRIPTION
TYPE
DEFAULT
15:8
7
RESERVED
RO
-
INT7
RO/LH
0b
0 = not source of interrupt
1 = ENERGYON generated
6
5
4
3
2
1
0
INT6
RO/LH
RO/LH
RO/LH
RO/LH
RO/LH
RO/LH
RO
0b
0b
0b
0b
0b
0b
0b
0 = not source of interrupt
1 = Auto-Negotiation complete
INT5
0 = not source of interrupt
1 = Remote Fault Detected
INT4
0 = not source of interrupt
1 = Link Down (link status negated)
INT3
0 = not source of interrupt
1 = Auto-Negotiation LP Acknowledge
INT2
0 = not source of interrupt
1 = Parallel Detection Fault
INT1
0 = not source of interrupt
1 = Auto-Negotiation Page Received
RESERVED
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Datasheet
4.2.13
Interrupt Mask Register
Index (In Decimal): 30
Size:
16 bits
BITS
DESCRIPTION
TYPE
DEFAULT
15:8
7:1
RESERVED
RO
-
Mask Bits
0 = interrupt source is masked
1 = interrupt source is enabled
R/W
0000000b
Note:
Refer to Section 4.2.12, "Interrupt Source Flag Register," on
page 63 for details on the corresponding interrupt definitions.
0
RESERVED
RO
-
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Datasheet
4.2.14
PHY Special Control/Status Register
Index (In Decimal): 31
Size:
16 bits
BITS
DESCRIPTION
TYPE
DEFAULT
15:13
12
RESERVED
Autodone
RO
RO
-
0b
Auto-negotiation done indication:
0 = Auto-negotiation is not done or disabled (or not active)
1 = Auto-negotiation is done
11:7
6
RESERVED
R/W
R/W
-
Enable 4B5B
0 = bypass encoder/decoder
1 = enable 4B5B encoding/decoding. MAC Interface must be configured in
MII mode.
1b
5
RESERVED
RO
RO
-
4:2
Speed Indication
HCDSPEED value:
XXX
001 = 10BASE-T half-duplex
101 = 10BASE-T full-duplex
010 = 100BASE-TX half-duplex
110 = 100BASE-TX full-duplex
1:0
RESERVED
RO
-
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Datasheet
Chapter 5 Operational Characteristics
5.1
Absolute Maximum Ratings*
Supply Voltage (VDDIO, VDD1A, VDD2A) (Note 5.1) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +3.6V
Digital Core Supply Voltage (VDDCR) (Note 5.1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +1.5V
Ethernet Magnetics Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +3.6V
Positive voltage on signal pins, with respect to ground (Note 5.2) . . . . . . . . . . . . . . . . . . . . . . . . . . +6V
Negative voltage on signal pins, with respect to ground (Note 5.3) . . . . . . . . . . . . . . . . . . . . . . . .-0.5V
Positive voltage on XTAL1/CLKIN, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.6V
Positive voltage on XTAL2, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.5V
Ambient Operating Temperature in Still Air (TA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Note 5.40
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +150oC
Junction to Ambient (θJA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..48.3C/W
Junction to Case (θJC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..10.6oC/W
Lead Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to JEDEC Spec. J-STD-020
HBM ESD Performance per JEDEC JESD22-A114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 3A
IEC61000-4-2 Contact Discharge ESD Performance (Note 5.5) . . . . . . . . . . . . . . . . . . . . . . . . . .+/-8kV
IEC61000-4-2 Air-Gap Discharge ESD Performance (Note 5.5) . . . . . . . . . . . . . . . . . . . . . . . . .+/-15kV
Latch-up Performance per EIA/JESD 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..+/-150mA
Note 5.1 When powering this device from laboratory or system power supplies, it is important that
the absolute maximum ratings not be exceeded or device failure can result. Some power
supplies exhibit voltage spikes on their outputs when AC power is switched on or off. In
addition, voltage transients on the AC power line may appear on the DC output. If this
possibility exists, it is suggested that a clamp circuit be used.
Note 5.2 This rating does not apply to the following pins: XTAL1/CLKIN, XTAL2, RBIAS.
Note 5.3 This rating does not apply to the following pins: RBIAS.
Note 5.4 0oC to +85oC for extended commercial version, -40oC to +85oC for industrial version.
Note 5.5 Performed by independent 3rd party test facility.
*Stresses exceeding those listed in this section could cause permanent damage to the device. This is
a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Functional operation of the device at any condition exceeding those indicated in
Section 5.2, "Operating Conditions**", Section 5.1, "Absolute Maximum Ratings*", or any other
applicable section of this specification is not implied. Note, device signals are NOT 5 volt tolerant
unless specified otherwise.
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5.2
Operating Conditions**
Supply Voltage (VDDIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+1.62V to +3.6V
Analog Port Supply Voltage (VDD1A, VDD2A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+3.0V to +3.6V
Digital Core Supply Voltage (VDDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+1.14V to +1.26V
Ethernet Magnetics Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+2.25V to +3.6V
Ambient Operating Temperature in Still Air (TA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Note 5.4
**Proper operation of the device is guaranteed only within the ranges specified in this section. After
the device has completed power-up, VDDIO and the magnetics power supply must maintain their
voltage level with +/-10%. Varying the voltage greater than +/-10% after the device has completed
power-up can cause errors in device operation.
Note: Do not drive input signals without power supplied to the device.
5.3
Power Consumption
This section details the device power measurements taken over various operating conditions. Unless
otherwise noted, all measurements were taken with power supplies at nominal values (VDDIO, VDD1A,
VDD2A = 3.3V, VDDCR = 1.2V). See Section 3.8.3, "Power-Down Modes," on page 40 for a
description of the power down modes.
Table 5.1 Device Only Current Consumption and Power Dissipation
VDDA3.3
POWER
PINS(mA)
VDDCR
POWER
PIN(mA)
VDDIO
POWER
PIN(mA)
TOTAL
CURRENT
(mA)
TOTAL
POWER
(mW)
POWER PIN GROUP
Max
Typical
Min
28
26
23
21
18
18
5.2
4.3
2.4
54
48
43
176
158
100BASE-TX /W TRAFFIC
10BASE-T /W TRAFFIC
101
Note 5.6
Max
Typical
Min
10.2
9.4
12.9
11.4
10.9
0.98
0.4
24.1
21.2
20.4
79.5
70
9.2
0.3
44
Note 5.6
Max
Typical
Min
4.5
4.3
3.9
3
0.3
0.2
0
7.8
5.9
5.2
25
ENERGY DETECT
POWER DOWN
1.4
1.3
19.5
15.9
Note 5.6
Max
Typical
Min
0.4
0.3
0.3
2.6
1.2
1.1
0.3
0.2
0
3.3
1.7
1.4
10.9
5.6
GENERAL POWER DOWN
2.4
Note 5.6
Note: The current at VDDCR is either supplied by the internal regulator from current entering at
VDD2A, or from an external 1.2V supply when the internal regulator is disabled.
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Datasheet
Note: Current measurements do not include power applied to the magnetics or the optional external
LEDs. The Ethernet component current is typically 41mA in 100BASE-TX mode and 100mA in
10BASE-T mode, independent of the 2.5V or 3.3V supply rail of the transformer.
Note 5.6 Calculated with full flexPWR features activated: VDDIO=1.8V & internal regulator disabled.
5.4
DC Specifications
Table 5.2 details the non-variable I/O buffer characteristics. These buffer types do not support variable
voltage operation. Table 5.3 details the variable voltage I/O buffer characteristics. Typical values are
provided for 1.8V, 2.5V, and 3.3V VDDIO cases.
Table 5.2 Non-Variable I/O Buffer Characteristics
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
IS Type Input Buffer
Low Input Level
VILI
VIHI
-0.3
V
V
High Input Level
3.6
1.39
1.79
459
Negative-Going Threshold
Positive-Going Threshold
Schmitt Trigger Hysteresis
VILT
VIHT
VHYS
1.01
1.39
336
1.19
1.59
399
V
Schmitt trigger
Schmitt trigger
V
mV
(VIHT - VILT
)
Input Leakage
IIH
-10
10
2
uA
pF
Note 5.7
(VIN = VSS or VDDIO)
Input Capacitance
O12 Type Buffers
CIN
Low Output Level
High Output Level
VOL
VOH
0.4
V
V
IOL = 12mA
VDD2A - 0.4
IOH = -12mA
Note 5.8
ICLK Type Buffer
(XTAL1 Input)
Low Input Level
High Input Level
VILI
VIHI
-0.3
1.4
0.35
V
V
VDD2A + 0.4
Note 5.7 This specification applies to all inputs and tri-stated bi-directional pins. Internal pull-down
and pull-up resistors add +/- 50uA per-pin (typical).
Note 5.8 XTAL1/CLKIN can optionally be driven from a 25MHz single-ended clock oscillator.
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Table 5.3 Variable I/O Buffer Characteristics
1.8V 2.5V 3.3V
TYP TYP TYP
PARAMETER
VIS Type Input Buffer
Low Input Level
SYMBOL
MIN
MAX
UNITS
NOTES
VILI
VIHI
-0.3
V
V
High Input Level
3.6
1.76
1.90
288
Neg-Going Threshold
Pos-Going Threshold
VILT
VIHT
VHYS
0.64
0.81
102
0.83 1.15 1.41
0.99 1.29 1.65
V
Schmitt trigger
Schmitt trigger
V
Schmitt Trigger
Hysteresis (VIHT - VILT
158
136
138
mV
)
Input Leakage
IIH
-10
10
2
uA
pF
Note 5.9
(VIN = VSS or VDDIO)
Input Capacitance
VO8 Type Buffers
CIN
Low Output Level
VOL
VOH
0.4
V
V
IOL = 8mA
IOH = -8mA
VDDIO - 0.4
High Output Level
VOD8 Type Buffer
Low Output Level
VOL
0.4
V
IOL = 8mA
Note 5.9 This specification applies to all inputs and tri-stated bi-directional pins. Internal pull-down
and pull-up resistors add +/- 50uA per-pin (typical).
Table 5.4 100BASE-TX Transceiver Characteristics
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Peak Differential Output Voltage High
Peak Differential Output Voltage Low
Signal Amplitude Symmetry
Signal Rise and Fall Time
Rise and Fall Symmetry
Duty Cycle Distortion
VPPH
VPPL
VSS
950
-950
98
3.0
-
-
-
1050
-1050
102
5.0
mVpk
mVpk
%
Note 5.10
Note 5.10
Note 5.10
Note 5.10
Note 5.10
Note 5.11
-
TRF
-
nS
TRFS
DCD
VOS
-
0.5
nS
35
-
50
-
65
%
Overshoot and Undershoot
Jitter
5
%
1.4
nS
Note 5.12
Note 5.10 Measured at line side of transformer, line replaced by 100Ω (+/- 1%) resistor.
Note 5.11 Offset from 16nS pulse width at 50% of pulse peak.
Note 5.12 Measured differentially.
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Table 5.5 10BASE-T Transceiver Characteristics
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Transmitter Peak Differential Output Voltage
Receiver Differential Squelch Threshold
VOUT
VDS
2.2
2.5
2.8
V
Note 5.13
300
420
585
mV
Note 5.13 Min/max voltages guaranteed as measured with 100Ω resistive load.
5.5
AC Specifications
This section details the various AC timing specifications of the device.
Note: The MII/SMI timing adheres to the IEEE 802.3 specification. Refer to the IEEE 802.3
specification for additional timing information.
Note: The RMII timing adheres to the RMII Consortium RMII Specification R1.2.
5.5.1
Equivalent Test Load
Output timing specifications assume a 25pF equivalent test load, unless otherwise noted, as illustrated
in Figure 5.1 below.
OUTPUT
25 pF
Figure 5.1 Output Equivalent Test Load
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5.5.2
Power Sequence Timing
This diagram illustrates the device power sequencing requirements. The VDDIO, VDD1A, VDD2A and
magnetics power supplies can turn on in any order provided they all reach operational levels within
the specified time period tpon. Device power supplies can turn off in any order provided they all reach
0 volts within the specified time period poff
.
tpon
tpoff
VDDIO
Magnetics
Power
VDD1A,
VDD2A
Figure 5.2 Power Sequence Timing
Table 5.6 Power Sequence Timing Values
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tpon
tpoff
Power supply turn on time
Power supply turn off time
50
mS
mS
500
Note: When the internal regulator is disabled, a power-up sequencing relationship exists between
VDDCR and the 3.3V power supply. For additional information refer to Section 3.7.4,
"REGOFF: Internal +1.2V Regulator Configuration," on page 38.
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5.5.3
Power-On nRST & Configuration Strap Timing
This diagram illustrates the nRST reset and configuration strap timing requirements in relation to
power-on. A hardware reset (nRST assertion) is required following power-up. For proper operation,
nRST must be asserted for no less than trstia. The nRST pin can be asserted at any time, but must
not be deasserted before tpurstd after all external power supplies have reached 80% of their nominal
operating levels. In order for valid configuration strap values to be read at power-up, the tcss and tcsh
timing constraints must be followed. Refer to Section 3.8.5, "Resets," on page 41 for additional
information.
All External
Power Supplies
80%
tpurstd
tpurstv
trstia
nRST
tcss
tcsh
Configuration Strap
Pins Input
totaa
todad
Configuration Strap
Pins Output Drive
Figure 5.3 Power-On nRST & Configuration Strap Timing
Table 5.7 Power-On nRST & Configuration Strap Timing Values
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tpurstd
tpurstv
trstia
tcss
External power supplies at 80% to nRST deassertion
External power supplies at 80% to nRST valid
nRST input assertion time
25
0
mS
nS
μS
nS
nS
nS
nS
100
200
1
Configuration strap pins setup to nRST deassertion
Configuration strap pins hold after nRST deassertion
Output tri-state after nRST assertion
tcsh
totaa
todad
50
Output drive after nRST deassertion
2
800
(Note 5.14)
Note: nRST deassertion must be monotonic.
Note: Device configuration straps are latched as a result of nRST assertion. Refer to Section 3.7,
"Configuration Straps," on page 36 for details. Configuration straps must only be pulled high or
low and must not be driven as inputs.
Note 5.14 20 clock cycles for 25MHz, or 40 clock cycles for 50MHz.
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5.5.4
MII Interface Timing
This section specifies the MII interface transmit and receive timing. Please refer to Section 3.4.1, "MII,"
on page 30 for additional details.
tclkp
tclkh tclkl
RXCLK
tval
tval
thold
RXD[3:0]
RXDV
thold
tval
Figure 5.4 MII Receive Timing
Table 5.8 MII Receive Timing Values
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
NOTES
tclkp
tclkh
tclkl
tval
RXCLK period
RXCLK high time
Note 5.15
tclkp*0.4
tclkp*0.4
ns
ns
ns
ns
tclkp*0.6
tclkp*0.6
28.0
RXCLK low time
RXD[3:0], RXDV output valid from rising edge of
RXCLK
Note 5.16
Note 5.16
thold
RXD[3:0], RXDV output hold from rising edge of
RXCLK
10.0
ns
Note 5.15 40ns for 100BASE-TX operation, 400ns for 10BASE-T operation.
Note 5.16 Timing was designed for system load between 10 pf and 25 pf.
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tclkp
tclkh tclkl
TXCLK
tsu thold
tsu thold
thold
TXD[3:0]
TXEN
thold
tsu
Figure 5.5 MII Transmit Timing
Table 5.9 MII Transmit Timing Values
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
NOTES
tclkp
tclkh
tclkl
tsu
TXCLK period
Note 5.17
tclkp*0.4
tclkp*0.4
12.0
ns
ns
ns
ns
TXCLK high time
TXCLK low time
tclkp*0.6
tclkp*0.6
TXD[3:0], TXEN setup time to rising edge of
TXCLK
Note 5.18
Note 5.18
thold
TXD[3:0], TXEN hold time after rising edge of
TXCLK
0
ns
Note 5.17 40ns for 100BASE-TX operation, 400ns for 10BASE-T operation.
Note 5.18 Timing was designed for system load between 10 pf and 25 pf.
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5.5.5
RMII Interface Timing
tclkp
tclkh tclkl
CLKIN
(REF_CLK)
toval
toval
tohold
RXD[1:0],
RXER
tohold
toval
CRS_DV
TXD[1:0]
TXEN
tsu tihold
tsu tihold
tihold
tihold
tsu
Figure 5.6 RMII Timing
Table 5.10 RMII Timing Values
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
NOTES
tclkp
tclkh
tclkl
CLKIN period
20
ns
ns
ns
ns
CLKIN high time
CLKIN low time
tclkp*0.35
tclkp*0.35
tclkp*0.65
tclkp*0.65
14.0
toval
RXD[1:0], RXER, CRS_DV output valid from
rising edge of CLKIN
Note 5.19
Note 5.19
Note 5.19
Note 5.19
tohold
tsu
RXD[1:0], RXER, CRS_DV output hold from
rising edge of CLKIN
3.0
4.0
1.5
ns
ns
ns
TXD[1:0], TXEN setup time to rising edge of
CLKIN
tihold
TXD[1:0], TXEN input hold time after rising edge
of CLKIN
Note 5.19 Timing was designed for system load between 10 pf and 25 pf.
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5.5.5.1
RMII CLKIN Requirements
Table 5.11 RMII CLKIN (REF_CLK) Timing Values
PARAMETER
MIN
TYP
MAX
UNITS
NOTES
CLKIN frequency
50
MHz
ppm
%
CLKIN Frequency Drift
CLKIN Duty Cycle
CLKIN Jitter
± 50
60
40
150
psec
p-p – not RMS
5.5.6
SMI Timing
This section specifies the SMI timing of the device. Please refer to Section 3.5, "Serial Management
Interface (SMI)," on page 33 for additional details.
tclkp
tclkh tclkl
MDC
tohold
tval
tohold
MDIO
(Data-Out)
tsu tihold
MDIO
(Data-In)
Figure 5.7 SMI Timing
Table 5.12 SMI Timing Values
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
NOTES
tclkp
tclkh
tclkl
MDC period
400
ns
ns
ns
ns
MDC high time
MDC low time
160 (80%)
160 (80%)
MDIO (read from PHY) output valid from rising
edge of MDC
300
tval
tohold
tsu
MDIO (read from PHY) output hold from rising
edge of MDC
0
ns
ns
ns
MDIO (write to PHY) setup time to rising edge
of MDC
10
10
MDIO (write to PHY) input hold time after rising
edge of MDC
tihold
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5.6
Clock Circuit
The device can accept either a 25MHz crystal or a 25MHz single-ended clock oscillator (±50ppm)
input. If the single-ended clock oscillator method is implemented, XTAL2 should be left unconnected
and XTAL1/CLKIN should be driven with a nominal 0-3.3V clock signal. See Table 5.13 for the
recommended crystal specifications.
Table 5.13 Crystal Specifications
PARAMETER
SYMBOL
MIN
NOM
AT, typ
Fundamental Mode
Parallel Resonant Mode
MAX
UNITS
NOTES
Crystal Cut
Crystal Oscillation Mode
Crystal Calibration Mode
Frequency
Ffund
Ftol
-
25.000
-
MHz
PPM
PPM
PPM
PPM
pF
Frequency Tolerance @ 25oC
Frequency Stability Over Temp
Frequency Deviation Over Time
Total Allowable PPM Budget
Shunt Capacitance
-
-
±50
Note 5.20
Note 5.20
Note 5.21
Note 5.22
Ftemp
Fage
-
-
±50
-
+/-3 to 5
-
-
-
7 typ
20 typ
-
±50
CO
CL
-
-
Load Capacitance
-
-
-
pF
Drive Level
PW
R1
300
uW
Equivalent Series Resistance
Operating Temperature Range
XTAL1/CLKIN Pin Capacitance
XTAL2 Pin Capacitance
-
-
30
+85
-
Ohm
oC
Note 5.23
-
-
-
3 typ
3 typ
pF
Note 5.24
Note 5.24
-
pF
Note 5.20 The maximum allowable values for Frequency Tolerance and Frequency Stability are
application dependant. Since any particular application must meet the IEEE ±50 PPM Total
PPM Budget, the combination of these two values must be approximately ±45 PPM
(allowing for aging).
Note 5.21 Frequency Deviation Over Time is also referred to as Aging.
Note 5.22 The total deviation for the Transmitter Clock Frequency is specified by IEEE 802.3u as
±100 PPM.
Note 5.23 0oC for extended commercial version, -40oC for industrial version.
Note 5.24 This number includes the pad, the bond wire and the lead frame. PCB capacitance is not
included in this value. The XTAL1/CLKIN pin, XTAL2 pin and PCB capacitance values are
required to accurately calculate the value of the two external load capacitors. The total load
capacitance must be equivalent to what the crystal expects to see in the circuit so that the
crystal oscillator will operate at 25.000 MHz.
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Chapter 6 Package Outline
Figure 6.1 32-QFN Package
Table 6.1 32-QFN Dimensions
MIN
NOMINAL
MAX
REMARKS
A
A1
A2
D/E
D1/E1
D2/E2
L
b
k
e
0.70
0
-
4.90
4.55
3.20
0.30
0.18
0.35
0.85
0.02
0.65
5.00
4.75
3.30
0.40
0.25
0.45
1.00
0.05
0.90
5.10
4.95
3.40
0.50
0.30
-
Overall Package Height
Standoff
Mold Cap Thickness
X/Y Body Size
X/Y Mold Cap Size
X/Y Exposed Pad Size
Terminal Length
Terminal Width
Terminal to Exposed Pad Clearance
Terminal Pitch
0.50 BSC
Notes:
1. All dimensions are in millimeters unless otherwise noted.
2. Dimension “b” applies to plated terminals and is measured between 0.15 and 0.30 mm from the terminal tip.
3. The pin 1 identifier may vary, but is always located within the zone indicated.
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Figure 6.2 Recommended PCB Land Pattern
Figure 6.3 Taping Dimensions and Part Orientation
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Figure 6.4 Reel Dimensions
Figure 6.5 Tape Length and Part Quantity
Note: Standard reel size is 4,000 pieces per reel.
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Chapter 7 Datasheet Revision History
Table 7.1 Customer Revision History
SECTION/FIGURE/ENTRY
REVISION LEVEL & DATE
CORRECTION
Rev. 1.4
(08-23-12)
Section 4.2.2, "Basic Status
Register," on page 53
Updated definitions of bits 10:8.
Updated bit 11 definition.
Section 4.2.11, "Special
Control/Status Indications
Register," on page 62
Section 4.2.14, "PHY
Special Control/Status
Register," on page 65
Updated bit 6 definition.
Rev. 1.3
(03-12-12)
Company disclaimer on
page 2
Removed company address and phone numbers.
Ordering information modified.
Cover
Cover
Rev. 1.3
(04-20-11)
Added copper bond wire ordering codes to
LAN8710 ordering codes
Table 2.7, “Power Pins,” on
page 16
Updated VDDCR pin note to include requirement
of 1uF and 470pF decoupling capacitors in parallel
to ground on the VDDCR pin.
Figure 3.13 Power Supply
Diagram (1.2V Supplied by
Internal Regulator) on
Updated diagrams to include 1uF and 470pF
decoupling capacitors on the VDDCR pin.
page 46 and Figure 3.13
Power Supply Diagram
(1.2V Supplied by Internal
Regulator) on page 46
Table 4.2.9, “Special Modes
Register,” on page 60
Updated MIIMODE bit description and added note:
“When writing to this register the default value of
this bit must always be written back.”
Section 3.7.3, "RMIISEL:
MII/RMII Mode
Configuration," on page 37
Updated second paragraph to:
“When the nRST pin is deasserted, the MIIMODE
bit of the Special Modes Register is loaded
according to the RMIISEL configuration strap. The
mode is reflected in the MIIMODE bit of the Special
Modes Register.”
Section 3.8.9.2, "Far
Loopback," on page 43
Updated section to defeature information about
register control of the MII/RMII mode.
Rev. 1.2 (11-10-10)
Section 5.5.5, "RMII
Interface Timing," on
page 75
Updated diagrams and tables to include RXER.
Figure 6.1 32-QFN Package
on page 78 & Figure 6.2
Recommended PCB Land
Pattern on page 79
Updated package drawings.
Section 5.5.5, "RMII
Interface Timing," on
page 75
Corrected signal names on RMII timing diagrams
and tables.
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Table 7.1 Customer Revision History (continued)
SECTION/FIGURE/ENTRY CORRECTION
REVISION LEVEL & DATE
Section 5.5.4, "MII Interface
Timing," on page 73
Corrected signal names on MII timing diagrams
and tables. Updated Table 5.8 tval max to 28.0 ns.
Updated Table 5.9 tsu and thold values to 12.0 ns
and 0 ns, respectively.
Table 5.7, “Power-On nRST
& Configuration Strap
Timing Values,” on page 72
Updated todad description: “Output drive after
nRST deassertion”
Rev. 1.1 (04-09-10)
Section 5.1, "Absolute
Maximum Ratings*"
Modified “HBM ESD Performance by adding “per
JEDEC JESD22-A114” and changed “+/-5kV” to
“Class 3A”
Section 5.3, "Power
Consumption," on page 67
Corrected typo in the current consumption table
row title: “100BASE-TX /W TRAFFIC”
Section 5.3, "Power
Consumption," on page 67
Corrected typo in note regarding Ethernet
component current:
“The Ethernet component current is typically 41mA
in 100BASE-TX mode and 100mA in 10BASE-T
mode, independent of the 2.5V or 3.3V supply rail
of the transformer.”
Table 5.2, “Non-Variable I/O
Buffer Characteristics,” on
page 68
Corrected O12 VOH minimum value to “VDD2A -
0.4”
Corrected ICLK VILI maximum value to “0.35”
Corrected ICLK VIHI maximum value to “VDD2A +
0.4”
Section 5.2, "Operating
Conditions**," on page 67
Added note: “Do not drive input signals without
power supplied to the device.”
Section 5.1, "Absolute
Maximum Ratings*," on
page 66
Corrected IEC61000-4-2 Contact Discharge ESD
Performance to +/-8kV.
Section 4.2.4, "PHY
Identifier 2 Register," on
page 55
Corrected Model Number default value to
“001111b”.
Section 3.8.9.2, "Far
Loopback," on page 43
Added far loopback description.
Section 4.2.8, "Mode
Control/Status Register," on
page 59
Added FARLOOPBACK (bit 9) description.
Table 5.9, “MII Transmit
Timing Values,” on page 74
Corrected tsu and thold minimum values to 10 ns.
Rev. 1.0 (12-09-09)
Rev. 1.0 (04-15-09)
Document reworked for clarity and consistency with other SMSC documentation.
Initial Release
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