SL74HC299 [SLS]

8-Bit Bidirectional Universal Shift Register with Parallel I/O; 与并行I的8位双向通用移位寄存器/ O


型号：	SL74HC299
厂家：	SYSTEM LOGIC SEMICONDUCTOR
描述：	8-Bit Bidirectional Universal Shift Register with Parallel I/O 与并行I的8位双向通用移位寄存器/ O 移位寄存器
文件：	总8页 (文件大小：86K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SL74HC299

8-Bit Bidirectional Universal

Shift Register with Parallel I/O

High-Performance Silicon-Gate CMOS

The SL74HC299 is identical in pinout to the LS/ALS299. The device

inputs are compatible with standard CMOS outputs; with pullup

resistors, they are compatible with LS/ALSTTL outputs.

The SL74HC299 features a multiplexed parallel input/output data

port to achieve full 8-bit handling in a 20 pin package. Due to the large

output drive capability and the 3-state feature, this device is ideally

suited for interface with bus lines in a bus-oriented system.

ORDERING INFORMATION

SL74HC299N Plastic

SL74HC299D SOIC

T_A= -55° to 125° C for all packages

Two Mode-Select inputs and two Output Enable inputs are used to

choose the mode of operation as listed in the Function Table.

Synchronous parallel loading is accomplished by taking both Mode-

Select lines, S and S , high. This places the outputs in the high-

impedance state, which permits data applied to the data port to be

clocked into the register. Reading out of the register can be

accomplished when the outputs are enabled. The active-low

asynchronous Reset overrides all other inputs.

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 2.0 to 6.0 V

Low Input Current: 1.0 mA

PIN ASSIGNMENT

High Noise Immunity Characteristic of CMOS Devices

LOGIC DIAGRAM

PIN 20=V_CC

PIN 10 = GND

System Logic

SLS

Semiconductor

SL74HC299

MAXIMUM RATINGS^*

Symbol

Parameter

Value

-0.5 to +7.0

-1.5 to V_CC+1.5

-0.5 to V_CC+0.5

±20

Unit

V_CC

DC Supply Voltage (Referenced to GND)

DC Input Voltage (Referenced to GND)

DC Output Voltage (Referenced to GND)

DC Input Current, per Pin

V_OUT

I_IN

I_OUT

I_CC

DC Output Current, per Pin

±35

DC Supply Current, V_CCand GND Pins

±75

P_D

Power Dissipation in Still Air, Plastic DIP+

SOIC Package+

750

500

Tstg

T_L

Storage Temperature

-65 to +150

260

°C

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

^*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol

V_CC

Parameter

Min

2.0

Max

6.0

Unit

DC Supply Voltage (Referenced to GND)

DC Input Voltage, Output Voltage (Referenced to GND)

Operating Temperature, All Package Types

V , V_OUT

V_CC

T_A

-55

+125

°C

t_r, t_f

Input Rise and Fall Time (Figure 1)

V_CC=2.0 V

V_CC=4.5 V

V_CC=6.0 V

1000

500

400

This device contains protection circuitry to guard against damage due to high static voltages or electric

fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated

voltages to this high-impedance circuit. For proper operation, V and V_OUTshould be constrained to the range

GND£(V or V_OUT)£V_CC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ).

Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus.

System Logic

SLS

Semiconductor

SL74HC299

DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)

V_CC

Guaranteed Limit

Symbol

Parameter

Test Conditions

25 °C

£85

°C

£125

°C

Unit

-55°C

MinimumHigh-Level

Input Voltage

V_OUT=0.1 V or V_CC-0.1 V

êI_OUTê£ 20 mA

2.0

4.5

6.0

1.5

3.15

4.2

1.5

3.15

4.2

1.5

3.15

4.2

Maximum Low -Level

Input Voltage

V_OUT=0.1 V or V_CC-0.1 V

êI_OUTê £ 20 mA

2.0

4.5

6.0

0.3

0.9

1.2

0.3

0.9

1.2

0.3

0.9

1.2

V_OH

MinimumHigh-Level

Output Voltage

V =V or V

êI_OUTê £ 20 mA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

V =V or V

êI_OUTê £ 6.0 mA (P/Q)

êI_OUTê £ 7.8 mA (P/Q)

4.5

6.0

3.98

5.48

3.84

5.34

3.7

5.2

V =V or V

êI_OUTê £ 4.0 mA (Q’)

êI_OUTê £ 5.2 mA (Q’)

4.5

6.0

3.98

5.48

3.84

5.34

3.7

5.2

V_OL

Maximum Low-Level

Output Voltage

V = V or V

êI_OUTê £ 20 mA

2.0

4.5

6.0

0.1

V =V or V

êI_OUTê £ 6.0 mA (P/Q)

êI_OUTê £ 7.8 mA (P/Q)

4.5

6.0

0.26

0.33

0.4

V =V or V

êI_OUTê £ 4.0 mA (Q’)

êI_OUTê £ 5.2 mA (Q’)

4.5

6.0

0.26

0.33

0.4

I_IN

Maximum Input

Leakage Current

V =V_CCor GND

6.0

±0.1

±1.0

I_OZ

Maximum Three-State Output in High-Impedance

6.0

±0.5

±5.0

±10

Leakage Current

(Q_Athru Q_H)

State

V = V or V

IN IH

V_OUT=V_CCor GND

I_CC

Maximum Quiescent

Supply Current

(per Package)

V =V_CCor GND

I_OUT=0mA

6.0

8.0

160

System Logic

Semiconductor

SLS

SL74HC299

AC ELECTRICAL CHARACTERISTICS(C_L=50pF,Input t_r=t_f=6.0 ns)

V_CC

Guaranteed Limit

Symbol

f_max

Parameter

25 °C to £85°C

-55°C

£125°C

Unit

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 5)

2.0

4.5

6.0

5.0

4.0

3.4

MHz

t_PLH, t_PHLMaximum Propagation Delay, Clock to Q_A’ or Q_H’

(Figures 1 and 5)

2.0

4.5

6.0

170

215

255

t_PLH, t_PHLMaximum Propagation Delay, Clock to Q_Athru Q_H

(Figures 1 and 5)

2.0

4.5

6.0

160

200

240

t_PHL

Maximum Propagation Delay, Reset to Q_A’ or Q_H’

(Figures 2 and 5)

2.0

4.5

6.0

175

220

265

t_PHL

Maximum Propagation Delay, Reset to Q_Athru Q_H

(Figures 2 and 5)

2.0

4.5

6.0

190

240

285

t_PLZ, t_PHZMaximum Propagation Delay , OE1, OE2, S1, or S2

to Q_Athru Q_H(Figures 3 and 6)

2.0

4.5

6.0

150

190

225

t_PZL, t_PZHMaximum Propagation Delay , OE1, OE2, S1, or S2

to Q_Athru Q_H(Figures 3 and 6)

2.0

4.5

6.0

150

190

225

t_TLH, t_THLMaximum Output Transition Time, Q_Athru Q_H

(Figures 1 and 5)

2.0

4.5

6.0

t_TLH, t_THLMaximum Output Transition Time, Q_A’ thru Q_H’

(Figures 1 and 5)

2.0

4.5

6.0

110

C_IN

Maximum Input Capacitance)

C_OUT

Maximum Three-State I/O Capacitance

(I/O in High-Impedance State), Q_Athru Q_H

Power Dissipation Capacitance (Per Package),

Output Enable

Typical @25°C,V_CC=5.0 V

C_PD

Used to determine the no-load dynamic power

consumption:

240

P_D=C_PDV_CC²f+I_CCV_CC

System Logic

Semiconductor

SLS

SL74HC299

TIMING REQUIREMENTS(C_L=50pF,Input t_r=t_f=6.0 ns)

V_CC

Guaranteed Limit

Symbol

t_su

Parameter

25 °C to-55°C

£85°C

£125°C

Unit

Minimum Setup Time, Mode Select S1

or S2 to Clock (Figure 4)

2.0

4.5

6.0

100

125

150

t_su

Minimum Setup Time, Data Inputs S_A,

S_H, P_Athru P_Hto Clock

(Figure 4)

2.0

4.5

6.0

100

125

150

t_h

Minimum Hold Time, Clock to Mode

Select S1 or S2 (Figure 4)

2.0

4.5

6.0

120

150

180

t_h

Minimum Hold Time, Clock to Data

Inputs, S_A, S_H, P_Athru P_H(Figure 4)

2.0

4.5

6.0

t_rec

Minimum Recovery Time, Reset

Inactive to Clock (Figure 2)

2.0

4.5

6.0

t_w

Minimum Pulse Width, Clock (Figure

2.0

4.5

6.0

100

120

t_w

Minimum Pulse Width, Reset (Figure

2.0

4.5

6.0

100

120

t_r, t_f

Maximum Input Rise and Fall Times

(Figure 1)

2.0

4.5

6.0

1000

500

400

1000

500

400

1000

500

400

System Logic

Semiconductor

SLS

SL74HC299

FUNCTION TABLE

Inputs

Output

Enables

Response

Mode Reset Mode

Select

Clock

Serial P_A/ P_B/ P_C/ P_D/ P_E/ P_F/ P_G/ P_H/ Q_A’ Q_H’

Inputs Q_AQ_BQ_CQ_DQ_EQ_FQ_GQ_H

S₂S₁OE1 OE2

D_AD_H

Reset

Q_Athrough Q_H=Z

Shift

Right

Shift Right: Q_Athrough Q_H=Z;

D_AF_A; F_AF_B; etc

Q_G

Shift Right: Q_Athrough Q_H=Z;

D_AF_A; F_AF_B; etc

Q_G

Shift Right: D_AF_A=Q_A;

F_A

Shift Left: Q_Athrough Q_H=Z;

D_HF_H; F_HF_G; etc

F_B=Q_B; etc

Shift

Left

Q_B

P_A

Shift Left: Q_Athrough Q_H=Z;

D_HF_H; F_HF_G; etc

Shift Left: D_H

F_H=Q_H;

F_H

F_G=Q_G; etc

Parallel

Load

Parallel Load:P_N

F_N

P_H

Hold

Hold: Q_Athrough Q_H=Z; F_N=F_N

Hold: Q_N=Q_H

P_A

P_H

Z = high impedance

D = data on serial input

F = flip-flop (see Logic Diagram)

When one or both output controls are high the eight input/output terminals are disabled to the high-

impedance state; however, sequential operation or clearing of the register is not affected.

System Logic

SLS

Semiconductor

SL74HC299

Figure 1. Switching Waveforms

Figure 2. Switching Waveforms

Figure 3a. Switching Waveforms

Figure 3b. Switching Waveforms

Figure 4. Switching Waveforms

Figure 5. Test Circuit

Figure 6. Test Circuit

System Logic

Semiconductor

SLS

SL74HC299

EXPANDED LOGIC DIAGRAM

System Logic

Semiconductor

SLS

SL74HC299 [SLS]

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