AP107-81 [SKYWORKS]
Narrow Band Medium Power Amplifier, 1850MHz Min, 1910MHz Max, SOIC-16;
| 型号： | AP107-81 |
| 厂家： | 
SKYWORKS SOLUTIONS INC. |
| 描述： | Narrow Band Medium Power Amplifier, 1850MHz Min, 1910MHz Max, SOIC-16 射频 微波 |
| 文件： | 总4页 (文件大小：45K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GaAs IC 1.9 GHz Power Amplifier
AP107-81
Features
SOIC-16 Slug
■ PCS TDMA IS136
0.050 (1.27 mm) BSC
0.158 (4.00 mm)
0.150 (3.80 mm)
16
9
■ PCS CDMA IS95
■ Linear Power up to 31 dBm (PEP)
■ 6 V Operation
0.244 (6.20 mm)
0.228 (5.80 mm)
PIN
INDICATOR
1
8
■ Efficiency Greater Than 30%
HEAT SLUG 0.066 X 0.140 REF
LOCATED ON CENTER-LINE
■ High Power 16 Lead SOIC Package
OF THE PACKAGE
with Slug
1
8
0.65 (1.65 mm) MAX.
0.394 (10.00 mm)
0.386 (9.80 mm)
0.004
(0.010 mm)
MAX.
Description
The AP107-81 is a low cost IC power amplifier designed
for the 1.85–1.91 GHz frequency band. It features 5
cell battery operation and operates with excellent
linearity and high efficiency. The amplifier is designed
to be stable over a temperature range of -30 to 100°C and
over 3:1 VSWR loads.
16
9
Electrical Specifications at 25°C1,2
Characteristic
Condition
Frequency
1.85–1.91 GHz
Min.
Typ.
Max.
Unit
dBm
%
Output Power (PEP)
P
P
P
P
P
≤ 2 dBm (Avg.)
31
30
27
25
IN
Efficiency
(PEP) = 31 dBm
35
30
OUT
Gain (Small Signal)
Gain (Large Signal)
Noise in the Receive Band
= -20 dBm
33
31
dB
IN
(PEP) = 31 dBm
28
dB
OUT
(PEP) = 31 dBm
-100
-95
dBm
OUT
R
R
Band = 1930–1990 MHz
Bandwidth = 30 kHz
X
X
Negative Bias Current
Input VSWR
P
P
P
P
P
(PEP) = 31 dBm
6
8
mA
OUT
= -30 to +2 (Avg.)
2:1
IN
IM3@ Rated P
IM5@ Rated P
= 31 dBm (PEP)
= 31 dBm (PEP)
= 31 dBm (PEP)
-26
-35
dBc
dBc
OUT
OUT
OUT
OUT
OUT
Harmonic Power
2fo
3fo
-30
-45
dBc
dBc
Modulation
Channel Spacing = 30 kHz, 832 Channels, Pi/4 QPSK
P
ADJ
30 kHz
60 kHz
90 kHz
-30
-50
-55
dBc
dBc
dBc
Input Impedance
50
Ω
Ω
Load Impedance
9-j5.4
(Measured at Pins 12 & 13)
Skyworks Solutions, Inc. [978] 241-7000 • Fax [978] 241-7906 • Email sales@skyworksinc.com • www.skyworksinc.com
1
Specifications subject to change without notice. 3/99A
GaAs IC 1.9 GHz Power Amplifier
AP107-81
Typical Performance Data (1.85–1.91 GHz)
30
29
28
27
26
25
24
23
22
21
45
40
35
30
25
20
15
10
5
15
20
25
30
35
40
45
50
55
60
65
Gain
3
IM3
PAE
IM5
IM7
0
1516 17 18 19 20 21 22 23 24 25 26 27 28 29 30
POUT (dBm)
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
POUT (dBm)
Figure 1. Gain, P.A.E. vs. Output Power
Figure 2. Intermodulation
Distortion vs. Output Power
34
32
30
28
26
24
22
20
18
16
14
12
10
8
34
32
30
6.5 V
5.8 V
28
26
24
22
20
18
16
14
12
10
8
5.0 V
-30˚C
Room
+85˚C
6
-20-18 -16-14-12-10 -8 -6 -4 -2
0 2 4 6 8
-20-18-16-14-12-10 -8 -6 -4 -2
0
2
4
6
8
PIN (dBm)
PIN (dBm)
Figure 4. POUT vs. PIN Over Temperature
Figure 3. POUT vs. PIN Over Drain Voltage
30.0
29.5
29.0
28.5
250
200
28.0
27.5
27.0
26.5
26.0
25.5
25.0
24.5
24.0
1.85 GHz
Idq
150
1.91 GHz
100
50
1.88 GHz
0
3.9 3.95 4.0 4.05 4.1 4.15 4.2 4.25 4.3
8 10 12 14 16 18 20 22 24 26 27 28 30
POUT (dBm)
VREF (V)
Figure 6. Quiescent Current vs.
Reference Voltage
Figure 5. Gain vs. POUT Over Frequency
1. Performance in Figures 1, 2, 3, 4 and 5 is with VREF set to 4.1 V through resistive voltage divider as shown in schematic.
2. Performance shown in Figures 1 and 2 is with a two-tone input signal at 1.88 GHz and 1.88001 GHz.
3. Performance in Figures 3, 4 and 7 is with a 1.88 GHz CW input signal.
4. For Figures 6 and 7, VREF was varied using a DC supply connected directly to the VREF pin.
2
Skyworks Solutions, Inc. [978] 241-7000 • Fax [978] 241-7906 • Email sales@skyworksinc.com • www.skyworksinc.com
Specifications subject to change without notice. 3/99A
GaAs IC 1.9 GHz Power Amplifier
AP107-81
30.0
29.0
Output Matching Circuit
The output match for the AP107 is provided externally in
order to improve performance, reduce cost and add
flexibility. By making use of either ceramic surface mount
components or a distributed microstrip network, a much
lower loss match is achievable than could be obtained
using integrated elements on GaAs.This lower loss results
in better linearity and efficiency at rated output power for
the amplifier. Also, by keeping these elements external to
the GaAs IC, die size is smaller and the overall cost is thus
reduced.This off-chip approach also permits the flexibility
to tweak the amplifier for optimum performance at different
powers, and/or frequencies.
4.3 V
4.1 V
28.0
27.0
26.0
25.0
24.0
3.9 V
20 22
26 28 30 32
24
8 10 12 14 16 18
POUT (dBm)
The board schematic demonstrates a distributed load
matching network on FR4 substrate, which presents the
optimum load match while also providing a path for
DC bias to the output stage.
Figure 7. Gain vs. P
vs.
OUT
Reference Voltage
Power Amplifier Typical Configuration
C28
1000 pF
C12
1000 pF
C11
100 pF 8.2 pF
C10
10 µF
C21
C27
100 pF
Power Supply
C26
Voltage
V
L3
12 nH
+
DD
8.2 pF
5.8 V
C3
1000 pF
C2
C1
AP107-81
100 pF 8.2 pF
FR4 Substrate Parameters
Er = 4.5 H = 14 T = 0.7 Rho = 1.2
V
1
DD2
15
V
V
V
G2
14
REF
DD1
L1
1.8 nH
mline
mline
mline
C22
RF Out
RF Out
RF Out
11
C6
1000 pF
C5
C4
GND
W = 26 L = 70 15 pF 50 Ω RF output
mstub
W = 50 L = 50
100 pF 8.2 pF
W = 50 L = 230
RF In
RF In
L2
V
V
G3
G1
3.3 nH
V
V
SS
DBC
50 Ω RF input
C29
1.2 pF
C9
1000 pF
C8
C7
C16
100 pF
100 pF 8.2 pF
C18
C17
8.2 pF
C19
100 pF
C13
8.2 pF
C14
100 pF
C15
1000 pF
C30
10 µF
100 pF
C 20
3.3k
R1
R2
1000 pF
+
-4 V
V
SS
8.2k
Negative Supply Voltage
-
Bias Controller Circuit
Standby Mode
An on-chip bias controller eliminates the need to
individually adjust the gate bias voltages.This circuit uses
+5.8 V and an externally supplied negative voltage
(-4 V) to set the gate voltages on each stage for the proper
The power amplifier should be turned off whenever
possible to reduce overall power consumption.The AP107
can be turned off in a number of ways. The simplest
method is to switch the bias controller voltage (Pin 8) open,
which has the effect of setting the gate voltages to
bias current. The voltage on Pin 3 (V
), which can be
REG
adjusted using the off-chip resistors R1 and R2, can be
used to vary the quiescent current thus providing some
gain control and also allowing higher efficiency operation
at lower output power levels. However, to obtain the
specified linearity at rated power, the amplifier should be
biased with 150-200 mA of quiescent current.
approximately V (-4 V).The bias current of the amplifier
SS
in this condition will drop to less than 1 mA. By adding
PMOS switches to the drain lines, bias-off currents of the
order of <10 µA can be obtained.
Skyworks Solutions, Inc. [978] 241-7000 • Fax [978] 241-7906 • Email sales@skyworksinc.com • www.skyworksinc.com
3
Specifications subject to change without notice. 3/99A
GaAs IC 1.9 GHz Power Amplifier
AP107-81
Pin Out Assignments
Pin Out
Pin 2:V
RF RF
G2
VDD2 N/C N/C Out Out N/C VG3 VSS
Second stage gate voltage tap. Should be RF bypassed.
16
15
14
13
12
11
10
9
Pin 3:V
REF
Sets quiescent current of amplifier. Nominal value of
~4.1 V can be set, by voltage dividing from V (5.8 V)
DBC
using resistors R1 and R2 as shown in the schematic.
Pin 4:V
DD1
Drain of stage 1. Requires matching inductor, good
RF bypassing and the +5.8 V nominal supply voltage.
1
2
3
4
5
6
7
8
N/C VG2 VREF VDD1 GND RF In VG1 VDBC
Pin 5: GND
DC and RF ground.
Pin Configuration
Pin 6: RF In
50 Ω RF input. Series inductor on input line improves input
match.
Terminal
Symbol
Function
Not Connected
1
2
3
4
5
6
7
8
N/C
Pin 7:V
G1
V
V
V
Gate Voltage 2
Reference Voltage
Drain Voltage 1
Ground
G2
First stage gate voltage tap. Requires good RF bypassing.
REF
DD1
Pin 8:V
DBC
Bias controller supply voltage. Connect to +5.8 V
nominal supply voltage.
GND
RF In
RF Input
Pin 9:V
SS
V
V
Gate Voltage 1
Positive Bias
G1
Negative voltage for bias controller circuit. Nominally -4 V.
DBC
Pin 10:V
G3
Controller Supply Voltage
Third stage gate voltage tap. Requires good
RF bypassing.
9
V
V
Negative Bias
Controller Supply Voltage
SS
Pin 12, 13: RF Out/V
10
11
12
13
14
15
16
Gate Voltage 3
DD3
G3
RF output and bias feed for third stage drain. Output
matching is required to transform the optimum load
impedance to 50 Ω. The circuit must also provide a path
for the +5.8 V nominal DC bias and have good
RF bypassing.
N/C
Not Connected
RF Out/V
RF Out/V
N/C
RF Output/Drain Voltage 3
RF Output/Drain Voltage 3
Not Connected
DD3
DD3
N/C
Not Connected
Pin 16:V
DD2
V
Drain Voltage 2
DD2
Second stage drain voltage. Requires matching inductor,
good RF bypassing and connection to the +5.8 V nominal
supply voltage.
Absolute Maximum Ratings
Characteristic
Value
10 V
Drain Voltage (V
)
DD
Bias Voltage (V
)
-6 V
SS
Reference Voltage (V
)
6 V
REF
Power Input (P
)
12 dBm
-30 to +100°C
-35 to +120°C
IN
Operating Temperature (T
)
OPT
Storage Temperature (T
)
STG
4
Skyworks Solutions, Inc. [978] 241-7000 • Fax [978] 241-7906 • Email sales@skyworksinc.com • www.skyworksinc.com
Specifications subject to change without notice. 3/99A
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