SP8605 [SIPEX]
12-Bit Sampling A/D Converters; 12位采样A / D转换器
| 型号： | SP8605 |
| 厂家： | 
SIPEX CORPORATION |
| 描述： | 12-Bit Sampling A/D Converters |
| 文件： | 总11页 (文件大小：209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SP8603, SP8605, SP8610
12-Bit Sampling A/D Converters
■ 3µs, 5µs or 10µs Sample/Conversion
Time
■ Unipolar 0V to +10V and 0V to +5V
Input
■ No Missing Codes Over Temperature
■ AC Performance Over Temperature
72dB Signal–to–Noise Ratio at Nyquist
85dB Spurious–free Dynamic Range at
49kHz
–81dB Total Harmonic Distortion at 49kHz
■ Internal Sample/Hold, Reference,
Clock, and 3-State Outputs
■ Power Dissipation: 90mW
■ 28–Pin Narrow PDIP and SOIC
Packages
DESCRIPTION…
TheSP86XXSeriesarecomplete,unipolar,12-bitsampling A/Dconvertersusingstate-of-the-art
CMOS structures. They contain a complete 12-bit successive approximation A/D converter with
internalsample/hold,reference,clock,digitalinterfaceformicroprocessorcontrol,andthree-state
output drivers. Power dissipation is only 90mW. AC and DC performance are completely
specified. Sampling/conversion rates of 3µs, 5µs and 10µs are offered.
CS R/C HBE
Clock
Control
Logic
BUSY
SAR
Output
Latches
And
Three
State
0V to10V
CDAC
.....
Three
State
Parallel
Output
Data
IN
.....
0V to 5V
IN
Drivers
Comparator
Internal
Ref
.....
.....
Bus
VREF Output
(1.2043V)
79
Lead Temperature (soldering, 10s) ..................................... +300°C
Thermal Resistance. ØJA
Plastic DIP ....................................................................... 50°C/W
SOIC .............................................................................. 100°C/W
ABSOLUTE MAXIMUM RATINGS
:
These are stress ratings only and functional operation of the device
at these or any other above those indicated in the operation
sections of the specifications below is not implied. Exposure to
absolute maximum rating conditions for extended periods of time
may affect reliability.
VS to Digital Common ............................................................... +7V
Pin 26 (VSO) to Pin 27 (VSA) .................................................... ±0.3V
Analog Common to Digital Common ...................................... ±0.3V
Control Inputs to Digital Common ....................... –0.3 to VS + 0.3 V
Analog Input Voltage ................................................... –3.0/+16.5V
Maximum Junction Temperature ........................................... 160°C
Internal Power Dissipation .................................................. 750mW
SPECIFICATIONS
(TA = 25°C; Sampling Frequency, FS, = 333kHz for SP8603, 200kHz for SP8605, 100kHz for SP8610, VS = +5V, unless otherwise specified.)
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
ANALOG INPUT
Voltage Ranges
Impedance
0V to +5V, 0V to +10V
V
Unipolar
0 to +10V Range
0 to +5V Range
5.4
3.9
7.7
5.6
10.0
7.3
kΩ
kΩ
T
T
MIN ≤ TA ≤ TMAX
MIN ≤ TA ≤ TMAX
DC PERFORMANCE
Full Scale Error
Externally adjustable to zero;
TMIN ≤ TA ≤ TMAX
Note 1
–K
±0.1
±0.50
±0.75
±0.95
%FSR
LSB
Integral Linearity Error
–K
±0.35
Differential Linearity Error
–K
±0.35
LSB
No Missing Codes
Unipolar Zero
–K
Guaranteed
Externally adjustable to zero
±1
±5
LSB
T
MIN ≤ TA ≤ TMAX
INTERNAL REFERENCE
Voltage Output
Output Source Current
Output Resistance
1.1440 1.2043 1.2645
V
µA
Ω
100
280
AC PERFORMANCE
T
MIN ≤ TA ≤ TMAX
SP8603
Conversion Time
Complete Cycle
Throughput Rate
Spurious-Free Dynamic Range
@ 49kHz
@ 161kHz
Total Harmonic Distortion
@ 49kHz
@ 161kHz
Signal to Noise Ratio (SNR)
@ 49kHz
@ 161kHz
Signal to (Noise + Distortion) Ratio
@ 49kHz
2.6
µs
µs
kHz
3.0
333
Note 2
Note 2
Note 2
Note 2
85
72
dB
dB
–81
–71
dB
dB
72
72
dB
dB
71
68
dB
dB
@ 161kHz
SP8605
Conversion Time
Complete Cycle
Throughput Rate
Spurious-Free Dynamic Range
@ 49kHz
@ 97kHz
Total Harmonic Distortion
@ 49kHz
4.5
µs
µs
kHz
5.0
200
Note 2
Note 2
85
77
dB
dB
–81
–76
dB
dB
@ 97kHz
80
SPECIFICATIONS
(TA = 25°C; Sampling Frequency, FS, = 333kHz for SP8603, 200kHz for SP8605, 100kHz for SP8610, VS = +5V, unless otherwise specified.)
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
AC PERFORMANCE
T
MIN ≤ TA ≤ TMAX
SP8605
Signal to Noise Ratio (SNR)
@ 49kHz
@ 97kHz
Signal to (Noise + Distortion) Ratio
@ 49kHz
Note 2
Note 2
72
72
dB
dB
71
70
dB
dB
@ 97kHz
SP8610
Conversion Time
Complete Cycle
9.5
µs
µs
10.0
Throughput Rate
100
kHz
dB
dB
dB
dB
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal to Noise Ratio (SNR)
Signal to (Noise + Distortion) Ratio
85
–81
72
@ 49kHz; Note 2
@ 49kHz; Note 2
@ 49kHz; Note 2
@ 49kHz; Note 2
71
SAMPLING DYNAMICS
Aperture Delay
Aperture Jitter
Transient Response
–K
13
ns
150
ps, rms
Note 3
Note 4
150
150
ns
ns
Overvoltage Recovery
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
–0.3
+2.4
+0.8
+5.3
±50
±5
V
V
µA
µA
±0.1
IIH
DIGITAL OUTPUTS
Resolution
Data Format
Data Coding
VOL
12
Bits
Parallel; 12-bit or 8-bit/4-bit
Binary
0.0
+2.4
+0.4
VDD
±5
V
V
µA
ISINK = 1.6mA
ISOURCE = 1.6mA
VOH
ILEAKAGE (High-Z State)
±0.1
POWER SUPPLY REQUIREMENTS
Rated Voltage
Current
Power Consumption
+4.75
+5.0
18
90
+5.25
21
V
mA
mW
VS (VSA and VSD
)
IS
ENVIRONMENTAL AND MECHANICAL
Specification
–K
0
+70
°C
°C
Storage
Package
–KN
–65
+150
28–pin Narrow DIP
28–pin SOIC
–KS
NOTES
1.
LSB means Least Significant Bit. For SP86xx Series, 1LSB = 1.22mV for 5V range, 1 LSB =
2.44mV for 10V range.
2.
3.
4.
All specifications in dB are referred to a full-scale input, either 10V or 5V.
For full-scale step input, 12-bit accuracy attained in specified time.
Recovers to specified performance in specified time after 2 x FS input overvoltage.
81
HBE is HIGH.
PINOUT
Pin 13 — D4 — Data Bit 4 if HBE is LOW; LOW if
HBE is HIGH.
N.C.
1
2
28 N.C.
±10V IN
±5V IN
VREF
27 V
26 V
SA
SD
3
Pin 14 —N.C.—This pin is not internally connected.
Pin 15 —N.C.—This pin is not internally connected.
4
25 N.C.
24 BUSY
23 CS
AGND
5
D
D
6
11
10
SP8603
SP8605
SP8610
7
22 R/C
21 HBE
Pin 16— DGND — Digital Ground. Connect to
pin 5 at the device.
D
8
9
8
7
6
5
4
D
9
20 D
19 D
18 D
17 D
0
1
2
3
Pin 17 — D3 — Data Bit 3 if HBE is LOW; Data Bit
11 if HBE is HIGH.
D
D
D
D
10
11
12
13
Pin 18 — D2 — Data Bit 2 if HBE is LOW; Data Bit
10 if HBE is HIGH.
16 DGND
15 N.C.
N.C. 14
Pin 19— D — Data Bit 1 if HBE is LOW; Data Bit
9 if HBE is1HIGH.
PIN ASSIGNMENT
Pin 1 —No Connection —This pin is not internally
connected.
Pin 20 — D0 — Data Bit 0 if HBE is LOW. Least
Significant Bit (LSB). Data Bit 8 if HBE is HIGH.
Pin 21 — HBE — High Byte Enable, When held
LOW, data output as 12-bits in parallel. When
held HIGH, four MSBs presented on pins 17–
20, pins 10 – 13 output LOWs. Must be LOW to
initiate conversion.
Pin 2 — IN — 0V to 10V Analog Input. Connected
to AGND f1or 10V range.
Pin 3 — IN2 — 0V to 5V Analog Input. Connected
to AGND for 5V range.
Pin22—R/C—Read/Convert.Fallingedgeinitiates
conversion when CS is LOW, HBE is LOW, and
BUSY is HIGH.
Pin 4 — VREF – Internal Voltage. Reference Output.
Pin 5 — AGND — Analog Ground. Connect to
pin 16 at the device.
Pin 23 — CS — Chip Select. Outputs in Hi-Z state
when HIGH. Must be LOW to initiate conversion or
read data.
Pin 6 — D11 — Data Bit 11. Most Significant Bit
(MSB).
Pin 24 — BUSY — Output LOW during
conversion. Data valid on rising edge in Con-
vert Mode.
Pin 7 — D10 — Data Bit 10.
Pin 8— D9 — Data Bit 9.
Pin 9 — D8 — Data Bit 8.
Pin25 — N.C. —Thispinisnotinternallyconnected.
Pin26—V —PositiveDigitalPowerSupply,+5V.
Connect toSpDin 27, and bypass to DGND.
Pin 10 — D7 — Data Bit 7 if HBE is LOW; LOW if
HBE is HIGH.
Pin 27 — VSA — Positive Analog Power Supply.
+5V. Connect to pin 26, and bypass to AGND.
Pin 11 — D6 — Data Bit 6 if HBE is LOW; LOW if
HBE is HIGH.
Pin28—N.C.—Thispinisnotinternallyconnected.
Pin 12 — D5 — Data Bit 5 if HBE is LOW; LOW if
82
after the conversion is completed and the data has
been transferred to the output drivers. Thus, the
rising edge can be used to read the data from the
conversion. Also, during conversion, the BUSY
signal puts the output data lines in Hi-Z states and
inhibits the input lines. This means that pulses on
R/Careignored,sothatnewconversionscannotbe
initiated during a conversion.
FEATURES...
The SP86XX Series are specified at sampling
rates of 333kHz (SP8603), 200kHz (SP8605) or
100kHz(SP8610). Conversiontimesarefactory
set for 2.70µs, 4.7µs and 9.7µs maximum, re-
spectively, over temperature, and the high-
speed sampling input stage insures a total acqui-
sition and conversion time of 3µs, 5µs and 10µs
maximum, respectively, over temperature. Pre-
cision, laser-trimmed scaling resistors provide
industry-standard input ranges of 0V to +5V or
0V to +10V.
The SP86XX Series will begin acquiring a new
sample just prior to the BUSY output rising, and
willtracktheinputsignaluntilthenextconversion
is started.
The 28-pin SP86XX Series are available in
narrow plastic DIP, and SOIC packages and it
operatesfromasingle+5Vsupply.TheSP86XX
Series are available in grades specified over the
0°C to +70°C commercial temperature ranges.
IntheReadMode,R/CiskeptnormallyLOW,and
a HIGH pulse is used to read data and initiate a
conversion. In this mode, the rising edge of R/C
will enable the output data pins, and the data from
the previous conversion becomes valid. The fall-
ing edge then puts the SP86XX Series in a hold
mode, and initiates a new conversion.
OPERATION
Basic Operation
Forusewithan8-bitbus,thedatacanbereadoutintwo
bytes under the control of HBE. With a LOW input
onHBE,attheendofaconversion,the8LSBsofdata
areloadedintotheoutputdriversonD throughD4 and
D3 through D0. Taking HBE HIGH 7then loads the 4
MSBs on D3 through D0, with D7 through D4 being
forced LOW.
Figure1showsthesimplehookupcircuitrequired
to operate the SP86XX Series in a 0V to +10V
range in the Convert Mode. A convert command
arriving on R/C puts the SP86XX Series in the
HOLD mode, and a conversion is started. This
pulse must be LOW for a minimum of 40ns.
Becausethispulseestablishesthesamplinginstant
oftheA/D,itmusthaveverylowjitter. BUSYwill
beheldLOWduringtheconversion,andrisesonly
Analog Input Ranges
The SP86XX Series offers two standard unipolar
input ranges: 0V to +10V and 0V to +5V. If a 10V
unipolar range is required, the analog input signal
should be connected to pin 2. A signal requiring a
5Vunipolar rangeshouldbeconnectedtopin3.In
either case, the other pin of the two must be
grounded or connected to the adjustment circuits
described in the section on calibration.
N.C.
IN 1
IN 2
N.C.
28
1
2
+5V
+5V 27
+5V 26
+
6.8µF
0.1µF
Input
3
4
5
6
7
8
9
V
N.C. 25
REF
AGND
BUSY 24
Busy
D11 (MSB) CS 23
D10
D9
R/C 22
HBE 21
Controlling The SP86XX Series
Convert
Command
The SP86XX Series can be easily interfaced to most
microprocessor-based and other digital systems. The
microprocessor may take full control of each conver-
sion, or the SP86XX Series may operate in a stand-
alone mode, controlled only by the R/C input. Full
control consists of initiating the conversion and read-
ingtheoutputdataatusercommand,transmittingdata
either all 12-bits in one parallel word, or in two 8-bit
bytes.Thethreecontrolinputs(CS,R/CandHBE)are
all TTL/CMOS compatible. The functions of the
D8
D0 (LSB) 20
D1 19
10 D7
11 D6
12 D5
13 D4
D2 18
D3 17
DGND 16
14
15
N.C.
N.C.
D0
(LSB)
D11
(MSB)
Data
Out
Figure 1. Basic 0V to 10V Operation
83
CS R/C HBE BUSY
OPERATION
in Table 2. No other combination of states or transi-
tionswillinitiateaconversion.Conversionisinhibited
if either CS or HBE are HIGH, or if BUSY is LOW.
CS and HBE should be stable a minimum of 25ns
priortothetransitiononR/C.Timingrelationshipsfor
start of conversion are illustrated in Figure 7.
1
X
X
1
None – outputs in Hi-Z state.
0
0
1
0
0
0
1
1
Holds signal and initiates conversion.
1
1
Output three-state buffers enabled once
conversion has finished.
0
0
1
1
1
1
Enable hi-byte in 8-bit bus mode.
1
0
Inhibit start of conversion.
The BUSY output indicates the current state of the
converter by being LOW only during conversion.
During this time the three-state output buffers remain
in a Hi-Z state, and therefore data cannot be read
during conversion. During this period, additional
transitions on the three digital inputs (CS, R/C and
HBE) will be ignored, so that conversion cannot be
prematurely terminated or restarted.
0
0
1
1
0
None – outputs in Hi-Z state.
X
X
X
Conversion in progress. Outputs Hi-Z
state. New conversion inhibited until
present conversion has finished.
Table 1. Control Line Functions
control lines are shown in Table 1.
Internal Clock
For stand-alone operation, control of the SP86XX
Series is accomplished by a single control line
connected to R/C. In this mode, CS and HBE are
connected to GND. The output data are presented
as 12-bit words. The stand-alone mode is used in
systemscontainingdedicatedinputportswhichdo
not require full bus interface capability.
The SP86XX Series has an internal clock that is
factory trimmed to achieve the typical conversion
times given in the specifications, and a maximum
conversion time over the full operating tempera-
ture range of 2.7µs, 4.7µs or 9.7µs, depending on
the model. No external adjustments are required,
and with the guaranteed maximum acquisition
time of 300ns, throughput performance is assured
withconvertpulsesascloseas3µsfortheSP8603.
ConversionisinitiatedbyaHIGH-to-LOWtransition
onR/C.Thethree-statedataoutputbuffersareenabled
when R/C is HIGH and BUSY is HIGH. Thus, there
are two possible modes of operation: conversion can
be initiated with either positive or negative pulses. In
either case, the R/C pulse must remain LOW a
minimum of 40ns.
Reading Data
Afterconversionisinitiated,theoutputbuffersremain
in a Hi-Z state until the following three logic condi-
tionsaresimultaneouslymet:R/CisHIGH, BUSYis
HIGH and CS is LOW. Upon satisfying these condi-
tions, the data lines are enabled according to the state
of HBE. See Figure 7 for timing relationships and
specifications.
Figure 5 illustrates timing when conversion is initi-
ated by an R/C pulse which goes LOW and returns
HIGH during the conversion. In this case (Convert
Mode),thethree-stateoutputsgointotheHi-Zstatein
responsetothefallingedgeofR/C,andareenabledfor
external access to the data after completion of the
conversion.
CALIBRATION...
Optional External Gain And Offset Trim
Offsetandfull-scaleerrorsmaybetrimmedtozero
using external offset and full-scale trim potenti-
ometersconnectedtotheSP86XXSeriesasshown
in Figure 3.
Figure 6 illustrates the timing when conversion is
initiated by a positive R/C pulse. In this mode (Read
Mode), the output data from the previous conversion
is enabled during the HIGH portion of R/C. A new
conversion starts on the falling edge of R/C, and the
three-stateoutputsreturntotheHi-Zstateuntilthenext
occurrence of a HIGH on R/C.
If adjustment of offset and full scale is not required,
+10V
Input
2
3
2
3
SP8603/05/10
SP8603/05/10
+5V
Input
Conversion Start
A conversion is initiated on the SP86XX Series only
by a negative transition occurring on R/C, as shown
Figure 2. a) 10V Range b) 5V Range — Without Trims
84
INPUT VOLTAGE RANGE AND LSB VALUES
Input Voltage Range Defined As:
Analog Input Connected to Pin
Pin Connected to AGND
0V to +10V
0V to +5V
2
3
3
2
One Least Significant Bit (LSB)
FSR/212
10V/212
2.44mV
5V/212
1.22mV
OUTPUT TRANSITION VALUES
FFEH TO FFFH
+ FULL SCALE
+10V–3/2LSB
+5V–3/2LSB
+4.9982V
2.4994V
+9.963V
4.9988V
1.22mV
7FFH TO 800H
000H to 001H
Mid Scale
0V
0.6mV
Table 2. Input Voltages, Transition Voltages and LSB Values
FFEH = 4094DEC
.
connections as shown in Figure 2 should be used.
+10V Range Offset and Gain
Calibration Procedure
Offset — Apply 0.0012V to the +10V input at
pin 2. Adjust the offset potentiometer until the
LSB toggles on and off at code 0000 0000
Apply a precision input voltage source to your
chosen input range (10V range at pin 2 or 5V at
pin 3). Set the A/D to convert continuously.
Monitor the output code. Trim the offset first,
then gain. Use the appropriate input voltages
and output target codes for your chosen input
range as follows. The recommended offset cali-
bration voltage values eliminate interaction be-
tween the offset and gain calibration
0000BIN = 000H = 0000DEC
.
Gain—Apply9.9963Vtothe+10Vinputatpin
2. Adjust the gain potentiometer until the LSB
toggles on and off at code 1111 1111 1110BIN
=
FFEH = 4094DEC
.
+5V Range Offset and Gain
Offset—Apply0.0006Vtothe+5Vinputatpin
3. Adjust the offset potentiometer until the LSB
Layout Considerations
Because of the high resolution and linearity of the
SP86XX Series, system design problems such as
groundpathresistanceandcontactresistancebecome
very important.
toggles on and off at code 0000 0000 0000BIN
=
000H = 0000DEC
.
Gain — Apply 4.9982V to the +5V input at pin
3. Adjust the gain potentiometer until the LSB
The input resistance of the SP86XX Series is 6.3kΩ
or 4.2KΩ (for the 10V and 5V ranges respectively).
toggles on and off at code 1111 1111 1110BIN
=
GAIN ADJUST
GAIN ADJUST
SP86XX
+10V
Input
SP86XX
2
3
4
5
6
7
2
3
4
5
6
7
R =500Ω
2
+5V
Input
R =500Ω
2
+5V
+5V
R =10KΩ
1
10KΩ
R =10KΩ
100Ω
1
6.65KΩ
30.1KΩ
301Ω
10KΩ
–15V
–15V
UNIPOLAR ZERO ADJUST
a)
b)
Figure 3. a) 10V Range b) 5V Range — With External Trims
85
To avoid introducing distortion, the source resistance
must be very low, or constant with signal level. The
outputimpedanceprovidedbymostopampsisideal.
Pins 26 Digital Supply Voltage (VSD) and 27 Analog
SupplyVoltage(VSA)arebroughtouttoseparatepins
to maximize accuracy on the chip. They should be
connectedtogetherascloseaspossibletotheunit.Pin
27maybeslightlymoresensitivethanpin26tosupply
variations, but to maintain maximum system accu-
racy, both should be well–isolated from digital sup-
plies with wide load variations.
TheGNDpins(5and16)arealsoseparatedinternally,
and should be directly connected to a ground plane
undertheconverter.Agroundplaneisusuallythebest
solution for preserving dynamic performance and
reducing noise coupling into sensitive converter cir-
cuits. Where any compromises must be made, the
common return of the analog input signal should be
referenced to pin 5, AGND, on the SP86XX Series,
which prevents any voltage drops that might occur in
the power supply common returns from appearing in
series with the input signal.
Tolimittheeffectsofdigitalswitchingelsewhereina
system on the analog performance of the system, it
often makes sense to run a separate +5V supply
conductor from the supply regulator to any analog
components requiring +5V, including the SP86XX
Series. If the SP86XX Series traces cannot be
separated back to the power supply terminals, and
therefore share the same trace as the logic supply
currents, then a 10 Ohm isolating resistor should be
used between the board supply and pin 24 (V ) and
its bypass capacitors to keep VDA glitch–free. DTAhe VS
pins (26 and 27) should be connected together and
bypassed with a parallel combination of a 6.8µF
Tantalum capacitor and a 0.1µF ceramic capacitor
located close to the converter to obtain noise-free
operation. (See Figure 1). Noise on the power supply
lines can degrade converter performance, especially
noise and spikes from a switching power supply.
Appropriate supplies or filters must be used.
Couplingbetweenanaloginputanddigitallinesshould
be minimized by careful layout. For instance, if the
lines must cross, they should do so at right angles.
Parallel analog and digital lines should be separated
from each other by a pattern connected to common.
If external full scale and offset potentiometers are
used, the potentiometers and related resistors should
belocatedasclosetotheSP86XXSeriesaspossible.
“Hot Socket” Precaution
Two separate +5V VS pins, 26 and 27, are used to
minimizenoisecausedbydigitaltransients.Ifonepin
is powered and the other is not, the SP86XX Series
maydrawexcessivecurrent.Innormaloperation,this
is not a problem because both pins will be soldered
together. However, during evaluation, incoming in-
spection, repair, etc., where the potential of a “Hot
Socket”exists,careshouldbetakentoapplypowerto
R/C
tB
BUSY
tDBC
tC
Converter
Mode
Acquisition
Conversion
Acquisition
Conversion
tAP
Hold Time
SYMBOL/PARAMETER
MIN.
TYP.
MAX.
150
2.7
UNITS
tDBC BUSY delay from R/C
80
2.5
4.5
9.5
13
ns
µs
tB
BUSY Low
SP8603
SP8605
SP8610
4.7
µs
9.7
µs
tAP
Aperture Delay
ns
∆tAP Aperture Jitter
tC Conversion Time
150
ps, rms
2.47
4.47
9.47
2.70
4.70
9.70
µs
µs
µs
SP8603
SP8605
SP8610
Figure 4. Acquisition and Conversion Timing
86
tW
R/C
tB
BUSY
tDBC
tDBE
tAP
Converter
Mode
Acquire
tA
Acquire
Convert
tC
Convert
tDB
Data Valid
tHDR and tHL
Data
BUS
Data Valid
Hi-Z State
Hi-Z State
Figure 5. Convert Mode Timing — R/C Pulse LOW, Outputs Enabled After Conversion
the SP86XX Series only after it has been socketed.
First, care should be taken to avoid glitches during
criticaltimesinthesamplingandconversionprocess.
SincetheSP86XXSerieshasaninternalsample/hold
function, thesignalthatputsitintotheholdstate(R/C
going LOW) is critical, as it would be on any sample/
hold amplifier. The R/C falling edge should have a 5
to 10ns transition time, low jitter, and have minimal
ringing, especially during the 20ns after it falls.
Minimizing “Glitches”
Coupling of external transients into an analog-to-
digitalconvertercancauseerrorswhicharedifficultto
debug. In addition to the discussions earlier on layout
considerationsforsupplies,bypassingandgrounding,
thereareseveralotherusefulstepsthatcanbetakento
getthebestanalogperformanceoutofasystemusing
theSP86XXSeries. Thesepotentialsystemproblem
sources are particularly important to consider when
developing a new system, and looking for the causes
of errors in breadboards.
Although not normally required, it is also good prac-
tice to avoid glitches from coupling to the SP86XX
Series while bit decisions are being made. Since the
above discussion calls for a fast, clean rise and fall on
R/C
tW
tB
BUSY
tDBC
tDBE
tAP
tAP
Converter
Mode
Acquire
Convert
tC
Convert
Acquire
tA
tDD
tHDR and tHL
Hi-Z State
Data
Valid
Data
Valid
Data
BUS
Hi-Z State
Hi-Z State
Figure 6. Read Mode Timing — R/C Pulse HIGH, Outputs Enabled Only When R/C is High
87
AC DYNAMIC TIMING DATA
SYMBOL/PARAMETER
MIN .
TYP.
MAX.
UNITS
tW
R/C Pulse Width
40
ns
ns
tDBC
tB
BUSY delay from R/C
BUSY LOW
80
2.47
13
150
2.7
µs
tAP
Aperture Delay
ns
∆tAP
tC
Aperture Jitter
150
2.5
100
75
ps, rms
µs
Conversion Time
2.70
tDBE
tDB
BUSY from End of Conversion
BUSY Delay after Data Valid
Acquisition Time
ns
25
200
300
ns
tA
130
ns
tA + tC
Throughput Time
SP8603
3.0
5.0
10.0
20
µs
µs
µs
ns
ns
ns
ns
SP8605
SP8610
tHDR
tS
Valid Data Held After R/C LOW
CS or HBE LOW before R/C Falls
CS or HBE LOW after R/C Falls
Data Valid from CS LOW, R/C HIGH, and HBE
in Desired State (Load = 100pF)
Delay to Hi-Z State after R/C Falls or
CS Rises (3KΩ Pullup or Pulldown
50
5
25
tH
25
0
tDD
65
150
150
tHL
50
ns
All parameters Guaranteed By Design.
R/C, it makes sense to keep the rising edge of the
convert pulse outside the time when bit decisions are
being made. In other words, the convert pulse should
eitherbeshort(under100nssothatittransitionsbefore
the MSB decision), or relatively long (i.e., for the
SP8603, over 2.75µs to transition after the LSB
decision).
layout of the circuit in front of the SP86XX Series.
Finally, in multiplexed systems, the timing relative to
when the multiplexer is switched may affect the
analog performance of the system. In most applica-
tions, the multiplexer can be switched as soon as R/C
goes LOW (with appropriate delays), but this may
affect the conversion if the switched signal shows
glitches or significant ringing at the SP86XX Series
input. Whenever possible, it is safer to wait until the
conversion is completed before switching and multi-
plexer. The extremely fast acquisition time and con-
version time of the SP86XX Series make this practi-
cal in many applications.
Next, although the data outputs are forced into a Hi-Z
stateduringconversion, fastbustransientscanstillbe
capacitively coupled into the SP86XX Series. If the
data bus experiences fast transients during conver-
sion, these transients can be attenuated by adding a
logicbuffertothedataoutputs.TheBUSYoutputcan
be used to enable the buffer.
Naturally, transients on the analog input signal are to
be avoided, especially at times within ±20ns of R/C
going LOW, when they may be trapped as part of the
charge on the capacitor array. This requires careful
88
CS or
HBE
tS
tH
tW
R/C
BUSY
tDBC
Data
BUS
Data Valid
Hi-Z State
tHDR and tHL
Figure 7. Conversion Start Timing
ORDERING INFORMATION
0°C to +70°C
Model
Throughput
Package
SP8603KN .................................................................... 333kHz ............................................................................................... 28–pin, 0.3" Plastic DIP
SP8603KS .................................................................... 333kHz ........................................................................................................ 28–pin, 0.3" SOIC
SP8605KN .................................................................... 200kHz ............................................................................................... 28–pin, 0.3" Plastic DIP
SP8605KS .................................................................... 200kHz ........................................................................................................ 28–pin, 0.3" SOIC
SP8610KN .................................................................... 100kHz ............................................................................................... 28–pin, 0.3" Plastic DIP
SP8610KS .................................................................... 100kHz ........................................................................................................ 28–pin, 0.3" SOIC
89
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