SP7653ERL/TR [SIPEX]
Wide Input Voltage Range, 1.3MHz, Buck Regulator; 宽输入电压范围， 1.3MHz ，降压型稳压器
| 型号： | SP7653ERL/TR |
| 厂家： | 
SIPEX CORPORATION |
| 描述： | Wide Input Voltage Range, 1.3MHz, Buck Regulator |
| 文件： | 总15页 (文件大小：797K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SP7653
Wide Input Voltage Range,
1.3MHz, Buck Regulator
TM
Power
Blox
SP7653
FEATURES
DFN PACKAGE
7mm x 4mm
■ 2.5Vto20VStepDownAchievedUsingDualInput
26
P
1
2
3
LX
GND
■ OutputVoltagedownto0.8V
BOTTOM VIEW
P
25
GND
LX
■ 3AOutputCapability
Heatsink Pad 1
P
24
LX
GND
Connect to Lx
■ BuiltinLowRDSON PowerSwitches(40m1 typical)
■ HighlyIntegratedDesign,MinimalComponents
■ 1.3MHzFixedFrequencyOperation
■ UVLODetectsBothV andV
23
GND
4
LX
5
V
22
FB
V
CC
6
COMP
21
GND
CC
IN
Heatsink Pad 2
Co
n
n
e
c
t
t
o
G
N
D
UV
7
IN
20
■ OverTemperatureProtection
GND
GND
8
19
■ ShortCircuitProtectionwithAuto-Restart
■ WideBWAmpAllowsTypeIIorIIICompensation
■ ProgrammableSoftStart
■ HighEfficiency:Greaterthan95% Possible
■ AsynchronousStart-UpintoaPre-ChargedOutput
■ Small7mmx4mmDFNPackage
■ U.S.Patent#6,922,041
GND
SS
9
18
BST
V
10
NC
17
IN
Heatsink Pad 3
Connect to VIN
V
■ FastTransientResponse
11
IN
LX
16
V
12
IN
LX 15
13
V
14
LX
IN
Now Available in Lead Free Packaging
DESCRIPTION
TheSP7653isasynchronousstep-downswitchingregulator optimizedforhighefficiency. Thepartisdesignedtobe
especiallyattractivefordualsupply,12Vto20Vdistributedpowersystemssteppeddownwith5Vusedtopowerthe
controller.ThislowerV voltageminimizespowerdissipationinthepartandisusedtodrivethetopswitch.TheSP7653
CC
isdesignedtoprovideafullyintegratedbuckregulatorsolutionusingafixed1.3MHzfrequency,PWMvoltagemode
architecture.ProtectionfeaturesincludeUnderVoltageLockOut(UVLO),thermalshutdownandoutputshortcircuit
protection.TheSP7653isavailableinthespacesavingDFNpackage.
TYPICAL APPLICATION CIRCUIT
L1 IHLP2525CZER2R2M01
U1
2.2uH, Irate=8A
SP7653
DCR=18m1
1
2
26
25
24
23
22
21
20
19
18
17
16
15
14
PGND
PGND
PGND
GND
VFB
LX
LX
VOUT
3.30V
0-3A
RZ2
CZ2
C3:X5R
CERAMIC
C3
RZ3
1581 ,1%
3
LX
38.3k1 , 1%
1.5nF
4
47uF
6.3V
LX
R1
CP1
5
68.1k1 ,1%
CZ3
820pF
VCC
GND
GND
GND
BST
NC
3.3pF
6
COMP
UVIN
GND
SS
CVCC
2.2uF
7
CF1
100pF
GND2
8
9
R2
21.5k1 ,1%
RBST
10
11
12
13
CSS
22nF
VIN
5.111 ,
DBST
SD101AWS
1%
VIN
LX
VIN
LX
CBST
1uF
VIN
LX
VIN
12V
U2
Fs=1.3MHz
R3
SPX5205
VIN VOUT
GND
200k1 ,1%
C1,C5:
CERAMIC
X5R
1
5
4
Notes:
C1
22uF
16V
C5
22uF
16V
2
3
U1 Bottom-Side Layout should have
three Contacts which are
EN
BYP
isolated from one another: QT-
Drain Contact, QB-Drain Contact and
Controller-GND Contact.
R4
100k1 ,1%
C2
0.1uF
GND
ALL RESISTORS & CAPACITORS ARE SIZE
0603 UNLESS OTHERWISE SPECIFIED.
Date: ꢀꢀ/20/06
SP7653 Wide Input Voltage Range, ꢀ.3MHz, Buck Regulator
© Copyright 2006 Sipex Corporation
ꢀ
ABSOLUTE MAXIMUM RATINGS
Thesearestressratingsonlyandfunctionaloperationofthedeviceattheseratingsoranyotherabovethoseindicatedintheoperationsectionsofthe
specificationsbelowisnotimplied.Exposuretoabsolutemaximumratingconditionsforextendedperiodsoftimemayaffectreliability.
VCC ..................................................................................................7V
V ........................................................................................................................................... 20V
IN
StorageTemperature..................................................-65°Cto150°C
I X...............................................................................................................................................5A
L
PowerDissipation ...................................... InternallyLimitedviaOT
P
B
ST...............................................................................................27V
E
S
DRating ..........................................................................2kVH
B
M
LX-BST ............................................................................. -0.3Vto7V
LX....................................................................................... -1Vto20V
ThermalResistanceV .................................................................................... 5°C/W
JC
Allotherpins .......................................................... -0.3VtoV C+0.3V
C
ELECTRICAL SPECIFICATIONS
Unless otherwise specified: -40°C < TAMB < 85°C, -40°C< Tj< 125°C, 4.5V < V < 5.5V, 3V< Vin< 28V, Boost=LX+ 5V,
CC
LX =G
N
D=0.0V,UV =3.0V,CV =1µF,CCOMP =0.1µF,C =50nF,TypicalmeasuredatV =5V.
IN
CC
SS
CC
Thez denotesthespecificationswhichapplyoverthefulltemperaturerange,unlessotherwisespecified.
PARAMETER
MIN.
TYP.
MAX.
3
UNITS
CONDITIONS
QUIESCENT CURRENT
V SupplyCurrent(Noswitching)
1.5
8
mA
mA
V =0.9V
CC
FB
♦
♦
V SupplyCurrent(switching)
CC
BoostSupplyCurrent(No
0.2
4.0
0.4
mA
mA
V =0.9V
FB
switching)
BoostSupplyCurrent(switching)
PROTECTION: UVLO
V UVLOStartThreshold
4.00
100
2.3
4.25
200
2.5
4.5
300
2.65
400
1
V
mV
V
CC
V UVLOHysteresis
CC
♦
♦
UVINStartThreshold
UVINHysteresis
200
300
mV
µA
UVINInputCurrent
UVIN=3.0V
ERROR AMPLIFIER REFERENCE
2XGainConfig.,Measure
ErrorAmplifierReference
0.792 0.800 0.808
0.788 0.800 0.812
V
V
V ;V =5V,T=25ºC
FB CC
ErrorAmplifierReference
OverLineandTemperature
ErrorAmplifierTransconductance
ErrorAmplifierGain
6
mA/V
60
dB
NoLoad
COMPSinkCurrent
150
150
µA
V =0.9V,COMP=0.9V
FB
COMPSourceCurrent
µA
V =0.7V,COMP=2.2V
FB
V InputBiasCurrent
50
4
200
nA
V =0.8V
FB
FB
InternalPole
MHz
V
COMPClamp
2.5
-2
V =0.7V,TA=25ºC
FB
COMPClampTemp.Coefficient
mV/ºC
Date: ꢀꢀ/20/06
SP7653 Wide Input Voltage Range, ꢀ.3MHz, Buck Regulator
© Copyright 2006 Sipex Corporation
2
ELECTRICAL SPECIFICATIONS
Unless otherwise specified: -40°C < T MB < 85°C, -40°C< Tj< 125°C, 4.5V < V C < 5.5V, 3V< Vin< 28V, Boost = LX+ 5V,
A
C
LX=GN
D=0.0V,UVIN=3.0V,CV C =1µF,C OMP =0.1µF,C S =50nF,TypicalmeasuredatV C=5V.
C
C
S
C
Thez denotesthespecificationswhichapplyoverthefulltemperaturerange,unlessotherwisespecified.
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
CONTROL LOOP: PWM COMPARATOR, RAMP & LOOP DELAY PATH
RampAmplitude
RAMPOffset
0.92
1.1
1.1
1.28
180
V
V
T =25ºC,RAMPCOMP
A
untilGHstartsSwitching
RAMP offsetTemp.Coefficient
-2
mV/ºC
♦
♦
GHMinimumPulseWidth
90
ns
MaximumDutyRatio
Measuredjustbefore
pulsingbegins
MaximumControllableDutyRatio
92
97
%
MaximumDutyRatio
InternalOscillatorRatio
TIMERS: SOFTSTART
SSChargeCurrent:
100
1.1
%
Validfor20cycles
1.3
10
1.5
0.3
MHz
µA
♦
♦
SSDischargeCurrent:
1
mA
FaultPresent,SS=0.2V
PROTECTION: Short Circuit & Thermal
MeasuredV EF (0.8V)-
R
ShortCircuitThresholdVoltage
HiccupTimeout
0.2
0.25
200
20
V
ms
V
F
B
V =0.5V
FB
NumberofAllowableClockCycles
at100%DutyCycle
Cycles
MinimumGLPulseAfter20Cycles
ThermalShutdownTemperature
ThermalRecoveryTemperature
ThermalHysteresis
0.5
145
135
10
Cycles
V =0.7V
F
B
ºC
V =0.7V
F
B
ºC
ºC
OUTPUT: POWER STAGE
V =5V;I UT =3A
C
C
O
HighSideSwitchR O
40
40
mΩ
DS N
T MB =25ºC
A
V =5V;I UT =3A
C
C
O
SynchronousLowsideSwitchR O
mΩ
A
DS N
T MB =25ºC
A
MaximumOutputCurrent
3
Date: ꢀꢀ/20/06
SP7653 Wide Input Voltage Range, ꢀ.3MHz, Buck Regulator
© Copyright 2006 Sipex Corporation
3
PIN DESCRIPTION
Pin #
Pin Name
Description
1-3
4,8,19-21
P
GND
G
N
D
Groundconnectionforthesynchronousrectifier
GroundPin.ThecontrolcircuitryoftheICandlowerpowerdriverare
referencedtothispin.Returnseparatelyfromothergroundtracestothe(-)
terminalofC
O
UT
.
FeedbackVoltageandShortCircuitDetectionpin.Itistheinvertinginputof
theErrorAmplifierandservesastheoutputvoltagefeedbackpointforthe
BuckConverter.Theoutputvoltageissensedandcanbeadjustedthrough
anexternalresistordivider. WheneverV drops0.25Vbelowthepositive
5
V
F
B
FB
reference,ashortcircuitfaultisdetectedandtheICentershiccupmode.
OutputoftheErrorAmplifier.Itisinternallyconnectedtotheinvertinginputof
6
7
9
COMP
UVIN
SS
thePWMcomparator. Anoptimalfiltercombinationischosenandconnected
tothispinandeithergroundorV
FB
tostabilizethevoltagemodeloop.
UVLOinputforVIN voltage.ConnectaresistordividerbetweenVIN andUVIN
tosetminimumoperatingvoltage.
SoftStart.ConnectanexternalcapacitorbetweenSSandGNDtosetthe
softstartratebasedonthe10µAsourcecurrent.TheSSpinisheldlowviaa
1mA(min)currentduringallfaultconditions.
InputconnectiontothehighsideN-channelMOSFET.Placeadecoupling
capacitorbetweenthispinandPGND.
10-13
V
IN
14-16,23-26
LX
ConnectaninductorbetweenthispinandV
OUT
17
N
C
NoConnect
Highsidedriversupplypin. ConnectBSTtotheexternalboostdiodeand
capacitorasshownintheTypicalApplicationCircuitonpage1. Highside
driveris connectedbetweenBSTpinandSWNpin.
18
22
BST
Vcc
Inputforexternal5Vbiassupply
THEORY OF OPERATION
General Overview
The SP7653 is a fixed frequency, voltage mode,
synchronousPWMregulatoroptimizedforhigh
efficiency. The part has been designed to be
especially attractive for high input voltages of
2.5V to 20V.
The SP7653 contains two unique control fea-
tures that are very powerful in distributed appli-
cations. First, asynchronous driver control is
enabled during startup, to prohibit the low side
switch from pulling down the output until the
high side switch has attempted to turn on. Sec-
ond, a 100% duty cycle timeout ensures that the
low side switch is periodically enhanced during
extended periods at 100% duty cycle. This guar-
antees the synchronized refreshing of the Boost
capacitor during very large duty cycle ratios.
The heart of the SP7653 is a wide bandwidth
transconductance amplifier designed to accom-
modate Type II and Type III compensation
schemes. Aprecision0.8Vreference, presenton
the positive terminal of the error amplifier,
permits the programming of the output voltage
down to 0.8V via the VFB pin. The output of the
error amplifier, COMP, compared to a 1.1V
peak-to-peak ramp is responsible for trailing
edge PWM control. This voltage ramp, and
PWM control logic are governed by the internal
oscillator that accurately sets the PWM fre-
quency to 1.3MHz.
The SP7653 also contains a number of valuable
protection features. Programmable VIN UVLO
allowstheusertosettheexactvalueatwhichthe
conversion voltage can safely begin down con-
version, and an internal VCC UVLO which en-
sures that the controller itself has enough volt-
age to operate properly. Other protection fea-
Date: ꢀꢀ/20/06
SP7653 Wide Input Voltage Range, ꢀ.3MHz, Buck Regulator
© Copyright 2006 Sipex Corporation
ꢁ
THEORY OF OPERATION
Thermal and Short-Circuit Protection
tures include thermal shutdown and short-cir-
cuit detection. In the event that either a thermal,
short-circuit, or UVLO fault is detected, the
SP7653 is forced into an idle state where the
output drivers are held off for a finite period
before a restart is attempted.
Because the SP7653 is designed to drive large
output current, there is a chance that the power
converter will become too hot. Therefore, an
internal thermal shutdown (145°C) has been
included to prevent the IC from malfunctioning
at extreme temperatures.
Soft Start
“Soft Start” is achieved when a power converter
ramps up the output voltage while controlling
the magnitude of the input supply source cur-
rent. In a modern step down converter, ramping
up the positive terminal of the error amplifier
controls soft start. As a result, excess source
current can be defined as the current required to
charge the output capacitor:
A short-circuit detection comparator has also
been included in the SP7653 to protect against
an accidental short at the output of the power
converter. This comparator constantly monitors
the positive and negative terminals of the error
amplifier, and if the VFB pin falls more than
250mV (typical) below the positive reference, a
short-circuit fault is set. Because the SS pin
overridestheinternal0.8Vreferenceduringsoft
start, the SP7653 is capable of detecting short-
circuit faults throughout the duration of soft
start as well as in regular operation.
I
VIN = COUT * (6VOUT / 6TSOFT-START)
The SP7653 provides the user with the option to
program the soft start rate by tying a capacitor
from the SS pin to GND. The selection of this
capacitor is based on the 10uA pull up current
present at the SS pin and the 0.8V reference
voltage. Therefore, the excess source can be
redefined as:
Handling of Faults:
Upon the detection of power (UVLO), thermal,
or short-circuit faults, the SP7653 is forced into
an idle state where the SS and COMP pins are
pulled low and both switches are held off. In the
eventofUVLOfault, theSP7653remainsinthis
idle state until the UVLO fault is removed.
Upon the detection of a thermal or short-circuit
fault, aninternal200ms timerisactivated. Inthe
event of a short-circuit fault, a restart is at-
tempted immediately after the 200ms timeout
expires. Whereas, when a thermal fault is de-
tected, the 200ms delay continuously recycles
and a restart cannot be attempted until the ther-
mal fault is removed and the timer expires.
IVIN = COUT *[(DVOUT *10µA) /(CSS * 0.8V)]
Under Voltage Lock Out (UVLO)
The SP7653 contains two separate UVLO com-
parators to monitor the bias (VCC) and conver-
sion (VIN) voltages independently. The VCC
UVLO threshold is internally set to 4.25V,
whereas the VIN UVLO threshold is program-
mable through the UVIN pin. When the voltage
ontheUVIN pinisgreaterthan2.5V,theSP7653
is permitted to start up pending the removal of
all other faults. Both the VCC and VIN UVLO
comparatorshavebeendesignedwithhysteresis
to prevent noise from resetting a fault.
Error Amplifier and Voltage Loop
The heart of the SP7653 voltage error loop
compensationisahighperformance,wideband-
width transconductance amplifier. Because of
the amplifier’s current limited (+/-150µA)
transconductance, there are many ways to com-
pensate the voltage loop or to control the COMP
Date: ꢀꢀ/20/06
SP7653 Wide Input Voltage Range, ꢀ.3MHz, Buck Regulator
© Copyright 2006 Sipex Corporation
5
THEORY OF OPERATION
pin externally. If a simple, single-pole single-
zero response is desired, then compensation can
be as simple as an RC circuit to Ground. If a
more complex compensation is required, then
the amplifier has enough bandwidth (45° at 4
MHz) and enough gain (60dB) to run Type III
compensation schemes with adequate gain and
phase margins at crossover frequencies greater
than 50kHz.
V
B
ST
G
H
Voltage
V
S
WN
V(V
C
C)
GL
Voltage
0V
V(V )
IN
S
WN
The common mode output of the error amplifier
is 0.9V to 2.2V. Therefore, the PWM voltage
ramp has been set between 1.1V and 2.2V to
ensureproper0%to100%dutycyclecapability.
The voltage loop also includes two other very
important features. One is an asynchronous
startup mode. Basically, the synchronous recti-
fier cannot turn on unless the high side switch
has attempted to turn on or the SS pin has
exceeded 1.7V. This feature prevents the con-
troller from “dragging down” the output voltage
during startup or in fault modes. The second
feature is a 100% duty cycle timeout that en-
sures synchronized refreshing of the Boost ca-
pacitor at very high duty ratios. In the event that
the high side NFET is on for 20 continuous
clock cycles, a reset is given to the PWM flip-
flop half way through the 21st cycle. This forces
GL to rise for the cycle, in turn refreshing the
Boost capacitor. The boost capacitor is used to
generate a high voltage drive supply for the high
side switch, which is 5V above VIN.
Voltage
-0V
-V(Diode)V
V(V )+V(V
)
IN
CC
B
ST
Voltage
V(V
)
C
C
TIME
Setting Output Voltages
The SP7653 can be set to different output volt-
ages. The relationship in the following formula
is based on a voltage divider from the output to
the feedback pin VFB, which is set to an internal
reference voltage of 0.80V. Standard 1% metal
film resistors of surface mount size 0603 are
recommended.
VOUT = 0.80V ( R1 / R2 + 1 ) =>
Power MOSFETs
R1
.
R2 =
The SP7653 contains a pair of integrated low
resistance N-channel switches designed for up
to 3Amps. Care should be taken to de-rate the
output current based on the thermal conditions
in the system such as ambient temperature,
airflow and heat sinking. Maximum output cur-
rent could be limited by thermal limitations of a
particular application by taking advantage of
the integrated-over-temperature protective
scheme employed in the SP7653. The SP7653
incorporates a built-in overtemperature protec-
tion to prevent internal overheating.
{
( VOUT / 0.80V ) – 1
}
Where R1 = 68.1K1 and for VOUT = 0.80V
setting, simply remove R2 from the board. Fur-
thermore, one could select the value of the R1
and R2 combination to meet the exact output
voltagesettingbyrestrictingtheresistancerange
of R1 such that 50K1 < R1 < 100K1 for overall
system loop stability.
Date: ꢀꢀ/20/06
SP7653 Wide Input Voltage Range, ꢀ.3MHz, Buck Regulator
© Copyright 2006 Sipex Corporation
6
APPLICATIONS INFORMATION
Inductor Selection
IPP
IPEAK = IOUT (max)
+
There are many factors to consider in selecting
the inductor including core material, inductance
vs. frequency, current handling capability, effi-
ciency, size and EMI. In a typical SP7653 cir-
cuit, the inductor is chosen primarily for value,
saturationcurrentandDCresistance. Increasing
the inductor value will decrease output voltage
ripple, but degrade transient response. Low in-
ductor values provide the smallest size, but
cause large ripple currents, poor efficiency and
require more output capacitance to smooth out
the larger ripple current. The inductor must be
able to handle the peak current at the switching
frequency without saturating, and the copper
resistance in the winding should be kept as low
as possible to minimize resistive power loss. A
good compromise between size, loss and cost is
to set the inductor ripple current to be within
20% to 40% of the maximum output current.
2
...and provide low core loss at the high switch-
ing frequency. Low cost powdered-iron cores
have a gradual saturation characteristic but can
introduce considerable AC core loss, especially
whentheinductorvalueisrelativelylowandthe
ripplecurrentishigh.Ferritematerials,although
more expensive, have an abrupt saturation char-
acteristic with the inductance dropping sharply
when the peak design current is exceeded. Nev-
ertheless, they are preferred at high switching
frequencies because they present very low core
loss while the designer is only required to
prevent saturation. In general, ferrite or
molypermalloy materials are a better choice for
all but the most cost sensitive applications.
Optimizing Efficiency
The switching frequency and the inductor oper-
ating point determine the inductor value as fol-
lows:
The power dissipated in the inductor is equal to
the sum of the core and copper losses. To mini-
mizecopperlosses,thewindingresistanceneeds
to be minimized, but this usually comes at the
expense of a larger inductor. Core losses have a
more significant contribution at low output cur-
rent where the copper losses are at a minimum,
and can typically be neglected at higher output
currentswherethecopperlossesdominate.Core
loss information is usually available from the
magneticsvendor.Properinductorselectioncan
affect the resulting power supply efficiency by
more than 15%!
VOUT (VIN (max) <VOUT
)
L =
VIN (max) FS Kr IOUT (max)
where:
fS = switching frequency
Kr = ratio of the AC inductor ripple current to
the maximum output current
Thecopperlossintheinductorcanbecalculated
using the following equation:
The peak-to-peak inductor ripple current is:
P
L(Cu) = IL2(RMS) RWINDING
VOUT (VIN (max) <VOUT
)
IPP
=
where IL(RMS) is the RMS inductor current that
can be calculated as follows:
VIN(max) FS L
2
IPP
IOUT(max)
1
3
Once the required inductor value is selected, the
proper selection of core material is based on
peak inductor current and efficiency require-
ments. The core must be large enough not to
saturate at the peak inductor current...
IL(RMS) = IOUT(max) 1 +
(
)
Date: ꢀꢀ/20/06
SP7653 Wide Input Voltage Range, ꢀ.3MHz, Buck Regulator
© Copyright 2006 Sipex Corporation
7
APPLICATIONS INFORMATION
FS = Switching Frequency
Output Capacitor Selection
D = Duty Cycle
The required ESR (Equivalent Series Resis-
tance) and capacitance drive the selection of the
type and quantity of the output capacitors. The
ESR must be small enough that both the resis-
tive voltage deviation due to a step change in the
load current and the output ripple voltage do not
exceed the tolerance limits expected on the
output voltage. During an output load transient,
the output capacitor must supply all the addi-
tional current demanded by the load until the
SP7653 adjusts the inductor current to the new
value.
COUT = Output Capacitance Value
Input Capacitor Selection
The input capacitor should be selected for ripple
current rating, capacitance and voltage rating.
The input capacitor must meet the ripple current
requirement imposed by the switching current.
In continuous conduction mode, the source cur-
rent of the high-side MOSFET is approximately
a square wave of duty cycle VOUT/VIN. More
accurately, thecurrentwaveformistrapezoidal,
given a finite turn-on and turn-off, switch tran-
sition slope. Most of this current is supplied by
the input bypass capacitors. The RMS current
handling capability of the input capacitors is
determined at maximum output current and
under the assumption that the peak-to-peak in-
ductor ripple current is low; it is given by:
In order to maintain VOUT ,the capacitance must
belargeenoughsothattheoutputvoltageisheld
up while the inductor current ramps to the value
corresponding to the new load current. Addi-
tionally, the ESR in the output capacitor causes
a step in the output voltage equal to the current.
Because of the fast transient response and inher-
ent 100% to 0% duty cycle capability provided
by the SP7653 when exposed to an output load
transient, the output capacitor is typically cho-
sen for ESR, not for capacitance value.
ICIN(RMS) = IOUT(max)
3 D(1 - D)
The worst case occurs when the duty cycle D is
50% and gives an RMS current value equal to
IOUT/2. Select input capacitors with adequate
ripple current rating to ensure reliable opera-
tion.
The ESR of the output capacitor, combined with
the inductor ripple current, is typically the main
contributor to output voltage ripple. The maxi-
mum allowable ESR required to maintain a
specifiedoutputvoltageripplecanbecalculated
by:
The power dissipated in the input capacitor is:
6V UT
O
P
= IC2IN (rms) RESR(CIN)
RESR
)
CIN
I K-P
P
K
where:
This can become a significant part of power
losses in a converter and hurt the overall energy
transfer efficiency. The input voltage ripple
primarily depends on the input capacitor ESR
and capacitance. Ignoring the inductor ripple
current, the input voltage ripple can be deter-
mined by:
6VOUT = Peak-to-Peak Output Voltage Ripple
IPK-PK = Peak-to-Peak Inductor Ripple Current
The total output ripple is a combination of the
ESR and the output capacitance value and can
be calculated as follows:
IOUT (MAX )VOUT (VIN <VOUT
)
2 + (IPPRESR
)
6VIN = Iout(max) RESR(CIN )
+
2
IPP (1 – D)
2
FSCINVIN
6VOUT
=
COUTFS
Date: ꢀꢀ/20/06
SP7653 Wide Input Voltage Range, ꢀ.3MHz, Buck Regulator
© Copyright 2006 Sipex Corporation
ꢂ
APPLICATIONS INFORMATION
The first step of compensation design is to pick
the loop crossover frequency. High crossover
frequencyisdesirableforfasttransientresponse,
but often jeopardizes the power supply stability.
Crossover frequency should be higher than the
ESR zero but less than 1/5 of the switching
frequency or 60kHz. The ESR zero is contrib-
uted by the ESR associated with the output
capacitors and can be determined by:
The capacitor type suitable for the output capac-
itors can also be used for the input capacitors.
However, exercise extra caution when tantalum
capacitorsareused.Tantalumcapacitorsareknown
for catastrophic failure when exposed to surge
current, and input capacitors are prone to such
surge current when power supplies are connected
“live”tolowimpedancepowersources. Although
tantalum capacitors have been successfully em-
ployed at the input, it is generally not recom-
mended.
1
ƒZ(ESR)
=
2/ COUT RESR
The next step is to calculate the complex conju-
gate poles contributed by the LC output filter,
Loop Compensation Design
The open loop gain of the whole system can be
divided into the gain of the error amplifier,
PWM modulator, buck converter output stage,
and feedback resistor divider. In order to cross
over at the desired frequency cut-off (FCO), the
gain of the error amplifier must compensate for
the attenuation caused by the rest of the loop at
this frequency. The goal of loop compensation
is to manipulate loop frequency response such
that its crossover gain at 0db, results in a slope
of -20db/dec.
1
ƒP(LC)
=
2/ L COUT
When the output capacitors are Ceramic, the
SP7653 Evaluation Board requires a Type III
compensation circuit to give a phase boost of
180° in order to counteract the effects of an
underdamped resonance of the output filter at
the double pole frequency.
Type III Voltage Loop
Compensation
GAMP (s) Gain Block
PWM Stage
GPWM Gain
Block
Output Stage
G
OUT (s) Gain
Block
V
(SRz
2
Cz
2
+
1)(SR1Cz
3
+
1)
(SRESRCOU +1)
V AIN
UT S(R RT
+
R C)C UT
+
1]
+
_
VREF
(Volts)
VOUT
(Volts)
S
R1Cz2(SRz
3
Cz
3
+
1)(SRz
2
Cp
1
+
1)
[S^
2
L O
C
+
R M
P
_
P
P
E
S
D
O
Notes:R SR =OutputCa
pacitorEquivalentSeriesResistance.
E
R
DC =OutputIn
d
uctorD
C
Resistance.
V MP_PP =SP6
1
3
2InternalR
A
M
P
A
mplitu
d
ePeaktoPeakVolta
g
e.
RA
Co
n
dition:Cz2>>Cp1&R1>>Rz
3
OutputLo
a
dResistance>>R SR &R C
E
D
Voltage Feedback
FBK Gain Block
G
R
V E
R F
2
or
V U
O T
(R R )
1
+
2
VFBK
(Volts)
SP7653 Voltage Mode Control Loop with Loop Dynamic
Definitions:
R
R
R
ESR = Output Capacitor Equivalent Series Resistance
DC = Output Inductor DC Resistance
RAMP_PP = SP7653 internal RAMP Amplitude Peak to Peak Voltage
Conditions:
CZ2 >> Cp1 and R1 >> Rz3
Output Load Resistance >> RESR and RDC
Date: ꢀꢀ/20/06
SP7653 Wide Input Voltage Range, ꢀ.3MHz, Buck Regulator
© Copyright 2006 Sipex Corporation
ꢃ
APPLICATIONS INFORMATION
Gain
(dB)
ErrorAmplifierGain
BandwidthProduct
Condition:
C22>>CP1,R1>>RZ3
20Log(RZ2/R1)
Frequency
(Hz)
Bode Plot of Type III Error Amplifier Compensation.
CP1
RZ2
CZ2
RZ3
CZ3
V
OUT
5
-
R1
6
VFB
68.1k,1%
+
COMP
R
SET
CF1
+
0.8V
-
R
-0.8V)
(k1)
=54.48/(V
SET
OUT
Type III Error Amplifier Compensation Circuit
Date: ꢀꢀ/20/06
SP7653 Wide Input Voltage Range, ꢀ.3MHz, Buck Regulator
© Copyright 2006 Sipex Corporation
ꢀ0
APPLICATIONS INFORMATION
SP765X Thermal Resistance
The SP765X family has been tested with a
variety of footprint layouts along with different
copper area and thermal resistance has been
measured. The layouts were done on 4 layer
FR4 PCB with the top and bottom layers using
3oz copper and the Power and Ground layers
using 1oz copper.
Using a minimum of 0.1 square inches of (3
ounces of) copper on the top layer with no vias
connecting to the 3 other layers produced a
thermal resistance of 44°C/W. This thermal
impedance is only 22% higher than the medium
andlargefootprintlayouts, indicatingthatspace
constrained designs can still benefit thermally
from the Powerblox family of ICs. This indi-
cates that a minimum footprint of 0.1 square
inch, if used on a 4 layer board, can produce
44°C/W thermal resistance. This approach is
still very worthwhile if used in a space con-
strained design.
FortheMinimumfootprint,onlyabout0.1square
inch (of 3 ounces of) copper was used on the top
or footprint layer, and this layer had no vias to
connect to the 3 other layers. For the Medium
footprint, about 0.7 square inches (of 3 ounces
of) copper was used on the top layer, but vias
were used to connect to the other 3 layers. For
the Maximum footprint, about 1.0 square inch
(of3ouncesof)copperwasusedonthetoplayer
and many vias were used to connect to the 3
other layers.
The following page shows the footprint layouts
from an ORCAD file. The thermal data was
taken for still air, not with forced air. If forced
air is used, some improvement in thermal resis-
tance would be seen.
The results show that only about 0.7 square
inches (of 3 ounces of) copper on the top layer
and vias connecting to the 3 other layers are
needed to get the best thermal resistance of
36°C/W. Adding area on the top beyond the 0.7
square inches did not reduce thermal resistance.
SP765XThermalResistance
4LayerBoard:
TopLayer3ouncesCopper
GNDLayer1ounceCopper
PowerLayer1ounceCopper
BottomLayer3ouncesCopper
MinimumFootprint:44°C/W
TopLayer:0.1squareinch
NoViastoother3Layers
MediumFootprint:36°C/W
TopLayer:0.7squareinch
Viastoother3Layers
MaximumFootprint:36°C/W
TopLayer:1.0squareinch
Viastoother3Layers
Date: ꢀꢀ/20/06
SP7653 Wide Input Voltage Range, ꢀ.3MHz, Buck Regulator
© Copyright 2006 Sipex Corporation
ꢀꢀ
APPLICATIONS INFORMATION
Date: ꢀꢀ/20/06
SP7653 Wide Input Voltage Range, ꢀ.3MHz, Buck Regulator
© Copyright 2006 Sipex Corporation
ꢀ2
TYPICAL PERFORMANCE CHARACTERISTICS
EfficiencyvsOutputLoadat12Vin
100
90
80
70
60
50
40
Vout=5.0V
Vout=3.3V
Vout=2.5V
Vout=1.8V
Vout=1.5V
Vout=1.2V
0
0.5
1
1.5
2
2.5
2.5
3
OutputLoadCurrent(A)
EfficiencyvsOutputLoadat5Vin
100
90
80
70
60
50
40
Vout=3.3V
Vout=2.5V
Vout=1.8V
Vout=1.5V
Vout=1.2V
0
0.5
1
1.5
2
3
OutputLoadCurrent(A)
EfficiencyvsOutputLoadat3.3Vin
100
90
80
70
60
50
40
Vout=2.5V
Vout=1.8V
Vout=1.5V
Vout=1.2V
0
0.5
1
1.5
2
2.5
3
OutputLoadCurrent(A)
Date: ꢀꢀ/20/06
SP7653 Wide Input Voltage Range, ꢀ.3MHz, Buck Regulator
© Copyright 2006 Sipex Corporation
ꢀ3
PACKAGE: 26 PIN DFN
Date: ꢀꢀ/20/06
SP7653 Wide Input Voltage Range, ꢀ.3MHz, Buck Regulator
© Copyright 2006 Sipex Corporation
ꢀꢁ
ORDERING INFORMATION
Package
Part Number
Temperature
SP7653ER..............................................-40°Cto+85°C................................. 26Pin7X4DFN
SP7653ER-L...........................................-40°Cto+85°C............. (LeadFree)26Pin 7X4DFN
SP7653ER/TR ........................................-40°Cto+85°C................................. 26Pin7X4DFN
SP7653ER-L/TR .....................................-40°Cto+85°C............. (LeadFree)26Pin 7X4DFN
BulkPackminimumquantityis500.
/TR=TapeandReel. Packquantityis3,000DFN.
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Solved by Sipex
tm
Milpitas, CA ꢃ5035
TEL: (ꢁ0ꢂ) ꢃ3ꢁ-7500
FAX: (ꢁ0ꢂ) ꢃ35-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume
any liability arising out of the application or use of any product or circuit described herein; neither does it convey
any license under its patent rights nor the rights of others.
Date: ꢀꢀ/20/06
SP7653 Wide Input Voltage Range, ꢀ.3MHz, Buck Regulator
© Copyright 2006 Sipex Corporation
ꢀ5
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