SP6121 [SIPEX]

Low Voltage, Synchronous Step Down PWM Controller Ideal for 2A to 10A, Small Footprint, DC-DC Power Converters; 低电压同步降压PWM控制器,非常适合2A至10A ,占地面积小, DC-DC电源转换器
SP6121
型号: SP6121
厂家: SIPEX CORPORATION    SIPEX CORPORATION
描述:

Low Voltage, Synchronous Step Down PWM Controller Ideal for 2A to 10A, Small Footprint, DC-DC Power Converters
低电压同步降压PWM控制器,非常适合2A至10A ,占地面积小, DC-DC电源转换器

转换器 射频 微波 控制器
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®
SP6121  
Low Voltage, Synchronous Step Down PWM Controller  
Ideal for 2A to 10A, Small Footprint, DC-DC Power Converters  
FEATURES  
Optimized for Single Input Voltage - 3V to 5.5V  
1
2
3
4
8
7
6
5
VCC  
PDRV  
NDRV  
ISET  
High Efficiency: Greater than 95% possible  
Accurate, 500kHz Fixed Frequency Operation  
Fast Transient Response  
SP6121  
GND  
VFB  
8 Pin SOIC  
COMP  
ISENSE  
500µA, IQ (25µA in Shutdown)  
Internal, 0.4 V/ms, Soft Start Circuit  
Precision 1% Reference  
Now Available in Lead Free Packaging  
Resistor Programmable Output Voltage  
Lossless Adjustable Current Limit with  
High Side RDS(ON) Sensing  
0% to 100% Duty Cycle Range  
High Side PMOS Switch Negates Need for  
APPLICATIONS  
Supply Bias for  
- DSP  
- Microprocessor Core  
- I/O & Logic  
External Charge Pump  
Output Over Voltage Protection  
Hiccup Mode Current Limit Protection  
Video Cards  
Board Level Supply in  
Distributed Power Systems  
DESCRIPTION  
The SP6121 is a fixed frequency, voltage mode, synchronous PWM controller designed to work  
fromasingle5Vor3.3Vinputsupply,providingexcellentACandDCregulationforhighefficiency  
power conversion. The operating frequency is internally set at 500kHz, permitting the use of  
small, surface mount inductors and capacitors. Requiring only few external components, the  
SP6121 packaged in an 8-pin SOIC, is especially suited for low voltage applications where cost,  
small size and high efficiency are critical. With its low voltage capability and inherent 100% duty  
cycle operation, the SP6121 allows low dropout operation in the event of a low input supply  
voltage condition.  
TYPICAL APPLICATION CIRCUIT  
3.3V  
V
IN  
RSET  
2.3k  
C
IN  
RV  
CC  
5
47µF  
Ceramic 6.3V  
®®  
Q1  
Q2  
1.9V 8A  
1.8µH  
V
PDRV  
NDRV  
CC  
V
OUT  
CB  
3.3µF  
L1  
SP6121  
U1  
C
DS  
GND  
OUT  
470µF x 2  
R1  
5.2k  
I
SET  
V
FB  
I
COMP  
SENSE  
R2  
10k  
RZ  
10k  
CZ  
3.7nF  
CP  
50pF  
Q1 = FAIRCHILD FDS6375  
Q2 = FAIRCHILD FDS6690A  
DS = STMICROELECTRONICS STPS2L25BU  
L1 = PANASONIC ETQ-P6F1R6SFA  
COUT = SANYO 4TPB470M  
Date: 5/25/04  
SP6121 Low Voltage, Synchronous Step Down PWM Controller  
© Copyright 2004 Sipex Corporation  
1
ABSOLUTE MAXIMUM RATINGS  
VCC ...................................................................................................... 7V  
All other pins ............................... -0.3V to VCC+0.3V  
Peak Output Current < 10µs  
PDRV, NDRV....................................................... 2A  
Storage Temperature ...................... -65°C to 150°C  
Lead Temperature (Soldering, 10 sec) ..........300°C  
ESD Rating ............................................... 2kV HBM  
These are stress ratings only and functional  
operation of the device at these ratings or any other  
above those indicated in the operation sections of  
the specifications below is not implied. Exposure to  
absolute maximum rating conditions for extended  
periods of time may affect reliability.  
ELECTRICAL SPECIFICATIONS  
Unless otherwise specified: 0°C < TA < 70°C, 3.0V < VCC < 5.5V, CCOMP = 22nF, CPDRV = CNDRV = 3.3nF, VFB = 1.25V, ISET = ISENSE = VCC, GND=0V  
PARAMETER  
MIN  
TYP  
MAX UNITS CONDITIONS  
QUIESCENT CURRENT  
VCC Supply Current  
-
-
0.5  
25  
1.0  
60  
mA No Switching  
VCC Supply Current (Disabled)  
ERROR AMPLIFIER  
µA  
COMP = 0V  
Error Amplifier Transconductance  
COMP Sink Current  
600  
35  
35  
µs  
µA  
µA  
M  
nA  
15  
15  
65  
65  
VFB = 1.35V, COMP=0.8V, No Faults  
VFB =1.15V, COMP=1.8V  
COMP Source Current  
COMP Output Impedance  
VFB Input Bias Current  
ERROR AMPLIFIER REFERENCE  
Initial Accuracy  
3
100  
1.238 1.250 1.262  
1.225 1.250 1.275  
V
V
Trimmed with Error Amp in Unity Gain  
Error Amplifier Reference over  
Line, Load and Temperature  
OSCILLATOR & DELAY PATH  
Internal Oscillator Frequency  
Maximum Duty Cycle  
440  
100  
-
500  
560  
kHz  
%
-
-
-
COMP = 2V  
Minimum Duty Cycle  
0
%
COMP = 0.8V  
Minimum PDRV Pulse Width  
100  
ns  
VCC > 4.5V, Ramp up COMP voltage  
until PDRV starts switching  
CURRENT LIMIT  
Internal Current Limit Threshold  
ISET Sink Current  
125  
25  
160  
30  
195  
35  
mV  
µA  
VISET - VISENSE, TA = 25°C  
VISET =5V, TA = 25°C  
Current Limit Threshold and  
ISET Temperature Coefficient  
0.33  
%/C  
Current Limit Time Constant  
ISENSE Input Bias Current  
15  
-
µs  
-
100  
nA  
SOFT START, SHUTDOWN, UVLO  
Internal Soft Start Slew Rate  
0.4  
V/ms Measured at COMP pin on the  
transition from shutdown  
Internal Soft Start Delay Time  
COMP Discharge Current  
COMP Clamp Voltage  
1.5  
300  
0.7  
ms  
µA  
V
COMP charging to PDRV switching  
COMP = 0.5V, Fault Initiated  
VFB = 1.3V  
150  
0.6  
0.8  
COMP Clamp Current  
100  
µA  
COMP = 0.5V, VFB =1.15V  
Date: 5/25/04  
SP6121 Low Voltage, Synchronous Step Down PWM Controller  
© Copyright 2004 Sipex Corporation  
2
ELECTRICAL SPECIFICATIONS: Continued  
Unless otherwise specified: 0°C < TA < 70°C, 3.0V < VCC < 5.5V, CCOMP = 22nF, CPDRV = CNDRV = 3.3nF, VFB = 1.25V, ISET = ISENSE = VCC, GND=0V  
PARAMETER  
MIN  
TYP  
MAX UNITS CONDITIONS  
SOFT START, SHUTDOWN, UVLO: continued  
Shutdown Threshold Voltage  
Shutdown Input Pull-up Current  
VCC Start Threshold  
0.2  
0.3  
5
0.4  
V
µA  
V
Measured at COMP Pin  
COMP = 0.2V, Measured at COMP pin  
2.69  
2.59  
-
2.79  
2.69  
100  
2.89  
2.79  
-
VCC Stop Threshold  
V
VCC Hysteresis  
mV  
GATE DRIVERS  
PDRV Rise Time  
-
-
-
-
40  
40  
40  
40  
80  
50  
110  
110  
110  
110  
ns  
ns  
ns  
ns  
ns  
ns  
VCC > 4.5V  
VCC > 4.5V  
VCC > 4.5V  
VCC > 4.5V  
VCC > 4.5V  
VCC > 4.5V  
PDRV Fall Time  
NDRV Rise Time  
PDRV Fall Time  
PDRV to NDRV Non-Overlap Time  
NDRV to PDRV Non-Overlap Time  
PIN DESCRIPTION  
PIN NO. PIN NAME DESCRIPTION  
1
VCC  
Positive input supply for the control circuitry and gate drivers. Properly bypass this pin  
to GND with a low ESL/ESR ceramic capacitor.  
2
3
GND  
VFB  
Ground pin. Both power and control circuitry of the IC is referenced to this pin.  
Feedback Voltage Pin. It is the inverting input of the Error Amplifier and serves as the  
output voltage feedback point for the buck converter. The output voltage is sensed and  
can be adjusted through an external resistor divider.  
4
COMP  
Output of the Error Amplifier. It is internally connected to the non-inverting input of the  
PWM comparator. A lead-lag network is typically connected to the COMP pin to  
compensate the feedback loop in order to optimize the dynamic performance of the  
voltage mode control loop. Sleep mode can be invoked by pulling the COMP pin below  
0.2V with an external open-drain or open-collector transistor. Supply current is reduced  
to 25µA (typical) in shutdown. An internal 5µA pull-up ensures start-up.  
5
ISENSE  
Current Limit Sense pin. Connect this pin to the switching node at the junction between  
the two external power MOSFET transistors. This pin monitors the voltage dropped  
across the RDS(ON) of the high side P-channel MOSFET while it is conducting. When  
this drop exceeds the sum of the voltage programmed through the ISET pin plus the  
internal 160mV threshold, the overcurrent comparator sets the fault latch and termi-  
nates the output pulses. The controller stops switching and goes through a hiccup  
sequence. This prevents excessive power dissipation in the external power MOSFETs  
during an overload condition. An internal delay circuit prevents that very short and mild  
overload conditions, that could occur during a load transient, activate the current limit  
circuit.  
6
ISET  
Current Limit Threshold pin. An external resistor connected between this pin and the  
source of the high side P-channel MOSFET adds to the internal current limit threshold  
of 160mV. If a current limit threshold in excess of 160mV is required, the external  
programming resistor can properly be chosen based on the internal 30µA pull down  
current available on the ISET pin. Both this 30µA current source and the 160mV built-in  
current limit threshold have a positive temperature coefficient to provide first order  
correction for the temperature coefficient of the external P-channel MOSFET’s RDS(ON)  
.
7
8
NDRV  
PDRV  
High current driver output for the low side MOSFET switch. It is always low if PDRV is  
low or during a fault.  
High current driver output for the high side MOSFET switch. It is always high if NDRV  
is high or during a fault.  
Date: 5/25/04  
SP6121 Low Voltage, Synchronous Step Down PWM Controller  
© Copyright 2004 Sipex Corporation  
3
FUNCTIONAL DIAGRAM  
1V  
-
DRIVER ENABLE  
SHUTDOWN  
+
1.25V  
Reference  
-
VCC  
300mV  
+
FAULT  
GM  
ERROR  
AMP  
5µA  
0.4V/ms  
SOFTSTART  
PWM COMP  
RESET  
+
-
8
7
PDRV  
PWM  
Logic  
Dominant  
-
Synchronous  
Driver  
S
+
NDRV  
GND  
Q
VFB  
COMP  
VCC  
3
4
R
2
1
UVLO  
750mV RAMP  
F = 500kHz  
-
2.79V ON  
2.69V OFF  
+
Reset  
Dominant  
COMP  
ISET  
S
6
FAULT  
PDRV  
Q
30µA  
(3300 ppm/°C)  
Over Current  
(Gated S&H)  
SHUTDOWN  
R
+
X 3.3  
+
ISENSE  
5
-
530mV  
(3300 ppm/°C)  
-
THEORY OF OPERATION  
General Overview  
The SP6121 is a constant frequency, voltage  
mode, synchronous PWM controller designed  
for low voltage, DC/DC step down converters.  
It is intended to provide complete control for a  
high power, high efficiency, precisely regulated  
output voltage from a highly integrated 8-pin  
solution.  
MOSFET switch allowing for significant effi-  
ciencyimprovements.TheSP6121includestwo  
fast MOSFET drivers with internal non-overlap  
circuitry and drives a complementary pair of  
power transistors, P-channel on the high side,  
and N-channel on the low side. The use of a P-  
channel high side device minimizes complexity  
and external component count by eliminating  
theneedforachargepumpthatwouldotherwise  
be required to fully enhance an N-channel de-  
vice. Italsoallows inherent100%dutycyclefor  
lowdropoutoperationintheeventofalowinput  
supply voltage condition.  
The internal free-running oscillator accurately  
sets the PWM frequency at 500kHz without  
requiring any external elements and allows the  
use of physically small, low value external com-  
ponents without compromising performance. A  
transconductance amplifier is used for the error  
amplifier,whichcomparesanattenuatedsample  
of the output voltage with a precision reference  
voltage. The output of the error amplifier  
(COMP), is compared to a 0.75V peak-to-peak  
ramp waveform to provide PWM control. The  
COMP pin provides access to the output of the  
error amplifier and allows the use of external  
components to stabilize the voltage loop.  
The SP6121 includes an internal 0.4V/ms soft-  
start circuit that provides controlled ramp up of  
the output voltage, preventing overshoot and  
inrush current at power up.  
Current limiting is implemented by monitoring  
the voltage drop across the RDS(ON) of the high  
side P-channel MOSFET while it is conducting,  
thereby eliminating the need for an external  
sense resistor. The over-current comparator has  
a built-in threshold of 160mV that can be pro-  
grammed to higher values using a single exter-  
nal resistor, connected to the ISET pin, whose  
High efficiency is obtained through the use of  
synchronous rectification. Synchronous regula-  
tors replace the catch diode in the standard buck  
converter with a low RDS(ON) N-channel  
Date: 5/25/04  
SP6121 Low Voltage, Synchronous Step Down PWM Controller  
© Copyright 2004 Sipex Corporation  
4
THEORY OF OPERATION: continued  
value is selected to match the MOSFET charac-  
teristics. When the over-current threshold is  
exceeded, the over-current comparator sets the  
fault latch and terminates the output pulses. The  
controller stops switching and goes through a  
hiccupsequence.Thispreventsexcessivepower  
dissipation in the external power MOSFETs  
during an overload condition. An internal delay  
circuit prevents that very short and mild over-  
load conditions, that could occur during a load  
transient, activate the current limit circuit.  
If no faults are present, the SP6121 will initiate  
a soft start when VCC exceeds 2.79V.  
Hysteresis (about 100mV) in the UVLO com-  
parator provides noise immunity at start-up.  
Soft Start  
Soft start is required on step-down controllers to  
prevent excess inrush current through the power  
train during start-up. Typically this is managed  
by sourcing a controlled current into a timing  
capacitor and then using the voltage across this  
capacitor to slowly ramp up either the error amp  
reference or the error amp output (COMP). The  
control loop creates narrow width driver pulses  
while the output voltage is low and allows these  
pulses to increase to their steady-state duty  
cycle as the output voltage increases to its regu-  
lated value. As a result of controlling the induc-  
tor volt*second product during startup, inrush  
current is also controlled.  
A low power sleep mode can be invoked in the  
SP6121 by externally forcing the COMP pin  
below 0.3V. Quiescent supply current in sleep  
mode is typically less than 25µA. An internal  
5µA pull-up current at the COMP pin brings the  
SP6121 out of shutdown mode.  
The SP6121 also includes under-voltage lock-  
out and over-voltage protection. Output over-  
voltage protection is achieved by turning off the  
high side switch, and turning on the low side N-  
channel MOSFET full time.  
In the SP6121 the duration of the soft-start is  
controlled by an internal timing circuit that  
provides a 0.4V/ms slew-rate, which is used  
during start-up and over-current to set the hic-  
cup time. The SP6121 implements soft-start by  
rampinguptheerroramplifierreferencevoltage  
providing a controlled slew-rate of the output  
voltage, thereby preventing overshoot and in-  
rush current at power up.  
Enable  
Low quiescent mode or “Sleep Mode” is initi-  
ated by pulling the COMP pin below 0.3V with  
an external open-drain or open-collector tran-  
sistor. Supply current is reduced to 25µA (typi-  
cal) in shutdown. On power-up, assuming that  
VCC has exceeded the UVLO start threshold  
(2.79V), an internal 5µA pull-up current at the  
COMP pin brings the SP6121 out of shutdown  
mode and ensures start-up. During normal oper-  
ating conditions and in absence of a fault, an  
internal clamp prevents the COMP pin from  
swinging below 0.6V. This guarantees that dur-  
ing mild transient conditions, due either to line  
or load variations, the SP6121 does not enter  
shutdown unless it is externally activated.  
The presence of the output capacitor creates  
extracurrentdrawduringstartup. Simplystated,  
dVOUT/dt requires an average sustained current  
in the output capacitor and this current must be  
considered while calculating peak inrush cur-  
rent and over current thresholds. An approxi-  
mate expression to determine the excess inrush  
current due to the dVOUT/dt of the output capaci-  
tor COUT is:  
VOUT  
ICOUT = COUT*(0.4 V/ms) *  
1.25  
During Sleep Mode, the high side and low side  
MOSFETs are turned off and the internal soft  
start voltage is held low.  
As Figure 1 shows, the SS voltage controls a  
variety of signals. First, provided all the exter-  
nal fault conditions are removed, an internal  
5µApull-upattheCOMPpinbringstheSP6121  
out of shutdown mode. The internal timing  
circuit is then activated and controls the ramp-  
up of the error amp reference voltage. The  
COMP pin is pulled to 0.7V by the internal  
UVLO  
Assuming that there is not shutdown condition  
present, then the voltage on the VCC pin deter-  
mines operation of the SP6121. As VCC rises,  
the UVLO block monitors VCC and keeps the  
high side and low side MOSFETS off and the  
internalSSvoltagelowuntilVCC reaches2.79V.  
Date: 5/25/04  
SP6121 Low Voltage, Synchronous Step Down PWM Controller  
© Copyright 2004 Sipex Corporation  
5
THEORY OF OPERATION: continued  
Hiccup Mode  
clamp and then gradually charges preventing  
the error amplifier from forcing the loop to  
maximum duty cycle. As the COMP voltage  
crosses about 1V (valley voltage of the PWM  
ramp), the driver begins to switch the high side  
MOSFET with narrow pulses in an effort to  
keeptheconverteroutputregulated.TheSP6121  
operates at low duty cycle as the COMP voltage  
increases above 1V. As the error amp reference  
ramps upward, the driver pulses widen until a  
steady state value is reached and the output  
voltage is regulated to the final value ending the  
soft start charge cycle.  
When the converter enters a fault mode, the  
SP6121 holds the high side and low side  
MOSFETs off for a finite period of time. Pro-  
vided that the SP6121 is enabled, this time is set  
by the internal charge of the SS capacitor. In the  
event of an over-current condition, the current  
sense comparator sets the fault latch, which in  
turn discharge the internal SS capacitor, the  
COMP pin and holds the output drivers off.  
During this condition, the SP6121 stays off for  
the time it takes to discharge the COMP pin  
down below the 0.3V shutdown threshold. As  
soon as the COMP pin reaches 0.3V, the fault  
latch is reset and the SP6121 is allowed to  
attemptrestartjustlikeduringanormalsoftstart  
cycle. The COMP pin has to charge back to 1V  
before any output switching can take place. At  
this point, the regulator attempts to restart nor-  
mally by delivering short gate pulses to the  
output switches. If the over-current condition  
persists, the regulator will be kept off for the  
total time that it takes to charge the internal soft-  
start capacitor to within 1V from the input  
supply voltage VCC plus the time required by the  
COMP voltage to cross the 1V threshold. This  
total time is typically several milli-seconds and  
minimizes thermal stress to the regulator com-  
ponents as the over-current condition persists.  
COMP  
1 V  
0.7 V  
0.3 V  
0 V  
Internal SS  
dVss/dt = 0.4V/ms  
Voltage  
Error Amp  
Reference  
Voltage  
V
OUT = V(REF) * (1+R1/R2)  
1.25V  
The waveforms that describe the hiccup mode  
operation are shown in Figure 2.  
0 V  
I(L)  
V
-V  
(ISET) (ISENSE)  
160 mV  
Inductor  
Current  
0 V  
0 A  
COMP  
Voltage  
V(VCC  
)
3 V  
FAULT  
1.0 V  
0 V  
0.3 V  
0 V  
V(VCC  
)
V
(VCC)  
SWN  
Voltage  
PDRV  
Voltage  
0 V  
0V  
TIME  
TIME  
Figure 1. SP6121 Soft Start Waveforms  
Figure 2. SP6121 Hiccup mode waveforms  
Date: 5/25/04  
SP6121 Low Voltage, Synchronous Step Down PWM Controller  
© Copyright 2004 Sipex Corporation  
6
THEORY OF OPERATION: continued  
Output Drivers  
Over Current Protection  
The SP6121, unlike some other bipolar control-  
ler IC’s, incorporates gate drivers with rail-to-  
rail swing that help prevent spurious turn on due  
to capacitive coupling. The driver stage consists  
of one high side PMOS, 4driver, PDRV, and  
one low side, 4, NFET driver, NDRV, opti-  
mized for driving external power MOSFET’s in  
a synchronous buck topology. The output driv-  
ers also provide gate drive non-overlap mecha-  
nism that provides a dead time between PDRV  
and NDRV transitions to avoid potential shoot-  
through problems in the external MOSFET’s.  
Over current protection on the SP6121 is imple-  
mented through detection of an excess voltage  
condition across the high side PMOS switch  
during conduction. This is typically referred to  
ashighsideRDS(ON) detectionandeliminatesthe  
need of an external sense resistor. The over  
current comparator charges an internal sam-  
pling capacitor each time V(ISET) - V(ISENSE)  
exceeds the 160mV (typ) internal threshold and  
the PDRV voltage is low. The discharge/charge  
current ratio on the sampling capacitor is about  
2%. Therefore, provided that the over current  
condition persists, the capacitor voltage will be  
pumped up during each time PDRV switches  
low. This voltage will trigger an over current  
conditionuponreachingaCMOSinverterthresh-  
old. There are many advantages to this ap-  
proach. First, the filtering action of the gated S/  
H scheme protects against false and undesirable  
triggering that could occur during a minor tran-  
sient overload condition or supply line noise.  
Furthermore, the total amount of time to trigger  
the fault depends on the on-time of the PMOS  
switch.Ten,1µspulsesareequivalenttotwenty,  
500ns pulses or one, 10µs pulse, however, de-  
pending on the period, each scenario takes a  
different amount of total time to trigger a fault.  
Therefore, the fault becomes an indicator of  
average power in the PMOS switch.  
Figure3showstypicalwaveformsfortheoutput  
drivers. As with all synchronous designs, care  
must be taken to ensure that the MOSFETs are  
properly chosen for non-overlap time, enhance-  
mentgatedrivevoltage,onresistanceRDS(ON)  
,
reverse transfer capacitance Crss, input voltage  
and maximum output current.  
GATE DRIVER TEST CONDITIONS  
5 V  
90 %  
Vcc-2 V  
PDRV(NDRV)  
FALL TIME  
NON-OVERLAP  
10 %  
5 V  
90 %  
RISE TIME  
NDRV(PDRV)  
2 V  
10 %  
Althoughthe160mVinternalthresholdisfixed,  
the overall RDS(ON) detection voltage can be  
increased by placing a resistor from ISET to the  
source of the PMOS. A 30µA sink current pro-  
grams the additional voltage.  
V(VCC  
)
PDRV  
Voltage  
In order for the current limit circuit to operate  
properly and accurately, the ISET and ISENSE pins  
must be Kelvin connected to the high side  
PMOS’s source and drain pins.  
0 V  
V(VCC  
)
NDRV  
Voltage  
The 160mV threshold and 30µA ISET current  
have 3300 ppm/°C temperature coefficients in  
an effort to first order match the thermal charac-  
teristics of the RDS(ON) of the PMOS switch. It  
assumed that the SP6121 will be used in com-  
pact designs where there is a high amount of  
thermal coupling between the PMOS and the  
controller.  
0 V  
V(VCC=VIN  
)
SWN  
Voltage  
~ 0 V  
- V(Diode) V  
TIME  
Figure 3. SP6121 Output Driver Waveforms.  
Date: 5/25/04  
SP6121 Low Voltage, Synchronous Step Down PWM Controller  
© Copyright 2004 Sipex Corporation  
7
APPLICATION INFORMATION  
Inductor Selection  
There are many factors to consider in selecting  
the inductor including cost, efficiency, size and  
EMI. In a typical SP6121 circuit, the inductor is  
chosen primarily for value, saturation current  
andDCresistance.Increasingtheinductorvalue  
will decrease output voltage ripple, but degrade  
transientresponse. Lowinductorvaluesprovide  
the smallest size, but cause large ripple currents,  
poor efficiency and more output capacitance to  
smooth out the larger ripple current. The induc-  
tor must also be able to handle the peak current  
at the switching frequency without saturating,  
and the copper resistance in the winding should  
be kept as low as possible to minimize resistive  
power loss. A good compromise between size,  
loss and cost is to set the inductor ripple current  
tobewithin20%to40%ofthemaximumoutput  
current.  
duce considerable ac core loss, especially when  
the inductor value is relatively low and the  
ripple current is high. Ferrite materials, on the  
other hand, are more expensive and have an  
abrupt saturation characteristic with the induc-  
tance dropping sharply when the peak design  
current is exceeded. Nevertheless, they are pre-  
ferred at high switching frequencies because  
they present very low core loss and the design  
only needs to prevent saturation.  
The power dissipated in the inductor is equal to  
the sum of the core and copper losses. To mini-  
mizecopperlosses,thewindingresistanceneeds  
to be minimized, but this usually comes at the  
expense of a larger inductor. Core losses have a  
more significant contribution at low output cur-  
rent where the copper losses are at a minimum,  
and can typically be neglected at higher output  
currentswherethecopperlossesdominate.Core  
loss information is usually available from the  
magnetic vendor.  
The switching frequency and the inductor oper-  
ating point determine the inductor value as fol-  
lows:  
Thecopperlossintheinductorcanbecalculated  
using the following equation:  
VOUT (VIN (max) VOUT  
)
L =  
VIN (max) FS Kr IOUT (max)  
PL(Cu) = IL2(RMS) RWINDING  
where;  
where IL(RMS) is the RMS inductor current that  
can be calculated as follows:  
FS = switching frequency  
Kr = ratio of the peak to peak inductor ripple  
current to the maximum output current  
2
1
3
IPP  
IOUT(max)  
IL(RMS) = IOUT(max) 1 +  
(
)
The peak to peak inductor ripple current is:  
VOUT (VIN (max) VOUT  
)
Output Capacitor Selection  
IPP  
=
The required ESR (Equivalent Series Resis-  
tance) and capacitance drive the selection of the  
type and quantity of the output capacitors. The  
ESR must be small enough that both the resis-  
tive voltage deviation due to a step change in the  
load current and the output ripple voltage do not  
exceed the tolerance limits expected on the  
output voltage. During an output load transient,  
the output capacitor must supply all the addi-  
tional current demanded by the load until the  
SP6121 adjusts the inductor current to the new  
value. Therefore the capacitance must be large  
enough so that the output voltage is held up  
VIN(max) FS L  
Once the required inductor value is selected, the  
proper selection of core material is based on  
peak inductor current and efficiency require-  
ments. The core material must be large enough  
not to saturate at the peak inductor current  
IPP  
IPEAK = IOUT (max)  
+
2
and provide low core loss at the high switching  
frequency. Low cost powdered iron cores have  
a gradual saturation characteristic but can intro-  
Date: 5/25/04  
SP6121 Low Voltage, Synchronous Step Down PWM Controller  
© Copyright 2004 Sipex Corporation  
8
APPLICATIONS INFORMATION: Continued  
while the inductor current ramps up or down to  
the value corresponding to the new load current.  
Additionally, the ESR in the output capacitor  
causes a step in the output voltage equal to the  
ESR value multiplied by the change in load  
current. Because of the fast transient response  
providedbytheSP6121whenexposedtooutput  
load transient, the output capacitor is typically  
chosen for ESR , not for capacitance value.  
Panasonic offers the SP series of specialty poly-  
mer aluminum electrolytic surface mount ca-  
pacitors. These capacitors have a lower ESR  
thantantalumcapacitors,reducingthetotalnum-  
ber of capacitance required for a given transient  
response.  
Input Capacitor Selection  
The input capacitor should be selected for ripple  
current rating, capacitance and voltage rating.  
The input capacitor must meet the ripple current  
requirement imposed by the switching current.  
In continuous conduction mode, the source cur-  
rent of the high-side MOSFET is approximately  
a square wave of duty cycle VOUT/ VIN. Most of  
this current is supplied by the input bypass  
capacitors. The RMS value of input capacitor  
current is determined at the maximum output  
current and under the assumption that the peak  
to peak inductor ripple current is low, it is given  
by:  
The output capacitor’s ESR, combined with the  
inductor ripple current, is typically the main  
contributor to output voltage ripple. The maxi-  
mum allowable ESR required to maintain a  
specifiedoutputvoltageripplecanbecalculated  
by:  
VOUT  
RESR  
IPP  
where;  
VOUT = peak to peak output voltage ripple  
IPP = peak to peak inductor ripple current  
ICIN(rms) = IOUT(max)  
D(1 - D)  
The worse case occurs when the duty cycle D is  
50% and gives an RMS current value equal to  
IOUT/2. Select input capacitors with adequate  
ripple current rating to ensure reliable opera-  
tion.  
The total output ripple is a combination of the  
ESR and the output capacitance value and can  
be calculated as follows:  
IPP (1 – D)  
2
VOUT  
=
2 + (IPPRESR  
)
The power dissipated in the input capacitor is:  
(
)
COUTFS  
P
= IC2IN (rms) RESR(CIN)  
CIN  
where;  
This can become a significant part of power  
losses in a converter and reduce the overall  
energy transfer efficiency.  
D = duty cycle equal to VOUT/VIN  
COUT = output capacitance value  
The input voltage ripple primarily depends on  
the input capacitor ESR and capacitance. Ignor-  
ing the inductor ripple current, the input voltage  
ripple can be determined by:  
Recommended capacitors that can be used ef-  
fectively in SP6121 applications are: low-ESR  
aluminum electrolytic capacitors, OS-CON ca-  
pacitors that provide a very high performance/  
size ratio for electrolytic capacitors and low-  
ESR tantalum capacitors. AVX TPS series and  
KemetT510surfacemountcapacitorsarepopu-  
lartantalumcapacitorsthatworkwellinSP6121  
applications. POSCAP from Sanyo is a solid  
electrolytic chip capacitor that has low ESR and  
high capacitance. For the same ESR value,  
POSCAP has lower profile compared with tan-  
talum capacitor.  
IOUT(MAX)VOUT(VIN - VOUT  
)
VIN = IOUT(MAX)RESR(CIN)  
+
2
FSCINVIN  
The capacitor type suitable for the output ca-  
pacitors can also be used for the input capaci-  
tors. However, exercise extra caution when tan-  
talum capacitors are considered. Tantalum ca-  
pacitorsareknownforcatastrophicfailurewhen  
exposed to surge current, and input capacitors  
are prone to such surge current when power  
Date: 5/25/04  
SP6121 Low Voltage, Synchronous Step Down PWM Controller  
© Copyright 2004 Sipex Corporation  
9
APPLICATIONS INFORMATION: Continued  
supplies are connected ‘live’ to low impedance  
powersources.Certaintantalumcapacitors,such  
as AVX TPS series, are surge tested. For ge-  
neric tantalum capacitors, use 2:1 voltage derat-  
ing to protect the input capacitors from surge  
fall-out.  
Switching losses need to be taken into account  
for high switching frequency, since they are  
directly proportional to switching frequency.  
The conduction losses associated with top and  
bottom MOSFETs are determined by  
P
CH(max) = RDS(ON) OUT(max)  
I
2D  
PCL(max) = RDS(ON) OUT(max)  
I
2(1 - D),  
MOSFET Selection  
The SP6121 drives a PMOS MOSFET on the  
high side and an NMOS MOSFET synchronous  
rectifier on the low side. Using a PMOS switch  
on the high side negates the need for an external  
charge pump and simplifies the application cir-  
cuit.  
where;  
PCH(max) = conduction losses of the high side  
MOSFET  
PCL(max) = conduction losses of the low side  
MOSFET  
RDS(ON) = drain to source on resistance.  
The losses associated with MOSFETs can be  
divided into conduction and switching losses.  
Conduction losses are related to the on resis-  
tance of MOSFETs, and increase with the load  
current. Switching losses occur on each on/off  
transition when the MOSFETs experience both  
high current and voltage. Since the bottom  
MOSFET switches current from/to a paralleled  
diode (either its own body diode or a Schottky  
diode), the voltage across the MOSFET is no  
more than 1V during switching transition. As a  
result, its switching losses are negligible. The  
switching losses are difficult to quantify due to  
allthevariablesaffectingturnon/offtime.How-  
ever, makingtheassumptionthattheturnonand  
turn off transition times are equal, the transition  
time can be approximated by:  
The total power losses of the top MOSFET are  
the sum of switching and conduction losses. For  
synchronous buck converters of efficiency over  
90%, allow no more than 4% power losses for  
high or low side MOSFETs. For input voltages  
of 3.3V and 5V, conduction losses often domi-  
nate switching losses. Therefore, lowering the  
RDS(ON) of the MOSFETs always improves  
efficiency even though it gives rise to higher  
switching losses due to increased CISS  
.
Total gate charge is the charge required to turn  
the MOSFETs on and off under the specified  
operating conditions (VGS and VDS). The gate  
charge is provided by the SP6121 gate drive  
circuitry. (At 500kHz switching frequency, the  
gate charge is the dominant source of power  
dissipationintheSP6121.)Atlowoutputlevels,  
this power dissipation is noticeable as a reduc-  
tion in efficiency. The average current required  
to drive the high side and low side MOSFETs is:  
CISSVIN  
tT =  
,
IG  
where;  
CISS is the PMOS’s input capacitance, or the  
sum of the gate-to-source capacitance, CGS, and  
the drain-to-gate capacitance, CGD. This param-  
etercanbedirectlyobtainedfromtheMOSFET’s  
data sheet IG is the gate drive current provided  
by the SP6121 (approximately 1A at VIN=5V)  
and VIN is the input supply voltage.  
IG(av) = QGHFS + QGLFS,  
where;  
QGH = gate charge of PMOS  
QGL = gate charge of NMOS  
Therefore an approximate expression for the  
switching losses associated with the high side  
MOSFET can be given as:  
Considering that the gate charge current comes  
from the input supply voltage VIN, the power  
dissipated in the SP6121 due to the gate drive is:  
PSH(max) = (VIN(max) + VF)IOUT(max)tTFS ,  
where;  
PGATE DRIVE = VINIG(av)  
RDS(ON) varies greatly with the gate driver volt-  
age.TheMOSFETvendorsoftenspecifyRDS(ON)  
on multiple gate to source voltages (VGS), as  
tT = the switching transition time  
VF = free wheeling diode drop  
Date: 5/25/04  
SP6121 Low Voltage, Synchronous Step Down PWM Controller  
© Copyright 2004 Sipex Corporation  
10  
APPLICATIONS INFORMATION: Continued  
Schottky diode alleviates this noise and addi-  
tionally improves efficiency thanks to its low  
forward voltage. The reverse voltage across the  
diode is equal to input voltage, and the diode  
must be able to handle the peak current equal to  
the maximum load current.  
well as provide typical curve of RDS(ON) versus  
VGS. For 5V input, use the RDS(ON) specified at  
4.5V VGS. At the time of this publication, ven-  
dors, such as Fairchild, Siliconix and Interna-  
tional Rectifier, have started to specify RDS(ON)  
atVGS lessthan3V. Thishasprovidednecessary  
data for designs in which these MOSFETs are  
driven with 3.3V and made it possible to use  
SP6121 in 3.3V only applications.  
The power dissipation of the Schottky diode is  
determined by  
P
DIODE = 2VFIOUTTNOLFS  
Thermal calculation must be conducted to en-  
sure the MOSFET can handle the maximum  
load current. The junction temperature of the  
MOSFET, determined as follows, must stay  
below the maximum rating.  
where;  
TNOL = non-overlap time between PDRV and  
NDRV.  
VF = forward voltage of the Schottky diode.  
PMOSFET (max)  
TJ(max) =TA(max)  
+
,
Rθ  
JA  
®®  
COMP  
where;  
TA(max) = maximum ambient temperature  
MOSFET(max) = maximum power dissipation of  
R1  
C2  
P
SP6121  
the MOSFET  
C1  
RθJA = junction to ambient thermal resistance.  
RθJA of the device depends greatly on the board  
layout, as well as device package. Significant  
thermal improvement can be achieved in the  
maximum power dissipation through the proper  
design of copper mounting pads on the circuit  
board. For example, in a SO-8 package, plac-  
ing two 0.04 square inches copper pad di-  
rectly under the package, without occupying  
additional board space, can increase the maxi-  
mum power from approximately 1 to 1.2W.  
For DPAK package, enlarging the tap mount-  
ing pad to 1 square inches reduces the RθJA  
from 96°C/W to 40°C/W.  
Figure 4. The RC network connected to the COMP pin  
provides a pole and a zero to control loop.  
Loop Compensation Design  
The goal of loop compensation is to manipulate  
loopfrequencyresponsesuchthatitsgaincrosses  
over 0db at a slope of -20db/dec. The SP6121  
has a trans-conductance error amplifier and re-  
quires the compensation network to be con-  
nected between the COMP pin and ground, as  
shown in Figure 4.  
Schottky Diode Selection  
When paralleled with the bottom MOSFET, an  
optional Schottky diode can improve efficiency  
and reduce noise. Without this Schottky diode,  
the body diode of the bottom MOSFET con-  
ducts the current during the non-overlap time  
when both MOSFETs are turned off. Unfortu-  
nately, the body diode has high forward voltage  
and reverse recovery problem. The reverse re-  
covery of the body diode causes additional  
switching noises when the diode turns off. The  
The first step of compensation design is to pick  
the loop crossover frequency. High crossover  
frequencyisdesirableforfasttransientresponse,  
but often jeopardize the system stability. Cross-  
over frequency should be higher than the ESR  
zero but less than 1/5 of the switching fre-  
quency. TheESRzeroiscontributedbytheESR  
Date: 5/25/04  
SP6121 Low Voltage, Synchronous Step Down PWM Controller  
© Copyright 2004 Sipex Corporation  
11  
APPLICATIONS INFORMATION: Continued  
Tofine-tunethecompensation, itisnecessaryto  
physically measure the frequency response us-  
ing a network analyzer.  
associated with the output capacitors and can be  
determined by  
1
fZ(ESR)  
=
2πCOUTRESR  
Gain  
Crossover frequency of 20kHz is a sound first  
try if low ESR tantalum capacitors or poscaps  
are used at the output. The next step is to calcu-  
late the complex conjugate poles contributed by  
the LC output filter,  
-20db/dec  
-40db/dec  
Loop  
1
-20db/dec  
fP(LC)  
=
f
2π√ LCOUT  
The open loop gain of the whole system can be  
divided into the gain of the error amplifier,  
PWM modulator, buck converter, and feedback  
resistor divider. In order to crossover at the  
selected frequency fco, the gain of the error  
amplifier has to compensate for the attenuation  
caused by the rest of the loop at this frequency.  
IntheRCnetworkshowninFigure4,theproduct  
of R1 and the error amplifier transconductance  
determinesthisgain. Therefore, R1canbedeter-  
mined from the following equation that takes  
into account the typical error amplifier  
transconductance, reference voltage and PWM  
ramp built into the SP6121.  
-20db/dec  
Error Amplifier  
-20db/dec  
f
Figure 5. Frequency response of a stable system and its  
error amplifier.  
Overcurrent Protection  
975VOUT fCO fZ(ESR)  
R1 =  
Over current protection on the SP6121 is imple-  
mented through detection of an excess voltage  
condition across the high side PMOS switch  
during conduction. This is typically referred to  
as high side RDS(ON) detection. By using the  
RDS(ON) of Q1 to measure the output current, the  
current limit circuit eliminates the sense resistor  
that would otherwise be required and the corre-  
sponding loss associated with it. This improves  
the overall efficiency and reduces the number of  
components in the power path benefiting size  
and cost. RDS(ON) sensing is by default inaccu-  
rate and is primarily meant to protect the power  
supply during a fault condition. The overcurrent  
trip point will vary from unit to unit as the  
RDS(ON) of Q1 varies. The SP6121 provides a  
built-in 160mV threshold between the ISET and  
ISENSE pins. If a current limit threshold in excess  
of 160mV is required, an external programming  
resistor, RSET can be added between ISET pin and  
VIN as shown in Figure 6.  
2
VIN fP(LC)  
In Figure 4, R1 and C1 provides a zero fZ1 which  
needs to be placed at or below fP(LC). If fZ1 is  
made equal to fP(LC) for convenience, the value  
of C1 can be calculated as  
1
C1 =  
2πfP(LC)R1  
The optional C2 generates a pole fP1 with R1 to  
cut down high frequency noise for reliable op-  
eration. This pole should be placed one decade  
higher than the crossover frequency to avoid  
erosion of phase margin. Therefore, the value of  
the C2 can be derived from  
1
C2 =  
20πfCOR1  
Figure 5 illustrates the overall loop frequency  
response and frequency of each pole and zero.  
Date: 5/25/04  
SP6121 Low Voltage, Synchronous Step Down PWM Controller  
© Copyright 2004 Sipex Corporation  
12  
APPLICATIONS INFORMATION: Continued  
boththe30µAsinkcurrentpresentattheISET pin  
and the 160mV built-in current limit threshold  
have been designed with a positive temperature  
coefficientof about0.33%/Ctoprovidefirstorder  
correction for current limit versus temperature.  
This compensation relies on the high amount of  
thermal coupling that typically exists between the  
high side switch Q1 and the SP6121 due to the  
compact size of the power supply. With this first  
order compensation, the current limit trip point  
doesnotneedtobesettoanincreasedlevelatroom  
temperature to guarantee a desired output current  
level at higher temperatures.  
VIN  
SP6121  
RSET  
PDRV  
CIN  
160mV  
ISET  
-
+
+
-
Q1  
Q2  
ISENSE  
30µA  
L1  
VOUT  
COUT  
NDRV  
Figure 6. Current Limit Setting  
ThevalueofRSET canbeproperlychosenbasedon  
thedesiredcurrentlimitpointIMAX andtheinternal  
30µA pull down current available on the ISET pin  
according to the following expression:  
Output Voltage Program  
As shown in Figure 7(A), the voltage divider  
connecting to the VFB pin programs the output  
voltage according to  
IMAXRDS(ON) - 160mV  
RSET  
=
ISET  
where,  
R1  
VOUT = 1.25 1 +  
(
)
R2  
ISET = 30µA (typ) sink current from the ISET pin.  
where 1.25V is the internal reference voltage.  
Kelvin-Sense connections should be made di-  
rectly at the drain and source of Q1.  
SelectR2intherangeof10kto100k, andR1can  
be calculated using  
TheRDS(ON) sensingschemeimplementedinthe  
SP6121 provides two additional features that  
enhance the performance of the overcurrent  
function. First, aninternalsampleandholdfilter  
connected after the main current-sense com-  
parator, prevents that noise spikes or very short  
and mild overload conditions, that could occur  
during a load transient, spuriously activate the  
current limit circuitry. This typically eliminates  
the need of using any external filtering that would  
be otherwise required. Additionally, since the  
RDS(ON) has a positive temperature coefficient,  
R2(VOUT - 1.25)  
R1 =  
1.25  
For output voltage less than 1.25V, a simple  
circuit shown in Figure 7(B) can be used in  
which VREF is an external voltage reference  
greater than 1.25V. For simplicity, use the same  
resistor value for R1 and R2, then R3 is deter-  
mined as follows,  
(VREF - 1.25)R1  
2.5V - VOUT  
R3 =  
VOUT > 1.25V  
VOUT < 1.25V  
VREF  
R3  
®®  
®®  
R1  
R2  
R1  
R2  
VFB  
VFB  
SP6121  
SP6121  
A
B
Figure 7(A) A voltage divider connected to the VFB pin programs the output voltage. (B) A simple circuit using one  
external voltage reference programs the output voltages less than 1.25V.  
Date: 5/25/04  
SP6121 Low Voltage, Synchronous Step Down PWM Controller  
© Copyright 2004 Sipex Corporation  
13  
LAYOUT GUIDELINE  
PCB layout plays a critical role in proper func-  
tionoftheconvertersandEMIcontrol. Inswitch  
mode power supplies, loops carrying high di/dt  
give rise to EMI and ground bounces. The goal  
of layout optimization is to identify these loops  
and minimize them. It is also crucial on how to  
connect the controller ground such that its op-  
eration is not affected by noise. The following  
guideline should be followed to ensure proper  
operation.  
4. TheVCC bypasscapacitorshouldberightnext  
to the VCC and GND pins.  
5. The trace connecting the feedback resistors to  
the output should be short, direct and far away  
from the switch node, and switching compo-  
nents.  
6. Minimize the trace between PDRV/NDRV  
and the gates of the MOSFETs to reduce the  
impedance driving the MOSFETs. This is espe-  
cially important for the bottom MOSFET that  
tends to turn on through its Miller capacitor  
when the switch node swings high.  
1. A ground plane is recommended for minimiz-  
ing noises, copper losses and maximizing heat  
dissipation.  
7. Minimize the loop composed of input capaci-  
tors, top/bottomMOSFETsandSchottkydiode.  
This loop carries high di/dt current. Also in-  
crease the trace width to reduce copper losses.  
2. Beginthelayoutbyplacingthepowercompo-  
nents first. Orient the power circuitry to achieve  
a clean power flow path. If possible make all the  
connections on one side of the PCB with wide,  
copper filled areas.  
8. Maximizethetracewidthoftheloopconnect-  
ing the inductor, output capacitors, Schottky  
diode and bottom MOSFET.  
3. Connect the ground of feedback divider and  
compensation components directly to the GND  
pin of the IC using a dedicated ground trace.  
Then connect this pin as close as possible to the  
ground of the output capacitor.  
9. ISET and ISENSE connections to Q1 for current  
limiting must be make using Kelvin connec-  
tions.  
Date: 5/25/04  
SP6121 Low Voltage, Synchronous Step Down PWM Controller  
© Copyright 2004 Sipex Corporation  
14  
PACKAGE: 8 PIN NSOIC  
D
e
E/2  
B
E1  
E1/2  
E
B
SEE VIEW C  
1
b
INDEX AREA  
(D/2 X E1/2)  
Ø1  
TOP VIEW  
L2  
Ø
Ø1  
Seating Plane  
L
L1  
VIEW C  
Gauge Plane  
A2  
A
Seating Plane  
A1  
SIDE VIEW  
8 Pin NSOIC  
(JEDEC MS-012,  
AA - VARIATION)  
DIMENSIONS  
in  
(mm)  
SYMBOL  
MIN NOM MAX  
1.75  
0.25  
1.65  
0.51  
A
1.35  
-
-
-
-
-
A1  
A2  
b
0.10  
1.25  
0.31  
b
c
0.17  
0.25  
D
E
E1  
e
4.90 BSC  
6.00 BSC  
3.90 BSC  
1.27 BSC  
c
L
-
0.40  
1.27  
L1  
L2  
Ø
1.04 REF  
0.25 BSC  
-
BASE METAL  
8º  
SECTION B-B  
WITH PLATING  
0º  
5º  
Ø1  
-
15º  
8 PIN NSOIC  
Date: 5/25/04  
SP6121 Low Voltage, Synchronous Step Down PWM Controller  
© Copyright 2004 Sipex Corporation  
15  
ORDERING INFORMATION  
Operating Temperature Range Package Type  
Part Number  
SP6121CN ............................................... 0˚C to +70˚C ........................................... 8-Pin nSOIC  
SP6121CN/TR ......................................... 0˚C to +70˚C .......................................... 8-Pin nSOIC  
Available in lead free packaging. To order add "-L" suffix to part number.  
Example: SP6121CN/TR = standard; SP6121CN-L/TR = lead free  
/TR = Tape and Reel  
Pack quantity is 2500 for NSOIC.  
Corporation  
ANALOGEXCELLENCE  
Sipex Corporation  
Headquarters and  
Sales Office  
233 South Hillview Drive  
Milpitas, CA 95035  
TEL: (408) 934-7500  
FAX: (408) 935-7600  
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the  
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.  
Date: 5/25/04  
SP6121 Low Voltage, Synchronous Step Down PWM Controller  
© Copyright 2004 Sipex Corporation  
16  

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SIPEX

SP6122

Low Voltage, Micro 8, PFET, Buck Controller Ideal for 1A to 5A, Small Footprint, DC-DC Power Converters
SIPEX

SP6122

Trans Voltage Suppressor Diode, 500W, 35.8V V(RWM), Bidirectional, 1 Element, Silicon, HERMETIC SEALED, GLASS, E, 2 PIN
MICROSEMI

SP6122A

Trans Voltage Suppressor Diode, 500W, 35.8V V(RWM), Bidirectional, 1 Element, Silicon, HERMETIC SEALED, GLASS, E, 2 PIN
MICROSEMI

SP6122ACU

Low Voltage, Micro 8, PFET, Buck Controller Ideal for 1A to 5A, Small Footprint, DC-DC Power Converters
SIPEX