STK11C88-NF45ITR [SIMTEK]
32Kx8 SoftStore nvSRAM; 32Kx8 SoftStore的nvSRAM
| 型号： | STK11C88-NF45ITR |
| 厂家： | 
SIMTEK CORPORATION |
| 描述： | 32Kx8 SoftStore nvSRAM |
| 文件： | 总14页 (文件大小：389K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STK11C88
32Kx8 SoftStore nvSRAM
FEATURES
DESCRIPTION
• 25, 45 ns Read Access & R/W Cycle Time
• Unlimited Read/Write Endurance
• Pin Compatible with Industry Standard SRAMs
• Software-initiated STORE and RECALL
• Automatic RECALL to SRAM on Power Up
• Unlimited RECALL Cycles
The Simtek STK11C88 is a 256Kb fast static RAM
with a non-volatile Quantum Trap storage element
included with each memory cell.
The SRAM provides the fast access & cycle times,
ease of use and unlimited read & write endurance of
a normal SRAM.
• 1 Million Store Cycles
Data transfers under software control to the non-vol-
atile storage cell (the STORE operation). On power
up, data is automatically restored to the SRAM (the
RECALL operation). RECALL operations are also
available under software control.
• 100-Year Non-volatile Data Retention
• Single 5V ± 10% Power Supply
• Commercial and Industrial Temperatures
• 28-pin 300-mil and 330-mil SOIC Packages
(RoHS-Compliant)
The Simtek nvSRAM is the first monolithic non-
volatile memory to offer unlimited writes and reads.
It is the highest performance, most reliable non-
volatile memory available.
BLOCK DIAGRAM
QUANTUM TRAP
512 x 512
STORE/
RECALL
CONTROL
A5
A6
A7
A8
STORE
STATIC RAM
ARRAY
512 X 512
RECALL
A9
A11
A12
A13
A14
SOFTWARE
DETECT
A13 – A0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10
G
E
W
This product conforms to specifications per the
terms of Simtek standard warranty. The product
has completed Simtek internal qualification testing
and has reached production status.
Rev 0.3
Document Control #ML0012
February 2007
1
STK11C88
PIN CONFIGURATIONS
A14
28
27
26
25
24
23
22
21
20
19
18
1
2
3
4
VCC
A12
A7
A6
A5
A4
A3
W
A13
A8
5
6
7
8
A9
A11
G
A10
E
A2
A1
9
10
11
12
DQ7
DQ6
DQ5
DQ4
DQ3
A0
DQ0
DQ1
DQ2
VSS
17
16
15
13
14
28 - Pin 300 mil SOIC
28 - Pin 330 mil SOIC
PIN DESCRIPTIONS
Pin Name
-A
I/O
Description
A
Input
I/O
Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
14
0
DQ -DQ
7
0
E
Input
Input
W
Write Enable: The active low W enables data on the DQ pins to be written to the address
location latched by the falling edge of E
G
Input
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
V
V
Power Supply
Power Supply
Power: 5.0V, ±10%
Ground
CC
SS
Rev 0.3
Document Control #ML0012
February 2007
2
STK11C88
a
ABSOLUTE MAXIMUM RATINGS
Voltage on Input Relative to Ground. . . . . . . . . . . . . .–0.5V to 7.0V
Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V)
Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration). . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at condi-
tions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
DC CHARACTERISTICS
(V = 5.0V 10%)
CC
COMMERCIAL
INDUSTRIAL
SYMBOL
PARAMETER
Average V Current
UNITS
NOTES
MIN
MAX
MIN
MAX
b
I
97
70
100
70
mA
mA
t
t
= 25ns
= 45ns
CC
CC
AVAV
AVAV
1
c
I
I
Average V Current during STORE
3
3
mA
mA
All Inputs Don’t Care, V = max
CC
CC
CC
CC
2
3
b
Average V Current at t
CC
= 200ns
W ≥ (V – 0.2V)
AVAV
CC
10
10
5V, 25°C, Typical
All Others Cycling, CMOS Levels
d
d
I
I
I
I
Average V Current
CC
(Standby, Cycling TTL Input Levels)
30
22
31
23
mA
mA
t
t
= 25ns, E ≥ V
IH
SB
SB
AVAV
AVAV
1
2
= 45ns, E ≥ V
IH
V
Standby Current
E ≥ (V - 0.2V)
CC
All Others V ≤ 0.2V or ≥ (V – 0.2V)
CC
750
1
750
1
μA
μA
μA
(Standby, Stable CMOS Input Levels)
IN CC
Input Leakage Current
V
V
= max
CC
ILK
= V to V
CC
IN
SS
Off-State Output Leakage Current
V
V
= max
CC
OLK
5
5
= V to V , E or G ≥ V
IN
SS
CC
IH
V
V
V
V
T
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
2.2
V
+ .5
2.2
V + .5
CC
V
V
All Inputs
All Inputs
IH
CC
V
– .5
0.8
V – .5
SS
0.8
IL
SS
2.4
2.4
V
I
I
=– 4mA
= 8mA
OH
OL
OUT
OUT
0.4
70
0.4
85
V
0
–40
°C
A
Note b: ICC and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: ICC1 is the average current required for the duration of the STORE cycle (tSTORE ).
Note d: E ≥2VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1
5.0V
e
CAPACITANCE
(T = 25°C, f = 1.0MHz)
A
480 Ohms
SYMBOL
PARAMETER
Input Capacitance
Output Capacitance
MAX
UNITS
CONDITIONS
ΔV = 0 to 3V
ΔV = 0 to 3V
C
5
7
pF
IN
OUTPUT
30 pF
C
pF
OUT
INCLUDING
SCOPE AND
FIXTURE
255 Ohms
Note e: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
Rev 0.3
Document Control #ML0012
February 2007
3
STK11C88
SRAM READ CYCLES #1 & #2
(V = 5.0V + 10%)
CC
SYMBOLS
NO.
STK11C88-25 STK11C88-45
UNITS
PARAMETER
#1, #2
Alt.
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
Read Cycle Time
25
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
f
25
45
AVAV
RC
AA
g
3
Address Access Time
Output Enable to Data Valid
25
10
45
20
AVQV
4
GLQV
OE
OH
LZ
g
5
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
5
5
5
5
AXQX
6
ELQX
h
7
10
10
25
15
15
45
EHQZ
HZ
8
0
0
0
0
GLQX
OLZ
OHZ
PA
h
9
GHQZ
e
10
11
ELICCH
EHICCL
d, e
PS
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g: I/O state assumes E, G < VIL and W > VIH; device is continuously selected.
Note h: Measured 200mV from steady state output voltage.
f, g
SRAM READ CYCLE #1: Address Controlled
2
t
AVAV
ADDRESS
3
t
AVQV
5
t
AXQX
DQ (DATA OUT)
DATA VALID
f
SRAM READ CYCLE #2: E Controlled
2
t
AVAV
ADDRESS
E
1
11
EHICCL
t
ELQV
t
6
t
ELQX
7
t
EHQZ
G
9
t
4
GHQZ
t
GLQV
8
t
GLQX
DQ (DATA OUT)
DATA VALID
10
ELICCH
t
ACTIVE
STANDBY
I
CC
Rev 0.3
Document Control #ML0012
February 2007
4
STK11C88
SRAM WRITE CYCLES #1 & #2
(V = 5.0V + 10%)
CC
SYMBOLS
NO.
STK11C88-25
STK11C88-45
PARAMETER
UNITS
#1
#2
Alt.
MIN
25
20
20
10
0
MAX
MIN
45
30
30
15
0
MAX
12
13
14
15
16
17
18
19
20
21
t
t
t
WC
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
t
t
t
Write Pulse Width
WLWH
WLEH
WP
CW
DW
t
t
t
t
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
ELWH
DVWH
WHDX
ELEH
DVEH
EHDX
t
t
t
t
t
DH
t
t
t
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
20
0
30
0
AVWH
AVEH
AW
t
t
t
AS
AVWL
AVEL
t
t
t
0
0
WHAX
h, i
EHAX
WR
t
t
10
15
WLQZ
WZ
t
t
5
5
WHQX
OW
Note i: If W is low when E goes low, the outputs remain in the high-impedance state.
Note j: E or W must be ≥ VIH during address transitions.
j
SRAM WRITE CYCLE #1: W Controlled
12
AVAV
t
ADDRESS
19
WHAX
14
ELWH
t
t
E
17
AVWH
t
18
AVWL
t
13
WLWH
t
W
15
DVWH
16
WHDX
t
t
DATA IN
DATA VALID
20
WLQZ
t
21
WHQX
t
HIGH IMPEDANCE
DATA OUT
PREVIOUS DATA
j
SRAM WRITE CYCLE #2: E Controlled
12
AVAV
t
ADDRESS
14
ELEH
18
AVEL
19
EHAX
t
t
t
E
17
AVEH
t
13
WLEH
t
W
15
DVEH
16
EHDX
t
t
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
Rev 0.3
Document Control #ML0012
February 2007
5
STK11C88
STORE INHIBIT/POWER-UP RECALL
(V = 5.0V + 10%)
CC
SYMBOLS
STK11C88
NO.
PARAMETER
UNITS NOTES
Standard
MIN
MAX
550
10
22
23
24
25
t
t
Power-up RECALL Duration
STORE Cycle Duration
μs
ms
V
k
RESTORE
STORE
g
V
V
Low Voltage Trigger Level
Low Voltage Reset Level
4.0
4.5
SWITCH
RESET
3.6
V
Note k: tRESTORE starts from the time VCC rises above VSWITCH
.
STORE INHIBIT/POWER-UP RECALL
V
CC
5V
24
V
SWITCH
25
RESET
V
STORE INHIBIT
POWER-UP RECALL
22
RESTORE
t
DQ (DATA OUT)
POWER-UP
BROWN OUT
BROWN OUT
BROWN OUT
RECALL
STORE INHIBIT
STORE INHIBIT
STORE INHIBIT
NO RECALL
NO RECALL
RECALL WHEN
(V DID NOT GO
(V DID NOT GO
V
RETURNS
CC
CC
CC
BELOW V
)
BELOW V
)
ABOVE V
SWITCH
RESET
RESET
Rev 0.3
Document Control #ML0012
February 2007
6
STK11C88
SOFTWARE STORE/RECALL MODE SELECTION
E
W
A
- A (hex)
MODE
I/O
NOTES
13
0
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
L
H
m, n
Nonvolatile STORE
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
L
H
m, n
Nonvolatile RECALL
Note l: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
Note m: While there are 15 addresses on the STK11C88, only the lower 14 are used to control software modes.
n, o
SOFTWARE STORE/RECALL CYCLE
(V = 5.0V 10%)
CC
STK11C88-25
STK11C88-45
UNITS
NO.
SYMBOLS
PARAMETER
MIN
25
0
MAX
MIN
45
0
MAX
26
27
28
29
30
t
t
t
t
t
STORE/RECALL Initiation Cycle Time
ns
ns
ns
ns
μs
AVAV
n
n
Address Set-up Time
Clock Pulse Width
Address Hold Time
RECALL Duration
AVEL
20
20
30
20
ELEH
n
ELAX
n
20
20
RECALL
Note n: The software sequence is clocked with E controlled reads.
Note o: The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0E38, 31C7, 03E0, 3C1F,
303F, 0FC0) for a STORE cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a RECALL cycle. W must be high during all six consecutive
cycles.
o
SOFTWARE STORE/RECALL CYCLE: E Controlled
26
AVAV
26
t
AVAV
t
ADDRESS #1
ADDRESS #6
ADDRESS
27
AVEL
28
t
ELEH
t
E
29
ELAX
t
23
30
RECALL
t
STORE / t
HIGH IMPEDANCE
DATA VALID
DATA VALID
DQ (DATA
Rev 0.3
Document Control #ML0012
February 2007
7
STK11C88
nvSRAM OPERATION
The STK11C88 is a versatile memory chip that pro-
SOFTWARE NONVOLATILE STORE
vides several modes of operation. The STK11C88
operates like a standard 32K x 8 SRAM. A 32K x 8
array of non-volatile storage elements shadow the
SRAM. SRAM data can be copied to non-volatile
memory or non-volatile data can be recalled to the
SRAM.
The STK11C88 software STORE cycle is initiated by
executing sequential READ cycles from six specific
address locations. During the STORE cycle an erase
of the previous nonvolatile data is first performed,
followed by a program of the nonvolatile elements.
The program operation copies the SRAM data into
nonvolatile memory. Once a STORE cycle is initi-
ated, further input and output are disabled until the
cycle is completed.
NOISE CONSIDERATIONS
Note that the STK11C88 is a high-speed memory
and so must have a high-frequency bypass capaci-
Because a sequence of READs from specific
addresses is used for STORE initiation, it is impor-
tant that no other READ or WRITE accesses inter-
vene in the sequence or the sequence will be
aborted and no STORE or RECALL will take place.
tor of approximately 0.1μF connected between V
cc
and V , using leads and traces that are as short as
ss
possible. As with all high-speed CMOS ICs, normal
careful routing of power, ground and signals will help
prevent noise problems.
To initiate the software STORE cycle, the following
READ sequence must be performed:
SRAM READ
The STK11C88 performs a READ cycle whenever E
and G are low and W is high. The address specified
on pins A0-14 determines which of the 32,768 data
bytes will be accessed. When the READ is initiated
by an address transition, the outputs will be valid
after a delay of tAVQV (READ cycle #1). If the READ is
initiated by E or G, the outputs will be valid at tELQV or
at tGLQV, whichever is later (READ cycle #2). The data
outputs will repeatedly respond to address changes
within the tAVQV access time without the need for tran-
sitions on any control input pins, and will remain valid
until another address change or until E or G is
brought high.
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0FC0 (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
The software sequence must be clocked with E con-
trolled READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ cycles
and not WRITE cycles be used in the sequence,
although it is not necessary that G be low for the
sequence to be valid. After the tSTORE cycle time has
been fulfilled, the SRAM will again be activated for
READ and WRITE operation.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ0-7 will be writ-
ten into the memory if it is valid tDVWH before the end
of a W controlled WRITE or tDVEH before the end of an
E controlled WRITE.
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a sequence
of READ operations in a manner similar to the soft-
ware STORE initiation. To initiate the RECALL cycle,
the following sequence of READ operations must be
performed:
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
the common I/O lines. If G is left low, internal cir-
cuitry will turn off the output buffers tWLQZ after W
goes low.
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0C63 (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL cycle
Rev 0.3
Document Control #ML0012
February 2007
8
STK11C88
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the nonvola-
tile information is transferred into the SRAM cells.
After the tRECALL cycle time the SRAM will once again
be ready for READ and WRITE operations. The
RECALL operation in no way alters the data in the
Nonvolatile Elements. The nonvolatile data can be
recalled an unlimited number of times.
HARDWARE PROTECT
The STK11C88 offers hardware protection against
inadvertent STORE operation during low-voltage
conditions. When VCC < VSWITCH, all software STORE
operations are inhibited.
LOW AVERAGE ACTIVE POWER
The STK11C88 draws significantly less current
when it is cycled at times longer than 50ns. Figure 2
shows the relationship between ICC and READ cycle
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial tem-
perature range, VCC = 5.5V, 100% duty cycle on chip
enable). Figure 3 shows the same relationship for
WRITE cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK11C88 depends on the following items:
1) CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of READs to WRITEs; 5) the operating
POWER-UP RECALL
During power up, or after any low-power condition
(VCC < VRESET), an internal RECALL request will be
latched. When VCC once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
If the STK11C88 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
VCC or between E and system VCC.
temperature; 6) the V level; and 7) I/O loading.
cc
100
80
60
40
20
0
100
80
60
TTL
CMOS
40
TTL
20
CMOS
0
50
100
150
200
50
100
150
200
Cycle Time (ns)
Cycle Time (ns)
Figure 2: ICC (max) Reads
Figure 3: ICC (max) Writes
Rev 0.3
Document Control #ML0012
February 2007
9
STK11C88
ORDERING INFORMATION
STK11C88 - N F 25 I TR
Packaging Option
Blank = Tube
TR = Tape and Reel
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (–40 to 85°C)
Access Time
25 = 25ns
45 = 45ns
Lead Finish (Lead-Free Only)
F = 100% Sn (Matte Tin)
Package
S=Plastic 28-pin 330 mil SOIC
N=Plastic 28-pin 300 mil SOIC
Rev 0.3
Document Control #ML0012
February 2007
10
STK11C88
Ordering Codes
Part Number
STK11C88-SF25
Description
Temperature
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Industrial
5V 32Kx8 SoftStore nvSRAM SOP28-330
5V 32Kx8 SoftStore nvSRAM SOP28-330
5V 32Kx8 SoftStore nvSRAM SOP28-300
5V 32Kx8 SoftStore nvSRAM SOP28-300
5V 32Kx8 SoftStore nvSRAM SOP28-330
5V 32Kx8 SoftStore nvSRAM SOP28-330
5V 32Kx8 SoftStore nvSRAM SOP28-300
5V 32Kx8 SoftStore nvSRAM SOP28-300
5V 32Kx8 SoftStore nvSRAM SOP28-330
5V 32Kx8 SoftStore nvSRAM SOP28-330
5V 32Kx8 SoftStore nvSRAM SOP28-300
5V 32Kx8 SoftStore nvSRAM SOP28-300
5V 32Kx8 SoftStore nvSRAM SOP28-330
5V 32Kx8 SoftStore nvSRAM SOP28-330
5V 32Kx8 SoftStore nvSRAM SOP28-300
5V 32Kx8 SoftStore nvSRAM SOP28-300
STK11C88-SF45
STK11C88-NF25
STK11C88-NF45
STK11C88-SF25TR
STK11C88-SF45TR
STK11C88-NF25TR
STK11C88-NF45TR
STK11C88-SF25I
STK11C88-SF45I
STK11C88-NF25I
STK11C88-NF45I
STK11C88-SF25ITR
STK11C88-SF45ITR
STK11C88-NF25ITR
STK11C88-NF45ITR
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Rev 0.3
Document Control #ML0012
February 2007
11
STK11C88
Package Drawings
28 - Pin 300 mil SOIC
0.292 7.42
0.300 7.59
(
)
0.400 10.16
( )
0.410 10.41
Pin 1
Index
.050 (1.27)
BSC
0.701 17.81
0.711 18.06
(
)
0.097 2.46
( )
0.104 2.64
0.090 2.29
0.094 2.39
)
(
0.005 0.12
0.012 0.29
(
)
0.014 0.35
0.019 0.48
)
(
MIN
MAX
DIM = INCHES
0°
8°
0.009 0.23
( )
0.013 0.32
MIN
MAX
DIM = mm
)
(
0.024 0.61
(
)
Rev 0.3
Document Control #ML0012
February 2007
12
STK11C88
28 - Pin 330 mil SOIC
0.713
18.11
18.62
(
)
0.733
0.112
0.004
(2.845)
(0.102)
0.020
0.014
0.508
0.356
0.050 (1.270)
(
)
0.103
0.093
2.616
2.362
(
)
0.336
0.326
8.534
8.280
0.477
12.116
11.506
(
)
(
)
0.453
Pin 1
10°
0°
0.014
0.008
0.356
0.203
(
)
0.044
1.117
(
)
0.028
0.711
MIN
MAX
DIM = INCHES
DIM = mm
MIN
( MAX )
Rev 0.3
Document Control #ML0012
February 2007
13
STK11C88
Document Revision History
Revision
0.0
Date
December 2002
September 2003
March 2006
Summary
Removed 20 nsec device
0.1
Added lead free lead finish
0.2
Removed 35ns device, Removed Leaded Lead Finish, Removed DIP packages.
February 2007
Add fast power-down slew rate information
Add Tape & Reel Ordering Options
Add Product Ordering Code Listing
Add Package Outline Drawings
Reformat Entire Document
0.3
SIMTEK STK11C88 Datasheet, February 2007
Copyright 2007, Simtek Corporation. All rights reserved.
This datasheet may only be printed for the expressed use of Simtek Customers. No part of the datasheet may be reproduced in any other
form or means without the express written permission from Simtek Corporation. The information contained in this publication is believed to be
accurate, but changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any warranty, including
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its use. Nothing herein consti-
tutes a license, grant or transfer of any rights to any Simtek patent, copyright, trademark, or other proprietary right.
Rev 0.3
Document Control #ML0012
February 2007
14
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