EFR32FG14P232F256GM48-B [SILICON]

EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet;
EFR32FG14P232F256GM48-B
型号: EFR32FG14P232F256GM48-B
厂家: SILICON    SILICON
描述:

EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet

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中文:  中文翻译
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EFR32FG14 Flex Gecko Proprietary  
Protocol SoC Family Data Sheet  
The Flex Gecko proprietary protocol family of SoCs is part of the  
KEY FEATURES  
Wireless Gecko portfolio. Flex Gecko SoCs are ideal for enabling  
energy-friendly proprietary protocol networking for IoT devices.  
• 32-bit ARM® Cortex®-M4 core with 40  
MHz maximum operating frequency  
The single-die solution provides industry-leading energy efficiency, ultra-fast wakeup  
times, a scalable power amplifier, an integrated balun and no-compromise MCU fea-  
tures.  
• Up to 256 kB of flash and 32 kB of RAM  
• Pin-compatible across EFR32FG families  
(exceptions apply for 5V-tolerant pins)  
• 12-channel Peripheral Reflex System  
enabling autonomous interaction of MCU  
peripherals  
Flex Gecko applications include:  
• Home and Building Automation and Security  
• Metering  
• Autonomous Hardware Crypto Accelerator  
• Integrated PA with up to 19 dBm (2.4  
GHz) or 20 dBm (Sub-GHz) tx power  
• Electronic Shelf Labels  
• Industrial Automation  
• Integrated balun for 2.4 GHz  
• Commercial and Retail Lighting and Sensing  
• Robust peripheral set and up to 32 GPIO  
Core / Memory  
Clock Management  
Energy Management  
Other  
H-F Crystal  
Oscillator  
H-F  
RC Oscillator  
Voltage  
Voltage Monitor  
Regulator  
CRYPTO  
ARM CortexTM M4 processor  
with DSP extensions, FPU and MPU  
Flash Program  
Memory  
Auxiliary H-F RC  
Oscillator  
L-F  
DC-DC  
Power-On Reset  
Converter  
CRC  
SMU  
RC Oscillator  
L-F Crystal  
Oscillator  
Ultra L-F RC  
Oscillator  
Brown-Out  
Detector  
Debug Interface  
RAM Memory  
LDMA Controller  
32-bit bus  
Peripheral Reflex System  
Radio Transceiver  
Serial  
I/O Ports  
Timers and Triggers  
Analog I/F  
Interfaces  
RFSENSE  
Sub GHz  
DEMOD  
IFADC  
AGC  
I
External  
Interrupts  
ADC  
USART  
Timer/Counter  
Protocol Timer  
LNA  
RF Frontend  
PGA  
Analog  
Comparator  
PA  
Low Energy  
UARTTM  
General  
Purpose I/O  
Low Energy  
Timer  
Low Energy  
Sensor Interface  
Q
To Sub GHz  
receive I/Q  
mixers and PA  
IDAC  
RFSENSE  
BALUN  
I2C  
Pin Reset  
Pulse Counter  
Watchdog Timer  
Cryotimer  
2.4 GHz  
LNA  
I
VDAC  
Frequency  
Synthesizer  
MOD  
Real Time  
Counter and  
Calendar  
RF Frontend  
Pin Wakeup  
Op-Amp  
PA  
To 2.4 GHz receive  
I/Q mixers and PA  
To Sub GHz  
and 2.4 GHz PA  
Q
Lowest power mode with peripheral operational:  
EM0—Active EM1—Sleep  
EM2—Deep Sleep  
EM3—Stop  
EM4—Hibernate  
EM4—Shutoff  
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Rev. 1.2  
EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Feature List  
1. Feature List  
The EFR32FG14 highlighted features are listed below.  
Low Power Wireless System-on-Chip  
Wide selection of MCU peripherals  
• 12-bit 1 Msps SAR Analog to Digital Converter (ADC)  
• 2 × Analog Comparator (ACMP)  
High Performance 32-bit 40 MHz ARM Cortex®-M4 with  
DSP instruction and floating-point unit for efficient signal  
processing  
• 2 × Digital to Analog Converter (VDAC)  
• 2 × Operational Amplifier (Opamp)  
• Up to 256 kB flash program memory  
• Up to 32 kB RAM data memory  
• Digital to Analog Current Converter (IDAC)  
• Low-Energy Sensor Interface (LESENSE)  
• 2.4 GHz and Sub-GHz radio operation  
• Transmit power:  
• Up to 32 pins connected to analog channels (APORT)  
shared between analog peripherals  
• 2.4 GHz radio: Up to 19 dBm  
• Sub-GHz radio: Up to 20 dBm  
• Up to 32 General Purpose I/O pins with output state reten-  
tion and asynchronous interrupts  
Low Energy Consumption  
• 8 Channel DMA Controller  
• 8.4 mA RX current at 38.4 kbps, GFSK, 169 MHz  
• 8.8 mA RX current at 1 Mbps, GFSK, 2.4 GHz  
• 10.2 mA RX current at 250 kbps, DSSS-OQPSK, 2.4 GHz  
• 8.5 mA TX current at 0 dBm output power at 2.4 GHz  
• 35.3 mA TX current at 14 dBm output power at 868 MHz  
• 67 μA/MHz in Active Mode (EM0)  
• 12 Channel Peripheral Reflex System (PRS)  
• 2 × 16-bit Timer/Counter  
• 3 or 4 Compare/Capture/PWM channels  
• 1 × 32-bit Timer/Counter  
• 3 Compare/Capture/PWM channels  
• 32-bit Real Time Counter and Calendar  
• 16-bit Low Energy Timer for waveform generation  
• 1.3 μA EM2 DeepSleep current (16 kB RAM retention and  
RTCC running from LFRCO)  
• Wake on Radio with signal strength detection, preamble  
pattern detection, frame detection and timeout  
• 32-bit Ultra Low Energy Timer/Counter for periodic wake-up  
from any Energy Mode  
High Receiver Performance  
• 16-bit Pulse Counter with asynchronous operation  
• 2 × Watchdog Timer with dedicated RC oscillator  
• 2 × Universal Synchronous/Asynchronous Receiver/Trans-  
mitter (UART/SPI/SmartCard (ISO 7816)/IrDA/I2S)  
• -93.8 dBm sensitivity at 1 Mbit/s GFSK, 2.4 GHz  
• -103.3 dBm sensitivity at 250 kbps DSSS-OQPSK, 2.4 GHz  
• -126.2 dBm sensitivity at 600 bps, GFSK, 915 MHz  
• -120.6 dBm sensitivity at 2.4 kbps, GFSK, 868 MHz  
• -109.9 dBm sensitivity at 4.8 kbps, OOK, 433 MHz  
• -112.2 dBm sensitivity at 38.4 kbps, GFSK, 169 MHz  
Supported Modulation Formats  
• 2/4 (G)FSK with fully configurable shaping  
• BPSK / DBPSK TX  
Low Energy UART (LEUART)  
I2C interface with SMBus support and address recognition  
in EM3 Stop  
Wide Operating Range  
• 1.8 V to 3.8 V single power supply  
• Integrated DC-DC, down to 1.8 V output with up to 200 mA  
load current for system  
• OOK / ASK  
• Standard (-40 °C to 85 °C) and Extended (-40 °C to 125 °C)  
temperature grades available  
• Shaped OQPSK / (G)MSK  
• Configurable DSSS and FEC  
Support for Internet Security  
• General Purpose CRC  
Supported Protocols  
• Proprietary Protocols  
• Random Number Generator  
• Wireless M-Bus  
• Hardware Cryptographic Acceleration for AES 128/256,  
SHA-1, SHA-2 (SHA-224 and SHA-256) and ECC  
• Selected IEEE 802.15.4g SUN-FSK PHYs  
• Low Power Wide Area Networks  
QFN32 5x5 mm Package  
QFN48 7x7 mm Package  
Suitable for Systems Targeting Compliance With:  
• FCC Part 90.210 Mask D, FCC part 15.247, 15.231, 15.249  
• ETSI Category I Operation, EN 300 220, EN 300 328  
• ARIB T-108, T-96  
• China regulatory  
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Rev. 1.2 | 2  
EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Ordering Information  
2. Ordering Information  
Table 2.1. Ordering Information  
Frequency Band  
@ Max TX Power  
2.4 GHz @ 19 dBm  
Protocol  
Stack  
Flash RAM  
Ordering Code  
(kB)  
(kB)  
GPIO Package Temp Range  
EFR32FG14P233F256GM48-B  
Proprietary  
256  
32  
28  
QFN48  
-40 to +85°C  
• Sub-GHz @ 20 dBm  
EFR32FG14P233F128GM48-B  
Proprietary  
2.4 GHz @ 19 dBm  
128  
16  
28  
QFN48  
-40 to +85°C  
• Sub-GHz @ 20 dBm  
EFR32FG14P232F256GM48-B  
EFR32FG14P232F128GM48-B  
EFR32FG14P232F256GM32-B  
EFR32FG14P232F128GM32-B  
EFR32FG14P231F256GM48-B  
EFR32FG14P231F256IM48-B  
EFR32FG14P231F128GM48-B  
EFR32FG14P231F256GM32-B  
EFR32FG14P231F256IM32-B  
EFR32FG14P231F128GM32-B  
Proprietary  
Proprietary  
Proprietary  
Proprietary  
Proprietary  
Proprietary  
Proprietary  
Proprietary  
Proprietary  
Proprietary  
2.4 GHz @ 19 dBm  
2.4 GHz @ 19 dBm  
2.4 GHz @ 19 dBm  
2.4 GHz @ 19 dBm  
Sub-GHz @ 20 dBm  
Sub-GHz @ 20 dBm  
Sub-GHz @ 20 dBm  
Sub-GHz @ 20 dBm  
Sub-GHz @ 20 dBm  
Sub-GHz @ 20 dBm  
256  
128  
256  
128  
256  
256  
128  
256  
256  
128  
32  
16  
32  
16  
32  
32  
16  
32  
32  
16  
31  
31  
16  
16  
32  
32  
32  
16  
16  
16  
QFN48  
QFN48  
QFN32  
QFN32  
QFN48  
QFN48  
QFN48  
QFN32  
QFN32  
QFN32  
-40 to +85°C  
-40 to +85°C  
-40 to +85°C  
-40 to +85°C  
-40 to +85°C  
-40 to +125°C  
-40 to +85°C  
-40 to +85°C  
-40 to +125°C  
-40 to +85°C  
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Rev. 1.2 | 3  
EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Ordering Information  
EFR32 X G 1 4 P 733 F 256 G M 48 A R  
Tape and Reel (Optional)  
Revision  
Pin Count  
Package – M (QFN)  
Temperature Grade – G (-40 to +85 °C), -I (-40 to +125 °C)  
Flash Memory Size in kB  
Memory Type (Flash)  
Feature Set Code – r2r1r0  
r2: Reserved  
r1: RF Type – 3 (TRX), 2 (RX), 1 (TX)  
r0: Frequency Band – 1 (Sub-GHz), 2 (2.4 GHz), 3 (Dual-Band)  
Performance Grade – P (Performance), B (Basic), V (Value)  
Device Configuration  
Series  
Gecko  
Family – M (Mighty), B (Blue), F (Flex)  
Wireless Gecko 32-bit  
Figure 2.1. Ordering Code Key  
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Rev. 1.2 | 4  
Table of Contents  
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
3.2 Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
3.2.1 Antenna Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
3.2.2 Fractional-N Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . 9  
3.2.3 Receiver Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
3.2.4 Transmitter Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 9  
3.2.5 Wake on Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . .10  
3.2.6 RFSENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10  
3.2.7 Flexible Frame Handling . . . . . . . . . . . . . . . . . . . . . . . . .10  
3.2.8 Packet and State Trace . . . . . . . . . . . . . . . . . . . . . . . . .10  
3.2.9 Data Buffering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .10  
3.2.10 Radio Controller (RAC) . . . . . . . . . . . . . . . . . . . . . . . . .11  
3.2.11 Random Number Generator . . . . . . . . . . . . . . . . . . . . . . .11  
3.3 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12  
3.3.1 Energy Management Unit (EMU) . . . . . . . . . . . . . . . . . . . . . .12  
3.3.2 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . .12  
3.3.3 Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . .12  
3.4 General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . .12  
3.5 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13  
3.5.1 Clock Management Unit (CMU) . . . . . . . . . . . . . . . . . . . . . . .13  
3.5.2 Internal and External Oscillators. . . . . . . . . . . . . . . . . . . . . . .13  
3.6 Counters/Timers and PWM . . . . . . . . . . . . . . . . . . . . . . . . . .13  
3.6.1 Timer/Counter (TIMER) . . . . . . . . . . . . . . . . . . . . . . . . .13  
3.6.2 Wide Timer/Counter (WTIMER) . . . . . . . . . . . . . . . . . . . . . . .13  
3.6.3 Real Time Counter and Calendar (RTCC) . . . . . . . . . . . . . . . . . . .13  
3.6.4 Low Energy Timer (LETIMER) . . . . . . . . . . . . . . . . . . . . . . .14  
3.6.5 Ultra Low Power Wake-up Timer (CRYOTIMER) . . . . . . . . . . . . . . . . .14  
3.6.6 Pulse Counter (PCNT) . . . . . . . . . . . . . . . . . . . . . . . . . .14  
3.6.7 Watchdog Timer (WDOG). . . . . . . . . . . . . . . . . . . . . . . . .14  
3.7 Communications and Other Digital Peripherals . . . . . . . . . . . . . . . . . . .14  
3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) . . . . . . . . . .14  
3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) . . . . . . . . . .14  
2
3.7.3 Inter-Integrated Circuit Interface (I C) . . . . . . . . . . . . . . . . . . . . .14  
3.7.4 Peripheral Reflex System (PRS) . . . . . . . . . . . . . . . . . . . . . .14  
3.7.5 Low Energy Sensor Interface (LESENSE) . . . . . . . . . . . . . . . . . . .15  
3.8 Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15  
3.8.1 GPCRC (General Purpose Cyclic Redundancy Check) . . . . . . . . . . . . . . .15  
3.8.2 Crypto Accelerator (CRYPTO) . . . . . . . . . . . . . . . . . . . . . . .15  
3.8.3 Security Management Unit (SMU) . . . . . . . . . . . . . . . . . . . . . .15  
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3.9 Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15  
3.9.1 Analog Port (APORT) . . . . . . . . . . . . . . . . . . . . . . . . . .15  
3.9.2 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . . .15  
3.9.3 Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . .15  
3.9.4 Digital to Analog Current Converter (IDAC) . . . . . . . . . . . . . . . . . . .16  
3.9.5 Digital to Analog Converter (VDAC) . . . . . . . . . . . . . . . . . . . . .16  
3.9.6 Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . .16  
3.10 Reset Management Unit (RMU) . . . . . . . . . . . . . . . . . . . . . . . .16  
3.11 Core and Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . .16  
3.11.1 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . .16  
3.11.2 Memory System Controller (MSC) . . . . . . . . . . . . . . . . . . . . .16  
3.11.3 Linked Direct Memory Access Controller (LDMA) . . . . . . . . . . . . . . . .16  
3.12 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17  
3.13 Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . .18  
4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
4.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .19  
4.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . .20  
4.1.2 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . .22  
4.1.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .24  
4.1.4 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . .25  
4.1.5 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . .27  
4.1.6 Wake Up Times . . . . . . . . . . . . . . . . . . . . . . . . . . . .37  
4.1.7 Brown Out Detector (BOD) . . . . . . . . . . . . . . . . . . . . . . . .38  
4.1.8 Frequency Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . .39  
4.1.9 2.4 GHz RF Transceiver Characteristics . . . . . . . . . . . . . . . . . . . .40  
4.1.10 Sub-GHz RF Transceiver Characteristics . . . . . . . . . . . . . . . . . . .49  
4.1.11 Modem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73  
4.1.12 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74  
4.1.13 Flash Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . .78  
4.1.14 General-Purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . .79  
4.1.15 Voltage Monitor (VMON). . . . . . . . . . . . . . . . . . . . . . . . .81  
4.1.16 Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . .82  
4.1.17 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . .84  
4.1.18 Digital to Analog Converter (VDAC) . . . . . . . . . . . . . . . . . . . . .87  
4.1.19 Current Digital to Analog Converter (IDAC) . . . . . . . . . . . . . . . . . .90  
4.1.20 Operational Amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . .92  
4.1.21 Pulse Counter (PCNT) . . . . . . . . . . . . . . . . . . . . . . . . .95  
4.1.22 Analog Port (APORT) . . . . . . . . . . . . . . . . . . . . . . . . . .95  
4.1.23 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96  
4.1.24 USART SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99  
4.2 Typical Performance Curves  
. . . . . . . . . . . . . . . . . . . . . . . .100  
4.2.1 Supply Current  
4.2.2 DC-DC Converter  
4.2.3 2.4 GHz Radio  
. . . . . . . . . . . . . . . . . . . . . . . . . . 1. 01  
. . . . . . . . . . . . . . . . . . . . . . . . . 1.06  
. . . . . . . . . . . . . . . . . . . . . . . . . . 1.08  
5. Typical Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . .110  
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5.1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110  
5.2 RF Matching Networks . . . . . . . . . . . . . . . . . . . . . . . . . .112  
5.3 Other Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . 113  
6. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114  
6.1 QFN48 2.4 GHz and Sub-GHz Device Pinout. . . . . . . . . . . . . . . . . . . 114  
6.2 QFN48 2.4 GHz Device Pinout  
6.3 QFN48 Sub-GHz Device Pinout . . . . . . . . . . . . . . . . . . . . . . .118  
6.4 QFN32 2.4 GHz Device Pinout . . . . . . . . . . . . . . . . . . . . . . 1.20  
6.5 QFN32 Sub-GHz Device Pinout . . . . . . . . . . . . . . . . . . . . . . .122  
6.6 GPIO Functionality Table . . . . . . . . . . . . . . . . . . . . . . . . 1. 24  
6.7 Alternate Functionality Overview . . . . . . . . . . . . . . . . . . . . . . . 135  
6.8 Analog Port (APORT) Client Maps . . . . . . . . . . . . . . . . . . . . . .145  
. . . . . . . . . . . . . . . . . . . . . . 1.16  
7. QFN48 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 152  
7.1 QFN48 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . .152  
7.2 QFN48 PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . .154  
7.3 QFN48 Package Marking  
. . . . . . . . . . . . . . . . . . . . . . . . .156  
8. QFN32 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 157  
8.1 QFN32 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . .157  
8.2 QFN32 PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . .159  
8.3 QFN32 Package Marking  
. . . . . . . . . . . . . . . . . . . . . . . . .161  
9. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
System Overview  
3. System Overview  
3.1 Introduction  
The EFR32 product family combines an energy-friendly MCU with a highly integrated radio transceiver. The devices are well suited for  
any battery operated application as well as other systems requiring high performance and low energy consumption. This section gives a  
short introduction to the full radio and MCU system. The detailed functional description can be found in the EFR32xG14 Wireless  
Gecko Reference Manual.  
A block diagram of the EFR32FG14 family is shown in Figure 3.1 Detailed EFR32FG14 Block Diagram on page 8. The diagram  
shows a superset of features available on the family, which vary by OPN. For more information about specific device features, consult  
Ordering Information.  
Radio Transceiver  
Port I/O Configuration  
Digital Peripherals  
IOVDD  
Sub-GHz RF  
SUBGRF_IP  
SUBGRF_IN  
SUBGRF_OP  
SUBGRF_ON  
I
DEMOD  
IFADC  
AGC  
LNA  
LETIMER  
PA  
Port A  
Drivers  
PGA  
Q
PAn  
TIMER  
CRYOTIMER  
PCNT  
RFSENSE  
BALUN  
2.4 GHz RF  
I
Frequency  
LNA  
Synthesizer  
Port B  
Drivers  
PBn  
PCn  
PDn  
PFn  
2G4RF_IOP  
2G4RF_ION  
To RF  
MOD  
PA  
Frontend  
Circuits  
RTC / RTCC  
USART  
Q
Port  
Mapper  
Port C  
Drivers  
LEUART  
I2C  
Reset  
Management  
Unit  
ARM Cortex-M4 Core  
RESETn  
Port D  
Up to 256 KB ISP Flash  
Program Memory  
CRYPTO  
CRC  
Drivers  
Serial Wire  
Debug /  
Programming  
Debug Signals  
(shared w/GPIO)  
Brown Out /  
Power-On  
Reset  
A
H
B
A
P
B
Up to 32 KB RAM  
Memory Protection Unit  
Floating Point Unit  
DMA Controller  
Port F  
Drivers  
LESENSE  
Energy Management  
Analog Peripherals  
PAVDD  
RFVDD  
IOVDD  
AVDD  
IDAC  
Voltage  
Monitor  
-
+
Watchdog  
Timer  
VDAC  
DVDD  
bypass  
Op-Amp  
VDD  
Internal  
Reference  
Clock Management  
VREGVDD  
VREGSW  
DC-DC  
Converter  
Voltage  
Regulator  
ULFRCO  
AUXHFRCO  
LFRCO  
12-bit ADC  
DECOUPLE  
Temp  
Sense  
LFXTAL_P  
LFXTAL_N  
HFXTAL_P  
HFXTAL_N  
LFXO  
+
-
HFRCO  
HFXO  
Analog Comparator  
Figure 3.1. Detailed EFR32FG14 Block Diagram  
3.2 Radio  
The Flex Gecko family features a radio transceiver supporting proprietary wireless protocols.  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
System Overview  
3.2.1 Antenna Interface  
The EFR32FG14 family includes devices which support both single-band and dual-band RF communication over separate physical RF  
interfaces.  
The 2.4 GHz antenna interface consists of two pins (2G4RF_IOP and 2G4RF_ION) that interface directly to the on-chip BALUN. The  
2G4RF_ION pin should be grounded externally.  
The sub-GHz antenna interface consists of a differential transmit interface (pins SUBGRF_OP and SUBGRF_ON) and a differential re-  
ceive interface (pinsSUBGRF_IP and SUBGRF_IN).  
The external components and power supply connections for the antenna interface typical applications are shown in the RF Matching  
Networks section.  
3.2.2 Fractional-N Frequency Synthesizer  
The EFR32FG14 contains a high performance, low phase noise, fully integrated fractional-N frequency synthesizer. The synthesizer is  
used in receive mode to generate the LO frequency used by the down-conversion mixer. It is also used in transmit mode to directly  
generate the modulated RF carrier.  
The fractional-N architecture provides excellent phase noise performance combined with frequency resolution better than 100 Hz, with  
low energy consumption. The synthesizer has fast frequency settling which allows very short receiver and transmitter wake up times to  
optimize system energy consumption.  
3.2.3 Receiver Architecture  
The EFR32FG14 uses a low-IF receiver architecture, consisting of a Low-Noise Amplifier (LNA) followed by an I/Q down-conversion  
mixer, employing a crystal reference. The I/Q signals are further filtered and amplified before being sampled by the IF analog-to-digital  
converter (IFADC).  
The IF frequency is configurable from 150 kHz to 1371 kHz. The IF can further be configured for high-side or low-side injection, provid-  
ing flexibility with respect to known interferers at the image frequency.  
The Automatic Gain Control (AGC) module adjusts the receiver gain to optimize performance and avoid saturation for excellent selec-  
tivity and blocking performance. The 2.4 GHz radio is calibrated at production to improve image rejection performance. The sub-GHz  
radio can be calibrated on-demand by the user for the desired frequency band.  
Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow re-  
ceive bandwidths ranging from 0.1 to 2530 kHz. High carrier frequency and baud rate offsets are tolerated by active estimation and  
compensation. Advanced features supporting high quality communication under adverse conditions include forward error correction by  
block and convolutional coding as well as Direct Sequence Spread Spectrum (DSSS) for 2.4 GHz and sub-GHz bands.  
A Received Signal Strength Indicator (RSSI) is available for signal quality metrics, for level-based proximity detection, and for RF chan-  
nel access by Collision Avoidance (CA) or Listen Before Talk (LBT) algorithms. An RSSI capture value is associated with each received  
frame and the dynamic RSSI measurement can be monitored throughout reception.  
The EFR32FG14 features integrated support for antenna diversity to mitigate the problem of frequency-selective fading due to multipath  
propagation and improve link budget. Support for antenna diversity is available for specific PHY configurations in 2.4 GHz and sub-GHz  
bands. Internal configurable hardware controls an external switch for automatic switching between antennae during RF receive detec-  
tion operations.  
Note: Due to the shorter preamble of 802.15.4 and BLE packets, RX diversity is not supported.  
3.2.4 Transmitter Architecture  
The EFR32FG14 uses a direct-conversion transmitter architecture. For constant envelope modulation formats, the modulator controls  
phase and frequency modulation in the frequency synthesizer. Transmit symbols or chips are optionally shaped by a digital shaping  
filter. The shaping filter is fully configurable, including the BT product, and can be used to implement Gaussian or Raised Cosine shap-  
ing.  
Carrier Sense Multiple Access - Collision Avoidance (CSMA-CA) or Listen Before Talk (LBT) algorithms can be automatically timed by  
the EFR32FG14. These algorithms are typically defined by regulatory standards to improve inter-operability in a given bandwidth be-  
tween devices that otherwise lack synchronized RF channel access.  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
System Overview  
3.2.5 Wake on Radio  
The Wake on Radio feature allows flexible, autonomous RF sensing, qualification, and demodulation without required MCU activity, us-  
ing a subsystem of the EFR32FG14 including the Radio Controller (RAC), Peripheral Reflex System (PRS), and Low Energy peripher-  
als.  
3.2.6 RFSENSE  
The RFSENSE module generates a system wakeup interrupt upon detection of wideband RF energy at the antenna interface, providing  
true RF wakeup capabilities from low energy modes including EM2, EM3 and EM4.  
RFSENSE triggers on a relatively strong RF signal and is available in the lowest energy modes, allowing exceptionally low energy con-  
sumption. RFSENSE does not demodulate or otherwise qualify the received signal, but software may respond to the wakeup event by  
enabling normal RF reception.  
Various strategies for optimizing power consumption and system response time in presence of false alarms may be employed using  
available timer peripherals.  
3.2.7 Flexible Frame Handling  
EFR32FG14 has an extensive and flexible frame handling support for easy implementation of even complex communication protocols.  
The Frame Controller (FRC) supports all low level and timing critical tasks together with the Radio Controller and Modulator/Demodula-  
tor:  
• Highly adjustable preamble length  
• Up to 2 simultaneous synchronization words, each up to 32 bits and providing separate interrupts  
• Frame disassembly and address matching (filtering) to accept or reject frames  
• Automatic ACK frame assembly and transmission  
• Fully flexible CRC generation and verification:  
• Multiple CRC values can be embedded in a single frame  
• 8, 16, 24 or 32-bit CRC value  
• Configurable CRC bit and byte ordering  
• Selectable bit-ordering (least significant or most significant bit first)  
• Optional data whitening  
• Optional Forward Error Correction (FEC), including convolutional encoding / decoding and block encoding / decoding  
• Half rate convolutional encoder and decoder with constraint lengths from 2 to 7 and optional puncturing  
• Optional symbol interleaving, typically used in combination with FEC  
• Symbol coding, such as Manchester or DSSS, or biphase space encoding using FEC hardware  
• UART encoding over air, with start and stop bit insertion / removal  
• Test mode support, such as modulated or unmodulated carrier output  
• Received frame timestamping  
3.2.8 Packet and State Trace  
The EFR32FG14 Frame Controller has a packet and state trace unit that provides valuable information during the development phase.  
It features:  
• Non-intrusive trace of transmit data, receive data and state information  
• Data observability on a single-pin UART data output, or on a two-pin SPI data output  
• Configurable data output bitrate / baudrate  
• Multiplexed transmitted data, received data and state / meta information in a single serial data stream  
3.2.9 Data Buffering  
The EFR32FG14 features an advanced Radio Buffer Controller (BUFC) capable of handling up to 4 buffers of adjustable size from 64  
bytes to 4096 bytes. Each buffer can be used for RX, TX or both. The buffer data is located in RAM, enabling zero-copy operations.  
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System Overview  
3.2.10 Radio Controller (RAC)  
The Radio Controller controls the top level state of the radio subsystem in the EFR32FG14. It performs the following tasks:  
• Precisely-timed control of enabling and disabling of the receiver and transmitter circuitry  
• Run-time calibration of receiver, transmitter and frequency synthesizer  
• Detailed frame transmission timing, including optional LBT or CSMA-CA  
3.2.11 Random Number Generator  
The Frame Controller (FRC) implements a random number generator that uses entropy gathered from noise in the RF receive chain.  
The data is suitable for use in cryptographic applications.  
Output from the random number generator can be used either directly or as a seed or entropy source for software-based random num-  
ber generator algorithms such as Fortuna.  
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System Overview  
3.3 Power  
The EFR32FG14 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only  
a single external supply voltage is required, from which all internal voltages are created. An optional integrated DC-DC buck regulator  
can be utilized to further reduce the current consumption. The DC-DC regulator requires one external inductor and one external capaci-  
tor.  
The EFR32FG14 device family includes support for internal supply voltage scaling, as well as two different power domains groups for  
peripherals. These enhancements allow for further supply current reductions and lower overall power consumption.  
AVDD and VREGVDD need to be 1.8 V or higher for the MCU to operate across all conditions; however the rest of the system will  
operate down to 1.62 V, including the digital supply and I/O. This means that the device is fully compatible with 1.8 V components.  
Running from a sufficiently high supply, the device can use the DC-DC to regulate voltage not only for itself, but also for other PCB  
components, supplying up to a total of 200 mA.  
3.3.1 Energy Management Unit (EMU)  
The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and  
features are available and the amount of current the device consumes. The EMU can also be used to turn off the power to unused RAM  
blocks, and it contains control registers for the DC-DC regulator and the Voltage Monitor (VMON). The VMON is used to monitor multi-  
ple supply voltages. It has multiple channels which can be programmed individually by the user to determine if a sensed supply has  
fallen below a chosen threshold.  
3.3.2 DC-DC Converter  
The DC-DC buck converter covers a wide range of load currents and provides up to 90% efficiency in energy modes EM0, EM1, EM2  
and EM3, and can supply up to 200 mA to the device and surrounding PCB components. Patented RF noise mitigation allows operation  
of the DC-DC converter without degrading sensitivity of radio components. Protection features include programmable current limiting,  
short-circuit protection, and dead-time protection. The DC-DC converter may also enter bypass mode when the input voltage is too low  
for efficient operation. In bypass mode, the DC-DC input supply is internally connected directly to its output through a low resistance  
switch. Bypass mode also supports in-rush current limiting to prevent input supply voltage droops due to excessive output current tran-  
sients.  
3.3.3 Power Domains  
The EFR32FG14 has two peripheral power domains for operation in EM2 and EM3. If all of the peripherals in a peripheral power do-  
main are configured as unused, the power domain for that group will be powered off in the low-power mode, reducing the overall cur-  
rent consumption of the device.  
Table 3.1. Peripheral Power Subdomains  
Peripheral Power Domain 1  
Peripheral Power Domain 2  
ACMP0  
PCNT0  
ACMP1  
CSEN  
ADC0  
VDAC0  
LEUART0  
I2C0  
LETIMER0  
LESENSE  
APORT  
IDAC  
3.4 General Purpose Input/Output (GPIO)  
EFR32FG14 has up to 32 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or in-  
put. More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO  
pin. The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to  
several GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripher-  
als. The GPIO subsystem supports asynchronous external pin interrupts.  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
System Overview  
3.5 Clocking  
3.5.1 Clock Management Unit (CMU)  
The Clock Management Unit controls oscillators and clocks in the EFR32FG14. Individual enabling and disabling of clocks to all periph-  
eral modules is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility  
allows software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and  
oscillators.  
3.5.2 Internal and External Oscillators  
The EFR32FG14 supports two crystal oscillators and fully integrates four RC oscillators, listed below.  
• A high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing refer-  
ence for the MCU. Crystal frequencies in the range from 38 to 40 MHz are supported. An external clock source such as a TCXO can  
also be applied to the HFXO input for improved accuracy over temperature.  
• A 32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.  
• An integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The  
HFRCO employs fast startup at minimal energy consumption combined with a wide frequency range.  
• An integrated auxilliary high frequency RC oscillator (AUXHFRCO) is available for timing the general-purpose ADC and the Serial  
Wire Viewer port with a wide frequency range.  
• An integrated low frequency 32.768 kHz RC oscillator (LFRCO) can be used as a timing reference in low energy modes, when crys-  
tal accuracy is not required.  
• An integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy con-  
sumption in low energy modes.  
3.6 Counters/Timers and PWM  
3.6.1 Timer/Counter (TIMER)  
TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the  
PRS system. The core of each TIMER is a 16-bit counter with up to 4 compare/capture channels. Each channel is configurable in one  
of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output  
reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER supports generation of pulse-width  
modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional  
dead-time insertion available in timer unit TIMER_0 only.  
3.6.2 Wide Timer/Counter (WTIMER)  
WTIMER peripherals function just as TIMER peripherals, but are 32 bits wide. They keep track of timing, count events, generate PWM  
outputs and trigger timed actions in other peripherals through the PRS system. The core of each WTIMER is a 32-bit counter with up to  
4 compare/capture channels. Each channel is configurable in one of three modes. In capture mode, the counter state is stored in a  
buffer at a selected input event. In compare mode, the channel output reflects the comparison of the counter to a programmed thresh-  
old value. In PWM mode, the WTIMER supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by  
the sequence of values written to the compare registers, with optional dead-time insertion available in timer unit WTIMER_0 only.  
3.6.3 Real Time Counter and Calendar (RTCC)  
The Real Time Counter and Calendar (RTCC) is a 32-bit counter providing timekeeping in all energy modes. The RTCC includes a  
Binary Coded Decimal (BCD) calendar mode for easy time and date keeping. The RTCC can be clocked by any of the on-board oscilla-  
tors with the exception of the AUXHFRCO, and it is capable of providing system wake-up at user defined instances. When receiving  
frames, the RTCC value can be used for timestamping. The RTCC includes 128 bytes of general purpose data retention, allowing easy  
and convenient data storage in all energy modes down to EM4H.  
A secondary RTC is used by the RF protocol stack for event scheduling, leaving the primary RTCC block available exclusively for appli-  
cation software.  
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System Overview  
3.6.4 Low Energy Timer (LETIMER)  
The unique LETIMER is a 16-bit timer that is available in energy mode EM2 Deep Sleep in addition to EM1 Sleep and EM0 Active. This  
allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed  
while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of wave-  
forms with minimal software intervention. The LETIMER is connected to the Real Time Counter and Calendar (RTCC), and can be  
configured to start counting on compare matches from the RTCC.  
3.6.5 Ultra Low Power Wake-up Timer (CRYOTIMER)  
The CRYOTIMER is a 32-bit counter that is capable of running in all energy modes. It can be clocked by either the 32.768 kHz crystal  
oscillator (LFXO), the 32.768 kHz RC oscillator (LFRCO), or the 1 kHz RC oscillator (ULFRCO). It can provide periodic Wakeup events  
and PRS signals which can be used to wake up peripherals from any energy mode. The CRYOTIMER provides a wide range of inter-  
rupt periods, facilitating flexible ultra-low energy operation.  
3.6.6 Pulse Counter (PCNT)  
The Pulse Counter (PCNT) peripheral can be used for counting pulses on a single input or to decode quadrature encoded inputs. The  
clock for PCNT is selectable from either an external source on pin PCTNn_S0IN or from an internal timing reference, selectable from  
among any of the internal oscillators, except the AUXHFRCO. The module may operate in energy mode EM0 Active, EM1 Sleep, EM2  
Deep Sleep, and EM3 Stop.  
3.6.7 Watchdog Timer (WDOG)  
The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed  
monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can  
also monitor autonomous systems driven by PRS.  
3.7 Communications and Other Digital Peripherals  
3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)  
The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O module. It supports full duplex asynchronous  
UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices sup-  
porting:  
• ISO7816 SmartCards  
• IrDA  
I2S  
3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)  
The unique LEUARTTM provides two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow  
UART communication up to 9600 baud. The LEUART includes all necessary hardware to make asynchronous serial communication  
possible with a minimum of software intervention and energy consumption.  
3.7.3 Inter-Integrated Circuit Interface (I2C)  
The I2C module provides an interface between the MCU and a serial I2C bus. It is capable of acting as both a master and a slave and  
supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates from 10  
kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system. The  
interface provided to software by the I2C module allows precise timing control of the transmission process and highly automated trans-  
fers. Automatic recognition of slave addresses is provided in active and low energy modes.  
3.7.4 Peripheral Reflex System (PRS)  
The Peripheral Reflex System provides a communication network between different peripheral modules without software involvement.  
Peripheral modules producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer periph-  
erals which in turn perform actions in response. Edge triggers and other functionality such as simple logic operations (AND, OR, NOT)  
can be applied by the PRS to the signals. The PRS allows peripheral to act autonomously without waking the MCU core, saving power.  
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3.7.5 Low Energy Sensor Interface (LESENSE)  
The Low Energy Sensor Interface LESENSETM is a highly configurable sensor interface with support for up to 16 individually configura-  
ble sensors. By controlling the analog comparators, ADC, and DAC, LESENSE is capable of supporting a wide range of sensors and  
measurement schemes, and can for instance measure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a  
programmable finite state machine which enables simple processing of measurement results without CPU intervention. LESENSE is  
available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in applications with a strict energy  
budget.  
3.8 Security Features  
3.8.1 GPCRC (General Purpose Cyclic Redundancy Check)  
The GPCRC module implements a Cyclic Redundancy Check (CRC) function. It supports both 32-bit and 16-bit polynomials. The sup-  
ported 32-bit polynomial is 0x04C11DB7 (IEEE 802.3), while the 16-bit polynomial can be programmed to any value, depending on the  
needs of the application.  
3.8.2 Crypto Accelerator (CRYPTO)  
The Crypto Accelerator is a fast and energy-efficient autonomous hardware encryption and decryption accelerator. EFR32 devices sup-  
port AES encryption and decryption with 128- or 256-bit keys, ECC over both GF(P) and GF(2m), SHA-1 and SHA-2 (SHA-224 and  
SHA-256).  
Supported block cipher modes of operation for AES include: ECB, CTR, CBC, PCBC, CFB, OFB, GCM, CBC-MAC, GMAC and CCM.  
Supported ECC NIST recommended curves include P-192, P-224, P-256, K-163, K-233, B-163 and B-233.  
The CRYPTO1 block is tightly linked to the Radio Buffer Controller (BUFC) enabling fast and efficient autonomous cipher operations on  
data buffer content. It allows fast processing of GCM (AES), ECC and SHA with little CPU intervention.  
CRYPTO also provides trigger signals for DMA read and write operations.  
3.8.3 Security Management Unit (SMU)  
The Security Management Unit (SMU) allows software to set up fine-grained security for peripheral access, which is not possible in the  
Memory Protection Unit (MPU). Peripherals may be secured by hardware on an individual basis, such that only priveleged accesses to  
the peripheral's register interface will be allowed. When an access fault occurs, the SMU reports the specific peripheral involved and  
can optionally generate an interrupt.  
3.9 Analog  
3.9.1 Analog Port (APORT)  
The Analog Port (APORT) is an analog interconnect matrix allowing access to many analog modules on a flexible selection of pins.  
Each APORT bus consists of analog switches connected to a common wire. Since many clients can operate differentially, buses are  
grouped by X/Y pairs.  
3.9.2 Analog Comparator (ACMP)  
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-  
er. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption  
is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The  
ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the  
programmable threshold.  
3.9.3 Analog to Digital Converter (ADC)  
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 Msps. The output  
sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples.  
The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide range of  
sources, including pins configurable as either single-ended or differential.  
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3.9.4 Digital to Analog Current Converter (IDAC)  
The Digital to Analog Current Converter can source or sink a configurable constant current. This current can be driven on an output pin  
or routed to the selected ADC input pin for capacitive sensing. The full-scale current is programmable between 0.05 µA and 64 µA with  
several ranges consisting of various step sizes.  
3.9.5 Digital to Analog Converter (VDAC)  
The Digital to Analog Converter (VDAC) can convert a digital value to an analog output voltage. The VDAC is a fully differential, 500  
ksps, 12-bit converter. The opamps are used in conjunction with the VDAC, to provide output buffering. One opamp is used per single-  
ended channel, or two opamps are used to provide differential outputs. The VDAC may be used for a number of different applications  
such as sensor interfaces or sound output. The VDAC can generate high-resolution analog signals while the MCU is operating at low  
frequencies and with low total power consumption. Using DMA and a timer, the VDAC can be used to generate waveforms without any  
CPU intervention. The VDAC is available in all energy modes down to and including EM3.  
3.9.6 Operational Amplifiers  
The opamps are low power amplifiers with a high degree of flexibility targeting a wide variety of standard opamp application areas, and  
are available down to EM3. With flexible built-in programming for gain and interconnection they can be configured to support multiple  
common opamp functions. All pins are also available externally for filter configurations. Each opamp has a rail to rail input and a rail to  
rail output. They can be used in conjunction with the VDAC module or in stand-alone configurations. The opamps save energy, PCB  
space, and cost as compared with standalone opamps because they are integrated on-chip.  
3.10 Reset Management Unit (RMU)  
The RMU is responsible for handling reset of the EFR32FG14. A wide range of reset sources are available, including several power  
supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset.  
3.11 Core and Memory  
3.11.1 Processor Core  
The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:  
• ARM Cortex-M4 RISC processor achieving 1.25 Dhrystone MIPS/MHz  
• Memory Protection Unit (MPU) supporting up to 8 memory segments  
• Up to 256 kB flash program memory  
• Up to 32 kB RAM data memory  
• Configuration and event handling of all modules  
• 2-pin Serial-Wire debug interface  
3.11.2 Memory System Controller (MSC)  
The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable  
from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code  
is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a  
read-only page in the information block containing system and device calibration data. Read and write operations are supported in en-  
ergy modes EM0 Active and EM1 Sleep.  
3.11.3 Linked Direct Memory Access Controller (LDMA)  
The Linked Direct Memory Access (LDMA) controller allows the system to perform memory operations independently of software. This  
reduces both energy consumption and software workload. The LDMA allows operations to be linked together and staged, enabling so-  
phisticated operations to be implemented.  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
System Overview  
3.12 Memory Map  
The EFR32FG14 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.  
Figure 3.2. EFR32FG14 Memory Map — Core Peripherals and Code Space  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
System Overview  
Figure 3.3. EFR32FG14 Memory Map — Peripherals  
3.13 Configuration Summary  
The features of the EFR32FG14 are a subset of the feature set described in the device reference manual. The table below describes  
device specific implementation of the features. Remaining modules support full configuration.  
Table 3.2. Configuration Summary  
Module  
Configuration  
IrDA  
Pin Connections  
USART0  
US0_TX, US0_RX, US0_CLK, US0_CS  
SmartCard  
I2S  
USART1  
US1_TX, US1_RX, US1_CLK, US1_CS  
SmartCard  
with DTI  
-
TIMER0  
TIMER1  
WTIMER0  
TIM0_CC[2:0], TIM0_CDTI[2:0]  
TIM1_CC[3:0]  
with DTI  
WTIM0_CC[2:0], WTIM0_CDTI[2:0]  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
4. Electrical Specifications  
4.1 Electrical Characteristics  
All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:  
• Typical values are based on TAMB=25 °C and VDD= 3.3 V, by production test and/or technology characterization.  
• Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output pow-  
er-specific external RF impedance-matching networks for interfacing to a 50 Ω source or load.  
• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,  
unless stated otherwise.  
Refer to 4.1.2.1 General Operating Conditions for more details about operational supply and temperature limits.  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
4.1.1 Absolute Maximum Ratings  
Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of  
the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure  
to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and relia-  
bility data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx.  
Table 4.1. Absolute Maximum Ratings  
Parameter  
Symbol  
TSTG  
Test Condition  
Min  
-50  
-0.3  
Typ  
Max  
150  
3.8  
1
Unit  
°C  
Storage temperature range  
Voltage on any supply pin  
VDDMAX  
VDDRAMPMAX  
V
Voltage ramp rate on any  
supply pin  
V / µs  
5V tolerant GPIO pins1 2 3  
Standard GPIO pins  
DC voltage on any GPIO pin VDIGPIN  
-0.3  
Min of 5.25  
and IOVDD  
+2  
V
-0.3  
-0.3  
IOVDD+0.3  
V
V
Voltage on HFXO pins  
VHFXOPIN  
1.4  
10  
Input RF level on pins  
2G4RF_IOP and  
2G4RF_ION  
PRFMAX2G4  
dBm  
Voltage differential between VMAXDIFF2G4  
RF pins (2G4RF_IOP -  
2G4RF_ION)  
-50  
50  
mV  
V
Absolute voltage on RF pins VMAX2G4  
2G4RF_IOP and  
-0.3  
3.3  
2G4RF_ION  
Absolute voltage on Sub-  
GHz RF pins  
VMAXSUBG  
Pins SUBGRF_OP and  
SUBGRF_ON  
-0.3  
-0.3  
3.3  
0.3  
V
V
Pins SUBGRF_IP and  
SUBGRF_IN,  
Total current into VDD power IVDDMAX  
lines  
Source  
200  
200  
mA  
mA  
Total current into VSS  
ground lines  
IVSSMAX  
Sink  
Current per I/O pin  
IIOMAX  
Sink  
50  
50  
mA  
mA  
mA  
mA  
°C  
Source  
Current for all I/O pins  
Junction temperature  
IIOALLMAX  
Sink  
200  
200  
105  
125  
Source  
TJ  
-G grade devices  
-I grade devices  
-40  
-40  
°C  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
Parameter  
Note:  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
1. When a GPIO pin is routed to the analog module through the APORT, the maximum voltage = IOVDD.  
2. Valid for IOVDD in valid operating range or when IOVDD is undriven (high-Z). If IOVDD is connected to a low-impedance source  
below the valid operating range (e.g. IOVDD shorted to VSS), the pin voltage maximum is IOVDD + 0.3 V, to avoid exceeding the  
maximum IO current specifications.  
3. To operate above the IOVDD supply rail, over-voltage tolerance must be enabled according to the GPIO_Px_OVTDIS register.  
Pins with over-voltage tolerance disabled have the same limits as Standard GPIO.  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
4.1.2 Operating Conditions  
When assigning supply sources, the following requirements must be observed:  
• VREGVDD must be greater than or equal to AVDD, DVDD, RFVDD, PAVDD and all IOVDD supplies.  
• VREGVDD = AVDD  
• DVDD ≤ AVDD  
• IOVDD ≤ AVDD  
• RFVDD ≤ AVDD  
• PAVDD ≤ AVDD  
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Rev. 1.2 | 22  
EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
4.1.2.1 General Operating Conditions  
Table 4.2. General Operating Conditions  
Parameter  
Symbol  
Test Condition  
Min  
-40  
-40  
1.8  
Typ  
25  
Max  
85  
Unit  
°C  
°C  
V
Operating ambient tempera- TA  
ture range5  
-G temperature grade  
-I temperature grade  
25  
125  
3.8  
AVDD supply voltage2  
VAVDD  
3.3  
VREGVDD operating supply VVREGVDD  
voltage2 1  
DCDC in regulation  
2.4  
1.8  
1.8  
3.3  
3.3  
3.3  
3.8  
3.8  
3.8  
V
V
V
DCDC in bypass, 50mA load  
DCDC not in use. DVDD external-  
ly shorted to VREGVDD  
VREGVDD current  
IVREGVDD  
DCDC in bypass, T ≤ 85 °C  
DCDC in bypass, T > 85 °C  
200  
100  
mA  
mA  
V
RFVDD operating supply  
voltage  
VRFVDD  
1.62  
VVREGVDD  
DVDD operating supply volt- VDVDD  
age  
1.62  
1.62  
1.62  
0.75  
VVREGVDD  
VVREGVDD  
VVREGVDD  
2.75  
V
V
PAVDD operating supply  
voltage  
VPAVDD  
IOVDD operating supply volt- VIOVDD  
age  
All IOVDD pins  
V
DECOUPLE output capaci-  
tor3 4  
CDECOUPLE  
1.0  
µF  
Difference between AVDD  
dVDD  
0.1  
V
and VREGVDD, ABS(AVDD-  
VREGVDD)2  
HFCORECLK frequency  
fCORE  
VSCALE2, MODE = WS1  
VSCALE0, MODE = WS0  
VSCALE2  
40  
20  
40  
20  
MHz  
MHz  
MHz  
MHz  
HFCLK frequency  
fHFCLK  
VSCALE0  
Note:  
1. The minimum voltage required in bypass mode is calculated using RBYP from the DCDC specification table. Requirements for  
other loads can be calculated as VDVDD_min+ILOAD * RBYP_max  
.
2. VREGVDD must be tied to AVDD. Both VREGVDD and AVDD minimum voltages must be satisfied for the part to operate.  
3. The system designer should consult the characteristic specs of the capacitor used on DECOUPLE to ensure its capacitance val-  
ue stays within the specified bounds across temperature and DC bias.  
4. VSCALE0 to VSCALE2 voltage change transitions occur at a rate of 10 mV / usec for approximately 20 usec. During this transi-  
tion, peak currents will be dependent on the value of the DECOUPLE output capacitor, from 35 mA (with a 1 µF capacitor) to 70  
mA (with a 2.7 µF capacitor).  
5. The maximum limit on TA may be lower due to device self-heating, which depends on the power dissipation of the specific appli-  
cation. TA (max) = TJ (max) - (THETAJA x PowerDissipation). Refer to the Absolute Maximum Ratings table and the Thermal  
Characteristics table for TJ and THETAJA  
.
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
4.1.3 Thermal Characteristics  
Table 4.3. Thermal Characteristics  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
64.5  
51.6  
47.7  
26.2  
23.1  
22.1  
82.1  
64.7  
56.3  
36.8  
32  
Max  
Unit  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
Thermal resistance, QFN48 THETAJA_QFN48 2-Layer PCB, Air velocity = 0 m/s  
Package  
2-Layer PCB, Air velocity = 1 m/s  
2-Layer PCB, Air velocity = 2 m/s  
4-Layer PCB, Air velocity = 0 m/s  
4-Layer PCB, Air velocity = 1 m/s  
4-Layer PCB, Air velocity = 2 m/s  
Thermal resistance, QFN32 THETAJA_QFN32 2-Layer PCB, Air velocity = 0 m/s  
Package  
2-Layer PCB, Air velocity = 1 m/s  
2-Layer PCB, Air velocity = 2 m/s  
4-Layer PCB, Air velocity = 0 m/s  
4-Layer PCB, Air velocity = 1 m/s  
4-Layer PCB, Air velocity = 2 m/s  
30.6  
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Rev. 1.2 | 24  
EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
4.1.4 DC-DC Converter  
Test conditions: L_DCDC=4.7 µH (Murata LQH3NPN4R7MM0L), C_DCDC=4.7 µF (Samsung CL10B475KQ8NQNC), V_DCDC_I=3.3  
V, V_DCDC_O=1.8 V, I_DCDC_LOAD=50 mA, Heavy Drive configuration, F_DCDC_LN=7 MHz, unless otherwise indicated.  
Table 4.4. DC-DC Converter  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Input voltage range  
VDCDC_I  
Bypass mode, IDCDC_LOAD = 50  
mA  
1.8  
VVREGVDD_  
V
MAX  
Low noise (LN) mode, 1.8 V out-  
put, IDCDC_LOAD = 100 mA, or  
Low power (LP) mode, 1.8 V out-  
put, IDCDC_LOAD = 10 mA  
2.4  
VVREGVDD_  
V
MAX  
Low noise (LN) mode, 1.8 V out-  
put, IDCDC_LOAD = 200 mA  
2.6  
1.8  
VVREGVDD_  
V
V
MAX  
Output voltage programma- VDCDC_O  
ble range1  
VVREGVDD  
Regulation DC accuracy  
ACCDC  
Low Noise (LN) mode, 1.8 V tar-  
get output  
1.7  
1.9  
2.2  
V
V
Regulation window4  
WINREG  
Low Power (LP) mode,  
LPCMPBIASEMxx3 = 0, 1.8 V tar-  
get output, IDCDC_LOAD ≤ 75 µA  
1.63  
Low Power (LP) mode,  
1.63  
2.1  
V
LPCMPBIASEMxx3 = 3, 1.8 V tar-  
get output, IDCDC_LOAD ≤ 10 mA  
Steady-state output ripple  
VR  
Radio disabled  
3
mVpp  
mV  
CCM Mode (LNFORCECCM3 =  
1), Load changes between 0 mA  
and 100 mA  
Output voltage under/over-  
shoot  
VOV  
25  
60  
DCM Mode (LNFORCECCM3 =  
0), Load changes between 0 mA  
and 10 mA  
45  
90  
mV  
Overshoot during LP to LN  
CCM/DCM mode transitions com-  
pared to DC level in LN mode  
200  
40  
mV  
mV  
Undershoot during BYP/LP to LN  
CCM (LNFORCECCM3 = 1) mode  
transitions compared to DC level  
in LN mode  
Undershoot during BYP/LP to LN  
100  
mV  
DCM (LNFORCECCM3 = 0) mode  
transitions compared to DC level  
in LN mode  
DC line regulation  
DC load regulation  
VREG  
Input changes between  
VVREGVDD_MAX and 2.4 V  
0.1  
0.1  
%
%
IREG  
Load changes between 0 mA and  
100 mA in CCM mode  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Max load current  
ILOAD_MAX  
Low noise (LN) mode, Heavy  
Drive2, T ≤ 85 °C  
200  
mA  
Low noise (LN) mode, Heavy  
Drive2, T > 85 °C  
1
4.7  
100  
100  
50  
mA  
mA  
mA  
µA  
Low noise (LN) mode, Medium  
Drive2  
Low noise (LN) mode, Light  
Drive2  
Low power (LP) mode,  
LPCMPBIASEMxx3 = 0  
75  
Low power (LP) mode,  
LPCMPBIASEMxx3 = 3  
10  
mA  
µF  
DCDC nominal output ca-  
pacitor5  
CDCDC  
25% tolerance  
4.7  
DCDC nominal output induc- LDCDC  
tor  
20% tolerance  
4.7  
4.7  
1.2  
4.7  
2.5  
µH  
Resistance in Bypass mode RBYP  
Note:  
1. Due to internal dropout, the DC-DC output will never be able to reach its input voltage, VVREGVDD  
.
2. Drive levels are defined by configuration of the PFETCNT and NFETCNT registers. Light Drive: PFETCNT=NFETCNT=3; Medi-  
um Drive: PFETCNT=NFETCNT=7; Heavy Drive: PFETCNT=NFETCNT=15.  
3. LPCMPBIASEMxx refers to either LPCMPBIASEM234H in the EMU_DCDCMISCCTRL register or LPCMPBIASEM01 in the  
EMU_DCDCLOEM01CFG register, depending on the energy mode.  
4. LP mode controller is a hysteretic controller that maintains the output voltage within the specified limits.  
5. Output voltage under/over-shoot and regulation are specified with CDCDC 4.7 µF. Different settings for DCDCLNCOMPCTRL  
must be used if CDCDC is lower than 4.7 µF. See Application Note AN0948 for details.  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
4.1.5 Current Consumption  
4.1.5.1 Current Consumption 3.3 V without DC-DC Converter  
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 3.3 V. T = 25 °C. DCDC is off.  
Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.  
Table 4.5. Current Consumption 3.3 V without DC-DC Converter  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Current consumption in EM0 IACTIVE  
mode with all peripherals dis-  
abled  
38.4 MHz crystal, CPU running  
while loop from flash1  
123  
µA/MHz  
38 MHz HFRCO, CPU running  
Prime from flash  
96  
93  
103  
µA/MHz  
µA/MHz  
µA/MHz  
µA/MHz  
µA/MHz  
µA/MHz  
µA/MHz  
µA/MHz  
38 MHz HFRCO, CPU running  
while loop from flash  
38 MHz HFRCO, CPU running  
CoreMark from flash  
116  
95  
26 MHz HFRCO, CPU running  
while loop from flash  
106  
384  
1 MHz HFRCO, CPU running  
while loop from flash  
227  
82  
Current consumption in EM0 IACTIVE_VS  
mode with all peripherals dis-  
abled and voltage scaling  
enabled  
19 MHz HFRCO, CPU running  
while loop from flash  
1 MHz HFRCO, CPU running  
while loop from flash  
198  
73  
38.4 MHz crystal1  
38 MHz HFRCO  
26 MHz HFRCO  
1 MHz HFRCO  
19 MHz HFRCO  
1 MHz HFRCO  
Current consumption in EM1 IEM1  
mode with all peripherals dis-  
abled  
44  
46  
47  
51  
µA/MHz  
µA/MHz  
µA/MHz  
µA/MHz  
µA/MHz  
178  
41  
335  
Current consumption in EM1 IEM1_VS  
mode with all peripherals dis-  
abled and voltage scaling  
enabled  
158  
Current consumption in EM2 IEM2_VS  
mode, with voltage scaling  
enabled  
Full 32 kB RAM retention and  
RTCC running from LFXO  
1.9  
2.2  
1.9  
µA  
µA  
µA  
Full 32 kB RAM retention and  
RTCC running from LFRCO  
1 bank (16 kB) RAM retention and  
RTCC running from LFRCO2  
3.3  
Current consumption in EM3 IEM3_VS  
mode, with voltage scaling  
enabled  
Full 32 kB RAM retention and  
CRYOTIMER running from ULFR-  
CO  
1.44  
3.0  
µA  
Current consumption in  
EM4H mode, with voltage  
scaling enabled  
IEM4H_VS  
128 byte RAM retention, RTCC  
running from LFXO  
0.89  
0.55  
0.54  
µA  
µA  
µA  
128 byte RAM retention, CRYO-  
TIMER running from ULFRCO  
128 byte RAM retention, no RTCC  
0.8  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Current consumption in  
EM4S mode  
IEM4S  
No RAM retention, no RTCC  
0.04  
0.085  
µA  
Note:  
1. CMU_HFXOCTRL_LOWPOWER=0.  
2. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
4.1.5.2 Current Consumption 3.3 V using DC-DC Converter  
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD = 1.8 V DC-DC  
output. T = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.  
Table 4.6. Current Consumption 3.3 V using DC-DC Converter  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Current consumption in EM0 IACTIVE_DCM  
mode with all peripherals dis-  
abled, DCDC in Low Noise  
DCM mode2  
38.4 MHz crystal, CPU running  
while loop from flash4  
84  
µA/MHz  
38 MHz HFRCO, CPU running  
Prime from flash  
68  
67  
µA/MHz  
µA/MHz  
µA/MHz  
µA/MHz  
µA/MHz  
µA/MHz  
38 MHz HFRCO, CPU running  
while loop from flash  
38 MHz HFRCO, CPU running  
CoreMark from flash  
80  
26 MHz HFRCO, CPU running  
while loop from flash  
73  
1 MHz HFRCO, CPU running  
while loop from flash  
606  
94  
Current consumption in EM0 IACTIVE_CCM  
mode with all peripherals dis-  
abled, DCDC in Low Noise  
CCM mode1  
38.4 MHz crystal, CPU running  
while loop from flash4  
38 MHz HFRCO, CPU running  
Prime from flash  
79  
78  
µA/MHz  
µA/MHz  
µA/MHz  
µA/MHz  
µA/MHz  
µA/MHz  
µA/MHz  
38 MHz HFRCO, CPU running  
while loop from flash  
38 MHz HFRCO, CPU running  
CoreMark from flash  
90  
26 MHz HFRCO, CPU running  
while loop from flash  
90  
1 MHz HFRCO, CPU running  
while loop from flash  
1109  
97  
Current consumption in EM0 IACTIVE_CCM_VS 19 MHz HFRCO, CPU running  
mode with all peripherals dis-  
abled and voltage scaling  
enabled, DCDC in Low  
Noise CCM mode1  
while loop from flash  
1 MHz HFRCO, CPU running  
while loop from flash  
1093  
38.4 MHz crystal4  
38 MHz HFRCO  
26 MHz HFRCO  
1 MHz HFRCO  
19 MHz HFRCO  
1 MHz HFRCO  
Current consumption in EM1 IEM1_DCM  
mode with all peripherals dis-  
abled, DCDC in Low Noise  
55  
µA/MHz  
38  
45  
µA/MHz  
µA/MHz  
µA/MHz  
µA/MHz  
µA/MHz  
DCM mode2  
580  
48  
Current consumption in EM1 IEM1_DCM_VS  
mode with all peripherals dis-  
abled and voltage scaling  
569  
enabled, DCDC in Low  
Noise DCM mode2  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Current consumption in EM2 IEM2_VS  
mode, with voltage scaling  
enabled, DCDC in LP mode3  
Full 32 kB RAM retention and  
RTCC running from LFXO  
1.4  
µA  
Full 32 kB RAM retention and  
RTCC running from LFRCO  
1.5  
1.3  
µA  
µA  
1 bank (16 kB) RAM retention and  
RTCC running from LFRCO5  
Current consumption in EM3 IEM3_VS  
mode, with voltage scaling  
enabled  
Full 32 kB RAM retention and  
CRYOTIMER running from ULFR-  
CO  
1.02  
µA  
Current consumption in  
EM4H mode, with voltage  
scaling enabled  
IEM4H_VS  
128 byte RAM retention, RTCC  
running from LFXO  
0.74  
0.48  
µA  
µA  
128 byte RAM retention, CRYO-  
TIMER running from ULFRCO  
128 byte RAM retention, no RTCC  
No RAM retention, no RTCC  
0.48  
0.07  
µA  
µA  
Current consumption in  
EM4S mode  
IEM4S  
Note:  
1. DCDC Low Noise CCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=6.4 MHz (RCOBAND=4), ANASW=DVDD.  
2. DCDC Low Noise DCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=3.0 MHz (RCOBAND=0), ANASW=DVDD.  
3. DCDC Low Power Mode = Medium Drive (PFETCNT=NFETCNT=7), LPOSCDIV=1, LPCMPBIASEM234H=0, LPCLIMILIM-  
SEL=1, ANASW=DVDD.  
4. CMU_HFXOCTRL_LOWPOWER=0.  
5. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
4.1.5.3 Current Consumption 1.8 V without DC-DC Converter  
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 1.8 V. T = 25 °C. DCDC is off.  
Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.  
Table 4.7. Current Consumption 1.8 V without DC-DC Converter  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Current consumption in EM0 IACTIVE  
mode with all peripherals dis-  
abled  
38.4 MHz crystal, CPU running  
while loop from flash1  
123  
µA/MHz  
38 MHz HFRCO, CPU running  
Prime from flash  
96  
93  
µA/MHz  
µA/MHz  
µA/MHz  
µA/MHz  
µA/MHz  
µA/MHz  
µA/MHz  
µA/MHz  
38 MHz HFRCO, CPU running  
while loop from flash  
38 MHz HFRCO, CPU running  
CoreMark from flash  
115  
95  
26 MHz HFRCO, CPU running  
while loop from flash  
1 MHz HFRCO, CPU running  
while loop from flash  
224  
81  
Current consumption in EM0 IACTIVE_VS  
mode with all peripherals dis-  
abled and voltage scaling  
enabled  
19 MHz HFRCO, CPU running  
while loop from flash  
1 MHz HFRCO, CPU running  
while loop from flash  
195  
74  
38.4 MHz crystal1  
38 MHz HFRCO  
26 MHz HFRCO  
1 MHz HFRCO  
19 MHz HFRCO  
1 MHz HFRCO  
Current consumption in EM1 IEM1  
mode with all peripherals dis-  
abled  
44  
46  
µA/MHz  
µA/MHz  
µA/MHz  
µA/MHz  
µA/MHz  
175  
41  
Current consumption in EM1 IEM1_VS  
mode with all peripherals dis-  
abled and voltage scaling  
enabled  
155  
Current consumption in EM2 IEM2_VS  
mode, with voltage scaling  
enabled  
Full 32 kB RAM retention and  
RTCC running from LFXO  
1.7  
1.9  
1.7  
µA  
µA  
µA  
Full 32 kB RAM retention and  
RTCC running from LFRCO  
1 bank (16 kB) RAM retention and  
RTCC running from LFRCO2  
Current consumption in EM3 IEM3_VS  
mode, with voltage scaling  
enabled  
Full 32 kB RAM retention and  
CRYOTIMER running from ULFR-  
CO  
1.33  
µA  
Current consumption in  
EM4H mode, with voltage  
scaling enabled  
IEM4H_VS  
128 byte RAM retention, RTCC  
running from LFXO  
0.80  
0.44  
µA  
µA  
128 byte RAM retention, CRYO-  
TIMER running from ULFRCO  
128 byte RAM retention, no RTCC  
no RAM retention, no RTCC  
0.43  
0.04  
µA  
µA  
Current consumption in  
EM4S mode  
IEM4S  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
Parameter  
Note:  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
1. CMU_HFXOCTRL_LOWPOWER=0.  
2. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1  
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Rev. 1.2 | 32  
EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
4.1.5.4 Current Consumption Using Radio 3.3 V with DC-DC  
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD = 1.8 V. T = 25  
°C. Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.  
Table 4.8. Current Consumption Using Radio 3.3 V with DC-DC  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Current consumption in re-  
ceive mode, active packet  
reception (MCU in EM1 @  
38.4 MHz, peripheral clocks  
disabled), T ≤ 85 °C  
IRX_ACTIVE  
500 kbit/s, 2GFSK, F = 915 MHz,  
Radio clock prescaled by 4  
9.3  
10.2  
mA  
38.4 kbit/s, 2GFSK, F = 868 MHz,  
Radio clock prescaled by 4  
8.6  
8.6  
8.6  
8.6  
8.4  
8.8  
10.2  
10.2  
10.2  
10.2  
10.2  
10.2  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
38.4 kbit/s, 2GFSK, F = 490 MHz,  
Radio clock prescaled by 4  
50 kbit/s, 2GFSK, F = 433 MHz,  
Radio clock prescaled by 4  
38.4 kbit/s, 2GFSK, F = 315 MHz,  
Radio clock prescaled by 4  
38.4 kbit/s, 2GFSK, F = 169 MHz,  
Radio clock prescaled by 4  
1 Mbit/s, 2GFSK, F = 2.4 GHz,  
Radio clock prescaled by 4  
802.15.4 receiving frame, F = 2.4  
GHz, Radio clock prescaled by 3  
Current consumption in re-  
ceive mode, active packet  
reception (MCU in EM1 @  
38.4 MHz, peripheral clocks  
disabled), T > 85 °C  
IRX_ACTIVE_HT  
500 kbit/s, 2GFSK, F = 915 MHz,  
Radio clock prescaled by 4  
13  
38.4 kbit/s, 2GFSK, F = 868 MHz,  
Radio clock prescaled by 4  
13  
38.4 kbit/s, 2GFSK, F = 490 MHz,  
Radio clock prescaled by 4  
13  
50 kbit/s, 2GFSK, F = 433 MHz,  
Radio clock prescaled by 4  
13  
38.4 kbit/s, 2GFSK, F = 315 MHz,  
Radio clock prescaled by 4  
13  
38.4 kbit/s, 2GFSK, F = 169 MHz,  
Radio clock prescaled by 4  
13  
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Rev. 1.2 | 33  
EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Current consumption in re-  
ceive mode, listening for  
packet (MCU in EM1 @ 38.4  
MHz, peripheral clocks disa-  
bled), T ≤ 85 °C  
IRX_LISTEN  
500 kbit/s, 2GFSK, F = 915 MHz,  
No radio clock prescaling  
10.2  
11  
mA  
38.4 kbit/s, 2GFSK, F = 868 MHz,  
No radio clock prescaling  
9.5  
9.5  
9.5  
9.4  
9.3  
9.6  
11.1  
11  
11  
11  
11  
11  
14  
14  
14  
14  
14  
14  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
38.4 kbit/s, 2GFSK, F = 490 MHz,  
No radio clock prescaling  
50 kbit/s, 2GFSK, F = 433 MHz,  
No radio clock prescaling  
38.4 kbit/s, 2GFSK, F = 315 MHz,  
No radio clock prescaling  
38.4 kbit/s, 2GFSK, F = 169 MHz,  
No radio clock prescaling  
1 Mbit/s, 2GFSK, F = 2.4 GHz, No  
radio clock prescaling  
802.15.4, F = 2.4 GHz, No radio  
clock prescaling  
Current consumption in re-  
ceive mode, listening for  
packet (MCU in EM1 @ 38.4  
MHz, peripheral clocks disa-  
bled), T > 85 °C  
IRX_LISTEN_HT  
500 kbit/s, 2GFSK, F = 915 MHz,  
No radio clock prescaling  
38.4 kbit/s, 2GFSK, F = 868 MHz,  
No radio clock prescaling  
38.4 kbit/s, 2GFSK, F = 490 MHz,  
No radio clock prescaling  
50 kbit/s, 2GFSK, F = 433 MHz,  
No radio clock prescaling  
38.4 kbit/s, 2GFSK, F = 315 MHz,  
No radio clock prescaling  
38.4 kbit/s, 2GFSK, F = 169 MHz,  
No radio clock prescaling  
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Rev. 1.2 | 34  
EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Current consumption in  
transmit mode (MCU in EM1  
@ 38.4 MHz, peripheral  
clocks disabled), T ≤ 85 °C  
ITX  
F = 915 MHz, CW, 20 dBm  
match, External PA supply = 3.3V  
90.2  
134.3  
mA  
F = 915 MHz, CW, 14 dBm  
match, External PA supply con-  
nected to DCDC output  
36  
42.5  
mA  
F = 868 MHz, CW, 20 dBm  
match, External PA supply = 3.3V  
79.7  
35.3  
106.7  
41  
mA  
mA  
F = 868 MHz, CW, 14 dBm  
match, External PA supply con-  
nected to DCDC output  
F = 490 MHz, CW, 20 dBm  
match, External PA supply = 3.3V  
93.8  
20.3  
125.4  
24  
mA  
mA  
F = 433 MHz, CW, 10 dBm  
match, External PA supply con-  
nected to DC-DC output  
F = 433 MHz, CW, 14 dBm  
match, External PA supply con-  
nected to DCDC output  
34  
41.5  
42  
mA  
mA  
F = 315 MHz, CW, 14 dBm  
match, External PA supply con-  
nected to DCDC output  
33.5  
F = 169 MHz, CW, 20 dBm  
match, External PA supply = 3.3V  
88.6  
8.5  
116.7  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
F = 2.4 GHz, CW, 0 dBm output  
power, Radio clock prescaled by 3  
F = 2.4 GHz, CW, 0 dBm output  
power, Radio clock prescaled by 1  
9.5  
F = 2.4 GHz, CW, 3 dBm output  
power  
16.5  
26.0  
34.0  
91.6  
F = 2.4 GHz, CW, 8 dBm output  
power  
F = 2.4 GHz, CW, 10.5 dBm out-  
put power  
F = 2.4 GHz, CW, 16.5 dBm out-  
put power, PAVDD connected di-  
rectly to external 3.3V supply  
F = 2.4 GHz, CW, 19.5 dBm out-  
put power, PAVDD connected di-  
rectly to external 3.3V supply  
131.0  
mA  
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Rev. 1.2 | 35  
EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Current consumption in  
transmit mode (MCU in EM1  
@ 38.4 MHz, peripheral  
clocks disabled), T > 85 °C  
ITX_HT  
F = 915 MHz, CW, 20 dBm  
match, External PA supply = 3.3V  
134.3  
mA  
F = 915 MHz, CW, 14 dBm  
match, External PA supply con-  
nected to DCDC output  
42.5  
mA  
F = 868 MHz, CW, 20 dBm  
match, External PA supply = 3.3V  
109.8  
41.3  
mA  
mA  
F = 868 MHz, CW, 14 dBm  
match, External PA supply con-  
nected to DCDC output  
F = 490 MHz, CW, 20 dBm  
match, External PA supply = 3.3V  
130.8  
24.4  
mA  
mA  
F = 433 MHz, CW, 10 dBm  
match, External PA supply con-  
nected to DC-DC output  
F = 433 MHz, CW, 14 dBm  
match, External PA supply con-  
nected to DCDC output  
41.5  
42  
mA  
mA  
mA  
F = 315 MHz, CW, 14 dBm  
match, External PA supply con-  
nected to DCDC output  
F = 169 MHz, CW, 20 dBm  
122.8  
match, External PA supply = 3.3V  
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Rev. 1.2 | 36  
EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
4.1.6 Wake Up Times  
Table 4.9. Wake Up Times  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Wake up time from EM1  
tEM1_WU  
3
AHB  
Clocks  
Wake up from EM2  
Wake up from EM3  
tEM2_WU  
Code execution from flash  
Code execution from RAM  
Code execution from flash  
Code execution from RAM  
Executing from flash  
10  
3
µs  
µs  
µs  
µs  
µs  
tEM3_WU  
10  
3
Wake up from EM4H1  
Wake up from EM4S1  
tEM4H_WU  
tEM4S_WU  
tRESET  
86  
Executing from flash  
290  
µs  
Time from release of reset  
source to first instruction ex-  
ecution  
Soft Pin Reset released  
Any other reset released  
50  
µs  
µs  
340  
Power mode scaling time  
tSCALE  
VSCALE0 to VSCALE2, HFCLK =  
19 MHz4 2  
31.8  
4.3  
µs  
µs  
VSCALE2 to VSCALE0, HFCLK =  
19 MHz3  
Note:  
1. Time from wake up request until first instruction is executed. Wakeup results in device reset.  
2. VSCALE0 to VSCALE2 voltage change transitions occur at a rate of 10 mV/µs for approximately 20 µs. During this transition,  
peak currents will be dependent on the value of the DECOUPLE output capacitor, from 35 mA (with a 1 µF capacitor) to 70 mA  
(with a 2.7 µF capacitor).  
3. Scaling down from VSCALE2 to VSCALE0 requires approximately 2.8 µs + 29 HFCLKs.  
4. Scaling up from VSCALE0 to VSCALE2 requires approximately 30.3 µs + 28 HFCLKs.  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
4.1.7 Brown Out Detector (BOD)  
Table 4.10. Brown Out Detector (BOD)  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
1.62  
Unit  
V
DVDD BOD threshold  
VDVDDBOD  
DVDD rising  
DVDD falling (EM0/EM1)  
DVDD falling (EM2/EM3)  
1.35  
1.3  
V
V
DVDD BOD hysteresis  
DVDD BOD response time  
AVDD BOD threshold  
VDVDDBOD_HYST  
18  
2.4  
mV  
µs  
V
tDVDDBOD_DELAY Supply drops at 0.1V/µs rate  
VAVDDBOD  
AVDD rising  
1.8  
AVDD falling (EM0/EM1)  
AVDD falling (EM2/EM3)  
1.62  
1.53  
V
V
AVDD BOD hysteresis  
AVDD BOD response time  
EM4 BOD threshold  
VAVDDBOD_HYST  
20  
2.4  
mV  
µs  
V
tAVDDBOD_DELAY Supply drops at 0.1V/µs rate  
VEM4DBOD  
AVDD rising  
AVDD falling  
1.7  
1.45  
V
EM4 BOD hysteresis  
VEM4BOD_HYST  
25  
300  
mV  
µs  
EM4 BOD response time  
tEM4BOD_DELAY Supply drops at 0.1V/µs rate  
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Rev. 1.2 | 38  
EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
4.1.8 Frequency Synthesizer  
Table 4.11. Frequency Synthesizer  
Parameter  
Symbol  
Test Condition  
2400 - 2483.5 MHz  
779 - 956 MHz  
584 - 717 MHz  
358 - 574 MHz  
191 - 358 MHz  
110 - 191 MHz  
2400 - 2483.5 MHz  
779 - 956 MHz  
584 - 717 MHz  
358 - 574 MHz  
191 - 358 MHz  
110 - 191 MHz  
2400 - 2483.5 MHz  
779 - 956 MHz  
584 - 717 MHz  
358 - 574 MHz  
191 - 358 MHz  
110 - 191 MHz  
2400 - 2483.5 MHz  
779 - 956 MHz  
584 - 717 MHz  
358 - 574 MHz  
191 - 358 MHz  
110 - 191 MHz  
Min  
2400  
779  
584  
358  
191  
110  
Typ  
Max  
2483.5  
956  
717  
574  
358  
191  
73  
Unit  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
Hz  
RF synthesizer frequency  
range  
fRANGE  
LO tuning frequency resolu- fRES  
tion with 38.4 MHz crystal  
24  
Hz  
18.3  
12.2  
7.3  
Hz  
Hz  
Hz  
4.6  
Hz  
Frequency deviation resolu- dfRES  
tion with 38.4 MHz crystal  
73  
Hz  
24  
Hz  
18.3  
12.2  
7.3  
Hz  
Hz  
Hz  
4.6  
Hz  
Maximum frequency devia-  
tion with 38.4 MHz crystal  
dfMAX  
1677  
559  
419  
280  
167  
105  
kHz  
kHz  
kHz  
kHz  
kHz  
kHz  
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Rev. 1.2 | 39  
EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
4.1.9 2.4 GHz RF Transceiver Characteristics  
4.1.9.1 RF Transmitter General Characteristics for 2.4 GHz Band  
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.  
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.  
Table 4.12. RF Transmitter General Characteristics for 2.4 GHz Band  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Maximum TX power1  
POUTMAX  
19 dBm-rated part numbers.  
PAVDD connected directly to ex-  
ternal 3.3V supply  
19.5  
dBm  
Minimum active TX Power  
Output power step size  
POUTMIN  
CW  
-30  
1
dBm  
dB  
POUTSTEP  
-5 dBm< Output power < 0 dBm  
0 dBm < output power <  
POUTMAX  
0.5  
dB  
Output power variation vs  
supply at POUTMAX  
POUTVAR_V  
1.8 V < VVREGVDD < 3.3 V,  
PAVDD connected directly to ex-  
ternal supply, for output power >  
10 dBm.  
4.5  
dB  
1.8 V < VVREGVDD < 3.3 V using  
DC-DC converter  
2.2  
1.5  
2.6  
1.5  
2.0  
0.4  
dB  
dB  
Output power variation vs  
temperature at POUTMAX  
POUTVAR_T  
From -40 to +85 °C, PAVDD con-  
nected to DC-DC output  
From -40 to +125 °C, PAVDD  
connected to DC-DC output  
dB  
From -40 to +85 °C, PAVDD con-  
nected to external supply  
dB  
From -40 to +125 °C, PAVDD  
connected to external supply  
dB  
Output power variation vs RF POUTVAR_F  
frequency at POUTMAX  
Over RF tuning frequency range  
dB  
RF tuning frequency range  
FRANGE  
2400  
2483.5  
MHz  
Note:  
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-  
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.  
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Rev. 1.2 | 40  
EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
4.1.9.2 RF Receiver General Characteristics for 2.4 GHz Band  
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.  
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.  
Table 4.13. RF Receiver General Characteristics for 2.4 GHz Band  
Parameter  
Symbol  
FRANGE  
SPURRX  
Test Condition  
Min  
2400  
Typ  
Max  
2483.5  
Unit  
MHz  
dBm  
dBm  
dBm  
RF tuning frequency range  
Receive mode maximum  
spurious emission  
30 MHz to 1 GHz  
1 GHz to 12 GHz  
-57  
-47  
Max spurious emissions dur- SPURRX_FCC  
ing active receive mode, per  
FCC Part 15.109(a)  
216 MHz to 960 MHz, Conducted  
Measurement  
-55.2  
Above 960 MHz, Conducted  
Measurement  
-47.2  
-24  
dBm  
dBm  
Level above which  
RFSENSE will trigger1  
RFSENSETRIG  
CW at 2.45 GHz  
Level below which  
RFSENSE will not trigger1  
RFSENSETHRES CW at 2.45 GHz  
-50  
dBm  
1% PER sensitivity  
SENS2GFSK  
2 Mbps 2GFSK signal  
250 kbps 2GFSK signal  
-89.6  
dBm  
dBm  
-100.7  
Note:  
1. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.  
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Rev. 1.2 | 41  
EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
4.1.9.3 RF Transmitter Characteristics for 2GFSK in the 2.4GHz Band, 1 Mbps Data Rate  
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.  
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.45 GHz. Maximum duty cycle of  
85%.  
Table 4.14. RF Transmitter Characteristics for 2GFSK in the 2.4GHz Band, 1 Mbps Data Rate  
Parameter  
Symbol  
TXBW  
Test Condition  
Min  
Typ  
761  
-9.5  
Max  
Unit  
Transmit 6dB bandwidth  
Power spectral density limit  
10 dBm  
kHz  
PSDLIMIT  
Per FCC part 15.247 at 10 dBm  
dBm/  
3kHz  
Per FCC part 15.247 at 20 dBm  
-2  
10  
dBm/  
3kHz  
Per ETSI 300.328 at 10 dBm/1  
MHz  
dBm  
MHz  
dBm  
Occupied channel bandwidth OCPETSI328  
per ETSI EN300.328  
99% BW at highest and lowest  
channels in band, 10 dBm  
1.1  
-47  
Emissions of harmonics out- SPURHRM_FCC 2nd,3rd, 5, 6, 8, 9,10 harmonics;  
of-band, per FCC part  
15.247  
continuous transmission of modu-  
lated carrier  
Spurious emissions out-of-  
band, excluding harmonics  
captured in SPURHARM,FCC  
Emissions taken at  
POUTMAX, PAVDD connec-  
ted to external 3.3 V supply  
SPUROOB_FCC  
Per FCC part 15.205/15.209,  
Above 2.483 GHz or below 2.4  
GHz; continuous transmission of  
-47  
-26  
dBm  
dBc  
.
CW carrier, Restricted Bands1 2  
Per FCC part 15.247, Above  
2.483 GHz or below 2.4 GHz;  
continuous transmission of CW  
carrier, Non-Restricted Bands  
Spurious emissions out-of-  
band; per ETSI 300.328  
SPURETSI328  
[2400-BW to 2400] MHz, [2483.5  
to 2483.5+BW] MHz  
-16  
-26  
dBm  
dBm  
[2400-2BW to 2400-BW] MHz,  
[2483.5+BW to 2483.5+2BW]  
MHz per ETSI 300.328  
Spurious emissions per ETSI SPURETSI440  
EN300.440  
47-74 MHz,87.5-108 MHz,  
174-230 MHz, 470-862 MHz  
-60  
dBm  
25-1000 MHz  
1-12 GHz  
-42  
-36  
dBm  
dBm  
Note:  
1. For 2476 MHz, 1.5 dB of power backoff is used to achieve this value.  
2. For 2478 MHz, 4.2 dB of power backoff is used to achieve this value.  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
4.1.9.4 RF Receiver Characteristics for 2GFSK in the 2.4GHz Band, 1 Mbps Data Rate  
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.  
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.45 GHz.  
Table 4.15. RF Receiver Characteristics for 2GFSK in the 2.4GHz Band, 1 Mbps Data Rate  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Signal is reference signal2. Packet  
length is 20 bytes.  
Max usable receiver input  
level, 0.1% BER  
SAT  
10  
dBm  
Signal is reference signal2. Using  
DC-DC converter.  
Sensitivity, 0.1% BER  
SENS  
-93.8  
dBm  
Signal to co-channel interfer- C/ICC  
er, 0.1% BER  
Desired signal 3 dB above refer-  
ence sensitivity.  
11.25  
-4.7  
dB  
dB  
N+1 adjacent channel selec- C/I1+  
tivity, 0.1% BER, with allowa-  
ble exceptions. Desired is  
Interferer is reference signal at +1  
MHz offset. Desired frequency  
2402 MHz ≤ Fc ≤ 2480 MHz  
reference signal at -67 dBm  
N-1 adjacent channel selec- C/I1-  
tivity, 0.1% BER, with allowa-  
ble exceptions. Desired is  
Interferer is reference signal at -1  
MHz offset. Desired frequency  
2402 MHz ≤ Fc ≤ 2480 MHz  
-4.8  
-45.8  
-49.4  
dB  
dB  
dB  
reference signal at -67 dBm  
Alternate selectivity, 0.1%  
BER, with allowable excep-  
tions. Desired is reference  
signal at -67 dBm  
C/I2  
Interferer is reference signal at ± 2  
MHz offset. Desired frequency  
2402 MHz ≤ Fc ≤ 2480 MHz  
Alternate selectivity, 0.1%  
BER, with allowable excep-  
tions. Desired is reference  
signal at -67 dBm  
C/I3  
Interferer is reference signal at ± 3  
MHz offset. Desired frequency  
2404 MHz ≤ Fc ≤ 2480 MHz  
Selectivity to image frequen- C/IIM  
cy, 0.1% BER. Desired is ref-  
erence signal at -67 dBm  
Interferer is reference signal at im-  
age frequency with 1 MHz preci-  
sion  
-40.5  
-49.4  
dB  
dB  
Selectivity to image frequen- C/IIM+1  
cy ± 1 MHz, 0.1% BER. De-  
sired is reference signal at  
-67 dBm  
Interferer is reference signal at im-  
age frequency ± 1 MHz with 1  
MHz precision  
Blocking, less than 0.1%  
BER. Desired is -67dBm  
BLE reference signal at  
2426MHz. Interferer is CW in  
BLOCKOOB  
Interferer frequency 30 MHz ≤ f ≤  
2000 MHz  
-5  
dBm  
dBm  
Interferer frequency 2003 MHz ≤ f  
≤ 2399 MHz3  
-10  
OOB range1  
Interferer frequency 2484 MHz ≤ f  
≤ 2997 MHz  
-10  
-10  
-17  
dBm  
dBm  
dBm  
Interferer frequency 3 GHz ≤ f ≤ 6  
GHz  
Interferer frequency 6 GHz ≤ f ≤  
12.75 GHz  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
Parameter  
Note:  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
1. Interferer max power limited by equipment capabilities and path loss. Minimum specified at 25 °C.  
2. Reference signal is defined 2GFSK at -67 dBm, Modulation index = 0.5, BT = 0.5, Bit rate = 1 Mbps, desired data = PRBS9;  
interferer data = PRBS15; frequency accuracy better than 1 ppm.  
3. Except -13 dBm at Desired Frequency - Crystal Frequency.  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
4.1.9.5 RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band  
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.  
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz. Maximum duty cycle of  
66%.  
Table 4.16. RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Error vector magnitude (off- EVM  
set EVM), per  
802.15.4-2011, not including  
2415 MHz channel  
Average across frequency. Signal  
is DSSS-OQPSK reference pack-  
et1  
3.8  
% rms  
Power spectral density limit  
PSDLIMIT  
Relative, at carrier ± 3.5 MHz, out-  
put power at POUTMAX  
-26  
-36  
dBc/  
100kHz  
Absolute, at carrier ± 3.5 MHz,  
dBm/  
100kHz  
3
output power at POUTMAX  
Per FCC part 15.247, output pow-  
er at POUTMAX  
-4.0  
dBm/  
3kHz  
ETSI  
12.1  
2.25  
dBm  
MHz  
Occupied channel bandwidth OCPETSI328  
per ETSI EN300.328  
99% BW at highest and lowest  
channels in band  
Spurious emissions of har-  
monics in restricted bands  
per FCC Part 15.205/15.209,  
Emissions taken at  
POUTMAX, PAVDD connec-  
ted to external 3.3 V supply,  
Test Frequency is 2450 MHz  
SPURHRM_FCC_ Continuous transmission of modu-  
-45.8  
dBm  
lated carrier  
R
Spurious emissions of har-  
monics in non-restricted  
bands per FCC Part  
SPURHRM_FCC_ Continuous transmission of modu-  
-26  
dBc  
lated carrier  
NRR  
15.247/15.35, Emissions tak-  
en at POUTMAX, PAVDD  
connected to external 3.3 V  
supply, Test Frequency is  
2450 MHz  
Spurious emissions out-of-  
band (above 2.483 GHz or  
below 2.4 GHz) in restricted  
bands, per FCC part  
15.205/15.209, Emissions  
taken at POUTMAX, PAVDD  
connected to external 3.3 V  
supply, Test Frequency =  
2450 MHz  
SPUROOB_FCC_ Restricted bands 30-88 MHz; con-  
-61  
-58  
-55  
-47  
dBm  
dBm  
dBm  
dBm  
tinuous transmission of modulated  
R
carrier  
Restricted bands 88-216 MHz;  
continuous transmission of modu-  
lated carrier  
Restricted bands 216-960 MHz;  
continuous transmission of modu-  
lated carrier  
Restricted bands >960 MHz; con-  
tinuous transmission of modulated  
carrier4 5  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Spurious emissions out-of-  
band in non-restricted bands  
per FCC Part 15.247, Emis-  
SPUROOB_FCC_ Above 2.483 GHz or below 2.4  
-26  
dBc  
GHz; continuous transmission of  
NR  
modulated carrier  
sions taken at POUTMAX  
,
PAVDD connected to exter-  
nal 3.3 V supply, Test Fre-  
quency = 2450 MHz  
Spurious emissions out-of-  
band; per ETSI 300.3282  
SPURETSI328  
[2400-BW to 2400], [2483.5 to  
2483.5+BW];  
-16  
-26  
dBm  
dBm  
[2400-2BW to 2400-BW],  
[2483.5+BW to 2483.5+2BW]; per  
ETSI 300.328  
Spurious emissions per ETSI SPURETSI440  
EN300.4402  
47-74 MHz,87.5-108 MHz,  
174-230 MHz, 470-862 MHz  
-60  
-42  
-36  
dBm  
dBm  
dBm  
25-1000 MHz, excluding above  
frequencies  
1G-14G  
Note:  
1. Reference packet is defined as 20 octet PSDU, modulated according to 802.15.4-2011 DSSS-OQPSK in the 2.4GHz band, with  
pseudo-random packet data content.  
2. Specified at maximum power output level of 10 dBm.  
3. For 2415 MHz, 2 dB of power backoff is used to achieve this value.  
4. For 2475 MHz, 2 dB of power backoff is used to achieve this value.  
5. For 2480 MHz, 13 dB of power backoff is used to achieve this value.  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
4.1.9.6 RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band  
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.  
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.  
Table 4.17. RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Signal is reference signal4. Packet  
length is 20 octets.  
Max usable receiver input  
level, 1% PER  
SAT  
10  
dBm  
Sensitivity, 1% PER  
SENS  
Signal is reference signal. Packet  
length is 20 octets. Using DC-DC  
converter.  
-103.3  
-103.3  
dBm  
dBm  
Signal is reference signal. Packet  
length is 20 octets. Without DC-  
DC converter.  
Co-channel interferer rejec- CCR  
tion, 1% PER  
Desired signal 3 dB above sensi-  
tivity limit  
-4.6  
40.7  
47  
dB  
dB  
dB  
High-side adjacent channel  
rejection, 1% PER. Desired  
is reference signal at 3dB  
above reference sensitivity  
ACRP1  
Interferer is reference signal at +1  
channel-spacing.  
Interferer is filtered reference sig-  
nal2 at +1 channel-spacing.  
level5  
Interferer is CW at +1 channel-  
spacing3.  
60.1  
dB  
Low-side adjacent channel  
rejection, 1% PER. Desired  
is reference signal at 3dB  
above reference sensitivity  
ACRM1  
ACR2  
IR  
Interferer is reference signal at -1  
channel-spacing.  
40.8  
47.5  
dB  
dB  
Interferer is filtered reference sig-  
nal2 at -1 channel-spacing.  
level5  
Interferer is CW at -1 channel-  
spacing.  
61.6  
51.5  
53.7  
dB  
dB  
dB  
Alternate channel rejection,  
1% PER. Desired is refer-  
ence signal at 3dB above  
reference sensitivity level5  
Interferer is reference signal at ± 2  
channel-spacing  
Interferer is filtered reference sig-  
nal2 at ± 2 channel-spacing  
Interferer is CW at ± 2 channel-  
spacing  
66.4  
50.4  
dB  
dB  
Interferer is CW in image band3  
Image rejection , 1% PER,  
Desired is reference signal at  
3dB above reference sensi-  
tivity level5  
Blocking rejection of all other BLOCK  
channels. 1% PER, Desired  
is reference signal at 3dB  
above reference sensitivity  
level5. Interferer is reference  
signal  
Interferer frequency < Desired fre-  
quency - 3 channel-spacing  
58.5  
56.4  
dB  
dB  
Interferer frequency > Desired fre-  
quency + 3 channel-spacing  
Blocking rejection of 802.11g BLOCK80211G  
signal centered at +12MHz  
or -13MHz1  
Desired is reference signal at 6dB  
above reference sensitivity level5  
54.8  
dB  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Upper limit of input power  
range over which RSSI reso-  
lution is maintained  
RSSIMAX  
5
dBm  
Lower limit of input power  
range over which RSSI reso-  
lution is maintained  
RSSIMIN  
-98  
dBm  
RSSI resolution  
RSSIRES  
RSSILIN  
over RSSIMIN to RSSIMAX  
0.25  
+/-6  
dB  
dB  
RSSI accuracy in the linear  
region as defined by  
802.15.4-2003  
Note:  
1. This is an IEEE 802.11b/g ERP-PBCC 22 MBit/s signal as defined by the IEEE 802.11 specification and IEEE 802.11g adden-  
dum.  
2. Filter is characterized as a symmetric bandpass centered on the adjacent channel having a 3dB bandwidth of 4.6 MHz and stop-  
band rejection better than 26 dB beyond 3.15 MHz from the adjacent carrier.  
3. Due to low-IF frequency, there is some overlap of adjacent channel and image channel bands. Adjacent channel CW blocker  
tests place the Interferer center frequency at the Desired frequency ± 5 MHz on the channel raster, whereas the image rejection  
test places the CW interferer near the image frequency of the Desired signal carrier, regardless of the channel raster.  
4. Reference signal is defined as O-QPSK DSSS per 802.15.4, Frequency range = 2400-2483.5 MHz, Symbol rate = 62.5 ksym-  
bols/s.  
5. Reference sensitivity level is -85 dBm.  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
4.1.10 Sub-GHz RF Transceiver Characteristics  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
4.1.10.1 Sub-GHz RF Transmitter characteristics for 915 MHz Band  
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA  
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 915 MHz.  
Table 4.18. Sub-GHz RF Transmitter characteristics for 915 MHz Band  
Parameter  
Symbol  
FRANGE  
Test Condition  
Min  
902  
18  
Typ  
Max  
930  
Unit  
MHz  
dBm  
RF tuning frequency range  
Maximum TX Power1  
POUTMAX  
External PA supply = 3.3V, 20  
dBm output power setting  
19.8  
23.3  
External PA supply connected to  
DC-DC output, 14 dBm output  
power setting  
12.6  
14.2  
16.1  
dBm  
Minimum active TX Power  
Output power step size  
POUTMIN  
-45.5  
0.5  
dBm  
dB  
POUTSTEP  
POUTVAR_V  
output power > 0 dBm  
Output power variation vs  
supply at POUTMAX  
1.8 V < VVREGVDD < 3.3 V, Exter-  
nal PA supply = 3.3 V, T = 25 °C  
4.8  
dB  
1.8 V < VVREGVDD < 3.3 V, Exter-  
nal PA supply connected to DC-  
DC output, T = 25 °C  
1.9  
dB  
Output power variation vs  
temperature, peak to peak  
POUTVAR_T  
-40 to +85 °C with External PA  
supply = 3.3 V  
0.6  
0.8  
0.7  
1.3  
1.6  
1.4  
dB  
dB  
dB  
-40 to +125 °C with External PA  
supply = 3.3 V  
-40 to +85 °C with External PA  
supply connected to DC-DC out-  
put  
-40 to +125 °C with External PA  
supply connected to DC-DC out-  
put  
1.0  
1.9  
dB  
Output power variation vs RF POUTVAR_F  
frequency  
External PA supply = 3.3 V, T =  
25 °C  
0.2  
0.3  
-45  
-26  
0.6  
0.6  
-42  
-20  
dB  
dB  
External PA supply connected to  
DC-DC output, T = 25 °C  
Spurious emissions of har-  
monics at 20 dBm output  
power, Conducted measure-  
ment, 20dBm match, Exter-  
nal PA supply = 3.3V, Test  
Frequency = 915 MHz  
SPURHARM_FCC In restricted bands, per FCC Part  
dBm  
dBc  
15.205 / 15.209  
_20  
In non-restricted bands, per FCC  
Part 15.231  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Spurious emissions out-of-  
band at 20 dBm output pow-  
er, Conducted measurement,  
20dBm match, External PA  
supply = 3.3V, Test Frequen-  
cy = 915 MHz  
SPUROOB_FCC_ In non-restricted bands, per FCC  
-26  
-20  
dBc  
Part 15.231  
20  
In restricted bands (30-88 MHz),  
per FCC Part 15.205 / 15.209  
-52  
-61  
-58  
-46  
-56  
-52  
dBm  
dBm  
dBm  
In restricted bands (88-216 MHz),  
per FCC Part 15.205 / 15.209  
In restricted bands (216-960  
MHz), per FCC Part 15.205 /  
15.209  
In restricted bands (>960 MHz),  
per FCC Part 15.205 / 15.209  
-47  
-47  
-26  
-42  
-42  
-20  
dBm  
dBm  
dBc  
Spurious emissions of har-  
monics at 14 dBm output  
power, Conducted measure-  
ment, 14dBm match, Exter-  
nal PA supply connected to  
DC-DC output, Test Fre-  
quency = 915 MHz  
SPURHARM_FCC In restricted bands, per FCC Part  
15.205 / 15.209  
_14  
In non-restricted bands, per FCC  
Part 15.231  
Spurious emissions out-of-  
band at 14 dBm output pow-  
er, Conducted measurement,  
14dBm match, External PA  
supply connected to DC-DC  
output, Test Frequency =  
915 MHz  
SPUROOB_FCC_ In non-restricted bands, per FCC  
-26  
-52  
-61  
-58  
-20  
-46  
-56  
-52  
dBc  
dBm  
dBm  
dBm  
Part 15.231  
14  
In restricted bands (30-88 MHz),  
per FCC Part 15.205 / 15.209  
In restricted bands (88-216 MHz),  
per FCC Part 15.205 / 15.209  
In restricted bands (216-960  
MHz), per FCC Part 15.205 /  
15.209  
In restricted bands (>960 MHz),  
per FCC Part 15.205 / 15.209  
-45  
1.0  
-42  
2.8  
dBm  
Error vector magnitude (off- EVM  
set EVM), per 802.15.4-2011  
Signal is DSSS-OQPSK reference  
packet. Modulated according to  
802.15.4-2011 DSSS-OQPSK in  
the 915MHz band, with pseudo-  
random packet data content. Ex-  
ternal PA supply = 3.3V.  
%rms  
Power spectral density limit  
PSD  
Relative, at carrier ± 1.2 MHz.  
Average spectral power shall be  
measured using a 100kHz resolu-  
tion bandwidth. The reference lev-  
el shall be the highest average  
spectral power measured within ±  
600kHz of the carrier frequency.  
External PA supply = 3.3V.  
-37.1  
-24.8  
dBc/  
100kHz  
Absolute, at carrier ± 1.2 MHz.  
Average spectral power shall be  
measured using a 100kHz resolu-  
tion bandwidth. External PA sup-  
ply = 3.3V.  
-24.2  
-20  
dBm/  
100kHz  
Note:  
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-  
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
4.1.10.2 Sub-GHz RF Receiver Characteristics for 915 MHz Band  
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA  
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 915 MHz.  
Table 4.19. Sub-GHz RF Receiver Characteristics for 915 MHz Band  
Parameter  
Symbol  
Test Condition  
Min  
902  
Typ  
Max  
930  
Unit  
MHz  
dBm  
Tuning frequency range  
FRANGE  
Max usable input level, 0.1% SAT500K  
BER  
Desired is reference 500 kbps  
GFSK signal4  
10  
Sensitivity  
SENS  
Desired is reference 4.8 kbps  
-107.8  
-100.7  
-99.5  
dBm  
dBm  
OOK signal3, 20% PER, T ≤ 85 °C  
Desired is reference 4.8 kbps  
OOK signal3, 20% PER, T > 85  
°C  
Desired is reference 600 bps  
GFSK signal6, 0.1% BER  
-126.2  
-108.2  
dBm  
dBm  
Desired is reference 50 kbps  
-104.2  
GFSK signal5, 0.1% BER, T ≤ 85  
°C  
Desired is reference 50 kbps  
GFSK signal5, 0.1% BER, T > 85  
°C  
-105.1  
-103.1  
-101.5  
-101.3  
-93.2  
dBm  
dBm  
dBm  
dBm  
dBm  
Desired is reference 100 kbps  
GFSK signal1, 0.1% BER, T ≤ 85  
°C  
Desired is reference 100 kbps  
GFSK signal1, 0.1% BER, T > 85  
°C  
Desired is reference 500 kbps  
GFSK signal4, 0.1% BER, T ≤ 85  
°C  
-98.2  
Desired is reference 500 kbps  
-93.1  
GFSK signal4, 0.1% BER, T > 85  
°C  
Desired is reference 400 kbps  
-95.2  
-91  
-91  
dBm  
dBm  
dBm  
GFSK signal2, 1% PER, T ≤ 85 °C  
Desired is reference 400 kbps  
GFSK signal2, 1% PER, T > 85 °C  
Desired is reference O-QPSK  
-100.1  
DSSS signal7, 1% PER, Payload  
length is 20 octets  
Level above which  
RFSENSETRIG  
CW at 915 MHz  
-28.1  
-50  
dBm  
dBm  
RFSENSE will trigger8  
Level below which  
RFSENSE will not trigger8  
RFSENSETHRES CW at 915 MHz  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Desired is 4.8 kbps OOK signal3  
at 3dB above sensitivity level,  
20% PER  
Adjacent channel selectivity, C/I1  
Interferer is CW at ± 1 ×  
channel-spacing  
48.1  
dB  
Desired is 600 bps GFSK signal6  
at 3dB above sensitivity level,  
0.1% BER  
71.4  
49.8  
51.1  
48.1  
41.4  
49.1  
56.3  
74.7  
55.8  
56.4  
51.8  
46.8  
57.7  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
Desired is 50 kbps GFSK signal5  
at 3dB above sensitivity level,  
0.1% BER  
Desired is 100 kbps GFSK signal1  
at 3dB above sensitivity level,  
0.1% BER  
Desired is 500 kbps GFSK signal4  
at 3dB above sensitivity level,  
0.1% BER  
Desired is 400 kbps 4GFSK sig-  
nal2 at 3dB above sensitivity level,  
0.1% BER  
Desired is reference O-QPSK  
DSSS signal7 at 3dB above sensi-  
tivity level, 1% PER  
Desired is 4.8 kbps OOK signal3  
at 3dB above sensitivity level,  
20% PER  
Alternate channel selectivity, C/I2  
Interferer is CW at ± 2 ×  
channel-spacing  
Desired is 600 bps GFSK signal6  
at 3dB above sensitivity level,  
0.1% BER  
Desired is 50 kbps GFSK signal5  
at 3dB above sensitivity level,  
0.1% BER  
Desired is 100 kbps GFSK signal1  
at 3dB above sensitivity level,  
0.1% BER  
Desired is 500 kbps GFSK signal4  
at 3dB above sensitivity level,  
0.1% BER  
Desired is 400 kbps 4GFSK sig-  
nal2 at 3dB above sensitivity level,  
0.1% BER  
Desired is reference O-QPSK  
DSSS signal7 at 3dB above sensi-  
tivity level, 1% PER  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Desired is 4.8 kbps OOK signal3  
at 3dB above sensitivity level,  
20% PER  
Image rejection, Interferer is C/IIMAGE  
CW at image frequency  
48.4  
dB  
Desired is 50 kbps GFSK signal5  
at 3dB above sensitivity level,  
0.1% BER  
54.9  
49.1  
47.9  
42.8  
48.9  
dB  
dB  
dB  
dB  
dB  
Desired is 100 kbps GFSK signal1  
at 3dB above sensitivity level,  
0.1% BER  
Desired is 500 kbps GFSK signal4  
at 3dB above sensitivity level,  
0.1% BER  
Desired is 400 kbps 4GFSK sig-  
nal2 at 3dB above sensitivity level,  
0.1% BER  
Desired is reference O-QPSK  
DSSS signal7 at 3dB above sensi-  
tivity level, 1% PER  
Blocking selectivity, 0.1%  
BER. Desired is 100 kbps  
GFSK signal at 3dB above  
sensitivity level  
C/IBLOCKER  
Interferer CW at Desired ± 1 MHz  
Interferer CW at Desired ± 2 MHz  
58.7  
62.5  
76.4  
dB  
dB  
dB  
Interferer CW at Desired ± 10  
MHz  
Desired is 100 kbps GFSK signal1  
at 3dB above sensitivity level  
Intermod selectivity, 0.1%  
BER. CW interferers at 400  
kHz and 800 kHz offsets  
C/IIM  
45  
5
dB  
Upper limit of input power  
range over which RSSI reso-  
lution is maintained  
RSSIMAX  
RSSIMIN  
RSSIRES  
dBm  
dBm  
Lower limit of input power  
range over which RSSI reso-  
lution is maintained  
-98  
RSSI resolution  
Over RSSIMIN to RSSIMAX range  
216-960 MHz  
0.25  
-55  
dBm  
dBm  
dBm  
Max spurious emissions dur- SPURRX_FCC  
ing active receive mode, per  
FCC Part 15.109(a)  
-49.2  
-41.2  
Above 960 MHz  
-47  
Max spurious emissions dur- SPURRX_ARIB  
ing active receive mode,per  
ARIB STD-T108 Section 3.3  
Below 710 MHz, RBW=100kHz  
710-900 MHz, RBW=1MHz  
900-915 MHz, RBW=100kHz  
915-930 MHz, RBW=100kHz  
930-1000 MHz, RBW=100kHz  
Above 1000 MHz, RBW=1MHz  
-60  
-61  
-61  
-61  
-60  
-53  
-54  
-55  
-55  
-55  
-54  
-47  
dBm  
dBm  
dBm  
dBm  
dBm  
dBm  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
Parameter  
Note:  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
1. Definition of reference signal is 100 kbps 2GFSK, BT=0.5, Δf = 50 kHz, RX channel BW = 198.024 kHz, channel spacing = 400  
kHz.  
2. Definition of reference signal is 400 kbps 4GFSK, BT=0.5, inner deviation = 33.3 kHz, RX channel BW = 368.920 kHz, channel  
spacing = 600 kHz.  
3. Definition of reference signal is 4.8 kbps OOK, RX channel BW = 306.036 kHz, channel spacing = 500 kHz.  
4. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 175 kHz, RX channel BW = 835.076 kHz, channel spacing = 1  
MHz.  
5. Definition of reference signal is 50 kbps 2GFSK, BT=0.5, Δf = 25 kHz, RX channel BW = 99.012 kHz, channel spacing = 200 kHz.  
6. Definition of reference signal is 600 bps 2GFSK, BT=0.5, Δf = 0.3 kHz, RX channel BW = 1.2 kHz, channel spacing = 300 kHz.  
7. Definition of reference signal is O-QPSK DSSS per 802.15.4, Frequency Range = 902-928 MHz, Data rate = 250 kbps, 16-chip  
PN sequence mapping.  
8. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
4.1.10.3 Sub-GHz RF Transmitter characteristics for 868 MHz Band  
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA  
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 868 MHz.  
Table 4.20. Sub-GHz RF Transmitter characteristics for 868 MHz Band  
Parameter  
Symbol  
FRANGE  
Test Condition  
Min  
863  
17.1  
Typ  
Max  
876  
Unit  
MHz  
dBm  
RF tuning frequency range  
Maximum TX Power1  
POUTMAX  
External PA connected directly to  
3.3V supply, 20 dBm output pow-  
er setting  
19.3  
22.9  
External PA supply connected to  
DC-DC output, 14 dBm output  
power setting  
11.4  
13.7  
16.5  
dBm  
Minimum active TX Power  
Output power step size  
POUTMIN  
-43.5  
0.5  
5
dBm  
dB  
POUTSTEP  
POUTVAR_V  
output power > 0 dBm  
Output power variation vs  
supply at POUTMAX  
1.8 V < VVREGVDD < 3.3 V, Exter-  
nal PA supply = 3.3 V, T = 25 °C  
dB  
1.8 V < VVREGVDD < 3.3 V, Exter-  
nal PA supply connected to DC-  
DC output, T = 25 °C  
2
dB  
Output power variation vs  
temperature, peak to peak  
POUTVAR_T  
-40 to +85 °C with External PA  
supply = 3.3 V  
0.6  
0.8  
0.5  
0.9  
1.3  
1.2  
dB  
dB  
dB  
-40 to +125 °C with External PA  
supply = 3.3 V  
-40 to +85 °C with External PA  
supply connected to DC-DC out-  
put  
-40 to +125 °C with External PA  
supply connected to DC-DC out-  
put  
0.7  
1.5  
dB  
Output power variation vs RF POUTVAR_F  
frequency  
External PA supply = 3.3 V, T =  
25 °C  
0.2  
0.2  
-35  
0.6  
0.8  
-30  
dB  
dB  
External PA supply connected to  
DC-DC output, T = 25 °C  
Spurious emissions of har-  
monics, Conducted meas-  
urement, External PA supply  
connected to DC-DC output,  
Test Frequency = 868 MHz  
SPURHARM_ETSI Per ETSI EN 300-220, Section  
7.8.2.1  
dBm  
Spurious emissions out-of-  
band, Conducted measure-  
ment, External PA supply  
connected to DC-DC output,  
Test Frequency = 868 MHz  
SPUROOB_ETSI Per ETSI EN 300-220, Section  
7.8.2.1 (47-74 MHz, 87.5-118  
MHz, 174-230 MHz, and 470-862  
MHz)  
-59  
-54  
dBm  
Per ETSI EN 300-220, Section  
7.8.2.1 (other frequencies below 1  
GHz)  
-42  
-36  
-36  
-30  
dBm  
dBm  
Per ETSI EN 300-220, Section  
7.8.2.1 (frequencies above 1  
GHz)  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Error vector magnitude (off- EVM  
set EVM), per 802.15.4-2015  
Signal is DSSS-BPSK reference  
packet. Modulated according to  
802.15.4-2015 DSSS-BPSK in the  
868MHz band, with pseudo-ran-  
dom packet data content. External  
PA supply connected to external  
3.3V supply  
5.7  
%rms  
Note:  
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-  
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
4.1.10.4 Sub-GHz RF Receiver Characteristics for 868 MHz Band  
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA  
Supply. RFVDD and external PA supply paths is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 868 MHz.  
Table 4.21. Sub-GHz RF Receiver Characteristics for 868 MHz Band  
Parameter  
Symbol  
Test Condition  
Min  
863  
Typ  
Max  
876  
Unit  
MHz  
dBm  
Tuning frequency range  
FRANGE  
Max usable input level, 0.1% SAT2k4  
BER  
Desired is reference 2.4 kbps  
GFSK signal1  
10  
Max usable input level, 0.1% SAT38k4  
BER  
Desired is reference 38.4 kbps  
GFSK signal2  
10  
dBm  
dBm  
dBm  
Sensitivity  
SENS  
Desired is reference 2.4 kbps  
GFSK signal1, 0.1% BER  
-120.6  
-109.5  
Desired is reference 38.4 kbps  
-105.4  
GFSK signal2, 0.1% BER, T ≤ 85  
°C  
Desired is reference 38.4 kbps  
-105.2  
dBm  
GFSK signal2, 0.1% BER, T > 85  
°C  
Desired is reference 500 kbps  
GFSK signal3, 0.1% BER  
-96.4  
-28.1  
-50  
dBm  
dBm  
dBm  
dB  
Level above which  
RFSENSETRIG  
CW at 868 MHz  
RFSENSE will trigger4  
Level below which  
RFSENSE will not trigger4  
RFSENSETHRES CW at 868 MHz  
Desired is 2.4 kbps GFSK signal1  
at 3dB above sensitivity level,  
0.1% BER  
Adjacent channel selectivity, C/I1  
Interferer is CW at ± 1 ×  
channel-spacing  
44.5  
56.9  
Desired is 38.4kbps GFSK signal2  
at 3dB above sensitivity level,  
0.1% BER  
35.4  
43  
dB  
dB  
dB  
dB  
dB  
Desired is 2.4kbps GFSK signal1  
at 3dB above sensitivity level,  
0.1% BER  
Alternate channel selectivity, C/I2  
Interferer is CW at ± 2 ×  
channel-spacing  
56.8  
48.2  
50.2  
48.7  
Desired is 38.4kbps GFSK signal2  
at 3dB above sensitivity level,  
0.1% BER  
Desired is 2.4kbps GFSK signal1  
at 3dB above sensitivity level,  
0.1% BER  
Image rejection, Interferer is C/IIMAGE  
CW at image frequency  
Desired is 38.4kbps GFSK signal2  
at 3dB above sensitivity level,  
0.1% BER  
Blocking selectivity, 0.1%  
BER. Desired is 2.4 kbps  
GFSK signal1 at 3 dB above  
sensitivity level  
C/IBLOCKER  
Interferer CW at Desired ± 1 MHz  
Interferer CW at Desired ± 2 MHz  
72.1  
77.5  
90.4  
dB  
dB  
dB  
Interferer CW at Desired ± 10  
MHz  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Upper limit of input power  
range over which RSSI reso-  
lution is maintained  
RSSIMAX  
5
dBm  
Lower limit of input power  
range over which RSSI reso-  
lution is maintained  
RSSIMIN  
RSSIRES  
-98  
dBm  
RSSI resolution  
Over RSSIMIN to RSSIMAX range  
30 MHz to 1 GHz  
0.25  
-63  
dBm  
dBm  
dBm  
Max spurious emissions dur- SPURRX  
ing active receive mode  
-57  
-47  
1 GHz to 12 GHz  
-53  
Note:  
1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 4.797 kHz, channel spacing = 12.5  
kHz.  
2. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 74.809 kHz, channel spacing = 100  
kHz.  
3. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 125 kHz, RX channel BW = 753.320 kHz.  
4. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
4.1.10.5 Sub-GHz RF Transmitter characteristics for 490 MHz Band  
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA  
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 490 MHz.  
Table 4.22. Sub-GHz RF Transmitter characteristics for 490 MHz Band  
Parameter  
Symbol  
FRANGE  
Test Condition  
Min  
470  
18.1  
Typ  
Max  
510  
Unit  
MHz  
dBm  
RF tuning frequency range  
Maximum TX Power1  
POUTMAX  
External PA supply = 3.3V  
20.3  
23.7  
Minimum active TX Power  
Output power step size  
POUTMIN  
-44.9  
0.5  
dBm  
dB  
POUTSTEP  
POUTVAR_V  
output power > 0 dBm  
Output power variation vs  
supply, peak to peak  
at 20 dBm;1.8 V < VVREGVDD  
<
4.3  
dB  
3.3 V, External PA supply connec-  
ted directly to external supply, T =  
25 °C  
Output power variation vs  
temperature, peak to peak  
POUTVAR_T  
-40 to +85 °C at 20 dBm  
-40 to +125 °C at 20 dBm  
T = 25 °C  
0.2  
0.3  
0.2  
0.9  
1.3  
0.4  
dB  
dB  
dB  
Output power variation vs RF POUTVAR_F  
frequency  
Harmonic emissions, 20  
dBm output power setting,  
490 MHz  
SPURHARM_CN Per China SRW Requirement,  
Section 2.1, frequencies below  
1GHz  
-40  
-36  
-54  
-36  
-30  
dBm  
dBm  
dBm  
Per China SRW Requirement,  
Section 2.1, frequencies above  
1GHz  
Spurious emissions, 20 dBm SPUROOB_CN  
output power setting, 490  
MHz  
Per China SRW Requirement,  
Section 3 (48.5-72.5MHz,  
76-108MHz, 167-223MHz,  
470-556MHz, and 606-798MHz)  
Per China SRW Requirement,  
Section 2.1 (other frequencies be-  
low 1GHz)  
-42  
-36  
dBm  
dBm  
Per China SRW Requirement,  
Section 2.1 (frequencies above  
1GHz)  
Note:  
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-  
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
4.1.10.6 Sub-GHz RF Receiver Characteristics for 490 MHz Band  
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA  
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 490 MHz.  
Table 4.23. Sub-GHz RF Receiver Characteristics for 490 MHz Band  
Parameter  
Symbol  
Test Condition  
Min  
470  
Typ  
Max  
510  
Unit  
dBm  
dBm  
Tuning frequency range  
FRANGE  
Max usable input level, 0.1% SAT2k4  
BER  
Desired is reference 2.4 kbps  
GFSK signal3  
10  
Max usable input level, 0.1% SAT38k4  
BER  
Desired is reference 38.4 kbps  
GFSK signal4  
10  
dBm  
dBm  
dBm  
Sensitivity  
SENS  
Desired is reference 2.4 kbps  
GFSK signal3, 0.1% BER  
-122.2  
-111.4  
Desired is reference 38.4 kbps  
-108.9  
GFSK signal4, 0.1% BER, T ≤ 85  
°C  
Desired is reference 38.4 kbps  
GFSK signal4, 0.1% BER, T > 85  
°C  
-116.8  
-107.9  
-113.9  
-113.2  
-104.7  
-104  
dBm  
dBm  
dBm  
dBm  
dBm  
Desired is reference 10 kbps  
GFSK signal2, 0.1% BER, T ≤ 85  
°C  
Desired is reference 10 kbps  
GFSK signal2, 0.1% BER, T > 85  
°C  
Desired is reference 100 kbps  
GFSK signal1, 0.1% BER, T ≤ 85  
°C  
-107.3  
Desired is reference 100 kbps  
GFSK signal1, 0.1% BER, T > 85  
°C  
Level above which  
RFSENSETRIG  
Desired is reference 100 kbps  
GFSK signal1, 0.1% BER  
48  
-28.1  
-50  
dBm  
dBm  
dB  
RFSENSE will trigger5  
Level below which  
RFSENSE will not trigger5  
RFSENSETHRES CW at 490 MHz  
Desired is 2.4 kbps GFSK signal3  
at 3dB above sensitivity level,  
0.1% BER  
Adjacent channel selectivity, C/I1  
Interferer is CW at ± 1 ×  
channel-spacing  
60.3  
Desired is 38.4kbps GFSK signal4  
at 3dB above sensitivity level,  
0.1% BER  
38.3  
45.6  
60.4  
52.6  
dB  
dB  
dB  
Desired is 2.4kbps GFSK signal3  
at 3dB above sensitivity level,  
0.1% BER  
Alternate channel selectivity, C/I2  
Interferer is CW at ± 2 ×  
channel-spacing  
Desired is 38.4kbps GFSK signal4  
at 3dB above sensitivity level,  
0.1% BER  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Desired is 2.4kbps GFSK signal3  
at 3dB above sensitivity level,  
0.1% BER  
Image rejection, Interferer is C/IIMAGE  
CW at image frequency  
56.5  
dB  
Desired is 38.4kbps GFSK signal4  
at 3dB above sensitivity level,  
0.1% BER  
54.1  
dB  
Blocking selectivity, 0.1%  
BER. Desired is 2.4 kbps  
GFSK signal3 at 3 dB above  
sensitivity level  
C/IBLOCKER  
Interferer CW at Desired ± 1 MHz  
Interferer CW at Desired ± 2 MHz  
73.9  
75.4  
90.2  
dB  
dB  
dB  
Interferer CW at Desired ± 10  
MHz  
Upper limit of input power  
range over which RSSI reso-  
lution is maintained  
RSSIMAX  
RSSIMIN  
RSSIRES  
5
dBm  
dBm  
Lower limit of input power  
range over which RSSI reso-  
lution is maintained  
-98  
RSSI resolution  
Over RSSIMIN to RSSIMAX range  
30 MHz to 1 GHz  
0.25  
-53  
dBm  
dBm  
dBm  
Max spurious emissions dur- SPURRX  
ing active receive mode  
-47  
-47  
1 GHz to 12 GHz  
-53  
Note:  
1. Definition of reference signal is 100 kbps 2GFSK, BT=0.5, Δf = 50 kHz, RX channel BW = 198.024 kHz.  
2. Definition of reference signal is 10 kbps 2GFSK, BT=0.5, Δf = 5 kHz, RX channel BW = 20.038 kHz.  
3. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 4.798 kHz, channel spacing = 12.5  
kHz.  
4. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 74.809 kHz, channel spacing = 100  
kHz.  
5. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.  
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EFR32FG14 Flex Gecko Proprietary Protocol SoC Family Data Sheet  
Electrical Specifications  
4.1.10.7 Sub-GHz RF Transmitter characteristics for 433 MHz Band  
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA  
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 433 MHz.  
Table 4.24. Sub-GHz RF Transmitter characteristics for 433 MHz Band  
Parameter  
Symbol  
FRANGE  
Test Condition  
Min  
426  
12.5  
Typ  
Max  
445  
Unit  
MHz  
dBm  
RF tuning frequency range  
Maximum TX Power1  
POUTMAX  
External PA supply connected to  
DC-DC output, 14dBm output  
power  
15.1  
17.4  
External PA supply connected to  
DC-DC output, 10dBm output  
power  
8.3  
10.6  
13.3  
dBm  
Minimum active TX Power  
Output power step size  
POUTMIN  
-42  
0.5  
1.7  
dBm  
dB  
POUTSTEP  
POUTVAR_V  
output power > 0 dBm  
Output power variation vs  
supply, peak to peak, Pout =  
10dBm  
At 10 dBm;1.8 V < VVREGVDD  
3.3 V, External PA supply = DC-  
DC output, T = 25 °C  
<
dB  
Output power variation vs  
temperature, peak to peak,  
Pout= 10dBm  
POUTVAR_T  
-40 to +85C at 10dBm  
-40 to +125C at 10dBm  
0.5  
<