EFR32BG22C224F512IM40-C [SILICON]
EFR32BG22 Wireless Gecko SoC Family;型号: | EFR32BG22C224F512IM40-C |
厂家: | SILICON |
描述: | EFR32BG22 Wireless Gecko SoC Family 无线 |
文件: | 总101页 (文件大小:1371K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
EFR32BG22 Wireless Gecko SoC Family
Data Sheet
The EFR32BG22 Wireless Gecko family of SoCs is part of the
Wireless Gecko portfolio. EFR32BG22 Wireless Gecko SoCs are
KEY FEATURES
ideal for enabling energy-friendly Bluetooth 5.2 networking for IoT
devices.
• 32-bit ARM® Cortex®-M33 core with 76.8
MHz maximum operating frequency
• Up to 512 kB of flash and 32 kB of RAM
The single-die solution combines a 76.8 MHz Cortex-M33 with a high performance 2.4
GHz radio to provide an industry-leading, energy efficient wireless, SoC for IoT connec-
ted applications.
• Energy-efficient radio core with low active
and sleep currents
• Bluetooth 5.2 Direction Finding
• Integrated PA with up to 6 dBm (2.4 GHz)
TX power
Wireless Gecko applications include:
• Asset Tags and Beacons
• Secure Boot with Root of Trust and
Secure Loader (RTSL)
• Consumer Electronics Remote Controls
• Portable Medical
• Bluetooth Mesh Low Power Nodes
• Sports, Fitness, and Wellness devices
• Connected Home
• Building Automation and Security
Core / Memory
Clock Management
Energy Management
Security
HF Crystal
Oscillator
HF
ARM CortexTM M33 processor
with DSP extensions,
FPU and TrustZone
RC Oscillator
Voltage
Regulator
DC-DC
Converter
Flash Program
Memory
Crypto Acceleration
Fast Startup
RC Oscillator
Precision LF
RC Oscillator
Power-On
Reset
Brown-Out
Detector
True Random
Number Generator
LDMA
Controller
LF Crystal
Oscillator
Ultra LF RC
Oscillator
ETM
Debug Interface
RAM Memory
32-bit bus
Peripheral Reflex System
Radio Subsystem
Serial
I/O Ports
Timers and Triggers
Analog I/F
Interfaces
ARM CortexTM
M0+ Radio
Controller
RFSENSE
w/ OOK Detect
DEMOD
IFADC
AGC
External
Interrupts
USART
PDM
Timer/Counter
Protocol Timer
ADC
General
Purpose I/O
Temperature
Sensor
Watchdog Timer
Low Energy Timer
RX/TX Frontend
with Integrated PA
BUFC RAM
FRC
Real Time
Capture Counter
Back-Up Real
Time Counter
EUART
I2C
Pin Reset
Frequency
Synthesizer
MOD
CRC
Pin Wakeup
Lowest power mode with peripheral operational:
EM0—Active
EM1—Sleep
EM2—Deep Sleep
EM3—Stop
EM4—Shutoff
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Rev. 1.0
EFR32BG22 Wireless Gecko SoC Family Data Sheet
Feature List
1. Feature List
The EFR32BG22 highlighted features are listed below.
• Low Power Wireless System-on-Chip
• Wide selection of MCU peripherals
High Performance 32-bit 76.8 MHz MHz ARM Cortex®-M33
with DSP instruction and floating-point unit for efficient sig-
nal processing
•
• Analog to Digital Converter (ADC)
• 12-bit @ 1 Msps
• 16-bit @ 76.9 ksps
• Up to 512 kB flash program memory
• Up to 32 kB RAM data memory
• Up to 26 General Purpose I/O pins with output state reten-
tion and asynchronous interrupts
• 2.4 GHz radio operation
• 8 Channel DMA Controller
• Radio Performance
• 12 Channel Peripheral Reflex System (PRS)
• -106.7 dBm sensitivity @ 125 kbps GFSK
• -98.9 dBm sensitivity @ 1 Mbit/s GFSK
• -96.2 dBm sensitivity @ 2 Mbit/s GFSK
• TX power up to 6 dBm
• 4 × 16-bit Timer/Counter with 3 Compare/Capture/PWM
channels
• 1 × 32-bit Timer/Counter with 3 Compare/Capture/PWM
channels
• 32-bit Real Time Counter
• 2.5 mA radio receive current
• 24-bit Low Energy Timer for waveform generation
• 1 × Watchdog Timer
• 3.4 mA radio transmit current @ 0 dBm output power
• 7.5 mA radio transmit current @ 6 dBm output power
• Low System Energy Consumption
• 3.6 mA RX current (1 Mbps GFSK)
• 4.1 mA TX current @ 0 dBm output power
• 8.2 mA TX current @ 6 dBm output power
• 27 μA/MHz in Active Mode (EM0) at 76.8 MHz
• 2 × Universal Synchronous/Asynchronous Receiver/Trans-
mitter (UART/SPI/SmartCard (ISO 7816)/IrDA/I2S)
• 1 × Enhanced Universal Asynchronous Receiver/Transmit-
ter (EUART)
2 × I2C interface with SMBus support
•
• Digital microphone interface (PDM)
• 1.40 μA EM2 DeepSleep current (32 kB RAM retention and
RTC running from LFXO)
• Precision Low-Frequency RC Oscillator to replace 32 kHz
sleep crystal
• 1.75 μA EM2 DeepSleep current (32 kB RAM retention and
RTC running from Precision LFRCO)
• RFSENSE with selective OOK mode
• Die temperature sensor with +/-1.5 degree C accuracy after
single-point calibration
• 0.17 μA EM4 current
• Supported Modulation Format
• 2 (G)FSK with fully configurable shaping
• OQPSK DSSS
• Wide Operating Range
• 1.71 V to 3.8 V single power supply
• -40 °C to 125 °C
• (G)MSK
• Security Features
• Protocol Support
• Secure Boot with Root of Trust and Secure Loader (RTSL)
• Bluetooth Low Energy (Bluetooth 5.2)
• Hardware Cryptographic Acceleration for AES128/256,
SHA-1, SHA-2 (up to 256-bit), ECC (up to 256-bit), ECDSA,
and ECDH
• Direction finding using Angle-of-Arrival (AoA) and Angle-of-
Departure (AoD)
• Proprietary
• True Random Number Generator (TRNG) compliant with
NIST SP800-90 and AIS-31
ARM® TrustZone®
•
• Secure Debug with lock/unlock
• Packages
• QFN40 5 mm × 5 mm × 0.85 mm
• QFN32 4 mm × 4 mm × 0.85 mm
• TQFN32 4 mm × 4 mm × 0.30 mm
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Rev. 1.0 | 2
EFR32BG22 Wireless Gecko SoC Family Data Sheet
Ordering Information
2. Ordering Information
Table 2.1. Ordering Information
Protocol
Stack
Max TX
Power
Max CPU
Speed
Flash RAM
(kB) (kB) GPIO Package Temp Range
Ordering Code
LFRCO
EFR32BG22C222F352GM32-C • Bluetooth
5.2
6 dBm
6 dBm
6 dBm
6 dBm
76.8 MHz Precision 352
76.8 MHz Precision 352
76.8 MHz Precision 352
76.8 MHz Precision 512
32
32
32
32
18 QFN32
26 QFN40
18 TQFN32
18 QFN32
-40 to 85 °C
-40 to 85 °C
-40 to 85 °C
-40 to 85 °C
• Proprietary
EFR32BG22C222F352GM40-C • Bluetooth
5.2
• Proprietary
EFR32BG22C222F352GN32-C • Bluetooth
5.2
• Proprietary
EFR32BG22C224F512GM32-C • Bluetooth
5.2
• Direction
finding
• Proprietary
EFR32BG22C224F512GM40-C • Bluetooth
5.2
6 dBm
6 dBm
6 dBm
6 dBm
76.8 MHz Precision 512
76.8 MHz Precision 512
76.8 MHz Precision 512
76.8 MHz Precision 512
32
32
32
32
26 QFN40
18 TQFN32
18 QFN32
26 QFN40
-40 to 85 °C
-40 to 85 °C
-40 to 125 °C
-40 to 125 °C
• Direction
finding
• Proprietary
EFR32BG22C224F512GN32-C • Bluetooth
5.2
• Direction
finding
• Proprietary
EFR32BG22C224F512IM32-C
EFR32BG22C224F512IM40-C
• Bluetooth
5.2
• Direction
finding
• Proprietary
• Bluetooth
5.2
• Direction
finding
• Proprietary
LE Long Range (125 kbps and 500 kbps) PHYs are only supported on part numbers which include AoA/AoD direction-finding capability.
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Rev. 1.0 | 3
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.1 Antenna Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.2 Fractional-N Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . 8
3.2.3 Receiver Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.4 Transmitter Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.5 Packet and State Trace . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.6 Data Buffering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.7 Radio Controller (RAC). . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.8 RFSENSE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4.1 Clock Management Unit (CMU) . . . . . . . . . . . . . . . . . . . . . . . 9
3.4.2 Internal and External Oscillators. . . . . . . . . . . . . . . . . . . . . . . 9
3.5 Counters/Timers and PWM . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5.1 Timer/Counter (TIMER) . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5.2 Low Energy Timer (LETIMER) . . . . . . . . . . . . . . . . . . . . . . .10
3.5.3 Real Time Clock with Capture (RTCC) . . . . . . . . . . . . . . . . . . . .10
3.5.4 Back-Up Real Time Counter . . . . . . . . . . . . . . . . . . . . . . . .10
3.5.5 Watchdog Timer (WDOG). . . . . . . . . . . . . . . . . . . . . . . . .10
3.6 Communications and Other Digital Peripherals . . . . . . . . . . . . . . . . . . .10
3.6.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) . . . . . . . . . .10
3.6.2 Enhanced Universal Asynchronous Receiver/Transmitter (EUART) . . . . . . . . . . .10
2
3.6.3 Inter-Integrated Circuit Interface (I C) . . . . . . . . . . . . . . . . . . . . .10
3.6.4 Peripheral Reflex System (PRS) . . . . . . . . . . . . . . . . . . . . . .11
3.6.5 Pulse Density Modulation (PDM) Interface . . . . . . . . . . . . . . . . . . .11
3.7 Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.7.1 Secure Boot with Root of Trust and Secure Loader (RTSL) . . . . . . . . . . . . .11
3.7.2 Cryptographic Accelerator. . . . . . . . . . . . . . . . . . . . . . . . .11
3.7.3 True Random Number Generator . . . . . . . . . . . . . . . . . . . . . .11
3.7.4 Secure Debug with Lock/Unlock. . . . . . . . . . . . . . . . . . . . . . .12
3.8 Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.8.1 Analog to Digital Converter (IADC) . . . . . . . . . . . . . . . . . . . . . .12
3.9 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.9.1 Energy Management Unit (EMU) . . . . . . . . . . . . . . . . . . . . . .13
3.9.2 Voltage Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.9.3 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.9.4 Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.10 Reset Management Unit (RMU) . . . . . . . . . . . . . . . . . . . . . . . .14
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3.11 Core and Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.11.1 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.11.2 Memory System Controller (MSC) . . . . . . . . . . . . . . . . . . . . .14
3.11.3 Linked Direct Memory Access Controller (LDMA) . . . . . . . . . . . . . . . .14
3.12 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.13 Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . .16
4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.2 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . .18
4.3 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . .19
4.4 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.4.1 DC-DC Operating Limits . . . . . . . . . . . . . . . . . . . . . . . . .23
4.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.6 Current Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.6.1 MCU current consumption using DC-DC at 3.0 V input . . . . . . . . . . . . . . .25
4.6.2 MCU current consumption at 3.0 V . . . . . . . . . . . . . . . . . . . . . .27
4.6.3 MCU current consumption at 1.8 V . . . . . . . . . . . . . . . . . . . . . .29
4.6.4 Radio current consumption at 3.0V using DCDC . . . . . . . . . . . . . . . . .31
4.7 Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
4.8 Wake Up, Entry, and Exit times . . . . . . . . . . . . . . . . . . . . . . . .34
4.9 RFSENSE Low-energy Wake-on-RF . . . . . . . . . . . . . . . . . . . . . .35
4.10 2.4 GHz RF Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . .36
4.10.1 RF Transmitter Characteristics. . . . . . . . . . . . . . . . . . . . . . .36
4.10.2 RF Receiver Characteristics . . . . . . . . . . . . . . . . . . . . . . .43
4.11 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.11.1 High Frequency Crystal Oscillator. . . . . . . . . . . . . . . . . . . . . .49
4.11.2 Low Frequency Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . .50
4.11.3 High Frequency RC Oscillator (HFRCO) . . . . . . . . . . . . . . . . . . .51
4.11.4 Fast Start_Up RC Oscillator (FSRCO) . . . . . . . . . . . . . . . . . . . .52
4.11.5 Precision Low Frequency RC Oscillator (LFRCO) . . . . . . . . . . . . . . . .53
4.11.6 Ultra Low Frequency RC Oscillator . . . . . . . . . . . . . . . . . . . . .53
4.12 GPIO Pins (3V GPIO pins) . . . . . . . . . . . . . . . . . . . . . . . . .54
4.13 Analog to Digital Converter (IADC) . . . . . . . . . . . . . . . . . . . . . . .56
4.14 Temperature Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
4.15 Brown Out Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . .59
4.15.1 DVDD BOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
4.15.2 LE DVDD BOD . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
4.15.3 AVDD and IOVDD BODs . . . . . . . . . . . . . . . . . . . . . . . .60
4.16 PDM Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . .61
4.16.1 Pulse Density Modulator (PDM), Common DBUS . . . . . . . . . . . . . . . .61
4.17 USART SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . .62
4.17.1 SPI Master Timing, Voltage Scaling = VSCALE2. . . . . . . . . . . . . . . . .63
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4.17.2 SPI Master Timing, Voltage Scaling = VSCALE1. . . . . . . . . . . . . . . . .63
4.18 USART SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . .64
4.18.1 SPI Slave Timing, Voltage Scaling = VSCALE2 . . . . . . . . . . . . . . . . .64
4.18.2 SPI Slave Timing, Voltage Scaling = VSCALE1 . . . . . . . . . . . . . . . . .65
4.19 I2C Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . .66
4.19.1 I2C Standard-mode (Sm) . . . . . . . . . . . . . . . . . . . . . . . .66
4.19.2 I2C Fast-mode (Fm) . . . . . . . . . . . . . . . . . . . . . . . . . .67
4.19.3 I2C Fast-mode Plus (Fm+) . . . . . . . . . . . . . . . . . . . . . . . .68
4.20 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . .68
4.20.1 Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
4.20.2 RF Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .71
4.20.3 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . .72
4.20.4 IADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
5. Typical Connections
. . . . . . . . . . . . . . . . . . . . . . . . . . .73
5.1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
5.2 RF Matching Networks . . . . . . . . . . . . . . . . . . . . . . . . . . .74
5.2.1 2.4 GHz Matching Network . . . . . . . . . . . . . . . . . . . . . . . .74
5.3 Other Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
6. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.1 QFN32 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . .75
6.2 QFN40 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.3 TQFN32 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . .79
6.4 Alternate Function Table. . . . . . . . . . . . . . . . . . . . . . . . . . .80
6.5 Analog Peripheral Connectivity . . . . . . . . . . . . . . . . . . . . . . . .81
6.6 Digital Peripheral Connectivity . . . . . . . . . . . . . . . . . . . . . . . . .82
7. QFN32 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 85
7.1 QFN32 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . .85
7.2 QFN32 PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . .87
7.3 QFN32 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . .89
8. TQFN32 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . 90
8.1 TQFN32 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . .90
8.2 TQFN32 PCB Land Pattern. . . . . . . . . . . . . . . . . . . . . . . . . .92
8.3 TQFN32 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . .94
9. QFN40 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 95
9.1 QFN40 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . .95
9.2 QFN40 PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . .97
9.3 QFN40 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . .98
10. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
System Overview
3. System Overview
3.1 Introduction
The EFR32 product family combines an energy-friendly MCU with a high performance radio transceiver. The devices are well suited for
secure connected IoT multi-protocol devices requiring high performance and low energy consumption. This section gives a short intro-
duction to the full radio and MCU system. The detailed functional description can be found in the EFR32xG22 Reference Manual.
A block diagram of the EFR32BG22 family is shown in Figure 3.1 Detailed EFR32BG22 Block Diagram on page 7. The diagram
shows a superset of features available on the family, which vary by OPN. For more information about specific device features, consult
Ordering Information.
Radio Subsystem
Port I/O Configuration
Digital Peripherals
IOVDD
RFSENSE
ARM CortexTM M0+
Radio Controller
DEMOD
IFADC
AGC
w/ OOK Detect
USART
EUART
I2C
RX/TX Frontend
with Integrated PA
BUFC RAM
FRC
Port A
Drivers
RF2G4_IO
PAn
Frequency
Synthesizer
MOD
Port B
CRC
PBn
PCn
PDn
Drivers
LETIMER
DBUS
Port
Mappers
TIMER
RTCC
Core and Memory
Port C
Drivers
Reset Management Unit,
Brown Out and POR
RESETn
ARM Cortex-M33 Core
with Floating Point Unit
PDM
Serial Wire and ETM
Debug / Programming
with Debug Challenge I/F
Port D
Drivers
Debug Signals
(shared w/GPIO)
Up to 512 KB ISP Flash
Program Memory
TRNG
A
H
B
A
P
B
CRYPTOACC
CRC
32 KB RAM
Trust Zone
Energy Management
PAVDD
RFVDD
IOVDD
AVDD
LDMA Controller
Analog Peripherals
Voltage
Monitor
Watchdog
Timer
Internal
Reference
Temperature
Sensor
DVDD
bypass
VREGVDD
VREGSW
DC-DC
Converter
Voltage
Regulator
Clock Management
ULFRCO
VDD
12-bit ADC
DECOUPLE
FSRCO
LFRCO
LFXO
LFXTAL_I
LFXTAL_O
HFXTAL_I
HFXTAL_O
HFRCO
HFXO
Figure 3.1. Detailed EFR32BG22 Block Diagram
3.2 Radio
The EFR32BG22 Wireless Gecko features a highly configurable radio transceiver supporting the Bluetooth Low Energy wireless proto-
col.
3.2.1 Antenna Interface
The 2.4 GHz antenna interface consists of a single-ended pin (RF2G4_IO). The external components for the antenna interface in typi-
cal applications are shown in the RF Matching Networks section.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
System Overview
3.2.2 Fractional-N Frequency Synthesizer
The EFR32BG22 contains a high performance, low phase noise, fully integrated fractional-N frequency synthesizer. The synthesizer is
used in receive mode to generate the LO frequency for the down-conversion mixer. It is also used in transmit mode to directly generate
the modulated RF carrier.
The fractional-N architecture provides excellent phase noise performance, frequency resolution better than 100 Hz, and low energy
consumption. The synthesizer’s fast frequency settling allows for very short receiver and transmitter wake up times to reduce system
energy consumption.
3.2.3 Receiver Architecture
The EFR32BG22 uses a low-IF receiver architecture, consisting of a Low-Noise Amplifier (LNA) followed by an I/Q down-conversion
mixer. The I/Q signals are further filtered and amplified before being sampled by the IF analog-to-digital converter (IFADC).
The IF frequency is configurable from 150 kHz to 1371 kHz. The IF can further be configured for high-side or low-side injection, provid-
ing flexibility with respect to known interferers at the image frequency.
The Automatic Gain Control (AGC) module adjusts the receiver gain to optimize performance and avoid saturation for excellent selec-
tivity and blocking performance. The 2.4 GHz radio is calibrated at production to improve image rejection performance.
Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow re-
ceive bandwidths ranging from 0.1 to 2530 kHz. High carrier frequency and baud rate offsets are tolerated by active estimation and
compensation. Advanced features supporting high quality communication under adverse conditions include forward error correction by
block and convolutional coding as well as Direct Sequence Spread Spectrum (DSSS).
A Received Signal Strength Indicator (RSSI) is available for signal quality metrics, for level-based proximity detection, and for RF chan-
nel access by Collision Avoidance (CA) or Listen Before Talk (LBT) algorithms. An RSSI capture value is associated with each received
frame and the dynamic RSSI measurement can be monitored throughout reception.
3.2.4 Transmitter Architecture
The EFR32BG22 uses a direct-conversion transmitter architecture. For constant envelope modulation formats, the modulator controls
phase and frequency modulation in the frequency synthesizer. Transmit symbols or chips are optionally shaped by a digital shaping
filter. The shaping filter is fully configurable, including the BT product, and can be used to implement Gaussian or Raised Cosine shap-
ing.
Carrier Sense Multiple Access - Collision Avoidance (CSMA-CA) or Listen Before Talk (LBT) algorithms can be automatically timed by
the EFR32BG22. These algorithms are typically defined by regulatory standards to improve inter-operability in a given bandwidth be-
tween devices that otherwise lack synchronized RF channel access.
3.2.5 Packet and State Trace
The EFR32BG22 Frame Controller has a packet and state trace unit that provides valuable information during the development phase.
It features:
• Non-intrusive trace of transmit data, receive data and state information
• Data observability on a single-pin UART data output, or on a two-pin SPI data output
• Configurable data output bitrate / baudrate
• Multiplexed transmitted data, received data and state / meta information in a single serial data stream
3.2.6 Data Buffering
The EFR32BG22 features an advanced Radio Buffer Controller (BUFC) capable of handling up to 4 buffers of adjustable size from 64
bytes to 4096 bytes. Each buffer can be used for RX, TX or both. The buffer data is located in RAM, enabling zero-copy operations.
3.2.7 Radio Controller (RAC)
The Radio Controller controls the top level state of the radio subsystem in the EFR32BG22. It performs the following tasks:
• Precisely-timed control of enabling and disabling of the receiver and transmitter circuitry
• Run-time calibration of receiver, transmitter and frequency synthesizer
• Detailed frame transmission timing, including optional LBT or CSMA-CA
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
System Overview
3.2.8 RFSENSE Interface
The RFSENSE block allows the device to remain in EM2, EM3 or EM4 and wake when RF energy above a specified threshold is detec-
ted. When operated in selective mode, the RFSENSE block performs OOK preamble and sync word detection, preventing false wake-
up events.
3.3 General Purpose Input/Output (GPIO)
EFR32BG22 has up to 26 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or
input. More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO
pin. The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to
several GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripher-
als. The GPIO subsystem supports asynchronous external pin interrupts.
All of the pins on ports A and port B are EM2 capable. These pins may be used by Low-Energy peripherals in EM2/3 and may also be
used as EM2/3 pin wake-ups. Pins on ports C and D are latched/retained in their current state when entering EM2 until EM2 exit upon
which internal peripherals could once again drive those pads.
A few GPIOs also have EM4 wake functionality. These pins are listed in the Alternate Function Table.
3.4 Clocking
3.4.1 Clock Management Unit (CMU)
The Clock Management Unit controls oscillators and clocks in the EFR32BG22. Individual enabling and disabling of clocks to all periph-
eral modules is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility
allows software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and
oscillators.
3.4.2 Internal and External Oscillators
The EFR32BG22 supports two crystal oscillators and fully integrates four RC oscillators, listed below.
• A high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing refer-
ence for the MCU. The HFXO provides excellent RF clocking performance using a 38.4 MHz crystal. The HFXO can also support an
external clock source such as a TCXO for applications that require an extremely accurate clock frequency over temperature.
• A 32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.
• An integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The
HFRCO employs fast start-up at minimal energy consumption combined with a wide frequency range, from 1 MHz to 76.8 MHz.
• An integrated fast start-up RC oscillator (FSRCO) that runs at a fixed 20 MHz
• An integrated low frequency 32.768 kHz RC oscillator (LFRCO) for low power operation without an external crystal. Precision mode
enables periodic recalibration against the 38.4 MHz HFXO crystal to improve accuracy to +/- 500 ppm, suitable for BLE sleep inter-
val timing.
• An integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy con-
sumption in low energy modes.
3.5 Counters/Timers and PWM
3.5.1 Timer/Counter (TIMER)
TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the
Peripheral Reflex System (PRS). The core of each TIMER is a 16-bit or 32-bit counter with up to 3 compare/capture channels. Each
channel is configurable in one of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In
compare mode, the channel output reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER
supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the
compare registers. In addition some timers offer dead-time insertion.
See 3.13 Configuration Summary for information on the feature set of each timer.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
System Overview
3.5.2 Low Energy Timer (LETIMER)
The unique LETIMER is a 24-bit timer that is available in energy mode EM0 Active, EM1 Sleep, EM2 Deep Sleep, and EM3 Stop. This
allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed
while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of wave-
forms with minimal software intervention. The LETIMER is connected to the Peripheral Reflex System (PRS), and can be configured to
start counting on compare matches from other peripherals such as the RTCC.
3.5.3 Real Time Clock with Capture (RTCC)
The Real Time Clock with Capture (RTCC) is a 32-bit counter providing timekeeping down to EM3. The RTCC can be clocked by any of
the on-board low-frequency oscillators, and it is capable of providing system wake-up at user defined intervals.
A secondary RTC is used by the RF protocol stack for event scheduling, leaving the primary RTCC block available exclusively for appli-
cation software.
3.5.4 Back-Up Real Time Counter
The Back-Up Real Time Counter (BURTC) is a 32-bit counter providing timekeeping in all energy modes, including EM4. The BURTC
can be clocked by any of the on-board low-frequency oscillators, and it is capable of providing system wake-up at user defined inver-
vals.
3.5.5 Watchdog Timer (WDOG)
The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed
monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can
also monitor autonomous systems driven by the Peripheral Reflex System (PRS).
3.6 Communications and Other Digital Peripherals
3.6.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O module. It supports full duplex asynchronous
UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices sup-
porting:
• ISO7816 SmartCards
• IrDA
I2S
•
3.6.2 Enhanced Universal Asynchronous Receiver/Transmitter (EUART)
The Enhanced Universal Asynchronous Receiver/Transmitter supports full duplex asynchronous UART communication with hardware
flow control, RS-485 and IrDA support. In EM0 and EM1 the EUART provides a high-speed, buffered communication interface.
When routed to GPIO ports A or B, the EUART may also be used in a low-energy mode and operate in EM2. A 32.768 kHz clock
source allows full duplex UART communication up to 9600 baud.
3.6.3 Inter-Integrated Circuit Interface (I2C)
The I2C module provides an interface between the MCU and a serial I2C bus. It is capable of acting as both a master and a slave and
supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates from 10
kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system. The
interface provided to software by the I2C module allows precise timing control of the transmission process and highly automated trans-
fers. Automatic recognition of slave addresses is provided in active and low energy modes. Note that not all instances of I2C are avalia-
ble in all energy modes.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
System Overview
3.6.4 Peripheral Reflex System (PRS)
The Peripheral Reflex System provides a communication network between different peripheral modules without software involvement.
Peripheral modules producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer periph-
erals which in turn perform actions in response. Edge triggers and other functionality such as simple logic operations (AND, OR, NOT)
can be applied by the PRS to the signals. The PRS allows peripherals to act autonomously without waking the MCU core, saving
power.
3.6.5 Pulse Density Modulation (PDM) Interface
The PDM module provides a serial interface and decimation filter for Pulse Density Modulation (PDM) microphones, isolated Sigma-
delta ADCs, digital sensors and other PDM or sigma delta bit stream peripherals. A programmable Cascaded Integrator Comb (CIC)
filter is used to decimate the incoming bit streams. PDM supports stereo or mono input data and DMA transfer.
3.7 Security Features
The following security features are available on the EFR32BG22:
• Secure Boot with Root of Trust and Secure Loader (RTSL)
• Cryptographic Accelerator
• True Random Number Generator (TRNG)
• Secure Debug with Lock/Unlock
3.7.1 Secure Boot with Root of Trust and Secure Loader (RTSL)
The Secure Boot with RTSL authenticates a chain of trusted firmware that begins from an immutable memory (ROM).
It prevents malware injection, prevents rollback, ensures that only authentic firmware is executed and protects Over The Air updates.
More information on this feature can be found in the Application Note AN1218: Series 2 Secure Boot with RTSL.
3.7.2 Cryptographic Accelerator
The Cryptographic Accelerator is an autonomous hardware accelerator which supports AES encryption and decryption with
128/192/256-bit keys, Elliptic Curve Cryptography (ECC) to support public key operations and hashes.
Supported block cipher modes of operation for AES include:
• ECB (Electronic Code Book)
• CTR (Counter Mode)
• CBC (Cipher Block Chaining)
• CFB (Cipher Feedback)
• GCM (Galois Counter Mode)
• CBC-MAC (Cipher Block Chaining Message Authentication Code)
• GMAC (Galois Message Authentication Code)
• CCM (Counter with CBC-MAC)
The Cryptographic Accelerator accelerates Elliptical Curve Cryptography and supports the NIST (National Institute of Standards and
Technology) recommended curves including P-192 and P-256 for ECDH(Elliptic Curve Diffie-Hellman) key derivation and ECDSA (El-
liptic Curve Digital Signature Algorithm) sign and verify operations.
Supported hashes include SHA-1, SHA2/224, and SHA-2/256.
This implementation provides a fast and energy efficient solution to state of the art cryptographic needs.
3.7.3 True Random Number Generator
The True Random Number Generator module is a non-deterministic random number generator that harvests entropy from a thermal
energy source. It includes start-up health tests for the entropy source as required by NIST SP800-90B and AIS-31 as well as online
health tests required for NIST SP800-90C.
The TRNG is suitable for periodically generating entropy to seed an approved pseudo random number generator.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
System Overview
3.7.4 Secure Debug with Lock/Unlock
For obvious security reasons, it is critical for a product to have its debug interface locked before being released in the field.
In addition, the EFR32BG22 also provides a secure debug unlock function that allows authenticated access based on public key cryp-
tography. This functionality is particularly useful for supporting failure analysis while maintaining confidentiality of IP and sensitive end-
user data.
More information on this feature can be found in the Application Note AN1190: EFR32xG2x Secure Debug.
3.8 Analog
3.8.1 Analog to Digital Converter (IADC)
The IADC is a hybrid architecture combining techniques from both SAR and Delta-Sigma style converters. It has a resolution of 12 bits
at 1 Msps and 16 bits at up to 76.9 ksps. Hardware oversampling reduces system-level noise over multiple front-end samples. The
IADC includes integrated voltage reference options. Inputs are selectable from a wide range of sources, including pins configurable as
either single-ended or differential.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
System Overview
3.9 Power
The EFR32BG22 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only
a single external supply voltage is required, from which all internal voltages are created. An optional integrated DC-DC buck regulator
can be utilized to further reduce the current consumption. The DC-DC regulator requires one external inductor and one external capaci-
tor.
The EFR32BG22 device family includes support for internal supply voltage scaling, as well as two different power domains groups for
peripherals. These enhancements allow for further supply current reductions and lower overall power consumption.
3.9.1 Energy Management Unit (EMU)
The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and
features are available and the amount of current the device consumes. The EMU can also be used to implement system-wide voltage
scaling and turn off the power to unused RAM blocks to optimize the energy consumption in the target application. The DC-DC regula-
tor operation is tightly integrated with the EMU.
3.9.2 Voltage Scaling
The EFR32BG22 supports supply voltage scaling for the LDO powering DECOUPLE, with independent selections for EM0 / EM1 and
EM2 / EM3. Voltage scaling helps to optimize the energy efficiency of the system by operating at lower voltages when possible. The
default EM0 / EM1 voltage scaling level is VSCALE2, which allows the core to operate in active mode at full speed. The intermediate
level, VSCALE1, allows operation in EM0 and EM1 at up to 40 MHz. The lowest level, VSCALE0, can be used to conserve power in
EM2 and EM3. The EMU will automatically switch the target voltage scaling level when transitioning between energy modes.
3.9.3 DC-DC Converter
The DC-DC buck converter covers a wide range of load currents, provides high efficiency in energy modes EM0, EM1, EM2 and EM3,
and can supply up to 60 mA for device and radio operation. RF noise mitigation allows operation of the DC-DC converter without signifi-
cantly degrading sensitivity of radio components. An on-chip supply-monitor signals when the supply voltage is low to allow bypass of
the regulator via programmable software interrupt. It employs soft switching at boot and DCDC regulating-to-bypass transitions to limit
the max supply slew-rate and mitigate inrush current.
3.9.4 Power Domains
The EFR32BG22 has three peripheral power domains for operation in EM2 and EM3, as well as the ability to selectively retain configu-
rations for EM0/EM1 peripherals. A small set of peripherals always remain powered on in EM2 and EM3, including all peripherals which
are available in EM4. If all of the peripherals in PD0B or PD0C are configured as unused, that power domain will be powered off in EM2
or EM3, reducing the overall current consumption of the device. Likewise, if the application can tolerate the setup time to re-configure
used EM0/EM1 peripherals on wake, register retention for these peripherals can be disabled to further reduce the EM2 or EM3 current.
Table 3.1. Peripheral Power Subdomains
Always available in EM2/EM3
Power Domain PD0B
LETIMER0
Power Domain PD0C
RTCC
LFRCO (Precision Mode)
LFRCO (Non-precision mode)1
IADC0
LFXO1
I2C0
BURTC1
RFSENSE1
WDOG0
EUART0
PRS
ULFRCO1
FSRCO
DEBUG
Note:
1. Peripheral also available in EM4.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
System Overview
3.10 Reset Management Unit (RMU)
The RMU is responsible for handling reset of the EFR32BG22. A wide range of reset sources are available, including several power
supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset.
3.11 Core and Memory
3.11.1 Processor Core
The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:
• ARM Cortex-M33 RISC processor achieving 1.50 Dhrystone MIPS/MHz
• ARM TrustZone security technology
• Embedded Trace Macrocell (ETM) for real-time trace and debug
• Up to 512 kB flash program memory
• Up to 32 kB RAM data memory
• Configuration and event handling of all modules
• 2-pin Serial-Wire debug interface
3.11.2 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable
from both the Cortex-M and DMA. In addition to the main flash array where Program code is normally written the MSC also provides an
Information block where additional information such as special user information or flash-lock bits are stored. There is also a read-only
page in the information block containing system and device calibration data. Read and write operations are supported in energy modes
EM0 Active and EM1 Sleep.
3.11.3 Linked Direct Memory Access Controller (LDMA)
The Linked Direct Memory Access (LDMA) controller allows the system to perform memory operations independently of software. This
reduces both energy consumption and software workload. The LDMA allows operations to be linked together and staged, enabling so-
phisticated operations to be implemented.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
System Overview
3.12 Memory Map
The EFR32BG22 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.
Figure 3.2. EFR32BG22 Memory Map — Core Peripherals and Code Space
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
System Overview
3.13 Configuration Summary
The features of the EFR32BG22 are a subset of the feature set described in the device reference manual. The table below describes
device specific implementation of the features. Remaining modules support full configuration.
Table 3.2. Configuration Summary
Module
Lowest Energy Mode
Configuration
EM21
EM1
EM2
I2C0
I2C1
IADC0
EM21
LETIMER0
PDM
EM1
2-channel
TIMER0
TIMER1
TIMER2
TIMER3
TIMER4
EUART0
EM1
32-bit, 3-channels, +DTI
16-bit, 3-channels, +DTI
16-bit, 3-channels, +DTI
16-bit, 3-channels, +DTI
16-bit, 3-channels, +DTI
EM1
EM1
EM1
EM1
EM1 - Full high-speed operation
EM21 - Low-energy operation, 9600 Baud
USART0
USART1
Note:
EM1
EM1
+IrDA, +I2S, +SmartCard
+IrDA, +I2S, +SmartCard
1. EM2 and EM3 operation is only supported for digital peripheral I/O on Port A and Port B. All GPIO ports support digital peripheral
operation in EM0 and EM1.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4. Electrical Specifications
4.1 Electrical Characteristics
All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:
• Typical values are based on TA=25 °C and all supplies at 3.0 V, by production test and/or technology characterization.
• Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output pow-
er-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.
• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,
unless stated otherwise.
Power Supply Pin Dependencies
Due to on-chip circuitry (e.g., diodes), some EFR32 power supply pins have a dependent relationship with one or more other power
supply pins. These internal relationships between the external voltages applied to the various EFR32 supply pins are defined below.
Exceeding the below constraints can result in damage to the device and/or increased current draw.
• VREGVDD & DVDD
• In systems using the DCDC converter, DVDD (the buck converter output) should be connected to the recommended LDCDC and
CDCDC, and should not be driven by an off-chip regulator.
• In systems not using the DCDC converter, DVDD must be shorted to VREGVDD on the PCB (VREGVDD=DVDD)
• DVDD ≥ DECOUPLE
• PAVDD ≥ RFVDD
• AVDD, IOVDD: No dependency with each other or any other supply pin
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.2 Absolute Maximum Ratings
Stresses beyond those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of
the devices at those or any other conditions beyond those indicated in the operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and relia-
bility data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx.
Table 4.1. Absolute Maximum Ratings
Parameter
Symbol
TSTG
Test Condition
Min
-50
Typ
—
Max
+150
3.8
Unit
°C
Storage temperature range
Voltage on any supply pin1
Junction temperature
VDDMAX
-0.3
—
V
TJMAX
-G grade
-I grade
—
—
—
—
—
—
+105
+125
1.0
°C
°C
Voltage ramp rate on any
supply pin
VDDRAMPMAX
V / µs
Voltage on HFXO pins
VHFXOPIN
-0.3
-0.3
—
—
1.4
V
V
DC voltage on any GPIO pin VDIGPIN
VIOVDD
0.3
+
DC voltage on RESETn pin2
VRESETn
-0.3
—
—
—
3.8
V
Input RF level on RF pins
RF2G4_IO
PRFMAX2G4
+10
dBm
Absolute voltage on RF pin
RF2G4_IO
VMAX2G4
-0.3
—
—
—
—
VPAVDD
0.3
+
V
Total current into VDD power IVDDMAX
lines
Source
Sink
200
mA
mA
Total current into VSS
ground lines
IVSSMAX
—
200
Current per I/O pin
Current for all I/O pins
Note:
IIOMAX
Sink
—
—
—
—
—
—
—
—
50
50
mA
mA
mA
mA
Source
Sink
IIOALLMAX
200
200
Source
1. The maximum supply voltage on VREGVDD is limited under certain conditions when using the DC-DC. See the DC-DC specifica-
tions for more details.
2. The RESETn pin has a pull-up device to the DVDD supply. For minimum leakage, RESETn should not exceed the voltage at
DVDD.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.3 General Operating Conditions
Table 4.2. General Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
-G temperature grade 1
Operating ambient tempera- TA
ture range
-40
—
+85
°C
-I temperature grade 1
EM0/1
-40
—
+125
° C
DVDD supply voltage
VDVDD
1.71
1.71
3.0
3.0
3.8
3.8
V
V
EM2/3/42
AVDD supply voltage
VAVDD
1.71
1.71
3.0
3.0
3.8
3.8
V
V
IOVDDx operating supply
voltage (All IOVDD pins)
VIOVDDx
PAVDD operating supply
voltage
VPAVDD
1.71
2.2
3.0
3.0
3.8
3.8
V
V
DC-DC in regulation3
VREGVDD operating supply VVREGVDD
voltage
DC-DC in bypass 60 mA load
1.8
3.0
3.0
3.8
3.8
V
V
DC-DC not in use. DVDD exter-
nally shorted to VREGVDD
1.71
RFVDD operating supply
voltage
VRFVDD
1.71
1.0
3.0
—
VPAVDD
V
DECOUPLE output capaci-
tor4
CDECOUPLE
1.0 µF ± 10% X8L capacitor used
for performance characterization.
2.75
µF
HCLK and SYSCLK frequen- fHCLK
cy
VSCALE2, MODE = WS1
VSCALE2, MODE = WS0
VSCALE1, MODE = WS0
VSCALE2
—
—
—
—
—
—
—
—
—
—
—
—
76.8
40
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
—
40
PCLK frequency
fPCLK
—
50
VSCALE1
—
40
EM01 Group A clock fre-
quency
fEM01GRPACLK
fEM01GRPBCLK
fRHCLK
VSCALE2
—
76.8
40
VSCALE1
—
EM01 Group B clock fre-
quency
VSCALE2
—
76.8
40
VSCALE1
—
Radio HCLK frequency5
VSCALE2 or VSCALE1
38.4
—
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
Parameter
Note:
Symbol
Test Condition
Min
Typ
Max
Unit
1. The device may operate continuously at the maximum allowable ambient TA rating as long as the absolute maximum TJMAX is not
exceeded. For an application with significant power dissipation, the allowable TA may be lower than the maximum TA rating. TA =
TJMAX - (THETAJA x PowerDissipation). Refer to the Absolute Maximum Ratings table and the Thermal Characteristics table for
TJMAX and THETAJA
.
2. The DVDD supply is monitored by the DVDD BOD in EM0/1 and the LE DVDD BOD in EM2/3/4.
3. The maximum supply voltage on VREGVDD is limited under certain conditions when using the DC-DC. See the DC-DC specifica-
tions for more details.
4. Murata GCM21BL81C105KA58L used for performance characterization. Actual capacitor values can be significantly de-rated
from their specified nominal value by the rated tolerance, as well as the application's AC voltage, DC bias, and temperature. The
minimum capacitance counting all error sources should be no less than 0.6 µF.
5. The recommended radio crystal frequency is 38.4 MHz. Any crystal frequency other than 38.4 MHz is expressly not supported.
See HFXO specifications for more detail on crystal tolerance.
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Rev. 1.0 | 20
EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.4 DC-DC Converter
Test conditions: LDCDC = 2.2 µH (Samsung CIG22H2R2MNE), CDCDC = 4.7 µF (Samsung CL10B475KQ8NQNC), VVREGVDD = 3.0 V,
VOUT = 1.8 V, IPKVAL in EM0/1 modes is set to 150 mA, and in EM2/3 modes is set to 90 mA, unless otherwise indicated.
Table 4.3. DC-DC Converter
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Input voltage range at
VREGVDD pin1
VVREGVDD
DCDC in regulation, ILOAD = 60
mA, EM0/EM1 mode
2.2
3.0
3.8*
V
DCDC in regulation, ILOAD = 5
1.8
3.0
3.8*
V
mA, EM0/EM1 or EM2/EM3 mode
Bypass mode
1.8
—
3.0
1.8
—
3.8
—
V
V
Regulated output voltage
Regulation DC accuracy
VOUT
ACCDC
VVREGVDD ≥ 2.2 V, Steady state in
EM0/EM1 mode or EM2/EM3
mode
-2.5
3.3
%
Regulation total accuracy
ACCTOT
With mode transitions between
EM0/EM1 and EM2/EM3 modes
-5
—
7
%
Steady-state output ripple
DC line regulation
VR
ILOAD = 20 mA in EM0/EM1 mode
—
—
14.3
5.5
—
—
mVpp
mV/V
VREG
ILOAD = 60 mA in EM0/EM1
mode, VVREGVDD ≥ 2.2 V
DC load regulation
Efficiency
IREG
EFF
Load current between 100 µA and
60 mA in EM0/EM1 mode
—
—
0.27
91
—
—
mV/mA
%
Load current between 100 µA and
60 mA in EM0/EM1 mode, or be-
tween 10 µA and 5 mA in
EM2/EM3 mode
Output load current
ILOAD
EM0/EM1 mode, DCDC in regula-
tion
—
—
—
—
60
5
mA
mA
EM2/EM3 mode, DCDC in regula-
tion
Bypass mode
—
—
—
60
10
mA
µF
Nominal output capacitor
CDCDC
4.7 µF ± 10% X7R capacitor used
for performance characterization2
4.7
Nominal inductor
LDCDC
CIN
± 20% tolerance
—
CDCDC
—
2.2
—
—
—
3
µH
µF
Ω
Nominal input capacitor
Resistance in bypass mode RBYP
Bypass switch from VREGVDD to
DVDD, VVREGVDD = 1.8 V
1.75
Powertrain PFET switch from
VREGVDD to VREGSW,
VVREGVDD = 1.8 V
—
0.86
1.5
Ω
Supply monitor threshold
programming range
VCMP_RNG
Programmable in 0.1 V steps
Supply falling edge trip point
2.0
-5
—
—
2.3
5
V
Supply monitor threshold ac- VCMP_ACC
curacy
%
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Rev. 1.0 | 21
EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Supply monitor threshold
hysteresis
VCMP_HYST
Positive hysteresis on the supply
rising edge referred to the falling
edge trip point
—
4
—
%
Supply monitor response
time
tCMP_DELAY
Supply falling edge at -100 mV /
µs
—
0.6
—
µs
Note:
1. The supported maximum VVREGVDD in regulation mode is a function of temperature and 10-year lifetime average load current.
See more details in 4.4.1 DC-DC Operating Limits.
2. Samsung CL10B475KQ8NQNC used for performance characterization. Actual capacitor values can be significantly de-rated from
their specified nominal value by the rated tolerance, as well as the application's AC voltage, DC bias, and temperature. The mini-
mum capacitance counting all error sources should be no less than 2.4 µF.
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Rev. 1.0 | 22
EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.4.1 DC-DC Operating Limits
The maximum supported voltage on the VREGVDD supply pin is limited under certain conditions. Maximum input voltage is a function
of temperature and the average load current over a 10-year lifetime. Figure 4.1 Lifetime average load current limit vs. Maximum input
voltage on page 23 shows the safe operating region under specific conditions. Exceeding this safe operating range may impact the
reliability and performance of the DC-DC converter.
The average load current for an application can typically be determined by examining the current profile during the time the device is
powered. For example, an application that is continuously powered which spends 99% of the time asleep consuming 2 µA and 1% of
the time active and consuming 10 mA has an average lifetime load current of about 102 µA.
Tj ≤ 125 °C
60
5
3.3
Maximum VVREGVDD (V)
3.8
Figure 4.1. Lifetime average load current limit vs. Maximum input voltage
The minimum input voltage for the DC-DC in EM0/EM1 mode is a function of the maximum load current, and the peak current setting.
Figure 4.2 Transient maximum load current vs. Minimum input voltage on page 23 shows the max load current vs. input voltage for
different DC-DC peak inductor current settings.
60
36
IPEAK = 150 mA
IPEAK = 90 mA
5
1.8
2.2
Minimum VVREGVDD (V)
Figure 4.2. Transient maximum load current vs. Minimum input voltage
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Rev. 1.0 | 23
EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.5 Thermal Characteristics
Table 4.4. Thermal Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
4-Layer PCB, Natural Convection1
Thermal Resistance Junction THE-
to Ambient QFN32 (4x4mm) TAJA_QFN32_4X4
Package
—
35.4
—
°C/W
4-Layer PCB, Natural Convection1
4-Layer PCB, Natural Convection1
Thermal Resistance Junction THE-
—
—
40.2
32.6
—
—
°C/W
°C/W
to Ambient TQFN32
(4x4mm) Package
TAJA_TQFN32_4X
4
Thermal Resistance, Junc-
tion to Ambient, QFN40
(5x5mm) Package
THE-
TAJA_QFN40_5X5
Note:
1. Measured according to JEDEC standard JESD51-2A. Integrated Circuit Thermal Test Method Environmental Conditions - Natural
Convection (Still Air).
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Rev. 1.0 | 24
EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.6 Current Consumption
4.6.1 MCU current consumption using DC-DC at 3.0 V input
Unless otherwise indicated, typical conditions are: VREGVDD = 3.0 V. AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8 V from DC-
DC. Voltage scaling level = VSCALE1. TA = 25 °C. Minimum and maximum values in this table represent the worst conditions across
process variation at TA = 25 °C.
Table 4.5. MCU current consumption using DC-DC at 3.0 V input
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in EM0 IACTIVE
mode with all peripherals dis-
abled
76.8 MHz HFRCO w/ DPLL refer-
enced to 38.4 MHz crystal, CPU
running Prime from flash,
VSCALE2
—
28
—
µA/MHz
76.8 MHz HFRCO w/ DPLL refer-
enced to 38.4 MHz crystal, CPU
running while loop from flash,
VSCALE2
—
—
27
37
—
—
µA/MHz
µA/MHz
76.8 MHz HFRCO w/ DPLL refer-
enced to 38.4 MHz crystal, CPU
running CoreMark loop from flash,
VSCALE2
38.4 MHz crystal, CPU running
Prime from flash
—
—
—
—
—
—
—
—
28
26
38
22
24
27
159
17
—
—
—
—
—
—
—
—
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
38.4 MHz crystal, CPU running
while loop from flash
38.4 MHz crystal, CPU running
CoreMark loop from flash
38 MHz HFRCO, CPU running
while loop from flash
26 MHz HFRCO, CPU running
while loop from flash
16 MHz HFRCO, CPU running
while loop from flash
1 MHz HFRCO, CPU running
while loop from flash
Current consumption in EM1 IEM1
mode with all peripherals dis-
abled
76.8 MHz HFRCO w/ DPLL refer-
enced to 38.4 MHz crystal,
VSCALE2
38.4 MHz crystal
38 MHz HFRCO
26 MHz HFRCO
16 MHz HFRCO
1 MHz HFRCO
—
—
—
—
—
17
13
—
—
—
—
—
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
15
18
150
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in EM2 IEM2_VS
mode, VSCALE0
Full RAM retention and RTC run-
ning from LFXO
—
1.40
—
µA
Full RAM retention and RTC run-
ning from LFRCO
—
—
1.40
1.75
—
—
µA
µA
Full RAM retention and RTC run-
ning from LFRCO in precision
mode
24 kB RAM retention and RTC
running from LFXO
—
—
1.32
1.66
—
—
µA
µA
24 kB RAM retention and RTC
running from LFRCO in precision
mode
8 kB RAM retention and RTC run-
ning from LFXO
—
—
—
1.21
1.20
1.03
—
—
—
µA
µA
µA
8 kB RAM retention and RTC run-
ning from LFRCO
8 kB RAM retention and RTC run-
ning from LFXO, Radio RAM and
CPU cache not retained
Current consumption in EM3 IEM3_VS
mode, VSCALE0
8 kB RAM retention and RTC run-
ning from ULFRCO
—
—
1.05
0.37
—
—
µA
µA
Additional current in EM2 or IPD0B_VS
EM3 when any peripheral in
PD0B is enabled1
Note:
1. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See for a list of the
peripherals in each power domain.
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Rev. 1.0 | 26
EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.6.2 MCU current consumption at 3.0 V
Unless otherwise indicated, typical conditions are: AVDD = DVDD = RFVDD = PAVDD = VREGVDD = 3.0 V. DC-DC not used. Voltage
scaling level = VSCALE1. TA = 25 °C. Minimum and maximum values in this table represent the worst conditions across process varia-
tion at TA = 25 °C.
Table 4.6. MCU current consumption at 3.0 V
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in EM0 IACTIVE
mode with all peripherals dis-
abled
76.8 MHz HFRCO w/ DPLL refer-
enced to 38.4 MHz crystal, CPU
running Prime from flash,
VSCALE2
—
42
—
µA/MHz
76.8 MHz HFRCO w/ DPLL refer-
enced to 38.4 MHz crystal, CPU
running while loop from flash,
VSCALE2
—
—
39
54
—
—
µA/MHz
µA/MHz
76.8 MHz HFRCO w/ DPLL refer-
enced to 38.4 MHz crystal, CPU
running CoreMark loop from flash,
VSCALE2
38.4 MHz crystal, CPU running
Prime from flash
—
—
—
—
—
—
—
—
40
39
55
33
35
40
228
24
—
—
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
38.4 MHz crystal, CPU running
while loop from flash
38.4 MHz crystal, CPU running
CoreMark loop from flash
—
38 MHz HFRCO, CPU running
while loop from flash
50
—
26 MHz HFRCO, CPU running
while loop from flash
16 MHz HFRCO, CPU running
while loop from flash
—
1 MHz HFRCO, CPU running
while loop from flash
830
—
Current consumption in EM1 IEM1
mode with all peripherals dis-
abled
76.8 MHz HFRCO w/ DPLL refer-
enced to 38.4 MHz crystal,
VSCALE2
38.4 MHz crystal
38 MHz HFRCO
26 MHz HFRCO
16 MHz HFRCO
1 MHz HFRCO
—
—
—
—
—
25
19
—
35
—
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
21
27
—
215
770
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Rev. 1.0 | 27
EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in EM2 IEM2_VS
mode, VSCALE0
Full RAM retention and RTC run-
ning from LFXO
—
1.94
—
µA
Full RAM retention and RTC run-
ning from LFRCO
—
—
—
1.95
1.81
2.34
4.9
—
µA
µA
µA
24 kB RAM retention and RTC
running from LFXO
24 kB RAM retention and RTC
running from LFRCO in precision
mode
—
8 kB RAM retention and RTC run-
ning from LFXO
—
—
—
1.64
1.65
1.39
—
—
—
µA
µA
µA
8 kB RAM retention and RTC run-
ning from LFRCO
8 kB RAM retention and RTC run-
ning from LFXO, Radio RAM and
CPU cache not retained
Current consumption in EM3 IEM3_VS
mode, VSCALE0
8 kB RAM retention and RTC run-
ning from ULFRCO
—
1.41
3.7
µA
Current consumption in EM4 IEM4
mode
No BURTC, no LF oscillator
BURTC with LFXO
—
—
—
0.17
0.50
234
0.43
—
µA
µA
µA
Current consumption during IRST
reset
Hard pin reset held
—
Additional current in EM2 or IPD0B_VS
EM3 when any peripheral in
PD0B is enabled1
—
0.56
—
µA
Note:
1. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See for a list of the
peripherals in each power domain.
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Rev. 1.0 | 28
EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.6.3 MCU current consumption at 1.8 V
Unless otherwise indicated, typical conditions are: AVDD = DVDD = RFVDD = PAVDD = VREGVDD = 1.8 V. DC-DC not used. Voltage
scaling level = VSCALE1. TA = 25 °C. Minimum and maximum values in this table represent the worst conditions across process varia-
tion at TA = 25 °C.
Table 4.7. MCU current consumption at 1.8 V
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in EM0 IACTIVE
mode with all peripherals dis-
abled
76.8 MHz HFRCO w/ DPLL refer-
enced to 38.4 MHz crystal, CPU
running Prime from flash,
VSCALE2
—
42
—
µA/MHz
76.8 MHz HFRCO w/ DPLL refer-
enced to 38.4 MHz crystal, CPU
running while loop from flash,
VSCALE2
—
—
39
54
—
—
µA/MHz
µA/MHz
76.8 MHz HFRCO w/ DPLL refer-
enced to 38.4 MHz crystal, CPU
running CoreMark loop from flash,
VSCALE2
38.4 MHz crystal, CPU running
Prime from flash
—
—
—
—
—
—
—
—
41
39
55
33
35
40
227
24
—
—
—
—
—
—
—
—
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
38.4 MHz crystal, CPU running
while loop from flash
38.4 MHz crystal, CPU running
CoreMark loop from flash
38 MHz HFRCO, CPU running
while loop from flash
26 MHz HFRCO, CPU running
while loop from flash
16 MHz HFRCO, CPU running
while loop from flash
1 MHz HFRCO, CPU running
while loop from flash
Current consumption in EM1 IEM1
mode with all peripherals dis-
abled
76.8 MHz HFRCO w/ DPLL refer-
enced to 38.4 MHz crystal,
VSCALE2
38.4 MHz crystal
38 MHz HFRCO
26 MHz HFRCO
16 MHz HFRCO
1 MHz HFRCO
—
—
—
—
—
25
19
—
—
—
—
—
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
21
27
213
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in EM2 IEM2_VS
mode, VSCALE0
Full RAM retention and RTC run-
ning from LFXO
—
1.87
—
µA
Full RAM retention and RTC run-
ning from LFRCO
—
—
—
1.86
1.73
2.26
—
—
—
µA
µA
µA
24 kB RAM retention and RTC
running from LFXO
24 kB RAM retention and RTC
running from LFRCO in precision
mode
8 kB RAM retention and RTC run-
ning from LFXO
—
—
—
1.57
1.56
1.32
—
—
—
µA
µA
µA
8 kB RAM retention and RTC run-
ning from LFRCO
8 kB RAM retention and RTC run-
ning from LFXO, Radio RAM and
CPU cache not retained
Current consumption in EM3 IEM3_VS
mode, VSCALE0
8 kB RAM retention and RTC run-
ning from ULFRCO
—
1.34
—
µA
Current consumption in EM4 IEM4
mode
No BURTC, no LF oscillator
BURTC with LFXO
—
—
—
0.13
0.44
190
—
—
—
µA
µA
µA
Current consumption during IRST
reset
Hard pin reset held
Additional current in EM2 or IPD0B_VS
EM3 when any peripheral in
PD0B is enabled1
—
0.54
—
µA
Note:
1. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See for a list of the
peripherals in each power domain.
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Rev. 1.0 | 30
EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.6.4 Radio current consumption at 3.0V using DCDC
RF current consumption measured with MCU in EM1, HCLK = 38.4 MHz, and all MCU peripherals disabled. Unless otherwise indica-
ted, typical conditions are: VREGVDD = 3.0V. AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8 V powered from DCDC. TA = 25 °C.
Minimum and maximum values in this table represent the worst conditions across process variation at TA = 25 °C.
Table 4.8. Radio current consumption at 3.0V using DCDC
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
System current consumption IRX_ACTIVE
in receive mode, active pack-
et reception
125 kbit/s, 2GFSK, f = 2.4 GHz,
VSCALE1, EM1P (Radio clocks
only)
—
3.7
—
mA
125 kbit/s, 2GFSK, f = 2.4 GHz,
VSCALE1
—
—
—
4.0
4.1
3.8
—
—
—
mA
mA
mA
125 kbit/s, 2GFSK, f = 2.4 GHz,
VSCALE2
500 kbit/s, 2GFSK, f = 2.4 GHz,
VSCALE1, EM1P (Radio clocks
only)
500 kbit/s, 2GFSK, f = 2.4 GHz,
VSCALE1
—
—
—
4.0
4.2
3.6
—
—
—
mA
mA
mA
500 kbit/s, 2GFSK, f = 2.4 GHz,
VSCALE2
1 Mbit/s, 2GFSK, f = 2.4 GHz,
VSCALE1, EM1P (Radio clocks
only)
1 Mbit/s, 2GFSK, f = 2.4 GHz,
VSCALE1
—
—
—
3.8
3.9
4.0
—
—
—
mA
mA
mA
1 Mbit/s, 2GFSK, f = 2.4 GHz,
VSCALE2
2 Mbit/s, 2GFSK, f = 2.4 GHz,
VSCALE1, EM1P (Radio clocks
only)
2 Mbit/s, 2GFSK, f = 2.4 GHz,
VSCALE1
—
—
4.2
4.4
—
—
mA
mA
2 Mbit/s, 2GFSK, f = 2.4 GHz,
VSCALE2
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Rev. 1.0 | 31
EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
System current consumption IRX_LISTEN
in receive mode, listening for
packet
125 kbit/s, 2GFSK, f = 2.4 GHz,
VSCALE1, EM1P (Radio clocks
only)
—
3.8
—
mA
125 kbit/s, 2GFSK, f = 2.4 GHz,
VSCALE1
—
—
—
4.0
4.1
3.8
—
—
—
mA
mA
mA
125 kbit/s, 2GFSK, f = 2.4 GHz,
VSCALE2
500 kbit/s, 2GFSK, f = 2.4 GHz,
VSCALE1, EM1P (Radio clocks
only)
500 kbit/s, 2GFSK, f = 2.4 GHz,
VSCALE1
—
—
—
4.0
4.1
3.6
—
—
—
mA
mA
mA
500 kbit/s, 2GFSK, f = 2.4 GHz,
VSCALE2
1 Mbit/s, 2GFSK, f = 2.4 GHz,
VSCALE1, EM1P (Radio clocks
only)
1 Mbit/s, 2GFSK, f = 2.4 GHz,
VSCALE1
—
—
—
3.8
4.0
4.1
—
—
—
mA
mA
mA
1 Mbit/s, 2GFSK, f = 2.4 GHz,
VSCALE2
2 Mbit/s, 2GFSK, f = 2.4 GHz,
VSCALE1, EM1P (Radio clocks
only)
2 Mbit/s, 2GFSK, f = 2.4 GHz,
VSCALE1
—
—
—
4.3
4.5
4.1
—
—
—
mA
mA
mA
2 Mbit/s, 2GFSK, f = 2.4 GHz,
VSCALE2
System current consumption ITX
in transmit mode
f = 2.4 GHz, CW, 0 dBm PA, 0
dBm output power, VSCALE1,
EM1P (Radio clocks only)
f = 2.4 GHz, CW, 6 dBm PA, 6
dBm output power, VSCALE1,
EM1P (Radio clocks only)
—
8.2
—
mA
f = 2.4 GHz, CW, 0 dBm PA, 0
dBm output power, VSCALE1
—
—
—
—
4.3
8.4
4.4
8.5
—
—
—
—
mA
mA
mA
mA
f = 2.4 GHz, CW, 6 dBm PA, 6
dBm output power, VSCALE1
f = 2.4 GHz, CW, 0 dBm PA, 0
dBm output power, VSCALE2
f = 2.4 GHz, CW, 6 dBm PA, 6
dBm output power, VSCALE2
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Rev. 1.0 | 32
EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.7 Flash Characteristics
Table 4.9. Flash Characteristics
Test Condition
Parameter
Symbol
Min
Typ
Max
Unit
Flash Supply voltage during VFLASH
write or erase
1.71
—
3.8
V
Flash erase cycles before
failure1
ECFLASH
TA ≤ 125 °C
TA ≤ 125 °C
10,000
—
—
cycles
Flash data retention1
Program Time
RETFLASH
tPROG
10
—
—
years
one word (32-bits)
42.1
10.3
11.4
11.7
—
44
10.9
12.9
13
45.6
11.3
14.4
14.3
1.45
1.34
1.28
uSec
uSec
ms
average per word over 128 words
Page Erase Time
Mass Erase Time
Program Current
Page Erase Current
Mass Erase Current
Note:
tPERASE
tMERASE
IPROG
Erases all of User Code area
ms
—
mA
IPERASE
IMERASE
Page Erase
Mass Erase
—
—
mA
—
—
mA
1. Flash data retention information is published in the Quarterly Quality and Reliability Report.
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Rev. 1.0 | 33
EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.8 Wake Up, Entry, and Exit times
Unless otherwise specified, these times are measured using the HFRCO at 19 MHz.
Table 4.10. Wake Up, Entry, and Exit times
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
WakeupTime from EM1
tEM1_WU
Code execution from flash
—
3
—
AHB
Clocks
Code execution from RAM
—
—
1.42
—
—
µs
µs
WakeupTime from EM2
tEM2_WU
Code execution from flash, No
Voltage Scaling
13.22
Code execution from RAM, No
Voltage Scaling
—
5.15
—
µs
Voltage scaling up one level1
Voltage scaling up two levels2
—
—
—
37.89
50.56
13.21
—
—
—
µs
µs
µs
WakupTime from EM3
tEM3_WU
Code execution from flash, No
Voltage Scaling
Code execution from RAM, No
Voltage Scaling
—
5.15
—
µs
Voltage scaling up one level1
—
—
37.90
50.55
—
—
µs
µs
Voltage scaling up two levels2
Code execution from flash
Code execution from flash
Code execution from flash
Code execution from flash
Code execution from flash
Up from VSCALE1 to VSCALE2
WakeupTime from EM4
Entry time to EM1
Entry time to EM2
Entry time to EM3
Entry time to EM4
tEM4_WU
tEM1_ENT
tEM2_ENT
tEM3_ENT
tEM4_ENT
tSCALE
—
—
—
—
—
—
—
8.81
1.29
5.23
5.23
9.96
32
—
—
—
—
—
—
—
ms
µs
µs
µs
µs
µs
µs
Voltage scaling in time in
EM03
Down from VSCALE2 to
VSCALE1
172
Note:
1. Voltage scaling one level is between VSCALE0 and VSCALE1 or between VSCALE1 and VSCALE2.
2. Voltage scaling two levels is between VSCALE0 and VSCALE2.
3. During voltage scaling in EM0, RAM is inaccessible and processor will be halted until complete.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.9 RFSENSE Low-energy Wake-on-RF
Table 4.11. RFSENSE Low-energy Wake-on-RF
Parameter
Symbol
Test Condition
Min
—
Typ
138
131
Max
—
Unit
nA
Average current
IRFSENSE
RF energy below wake threshold
Selective mode, RF energy above
threshold but no OOK sync detec-
ted
—
—
nA
RF level above which
THRESTRIG
Threshold set to -34 dBm
Threshold set to -22 dBm
Threshold set to -34 dBm
Threshold set to -22 dBm
-28
-19
—
—
—
—
—
—
—
dBm
dBm
dBm
dBm
RFSENSE will detect signal1
RF level below which
RFSENSE will not detect sig-
nal1
THRESNOTRIG
-40
-26
—
Sensitivity in selective OOK SENSOOK
mode1
Sensitivity for > 90% probability of
OOK detection2, threshold set to
-34 dBm
-28
—
—
dBm
Sensitivity for > 90% probability of
-19
—
—
dBm
OOK detection2, threshold set to
-22 dBm
Note:
1. Values collected with conducted measurements performed at the end of the matching network.
2. Selective wake signal is 1 kHz OOK Manchester-coded, 8 bits of preamble, 32-bit sync word.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.10 2.4 GHz RF Transceiver Characteristics
4.10.1 RF Transmitter Characteristics
4.10.1.1 RF Transmitter General Characteristics for the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8
V powered from DCDC. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.
Table 4.12. RF Transmitter General Characteristics for the 2.4 GHz Band
Parameter
Symbol
Test Condition
Min
2400
—
Typ
—
Max
2483.5
—
Unit
MHz
mA
RF tuning frequency range
FRANGE
Radio-only current consump- ITX_RADIO
tion while transmitting1
f = 2.4 GHz, CW, 0 dBm PA, 0
dBm output power
3.4
f = 2.4 GHz, CW, 6 dBm PA, 6
dBm output power
—
—
7.5
6
—
—
mA
Maximum TX power2
6 dBm PA3
0 dBm PA
6 dBm PA
0 dBm PA
POUTMAX
dBm
—
—
—
—
0
—
—
—
—
dBm
dBm
dBm
dB
Minimum active TX power
POUTMIN
-27
-28
0.04
Output power variation vs
supply voltage variation, fre-
quency = 2450 MHz
POUTVAR_V
6 dBm PA output power, using
DCDC with VREGVDD swept
from 1.8 to 3.0 V
0 dBm PA output power, using
DCDC with VREGVDD swept
from 1.8 to 3.0 V
—
0.03
—
dB
Output power variation vs
temperature, Frequency =
2450 MHz
POUTVAR_T
6 dBm PA at 6 dBm, (-40 to +125
°C)
—
—
—
—
0.18
1.4
—
—
—
—
dB
dB
dB
dB
0 dBm PA at 0 dBm, (-40 to +125
°C)
6 dBm PA at 6 dBm, (-40 to +85
°C)
0.17
1.0
0 dBm PA at 0 dBm, (-40 to +85
°C)
Output power variation vs RF POUTVAR_F
frequency
6 dBm PA, 6 dBm
0 dBm PA, 0 dBm
—
—
—
0.20
0.19
-47
—
—
—
dB
dB
Spurious emissions of har-
monics in restricted bands
per FCC Part 15.205/15.209
SPURHRM_FCC_ Continuous transmission of CW
dBm
carrier, Pout = POUTMAX, Test
Frequency = 2450 MHz.
R
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Spurious emissions out-of-
band (above 2.483 GHz or
below 2.4 GHz) in restricted
bands, per FCC part
SPUROOB_FCC_ Restricted bands 30-88 MHz,
—
-47
—
dBm
Continuous transmission of CW
R
carrier, Pout = POUTMAX, Test
Frequency = 2450 MHz
15.205/15.209
Restricted bands 88 - 216 MHz,
Continuous transmission of CW
carrier, Pout = POUTMAX, Test
Frequency = 2450 MHz
—
—
—
—
-47
-47
-47
-26
—
—
—
—
dBm
dBm
dBm
dBc
Restricted bands 216 - 960 MHz,
Continuous transmission of CW
carrier, Pout = POUTMAX, Test
Frequency = 2450 MHz
Restricted bands > 960 MHz,
Continuous transmission of CW
carrier, Pout = POUTMAX, Test
Frequency = 2450 MHz
Spurious emissions out-of-
band in non-restricted bands
per FCC Part 15.247
SPUROOB_FCC_ Frequencies above 2.483 GHz or
below 2.4 GHz, continuous trans-
NR
mission CW carrier, Pout
=
POUTMAX, Test Frequency =
2450 MHz
Spurious emissions per ETSI SPURETSI440
EN300.440
47-74 MHz,87.5-108 MHz,
174-230 MHz, 470-862 MHz, Pout
= POUTMAX, Test Frequency =
2450 MHz
—
—
-60
-42
—
—
dBm
dBm
25-1000 MHz, excluding above
frequencies. Pout = POUTMAX
,
Test Frequency = 2450 MHz
1G-14G, Pout = POUTMAX, Test
Frequency = 2450 MHz
—
—
-36
-26
—
—
dBm
dBm
Spurious emissions out-of-
band, per ETSI 300.328
SPURETSI328
[2400-2BW to 2400-BW],
[2483.5+BW to 2483.5+2BW],
Pout = POUTMAX, Test Frequency
= 2450 MHz
47-74 MHz, 87.5-118 MHz,
174-230 MHz, 470-862 MHz, Pout
= POUTMAX, Test Frequency =
2450 MHz
—
—
-60
-42
—
—
dBm
dBm
30-47 MHz, 74-87.5 MHz,
118-174 MHz, 230-470 MHz,
862-1000 MHz , Pout = POUTMAX
,
Test Frequency = 2450 MHz
1G-12.75 GHz, excluding bands
—
—
-36
-16
—
—
dBm
dBm
listed above, Pout = POUTMAX
,
Test Frequency = 2450 MHz
[2400-BW to 2400], [2483.5 to
2483.5+BW] Pout = POUTMAX
,
Test Frequency = 2450 MHz
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
Parameter
Note:
Symbol
Test Condition
Min
Typ
Max
Unit
1. Supply current to radio, supplied by DC-DC with 3.0 V, measured at VREGVDD.
2. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this data sheet can be found in the Max TX Power column of the Ordering Information Table.
3. The PA is capable of delivering higher than 6 dBm output power (see Figure 4.9 Transmitter Output Power on page 71). How-
ever, all transmitter characteristics and recommended application circuits are specified at 6 dBm output. If used with the recom-
mended application circuits above 6 dBm, harmonics may be higher than regulatory limits.
4.10.1.2 RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 1 Mbps Data Rate
Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8
V powered from DCDC. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.
Table 4.13. RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 1 Mbps Data Rate
Parameter
Symbol
Test Condition
Pout = 6 dBm
Pout = 0 dBm
Min
—
Typ
630
640
2.9
Max
—
Unit
kHz
kHz
Transmit 6 dB bandwidth
TXBW
—
—
Power spectral density limit
PSDLIMIT
Pout = 6 dBm, Per FCC part
15.247 at 6 dBm
—
—
dBm/
3kHz
Pout = 0 dBm, Per FCC part
15.247 at 0 dBm
—
—
—
—
—
—
—
—
-3.2
7.1
1.1
1.1
-41
-48
-47
-54
—
—
—
—
—
—
—
—
dBm/
3kHz
Per ETSI 300.328 at 10 dBm/1
MHz
dBm
MHz
MHz
dBm
dBm
dBm
dBm
Occupied channel bandwidth OCPETSI328
per ETSI EN300.328
Pout = 6 dBm 99% BW at highest
and lowest channels in band
Pout = 0 dBm 99% BW at highest
and lowest channels in band
In-band spurious emissions, SPURINB
with allowed exceptions1
Pout = 6 dbm, Inband spurs at ± 2
MHz
Pout = 0 dbm, Inband spurs at ± 2
MHz
Pout = 6 dBm Inband spurs at ± 3
MHz
Pout = 0dbm Inband spurs at ± 3
MHz
Note:
1. Per Bluetooth Core_5.1, Vol.6 Part A, Section 3.2.2, exceptions are allowed in up to three bands of 1 MHz width, centered on a
frequency which is an integer multiple of 1 MHz. These exceptions shall have an absolute value of -20 dBm or less.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.10.1.3 RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 2 Mbps Data Rate
Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8
V powered from DCDC. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.
Table 4.14. RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 2 Mbps Data Rate
Parameter
Symbol
Test Condition
Pout = 6 dBm
Pout = 0 dBm
Min
—
Typ
1250
1220
0.5
Max
—
Unit
kHz
kHz
Transmit 6 dB bandwidth
TXBW
—
—
Power spectral density limit
PSDLIMIT
Pout = 6 dBm, Per FCC part
15.247 at 6 dBm
—
—
dBm/
3kHz
Pout = 0 dBm, Per FCC part
15.247 at 0 dBm
—
—
—
—
—
—
—
—
-5.7
6.3
2.1
2.1
-41
-47
-46
-53
—
—
—
—
—
—
—
—
dBm/
3kHz
Per ETSI 300.328 at 10 dBm/1
MHz
dBm
MHz
MHz
dBm
dBm
dBm
dBm
Occupied channel bandwidth OCPETSI328
per ETSI EN300.328
Pout = 6 dBm 99% BW at highest
and lowest channels in band
Pout = 0 dBm 99% BW at highest
and lowest channels in band
In-band spurious emissions, SPURINB
with allowed exceptions1
Pout = 6 dbm, Inband spurs at ± 4
MHz
Pout = 0 dBm, Inband spurs at ± 4
MHz
Pout = 6 dBm Inband spurs at ± 6
MHz
Pout = 0 dbm Inband spurs at ± 6
MHz
Note:
1. Per Bluetooth Core_5.1, Vol.6 Part A, Section 3.2.2, exceptions are allowed in up to three bands of 1 MHz width, centered on a
frequency which is an integer multiple of 1 MHz. These exceptions shall have an absolute value of -20 dBm or less.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.10.1.4 RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 500 kbps Data Rate
Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8
V powered from DCDC. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.
Table 4.15. RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 500 kbps Data Rate
Parameter
Symbol
Test Condition
Pout = 6 dBm
Pout = 0 dBm
Min
—
Typ
640
650
2.8
Max
—
Unit
kHz
kHz
Transmit 6 dB bandwidth
TXBW
—
—
Power spectral density limit
PSDLIMIT
Pout = 6 dBm, Per FCC part
15.247 at 6 dBm
—
—
dBm/
3kHz
Pout = 0 dBm, Per FCC part
15.247 at 0 dBm
—
—
—
—
—
—
—
—
-3.5
7.1
1.1
1.1
-41
-48
-47
-54
—
—
—
—
—
—
—
—
dBm/
3kHz
Per ETSI 300.328 at 10 dBm/1
MHz
dBm
MHz
MHz
dBm
dBm
dBm
dBm
Occupied channel bandwidth OCPETSI328
per ETSI EN300.328
Pout = 6 dBm 99% BW at highest
and lowest channels in band
Pout = 0 dBm 99% BW at highest
and lowest channels in band
In-band spurious emissions, SPURINB
with allowed exceptions1
Pout = 6 dbm, Inband spurs at ± 2
MHz
Pout = 0 dbm, Inband spurs at ± 2
MHz
Pout = 6 dBm Inband spurs at ± 3
MHz
Pout = 0dbm Inband spurs at ± 3
MHz
Note:
1. Per Bluetooth Core_5.1, Vol.6 Part A, Section 3.2.2, exceptions are allowed in up to three bands of 1 MHz width, centered on a
frequency which is an integer multiple of 1 MHz. These exceptions shall have an absolute value of -20 dBm or less.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.10.1.5 RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 125 kbps Data Rate
Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8
V powered from DCDC. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.
Table 4.16. RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 125 kbps Data Rate
Parameter
Symbol
Test Condition
Pout = 6 dBm
Pout = 0 dBm
Min
—
Typ
600
600
2.0
Max
—
Unit
kHz
kHz
Transmit 6 dB bandwidth
TXBW
—
—
Power spectral density limit
PSDLIMIT
Pout = 6 dBm, Per FCC part
15.247 at 6 dBm
—
—
dBm/
3kHz
Pout = 0 dBm, Per FCC part
15.247 at 0 dBm
—
—
—
—
—
—
—
—
-4.2
7.1
1.1
1.1
-41
-47
-47
-54
—
—
—
—
—
—
—
—
dBm/
3kHz
Per ETSI 300.328 at 10 dBm/1
MHz
dBm
MHz
MHz
dBm
dBm
dBm
dBm
Occupied channel bandwidth OCPETSI328
per ETSI EN300.328
Pout = 6 dBm 99% BW at highest
and lowest channels in band
Pout = 0 dBm 99% BW at highest
and lowest channels in band
In-band spurious emissions, SPURINB
with allowed exceptions1
Pout = 6 dbm, Inband spurs at ± 2
MHz
Pout = 0 dbm, Inband spurs at ± 2
MHz
Pout = 6 dBm Inband spurs at ± 3
MHz
Pout = 0dbm Inband spurs at ± 3
MHz
Note:
1. Per Bluetooth Core_5.1, Vol.6 Part A, Section 3.2.2, exceptions are allowed in up to three bands of 1 MHz width, centered on a
frequency which is an integer multiple of 1 MHz. These exceptions shall have an absolute value of -20 dBm or less.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.10.1.6 RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8
V powered from DCDC. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.
Table 4.17. RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Error vector magnitude per
802.15.4-2011
EVM
Average across frequency, signal
is DSSS-OQPSK reference pack-
et, Pout = 6 dBm
—
3.0
—
% rms
Average across frequency, signal
is DSSS-OQPSK reference pack-
et, Pout = 0 dBm
—
3.0
—
% rms
Power spectral density limit
PSDLIMIT
Relative, at carrier ± 3.5 MHz,
Pout = 6 dBm
—
—
—
—
—
—
-50.7
-50.8
-52.5
-58.3
-1.4
—
—
—
—
—
—
dBc/
100kHz
Relative, at carrier ± 3.5 MHz,
Pout = 0 dBm
dBc/
100kHz
Absolute, at carrier ± 3.5 MHz,
Pout = 6 dBm
dBm/
100kHz
Absolute, at carrier ± 3.5 MHz,
Pout = 0 dBm
dBm/
100kHz
Per FCC part 15.247, Pout = 6
dBm
dBm/
3kHz
Per FCC part 15.247, Pout = 0
dBm
-7.4
dBm/
3kHz
ETSI 300.328 Pout = 6 dBm
ETSI 300.328 Pout = 0 dbm
—
—
—
5.6
-1.0
2.2
—
—
—
dBm
dBm
MHz
Occupied channel bandwidth OCPETSI328
per ETSI EN300.328
99% BW at highest and lowest
channels in band, Pout = 6 dBm
99% BW at highest and lowest
channels in band, Pout = 0 dBm
—
2.2
—
MHz
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.10.2 RF Receiver Characteristics
4.10.2.1 RF Receiver General Characteristics for the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8
V powered from DCDC. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.
Table 4.18. RF Receiver General Characteristics for the 2.4 GHz Band
Parameter
Symbol
Test Condition
Min
2400
—
Typ
—
Max
2483.5
—
Unit
MHz
mA
RF tuning frequency range
FRANGE
Radio-only current consump- IRX_RADIO
tion in receive mode1
2.5
Receive mode maximum
spurious emission
SPURRX
30 MHz to 1 GHz
1 GHz to 12 GHz
—
—
—
-63
-53
-47
—
—
—
dBm
dBm
dBm
Max spurious emissions dur- SPURRX_FCC
ing active receive mode, per
FCC Part 15.109(a)
216 MHz to 960 MHz, conducted
measurement
Above 960 MHz, conducted
measurement.
—
-47
—
dBm
2GFSK Sensitivity
SENS2GFSK
2 Mbps 2GFSK signal, 1% PER
—
—
-93
—
—
dBm
dBm
250 kbps 2GFSK signal, 0.1%
BER
-104
Note:
1. Supply current to radio, supplied by DC-DC with 3.0 V, measured at VREGVDD.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.10.2.2 RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 1 Mbps Data Rate
Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8
V powered from DCDC. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz, Packet length is 255 bytes.
Table 4.19. RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 1 Mbps Data Rate
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Signal is reference signal1
Max usable receiver input
level
SAT
—
10
—
dBm
Sensitivity
SENS
Signal is reference signal, 37 byte
payload2
—
—
-98.9
-97.4
—
—
dBm
dBm
Signal is reference signal, 255
byte payload1
With non-ideal signals3 1
(see notes)1 4
—
—
-96.9
8.7
—
—
dBm
dB
Signal to co-channel interfer- C/ICC
er
N ± 1 Adjacent channel se-
lectivity
C/I1
C/I2
C/I3
Interferer is reference signal at +1
MHz offset1 5 4 6
—
—
—
—
—
—
—
-6.6
-6.5
—
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
dB
Interferer is reference signal at -1
MHz offset1 5 4 6
N ± 2 Alternate channel se-
lectivity
Interferer is reference signal at +2
MHz offset1 5 4 6
-40.9
-39.9
-45.9
-46.2
-23.5
Interferer is reference signal at -2
MHz offset1 5 4 6
N ± 3 Alternate channel se-
lectivity
Interferer is reference signal at +3
MHz offset1 5 4 6
Interferer is reference signal at -3
MHz offset1 5 4 6
Selectivity to image frequen- C/IIM
cy
Interferer is reference signal at im-
age frequency with 1 MHz preci-
sion1 6
Selectivity to image frequen- C/IIM_1
cy ± 1 MHz
Interferer is reference signal at im-
age frequency +1 MHz with 1
—
—
—
-40.9
-6.6
—
—
—
dB
dB
MHz precision1 6
Interferer is reference signal at im-
age frequency -1 MHz with 1 MHz
precision1 6
n = 3 (see note7)
Intermodulation performance IM
-17.1
dBm
Note:
1. 0.017% Bit Error Rate.
2. 0.1% Bit Error Rate.
3. With non-ideal signals as specified in Bluetooth Test Specification RF-PHY.TS.5.0.1 section 4.7.1
4. Desired signal -67 dBm.
5. Desired frequency 2402 MHz ≤ Fc ≤ 2480 MHz.
6. With allowed exceptions.
7. As specified in Bluetooth Core specification version 5.1, Vol 6, Part A, Section 4.4
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.10.2.3 RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 2 Mbps Data Rate
Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8
V powered from DCDC. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz, Packet length is 255 bytes.
Table 4.20. RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 2 Mbps Data Rate
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Signal is reference signal1
Max usable receiver input
level
SAT
—
10
—
dBm
Sensitivity
SENS
Signal is reference signal, 37 byte
payload2
—
—
-96.2
-94.6
—
—
dBm
dBm
Signal is reference signal, 255
byte payload1
With non-ideal signals3 1
(see notes)1 4
—
—
-94.4
8.8
—
—
dBm
dB
Signal to co-channel interfer- C/ICC
er
N ± 1 Adjacent channel se-
lectivity
C/I1
C/I2
C/I3
Interferer is reference signal at +2
MHz offset1 5 4 6
—
—
—
—
—
—
—
-9.2
-6.6
—
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
dB
Interferer is reference signal at -2
MHz offset1 5 4 6
N ± 2 Alternate channel se-
lectivity
Interferer is reference signal at +4
MHz offset1 5 4 6
-43.3
-44.0
-48.6
-50.7
-23.8
Interferer is reference signal at -4
MHz offset1 5 4 6
N ± 3 Alternate channel se-
lectivity
Interferer is reference signal at +6
MHz offset1 5 4 6
Interferer is reference signal at -6
MHz offset1 5 4 6
Selectivity to image frequen- C/IIM
cy
Interferer is reference signal at im-
age frequency with 1 MHz preci-
sion1 6
Selectivity to image frequen- C/IIM_1
cy ± 2 MHz
Interferer is reference signal at im-
age frequency +2 MHz with 1
—
—
—
-43.3
-9.2
—
—
—
dB
dB
MHz precision1 6
Interferer is reference signal at im-
age frequency -2 MHz with 1 MHz
precision1 6
n = 3 (see note7)
Intermodulation performance IM
-18.8
dBm
Note:
1. 0.017% Bit Error Rate.
2. 0.1% Bit Error Rate.
3. With non-ideal signals as specified in Bluetooth Test Specification RF-PHY.TS.5.0.1 section 4.7.1
4. Desired signal -64 dBm.
5. Desired frequency 2402 MHz ≤ Fc ≤ 2480 MHz.
6. With allowed exceptions.
7. As specified in Bluetooth Core specification version 5.1, Vol 6, Part A, Section 4.4
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.10.2.4 RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 500 kbps Data Rate
Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8
V powered from DCDC. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz, Packet length is 255 bytes.
Table 4.21. RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 500 kbps Data Rate
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Signal is reference signal1
Max usable receiver input
level
SAT
—
10
—
dBm
Sensitivity
SENS
Signal is reference signal, 37 byte
payload2
—
—
-102.5
-101.2
—
—
dBm
dBm
Signal is reference signal, 255
byte payload1
With non-ideal signals3 1
(see notes)1 4
—
—
-100.2
2.7
—
—
dBm
dB
Signal to co-channel interfer- C/ICC
er
N ± 1 Adjacent channel se-
lectivity
C/I1
C/I2
C/I3
Interferer is reference signal at +1
MHz offset1 5 4 6
—
—
—
—
—
—
—
-8.0
-7.9
—
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
dB
Interferer is reference signal at -1
MHz offset1 5 4 6
N ± 2 Alternate channel se-
lectivity
Interferer is reference signal at +2
MHz offset1 5 4 6
-46.5
-49.9
-48.9
-53.8
-48.3
Interferer is reference signal at -2
MHz offset1 5 4 6
N ± 3 Alternate channel se-
lectivity
Interferer is reference signal at +3
MHz offset1 5 4 6
Interferer is reference signal at -3
MHz offset1 5 4 6
Selectivity to image frequen- C/IIM
cy
Interferer is reference signal at im-
age frequency with 1 MHz preci-
sion1 6
Selectivity to image frequen- C/IIM_1
cy ± 1 MHz
Interferer is reference signal at im-
age frequency +1 MHz with 1
—
—
-49.9
-46.5
—
—
dB
dB
MHz precision1 6
Interferer is reference signal at im-
age frequency -1 MHz with 1 MHz
precision1 6
Note:
1. 0.017% Bit Error Rate.
2. 0.1% Bit Error Rate.
3. With non-ideal signals as specified in Bluetooth Test Specification RF-PHY.TS.5.0.1 section 4.7.1
4. Desired signal -72 dBm.
5. Desired frequency 2402 MHz ≤ Fc ≤ 2480 MHz.
6. With allowed exceptions.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.10.2.5 RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 125 kbps Data Rate
Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8
V powered from DCDC. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz, Packet length is 255 bytes.
Table 4.22. RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 125 kbps Data Rate
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Signal is reference signal1
Max usable receiver input
level
SAT
—
10
—
dBm
Sensitivity
SENS
Signal is reference signal, 37 byte
payload2
—
—
-106.7
-106.4
—
—
dBm
dBm
Signal is reference signal, 255
byte payload1
With non-ideal signals3 1
(see notes)1 4
—
—
-105.8
0.9
—
—
dBm
dB
Signal to co-channel interfer- C/ICC
er
N ± 1 Adjacent channel se-
lectivity
C/I1
C/I2
C/I3
Interferer is reference signal at +1
MHz offset1 5 4 6
—
—
—
—
—
—
—
-13.6
-13.4
-52.6
-55.8
-53.7
-59.0
-52.7
—
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
dB
Interferer is reference signal at -1
MHz offset1 5 4 6
N ± 2 Alternate channel se-
lectivity
Interferer is reference signal at +2
MHz offset1 5 4 6
Interferer is reference signal at -2
MHz offset1 5 4 6
N ± 3 Alternate channel se-
lectivity
Interferer is reference signal at +3
MHz offset1 5 4 6
Interferer is reference signal at -3
MHz offset1 5 4 6
Selectivity to image frequen- C/IIM
cy
Interferer is reference signal at im-
age frequency with 1 MHz preci-
sion1 6
Selectivity to image frequen- C/IIM_1
cy ± 1 MHz
Interferer is reference signal at im-
age frequency +1 MHz with 1
—
—
-53.7
-52.6
—
—
dB
dB
MHz precision1 6
Interferer is reference signal at im-
age frequency -1 MHz with 1 MHz
precision1 6
Note:
1. 0.017% Bit Error Rate.
2. 0.1% Bit Error Rate.
3. With non-ideal signals as specified in Bluetooth Test Specification RF-PHY.TS.5.0.1 section 4.7.1
4. Desired signal -79 dBm.
5. Desired frequency 2402 MHz ≤ Fc ≤ 2480 MHz.
6. With allowed exceptions.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.10.2.6 RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8
V powered from DCDC. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.
Table 4.23. RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Signal is reference signal1. Packet
length is 20 octets
Max usable receiver input
level, 1% PER
SAT
—
10
—
dBm
Sensitivity, 1% PER
SENS
Signal is reference signal. Packet
length is 20 octets
—
—
—
-102.3
-1.7
—
—
—
dBm
dB
Co-channel interferer rejec- CCR
tion, 1% PER
Desired signal 3 dB above sensi-
tivity limit
High-side adjacent channel
rejection, 1% PER. Desired
is reference signal at 3 dB
above reference sensitivity
ACRP1
Interferer is reference signal at +1
channel-spacing
34.9
dB
level2
Low-side adjacent channel
rejection, 1% PER. Desired
is reference signal at 3 dB
above reference sensitivity
ACRM1
Interferer is reference signal at -1
channel-spacing
—
34.8
—
dB
level2
Alternate channel rejection,
1% PER. Desired is refer-
ence signal at 3 dB above
ACR2
Interferer is reference signal at ± 2
channel-spacing
—
—
47.1
34.1
—
—
dB
dB
reference sensitivity level2
Interferer is CW in image band3
Image rejection , 1% PER.
Desired is reference signal at
3 dB above reference sensi-
tivity level2
IR
Blocking rejection of all other BLOCK
channels, 1% PER. Desired
is reference signal at 3 dB
above reference sensitivity
level2. Interferer is reference
signal
Interferer frequency < Desired fre-
quency - 3 channel-spacing
—
—
53.2
53.1
—
—
dB
dB
Interferer frequency > Desired fre-
quency + 3 channel-spacing
RSSI resolution
RSSIRES
RSSILIN
-100 dBm to +5 dBm
—
—
0.25
+/-6
—
—
dB
dB
RSSI accuracy in the linear
region as defined by
802.15.4-2003
Note:
1. Reference signal is defined as O-QPSK DSSS per 802.15.4, Frequency range = 2400-2483.5 MHz, Symbol rate = 62.5 ksym-
bols/s.
2. Reference sensitivity level is -85 dBm.
3. Due to low-IF frequency, there is some overlap of adjacent channel and image channel bands. Adjacent channel CW blocker
tests place the Interferer center frequency at the Desired frequency ± 5 MHz on the channel raster, whereas the image rejection
test places the CW interferer near the image frequency of the Desired signal carrier, regardless of the channel raster.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.11 Oscillators
4.11.1 High Frequency Crystal Oscillator
Unless otherwise indicated, typical conditions are: AVDD = DVDD = 3.0 V. TA = 25 °C. Minimum and maximum values in this table
represent the worst conditions across process variation, operating supply voltage range, and operating temperature range.
Table 4.24. High Frequency Crystal Oscillator
Parameter
Symbol
Test Condition
see note1
Min
Typ
Max
Unit
Crystal Frequency
FHFXO
—
38.4
—
MHz
38.4 MHz, CL = 10 pF2 3
Supported crystal equivalent ESRHFXO_38M4
series resistance (ESR)
—
—
40
10
60
—
Ω
38.4 MHz, ESR = 40 Ohm3
Supported range of crystal
load capacitance4
CHFXO_LC
pF
Supply Current
Startup Time
IHFXO
—
—
415
160
—
—
µA
µs
TSTARTUP
38.4 MHz, ESR = 40 Ohm, CL =
10 pF
On-chip tuning cap step
size5
SSHFXO
—
0.04
—
pF
Note:
1. The BLE radio requires a 38.4 MHz crystal with a tolerance of ± 50 ppm over temperature and aging. Please use the recommen-
ded crystal.
2. The crystal should have a maximum ESR less than or equal to this maximum rating.
3. RF performance characteristics have been determined using crystals with an ESR of 40 Ω and CL of 10 pF.
4. Total load capacitance as seen by the crystal.
5. The tuning step size is the effective step size when incrementing one of the tuning capacitors by one count. The step size for the
each of the indivdual tuning capacitors is twice this value.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.11.2 Low Frequency Crystal Oscillator
Table 4.25. Low Frequency Crystal Oscillator
Parameter
Symbol
Test Condition
Min
—
Typ
32.768
—
Max
—
Unit
kHz
kΩ
kΩ
pF
Crystal Frequency
FLFXO
Supported Crystal equivalent ESRLFXO
series resistance (ESR)
GAIN = 0
GAIN = 1 to 3
GAIN = 0
GAIN = 1
GAIN = 2
—
80
—
—
100
6
Supported range of crystal
load capacitance 1
CLFXO_CL
4
—
6
—
10
pF
10
12.5
—
12.5
18
pF
GAIN = 3 (see note2)
—
pF
Current consumption
Startup Time
ICL12p5
ESR = 70 kOhm, CL = 12.5 pF,
GAIN3 = 2, AGC4 = 1
—
357
—
nA
TSTARTUP
ESR = 70 kOhm, CL = 7 pF,
GAIN3 = 1, AGC4 = 1
—
63
—
ms
On-chip tuning cap step size SSLFXO
—
—
0.26
4
—
—
pF
pF
On-chip tuning capacitor val- CLFXO_MIN
ue at minimum setting5
CAPTUNE = 0
On-chip tuning capacitor val- CLFXO_MAX
ue at maximum setting5
CAPTUNE = 0x4F
—
24.5
—
pF
Note:
1. Total load capacitance seen by the crystal
2. Crystals with a load capacitance of greater than 12 pF require external load capacitors.
3. In LFXO_CAL Register
4. In LFXO_CFG Register
5. The effective load capacitance seen by the crystal will be CLFXO/2. This is because each XTAL pin has a tuning cap and the two
caps will be seen in series by the crystal
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.11.3 High Frequency RC Oscillator (HFRCO)
Unless otherwise indicated, typical conditions are: AVDD = DVDD = 3.0 V. TA = 25 °C. Minimum and maximum values in this table
represent the worst conditions across process variation, operating supply voltage range, and operating temperature range.
Table 4.26. High Frequency RC Oscillator (HFRCO)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Frequency Accuracy
FHFRCO_ACC
For all production calibrated fre-
quencies
-3
—
3
%
Current consumption on all
supplies 1
IHFRCO
FHFRCO = 1 MHz
FHFRCO = 2 MHz
FHFRCO = 4 MHz
FHFRCO = 5 MHz
FHFRCO = 7 MHz
FHFRCO = 10 MHz
FHFRCO = 13 MHz
FHFRCO = 16 MHz
FHFRCO = 19 MHz
FHFRCO = 20 MHz
FHFRCO = 26 MHz
FHFRCO = 32 MHz
FHFRCO = 38 MHz
FHFRCO = 80 MHz
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
28
28
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
µA
µA
28
µA
30
µA
60
µA
66
µA
79
µA
88
µA
92
µA
105
118
141
172
289
2.72
µA
µA
µA
µA
µA
Clock out current for
HFRCODPLL2
ICLKOUT_HFRCOD FORECEEN bit of CTRL = 1 and
µA/MHz
the CLKOUTDIS0 bit of TEST = 1.
PLL
FORECEEN bit of CTRL i= 1 and
the CLKOUTDIS1 bit of TEST = 1.
—
0.36
—
µA/MHz
Startup Time3
TSTARTUP
FREQRANGE = 0 to 7
FREQRANGE = 8 to 15
—
—
1.2
0.6
—
—
µs
µs
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
3.71
4.39
5.25
6.22
7.88
9.9
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
5.24
6.26
7.55
9.01
11.6
14.6
17.0
20.9
24.7
30.4
34.9
44.4
51.0
64.6
74.8
87.4
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Band Frequency Limits4
fHFRCO_BAND
FREQRANGE = 0
FREQRANGE = 1
FREQRANGE = 2
FREQRANGE = 3
FREQRANGE = 4
FREQRANGE = 5
FREQRANGE = 6
FREQRANGE = 7
FREQRANGE = 8
FREQRANGE = 9
FREQRANGE = 10
FREQRANGE = 11
FREQRANGE = 12
FREQRANGE = 13
FREQRANGE = 14
FREQRANGE = 15
11.5
14.1
16.4
19.8
22.7
28.6
33.0
42.2
48.8
57.6
Note:
1. Does not include additional clock tree current. See specifications for additional current when selected as a clock source for a par-
ticular clock multiplexer.
2. When the HFRCO is enabled for characterization using the FORCEEN bit, the total current will be the HFRCO core current plus
the specified CLKOUT current. When the HFRCO is enabled on demand, the clock current may be different.
3. Hardware delay ensures settling to within ± 0.5%. Hardware also enforces this delay on a band change.
4. The frequency band limits represent the lowest and highest freqeuncy which each band can achieve over the operating range.
4.11.4 Fast Start_Up RC Oscillator (FSRCO)
Table 4.27. Fast Start_Up RC Oscillator (FSRCO)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
FSRCO frequency
FFSRCO
17.2
20
21.2
MHz
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.11.5 Precision Low Frequency RC Oscillator (LFRCO)
Table 4.28. Precision Low Frequency RC Oscillator (LFRCO)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Nominal oscillation frequen- FLFRCO
cy
—
32.768
—
kHz
Frequency accuracy
FLFRCO_ACC
Normal mode
-3
—
—
3
%
Precision mode1, across operat-
ing temperature range2
-500
500
ppm
Startup time
tSTARTUP
Normal mode
—
—
204
—
—
µs
Precision mode1
Normal mode
11.7
ms
Current consumption
ILFRCO
—
—
175
655
—
—
nA
nA
Precision mode1, T = stable at 25
°C 3
Note:
1. The LFRCO operates in high-precision mode when CFG_HIGHPRECEN is set to 1. High-precision mode is not available in EM4.
2. Includes ± 40 ppm frequency tolerance of the HFXO crystal.
3. Includes periodic re-calibration against HFXO crystal oscillator.
4.11.6 Ultra Low Frequency RC Oscillator
Table 4.29. Ultra Low Frequency RC Oscillator
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Oscillation Frequency
FULFRCO
0.944
1.0
1.095
kHz
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.12 GPIO Pins (3V GPIO pins)
Table 4.30. GPIO Pins (3V GPIO pins)
Test Condition
Parameter
Symbol
Min
Typ
Max
Unit
Leakage current
ILEAK_IO
MODEx = DISABLED, IOVDD =
1.71 V
—
1.9
—
nA
MODEx = DISABLED, IOVDD =
3.0 V
—
—
—
2.5
—
—
nA
nA
nA
MODEx = DISABLED, IOVDD =
3.8 V TA = 85 °C
150
200
Pins other than PA00, PA03,
PB00, PC03, PC04 and PD00;
MODEx = DISABLED, IOVDD =
3.8 V TA = 125 °C
—
Pins PA00, PA03, PB00, PC03,
PC04 and PD00; MODEx = DISA-
BLED, IOVDD = 3.8 V TA = 125
°C
—
—
550
nA
Input low voltage1
VIL
Any GPIO pin
RESETn
—
—
—
—
—
—
—
0.3*IOVDD
V
V
V
V
V
0.3*DVDD
Input high voltage1
VIH
Any GPIO pin
RESETn
0.7*IOVDD
0.7*DVDD
—
—
—
Hysteresis of input voltage
VHYS
Any GPIO pin
0.05*IOVD
D
RESETn
0.05*DVDD
—
—
—
—
V
V
Output high voltage
Output low voltage
GPIO rise time
VOH
Sourcing 20mA, IOVDD = 3.0 V
0.8 *
IOVDD
Sourcing 8mA, IOVDD = 1.71 V
Sinking 20mA, IOVDD = 3.0 V
Sinking 8mA, IOVDD = 1.71 V
0.6 *
IOVDD
—
—
—
V
V
VOL
—
—
—
—
—
—
0.2 *
IOVDD
—
0.4 *
IOVDD
V
TGPIO_RISE
IOVDD = 3.0 V, Cload = 50pF,
SLEWRATE = 4, 10% to 90%
8.4
13
—
—
—
—
ns
ns
ns
ns
IOVDD = 1.71 V, Cload = 50pF,
SLEWRATE = 4, 10% to 90%
GPIO fall time
TGPIO_FALL
IOVDD = 3.0 V, Cload = 50pF,
SLEWRATE = 4, 90% to 10%
7.1
11.9
IOVDD = 1.71 V, Cload = 50pF,
SLEWRATE = 4, 90% to 10%
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Pull up/down resistance2
RPULL
Any GPIO pin. Pull-up to IOVDD:
MODEn = DISABLE DOUT=1.
Pull-down to VSS: MODEn =
WIREDORPULLDOWN DOUT =
0.
35
44
55
kΩ
RESETn pin. Pull-up to DVDD
MODE = INPUT, DOUT = 1
35
—
44
27
55
—
kΩ
ns
Maximum filtered glitch width TGF
Note:
1. GPIO input thresholds are proportional to the IOVDD pin. RESETn input thresholds are proportional to DVDD.
2. GPIO pull-ups connect to IOVDD supply, pull-downs connect to VSS. RESETn pull-up connects to DVDD.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.13 Analog to Digital Converter (IADC)
Specified at 1 Msps, ADCCLK = 10 MHz, OSR=2, unless otherwise indicated.
Table 4.31. Analog to Digital Converter (IADC)
Parameter
Symbol
VAVDD
Test Condition
Min
Typ
—
Max
3.8
Unit
V
Main analog supply
Normal Mode
1.71
0
Maximum Input Range1
Full-Scale Voltage
VIN_MAX
Maximum allowable input voltage
—
AVDD
V
VFS
VIN
Voltage required for Full-Scale
measurement
—
VREF / Gain
—
Input Measurement Range
Differential Mode - Plus and Mi-
nus inputs
-VFS
—
—
+VFS
VFS
V
V
Single Ended Mode - One input
tied to ground
0
Input Sampling Capacitance Cs
Analog Gain = 1x
—
—
—
—
—
—
—
—
1.8
3.6
7.2
0.9
—
—
—
pF
pF
Analog Gain = 2x
Analog Gain = 4x
—
pF
Analog Gain = 0.5x
Normal Mode
—
pF
ADC clock frequency
Throughput rate
fCLK
10
1
MHz
Msps
ksps
µA
fSAMPLE
fCLK = 10 MHz, OSR = 2
fCLK = 10 MHz, OSR = 32
—
—
76.9
385
Current from all supplies,
Continuous operation
IADC_CONT
Normal Mode, 1 Msps, OSR = 2,
fCLK = 10 MHz
290
Current in Standby mode.
ADC is not functional but can
wake up in 1us.
ISTBY
Normal Mode
—
16
—
µA
ADC Startup Time
tstartup
From power down state
From Standby state
—
—
—
5
1
—
—
—
µs
µs
ADC Resolution2
Resolution
DNL
12
bits
Differential Nonlinearity
Differential Input, OSR = 2, (No
missing codes) .
-1
+/- 0.25
+/- 0.65
11.7
1.5
2.5
—
LSB12
LSB12
bits
Integral Nonlinearity
INL
Normal Mode, Differential Input,
OSR = 2.
-2.5
10.5
Effective number of bits3
ENOB
Differential Input. Gain = 1x, OSR
= 2, fIN = 10 kHz, Internal
VREF=1.21V. OSR=2
Differential Input. Gain = 1x, OSR
= 32, fIN = 2.5 kHz, Internal VREF
= 1.21 V.
—
—
13.5
14.3
—
—
bits
bits
Differential Input. Gain = 1x, OSR
= 32, fIN = 2.5 kHz, External
VREF = 1.25 V.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Signal to Noise + Distortion
Ratio3
SNDR
Differential Input. Gain=1x, OSR =
2, fIN = 10 kHz, Internal
VREF=1.21V
65
72.3
—
dB
Differential Input. Gain=2x, OSR =
2, fIN = 10 kHz, Internal
VREF=1.21V
—
—
—
—
72
72.3
68.8
72.5
-80.8
86.5
—
—
dB
dB
dB
dB
dB
Differential Input. Gain=4x, OSR =
2, fIN = 10 kHz, Internal
VREF=1.21V
Differential Input. Gain=0.5x, OSR
= 2, fIN = 10 kHz, Internal
VREF=1.21V
—
Total Harmonic Distortion
THD
Differential Input. Gain=1x, OSR =
2, fIN = 10 kHz, Internal
VREF=1.21V
-70
—
Spurious-Free Dynamic
Range
SFDR
CMRR
Differential Input. Gain=1x, OSR =
2, fIN = 10 kHz, Internal
VREF=1.21V
Common Mode Rejection
Ratio
Normal Mode. DC to 100 Hz
Normal Mode. AC high frequency
Normal mode. DC to 100 Hz
—
—
—
—
87.0
68.6
80.4
33.4
—
—
—
—
dB
dB
dB
dB
Power Supply Rejection Ra- PSRR
tio
Normal mode. AC high frequency,
using VREF pad.
Normal mode. AC high frequency,
using internal VBGR.
—
65.2
—
dB
%
%
%
%
%
Gain Error
GE
GAIN=1 and 0.5, using external
VREF, direct mode.
-0.3
-0.4
-0.7
-1.1
-1.5
0.069
0.151
0.186
0.227
0.023
0.3
0.4
0.7
1.1
1.5
GAIN=2, using external VREF, di-
rect mode.
GAIN=3, using external VREF, di-
rect mode.
GAIN=4, using external VREF, di-
rect mode.
Internal VREF4, all GAIN settings
GAIN=1 and 0.5, Differential Input
GAIN=2, Differential Input
Offset
OFFSET
-3
-4
0.27
0.27
0.25
0.29
—
3
LSB
LSB
LSB
LSB
V
4
GAIN=3, Differential Input
-4
4
4
GAIN=4, Differential Input
-4
External reference voltage
range1
VEVREF
1.0
AVDD
Internal Reference voltage
VIVREF
—
1.21
—
V
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
Parameter
Note:
Symbol
Test Condition
Min
Typ
Max
Unit
1. When inputs are routed to external GPIO pins, the maximum pin voltage is limited to the lower of the IOVDD and AVDD supplies.
2. ADC output resolution depends on the OSR and digital averaging settings. With no digital averaging, ADC output resolution is 12
bits at OSR=2, 13 bits at OSR = 4, 14 bits at OSR = 8, 15 bits at OSR = 16, 16 bits at OSR = 32 and 17 bits at OSR = 64. Digital
averaging has a similar impact on ADC output resolution. See the product reference manual for additional details.
3. The relationship between ENOB and SNDR is specified according to the equation: ENOB = (SNDR - 1.76) / 6.02.
4. Includes error from internal VREF drift.
4.14 Temperature Sense
Table 4.32. Temperature Sense
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Temperature sensor range1
TRANGE
-40
—
125
°C
Temperature sensor resolu- TRESOLUTION
tion
—
0.25
—
°C
Measurement noise (RMS)
TNOISE
Single measurement
—
—
0.6
—
—
°C
°C
16-sample average (TEMPAVG-
NUM = 0)
0.17
64-sample average (TEMPAVG-
NUM = 1)
—
—
0.12
3.14
—
—
—
3
°C
°C
°C
°C
°C
Temperature offset
TOFF
Mean error of uncorrected output
across full temperature range
Temperature sensor accura- TACC
cy2 3
Direct output accuracy after mean
error (TOFF) removed
-3
After linearization in software, no
calibration
-2
—
2
After linearization in software, with
single-temperature calibration at
25 °C4
-1.5
—
1.5
Measurement interval
tMEAS
—
250
—
ms
Note:
1. The sensor reports absolute die temperature in °K. All specifications are in °C to match the units of the specified product temper-
aure range.
2. Error is measured as the deviation of the mean temperature reading from the expected die temperature. Accuracy numbers rep-
resent statistical minimum and maximum using ± 4 standard deviations of measured error.
3. The raw output of the temperature sensor is a predictable curve. It can be linearized with a polynomial function for additional ac-
curacy.
4. Assuming calibration accuracy of ± 0.25 °C.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.15 Brown Out Detectors
4.15.1 DVDD BOD
BOD Thresholds on DVDD in EM0 and EM1 only, unless otherwise noted. Typical conditions are at TA = 25 °C. Minimum and maxi-
mum values in this table represent the worst conditions across process variation, operating supply voltage range, and operating tem-
perature range.
Table 4.33. DVDD BOD
Parameter
Symbol
Test Condition
Supply Rising
Supply Falling
Min
—
Typ
1.64
1.65
0.95
Max
1.71
—
Unit
V
BOD threshold
VDVDD_BOD
1.62
—
V
BOD response time
BOD hysteresis
Note:
tDVDD_BOD_DE-
Supply dropping at 100mV/µs
slew rate1
—
µs
LAY
VDVDD_BOD_HYS
—
20
—
mV
T
1. If the supply slew rate exceeds the specified slew rate, the BOD may trip later than expected (at a threshold below the minimum
specified threshold), or the BOD may not trip at all (e.g., if the supply ramps down and then back up at a very fast rate)
4.15.2 LE DVDD BOD
BOD thresholds on DVDD pin for low energy modes EM2 to EM4, unless otherwise noted.
Table 4.34. LE DVDD BOD
Parameter
Symbol
Test Condition
Min
1.5
—
Typ
—
Max
1.71
—
Unit
V
BOD threshold
BOD response time
VDVDD_LE_BOD
Supply Falling
tDVDD_LE_BOD_D Supply dropping at 2mV/µs slew
50
µs
rate1
ELAY
BOD hysteresis
VDVDD_LE_BOD_
—
20
—
mV
HYST
Note:
1. If the supply slew rate exceeds the specified slew rate, the BOD may trip later than expected (at a threshold below the minimum
specified threshold), or the BOD may not trip at all (e.g., if the supply ramps down and then back up at a very fast rate)
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.15.3 AVDD and IOVDD BODs
BOD thresholds for AVDD BOD and IOVDD BOD. Available in all energy modes.
Table 4.35. AVDD and IOVDD BODs
Parameter
Symbol
VBOD
Test Condition
Min
1.45
—
Typ
—
Max
1.71
—
Unit
V
BOD threshold
BOD response time
Supply falling
tBOD_DELAY
Supply dropping at 2mV/µs slew
rate1
50
µs
BOD hysteresis
VBOD_HYST
—
20
—
mV
Note:
1. If the supply slew rate exceeds the specified slew rate, the BOD may trip later than expected (at a threshold below the minimum
specified threshold), or the BOD may not trip at all (e.g., if the supply ramps down and then back up at a very fast rate)
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.16 PDM Timing Specifications
PDM Microphone Mode
PDM_CLK
tISU tIH
tISU tIH
PDM_DAT0-3
L
R
L
R
L
PDM Sensor Mode
PDM_CLK
tISU
tIH
PDM_DAT0-3
Figure 4.3. PDM Timing Diagrams
4.16.1 Pulse Density Modulator (PDM), Common DBUS
Timing specifications are for all PDM signals routed to the same DBUS (DBUSAB or DBUSCD), though routing to the same GPIO port
is the optimal configuration. CLOAD < 20 pF. System voltage scaling = VSCALE1 or VSCALE2. All GPIO set to slew rate = 6. Data delay
(PDM_CFG1_DLYMUXSEL) = 0.
Table 4.36. Pulse Density Modulator (PDM), Common DBUS
Parameter
Symbol
Test Condition
Microphone mode
Sensor mode
Min
—
Typ
—
—
—
—
—
—
—
—
Max
5
Unit
MHz
MHz
%
PDM_CLK frequency during FPDM_CLK
data transfer
—
20
PDM_CLK duty cycle
PDM_CLK rise time
PDM_CLK fall time
Input setup time
DCPDM_CLK
47.5
—
52.5
5.5
5.5
—
tR
ns
tF
—
ns
tISU
Microphone mode
Sensor mode
30
20
3
ns
—
ns
Input hold time
tIH
—
ns
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.17 USART SPI Master Timing
tCS_MO
CS
tSCLK_MO
SCLK
CLKPOL = 0
tSCLK
SCLK
CLKPOL = 1
MOSI
MISO
tSU_MI
tH_MI
Figure 4.4. SPI Master Timing (SMSDELAY = 0)
tCS_MO
CS
tSCLK_MO
SCLK
CLKPOL = 0
tSCLK
SCLK
CLKPOL = 1
MOSI
MISO
tSU_MI
tH_MI
Figure 4.5. SPI Master Timing (SMSDELAY = 1)
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.17.1 SPI Master Timing, Voltage Scaling = VSCALE2
Table 4.37. SPI Master Timing, Voltage Scaling = VSCALE2
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK period 1 2 3
tSCLK
2*tHFPERCL
—
—
ns
K
CS to MOSI 1 2
tCS_MO
tSCLK_MO
tSU_MI
-22
—
—
22.5
14.5
ns
ns
SCLK to MOSI 1 2
MISO setup time 1 2
-14.5
IOVDD = 1.62 V
IOVDD = 3.0 V
38.5
28.5
-8.5
—
—
—
—
—
—
ns
ns
ns
MISO hold time 1 2
tH_MI
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1
2. Measurement done with 8 pF output loading at 10% and 90% of VDD
.
3. tHFPERCLK is one period of the selected HFPERCLK.
4.17.2 SPI Master Timing, Voltage Scaling = VSCALE1
Table 4.38. SPI Master Timing, Voltage Scaling = VSCALE1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK period 1 2 3
tSCLK
2*tHFPERCL
—
—
ns
K
CS to MOSI 1 2
tCS_MO
tSCLK_MO
tSU_MI
-33
-15
—
—
34.5
26
ns
ns
SCLK to MOSI 1 2
MISO setup time 1 2
IOVDD = 1.62 V
IOVDD = 3.0 V
47
39
—
—
—
—
—
—
ns
ns
ns
MISO hold time 1 2
tH_MI
-9.5
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1
2. Measurement done with 8 pF output loading at 10% and 90% of VDD
.
3. tHFPERCLK is one period of the selected HFPERCLK.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.18 USART SPI Slave Timing
tCS_ACT_MI
CS
tCS_DIS_MI
SCLK
CLKPOL = 0
tSCLK_HI
tSCLK_LO
SCLK
tSU_MO
CLKPOL = 1
tSCLK
tH_MO
MOSI
MISO
tSCLK_MI
Figure 4.6. SPI Slave Timing
4.18.1 SPI Slave Timing, Voltage Scaling = VSCALE2
Table 4.39. SPI Slave Timing, Voltage Scaling = VSCALE2
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK period 1 2 3
tSCLK
6*tHFPERCL
—
—
ns
K
SCLK high time1 2 3
SCLK low time1 2 3
tSCLK_HI
2.5*tHFPER
—
—
—
—
ns
ns
CLK
tSCLK_LO
2.5*tHFPER
CLK
CS active to MISO 1 2
CS disable to MISO 1 2
MOSI setup time 1 2
MOSI hold time 1 2 3
SCLK to MISO 1 2 3
tCS_ACT_MI
tCS_DIS_MI
tSU_MO
25
19.5
4.5
5
—
—
—
—
—
47.5
38.5
—
ns
ns
ns
ns
ns
tH_MO
—
tSCLK_MI
22 +
1.5*tHFPER
33.5 +
2.5*tHFPER
CLK
CLK
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).
2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD).
3. tHFPERCLK is one period of the selected HFPERCLK.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.18.2 SPI Slave Timing, Voltage Scaling = VSCALE1
Table 4.40. SPI Slave Timing, Voltage Scaling = VSCALE1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK period 1 2 3
tSCLK
6*tHFPERCL
—
—
ns
K
SCLK high time1 2 3
SCLK low time1 2 3
tSCLK_HI
2.5*tHFPER
—
—
—
—
ns
ns
CLK
tSCLK_LO
2.5*tHFPER
CLK
CS active to MISO 1 2
CS disable to MISO 1 2
MOSI setup time 1 2
MOSI hold time 1 2 3
SCLK to MISO 1 2 3
tCS_ACT_MI
tCS_DIS_MI
tSU_MO
30.5
25
—
—
—
—
—
57.5
55
ns
ns
ns
ns
ns
7.5
8.5
—
tH_MO
—
tSCLK_MI
24.5 +
1.5*tHFPER
45.5 +
2.5*tHFPER
CLK
CLK
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).
2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD).
3. tHFPERCLK is one period of the selected HFPERCLK.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.19 I2C Electrical Specifications
4.19.1 I2C Standard-mode (Sm)
CLHR set to 0 in the I2Cn_CTRL register.
Table 4.41. I2C Standard-mode (Sm)
Test Condition
Parameter
Symbol
Min
Typ
Max
Unit
SCL clock frequency1
SCL clock low time
SCL clock high time
SDA set-up time
fSCL
0
—
100
kHz
tLOW
4.7
4
—
—
—
—
—
—
—
—
—
—
µs
µs
ns
ns
µs
tHIGH
tSU_DAT
tHD_DAT
250
0
SDA hold time
Repeated START condition tSU_STA
set-up time
4.7
Repeated START condition tHD_STA
hold time
4.0
—
—
µs
STOP condition set-up time tSU_STO
4.0
4.7
—
—
—
—
µs
µs
Bus free time between a
tBUF
STOP and START condition
Note:
1. The maximum SCL clock frequency listed is assuming that an arbitrary clock frequency is available. The maximum attainable
SCL clock frequency may be slightly less using the HFXO or HFRCO due to the limited frequencies available. The CLKDIV
should be set to a value that keeps the SCL clock frequency below the max value listed.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.19.2 I2C Fast-mode (Fm)
CLHR set to 1 in the I2Cn_CTRL register.
Table 4.42. I2C Fast-mode (Fm)
Test Condition
Parameter
Symbol
Min
Typ
Max
Unit
SCL clock frequency1
SCL clock low time
SCL clock high time
SDA set-up time
fSCL
0
—
400
kHz
tLOW
1.3
0.6
100
0
—
—
—
—
—
—
—
—
—
—
µs
µs
ns
ns
µs
tHIGH
tSU_DAT
tHD_DAT
SDA hold time
Repeated START condition tSU_STA
set-up time
0.6
Repeated START condition tHD_STA
hold time
0.6
—
—
µs
STOP condition set-up time tSU_STO
0.6
1.3
—
—
—
—
µs
µs
Bus free time between a
tBUF
STOP and START condition
Note:
1. The maximum SCL clock frequency listed is assuming that an arbitrary clock frequency is available. The maximum attainable
SCL clock frequency may be slightly less using the HFXO or HFRCO due to the limited frequencies available. The CLKDIV
should be set to a value that keeps the SCL clock frequency below the max value listed.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.19.3 I2C Fast-mode Plus (Fm+)
CLHR set to 1 in the I2Cn_CTRL register.
Table 4.43. I2C Fast-mode Plus (Fm+)
Test Condition
Parameter
Symbol
Min
Typ
Max
Unit
SCL clock frequency1
SCL clock low time
SCL clock high time
SDA set-up time
fSCL
0
—
1000
kHz
tLOW
0.5
0.26
50
—
—
—
—
—
—
—
—
—
—
µs
µs
ns
ns
µs
tHIGH
tSU_DAT
tHD_DAT
SDA hold time
0
Repeated START condition tSU_STA
set-up time
0.26
Repeated START condition tHD_STA
hold time
0.26
—
—
µs
STOP condition set-up time tSU_STO
0.26
0.5
—
—
—
—
µs
µs
Bus free time between a
tBUF
STOP and START condition
Note:
1. The maximum SCL clock frequency listed is assuming that an arbitrary clock frequency is available. The maximum attainable
SCL clock frequency may be slightly less using the HFXO or HFRCO due to the limited frequencies available. The CLKDIV
should be set to a value that keeps the SCL clock frequency below the max value listed.
4.20 Typical Performance Curves
Typical performance curves indicate typical characterized performance under the stated conditions.
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Electrical Specifications
4.20.1 Supply Current
Figure 4.7. EM0 and EM1 Typical Supply Current vs. Temperature
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
Figure 4.8. EM2 and EM4 Typical Supply Current vs. Temperature
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.20.2 RF Characteristics
Figure 4.9. Transmitter Output Power
Note: Although the 6 dBm PA is capable of delivering more than 6 dBm output power, all transmitter characteristics and recommended
application circuits are specifiat 6 dBm. Above 6 dBm, current consumption will increase and harmonics may be higher than regulatory
limits.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Electrical Specifications
4.20.3 DC-DC Converter
Performance characterized with Samsung CIG22H2R2MNE (LDCDC = 2.2 uH ) and Samsung CL10B475KQ8NQNC (CDCDC = 4.7 uF)
Figure 4.10. DC-DC Efficiency
4.20.4 IADC
Typical performance is shown using 10 MHz ADC clock for fastest sampling speed and adjusting oversampling ratio (OSR).
Figure 4.11. Typical ENOB vs. Oversampling Ratio
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Typical Connections
5. Typical Connections
5.1 Power
Typical power supply connections are shown in the following figures.
VDD
Main
Supply
+
–
VREGVDD
AVDD
IOVDD
VREGSW
VREGVSS
HFXTAL_I
HFXTAL_O
LFXTAL_I
38.4 MHz
DVDD
32.768 kHz
(optional)
LFXTAL_O
DECOUPLE
VDD
RFVDD
PAVDD
CDECOUPLE
Figure 5.1. EFR32BG22 Typical Application Circuit: Direct Supply Configuration without DCDC
VDD
Main
Supply
+
–
CIN
VREGVDD
AVDD
IOVDD
LDCDC
VDCDC
VREGSW
VREGVSS
HFXTAL_I
HFXTAL_O
LFXTAL_I
38.4 MHz
CDCDC
DVDD
32.768 kHz
(optional)
LFXTAL_O
DECOUPLE
CDECOUPLE
RFVDD
PAVDD
Figure 5.2. EFR32BG22 Typical Application Circuit: DCDC Configuration
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Typical Connections
5.2 RF Matching Networks
5.2.1 2.4 GHz Matching Network
The recommended RF matching network circuit diagram is shown in Figure 5.3 Typical RF impedance-matching network circuit on
page 74. Typical component values are shown in Table 5.1 Component Values on page 74. Please refer to the development board
Bill of Materials for specific part recommendation including tolerance, component size, recommended manufacturer, and recommended
part number.
L1
C2
C3
RF2G4_IO
50Ω
C1
Figure 5.3. Typical RF impedance-matching network circuit
Table 5.1. Component Values
Designator
Value
1.2 pF
1.3 pF
2.6 nH
18 pF
C1
C2
L1
C3
5.3 Other Connections
Other components or connections may be required to meet the system-level requirements. Application Note AN0002.2: "EFR32 Wire-
less Gecko Series 2 Hardware Design Considerations" contains detailed information on these connections. Application Notes can be
accessed on the Silicon Labs website (www.silabs.com/32bit-appnotes).
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Pin Definitions
6. Pin Definitions
6.1 QFN32 Device Pinout
Figure 6.1. QFN32 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-
ported features for each GPIO pin, see 6.4 Alternate Function Table, 6.5 Analog Peripheral Connectivity, and 6.6 Digital Peripheral
Connectivity.
Table 6.1. QFN32 Device Pinout
Pin Name
PC00
Pin(s) Description
Pin Name
PC01
Pin(s) Description
1
3
5
7
GPIO
2
4
6
8
GPIO
PC02
GPIO
PC03
GPIO
PC04
GPIO
PC05
GPIO
HFXTAL_I
High Frequency Crystal Input
HFXTAL_O
High Frequency Crystal Output
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Pin Definitions
Pin Name
Pin(s) Description
Pin Name
Pin(s) Description
Reset Pin. The RESETn pin is internally
pulled up to DVDD.
RESETn
9
RFVDD
10
Radio power supply
RFVSS
PAVDD
PB01
11
13
15
17
19
21
Radio Ground
RF2G4_IO
PB02
12
14
16
18
20
22
2.4 GHz Single-ended RF input/output
Power Amplifier (PA) power supply
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
PB00
PA00
PA01
PA02
PA03
PA04
PA05
Decouple outputput for on-chip voltage
regulator. An external decoupling ca-
pacitor is required at this pin.
PA06
23
GPIO
DECOUPLE
24
VREGSW
VREGVSS
AVDD
25
27
29
31
DCDC regulator switching node
DCDC ground
VREGVDD
DVDD
26
28
30
32
DCDC regulator input supply
Digital power supply
I/O power supply
GPIO
Analog power supply
GPIO
IOVDD
PD00
PD01
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Pin Definitions
6.2 QFN40 Device Pinout
Figure 6.2. QFN40 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-
ported features for each GPIO pin, see 6.4 Alternate Function Table, 6.5 Analog Peripheral Connectivity, and 6.6 Digital Peripheral
Connectivity.
Table 6.2. QFN40 Device Pinout
Pin Name
PC00
Pin(s) Description
Pin Name
PC01
Pin(s) Description
1
3
5
7
9
GPIO
2
4
GPIO
PC02
GPIO
PC03
GPIO
PC04
GPIO
PC05
6
GPIO
PC06
GPIO
PC07
8
GPIO
HFXTAL_I
High Frequency Crystal Input
HFXTAL_O
10
High Frequency Crystal Output
Reset Pin. The RESETn pin is internally
pulled up to DVDD.
RESETn
11
RFVDD
12
Radio power supply
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Pin Definitions
Pin Name
RFVSS
PAVDD
PB03
Pin(s) Description
Pin Name
RF2G4_IO
PB04
Pin(s) Description
13
15
17
19
21
23
25
27
Radio Ground
14
16
18
20
22
24
26
28
2.4 GHz Single-ended RF input/output
Power Amplifier (PA) power supply
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
PB02
PB01
PB00
PA00
PA01
PA02
PA03
PA04
PA05
PA06
PA07
Decouple outputput for on-chip voltage
regulator. An external decoupling ca-
pacitor is required at this pin.
PA08
29
GPIO
DECOUPLE
30
VREGSW
VREGVSS
AVDD
31
33
35
37
39
DCDC regulator switching node
DCDC ground
VREGVDD
DVDD
32
34
36
38
40
DCDC regulator input supply
Digital power supply
I/O power supply
GPIO
Analog power supply
GPIO
IOVDD
PD02
PD03
PD01
GPIO
PD00
GPIO
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Pin Definitions
6.3 TQFN32 Device Pinout
Figure 6.3. TQFN32 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-
ported features for each GPIO pin, see 6.4 Alternate Function Table, 6.5 Analog Peripheral Connectivity, and 6.6 Digital Peripheral
Connectivity.
Table 6.3. TQFN32 Device Pinout
Pin Name
PC00
Pin(s) Description
Pin Name
PC01
Pin(s) Description
1
3
5
7
GPIO
2
4
6
8
GPIO
PC02
GPIO
PC03
GPIO
PC04
GPIO
PC05
GPIO
HFXTAL_I
High Frequency Crystal Input
HFXTAL_O
High Frequency Crystal Output
Reset Pin. The RESETn pin is internally
pulled up to DVDD.
RESETn
RFVSS
9
RFVDD
10
12
Radio power supply
11
Radio Ground
RF2G4_IO
2.4 GHz Single-ended RF input/output
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Pin Definitions
Pin Name
PAVDD
PB01
Pin(s) Description
Pin Name
PB02
Pin(s) Description
13
15
17
19
21
Power Amplifier (PA) power supply
14
16
18
20
22
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
PB00
PA00
PA01
PA02
PA03
PA04
PA05
Decouple outputput for on-chip voltage
regulator. An external decoupling ca-
pacitor is required at this pin.
PA06
23
GPIO
DECOUPLE
24
VREGSW
VREGVSS
AVDD
25
27
29
31
DCDC regulator switching node
DCDC ground
VREGVDD
DVDD
26
28
30
32
DCDC regulator input supply
Digital power supply
I/O power supply
GPIO
Analog power supply
GPIO
IOVDD
PD00
PD01
6.4 Alternate Function Table
A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows what functions are
available on each device pin.
Table 6.4. GPIO Alternate Function Table
GPIO
Alternate Function
PC00
PC05
PC07
PB03
PB01
PB00
PA00
PA01
PA02
GPIO.EM4WU6
GPIO.EM4WU7
GPIO.EM4WU8
GPIO.EM4WU4
GPIO.EM4WU3
IADC0.VREFN
IADC0.VREFP
GPIO.SWCLK
GPIO.SWDIO
GPIO.THMSW_EN
GPIO.TRACEDA-
TA0
PA03
GPIO.SWV
GPIO.TDO
PA04
PA05
PD02
PD01
PD00
GPIO.TDI
GPIO.TRACECLK
GPIO.EM4WU0
GPIO.EM4WU9
LFXO.LFXTAL_I
LFXO.LFXTAL_O
LFXO.LF_EXTCLK
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Pin Definitions
6.5 Analog Peripheral Connectivity
Many analog resources are routable and can be connected to numerous GPIO's. The table below indicates which peripherals are avali-
able on each GPIO port. When a differential connection is being used Positive inputs are restricted to the EVEN pins and Negative
inputs are restricted to the ODD pins. When a single ended connection is being used positive input is avaliable on all pins. See the
device Reference Manual for more details on the ABUS and analog peripherals.
Table 6.5. ABUS Routing Table
Peripheral
Signal
PA
ODD
PB
ODD
PC
ODD
PD
ODD
EVEN
Yes
EVEN
Yes
EVEN
Yes
EVEN
Yes
IADC0
ana_neg
ana_pos
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Pin Definitions
6.6 Digital Peripheral Connectivity
Many digital resources are routable and can be connected to numerous GPIO's. The table below indicates which peripherals are avalia-
ble on each GPIO port.
Table 6.6. DBUS Routing Table
Peripheral.Resource
PORT
PC
PA
PB
PD
CMU.CLKIN0
Available
Available
Available
Available
CMU.CLKOUT0
CMU.CLKOUT1
CMU.CLKOUT2
EUART0.CTS
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
EUART0.RTS
EUART0.RX
EUART0.TX
FRC.DCLK
FRC.DFRAME
FRC.DOUT
I2C0.SCL
Available
Available
Available
Available
I2C0.SDA
I2C1.SCL
I2C1.SDA
LETIMER0.OUT0
LETIMER0.OUT1
MODEM.ANT0
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
MODEM.ANT1
MODEM.ANT_ROLL_OVER
MODEM.ANT_RR0
MODEM.ANT_RR1
MODEM.ANT_RR2
MODEM.ANT_RR3
MODEM.ANT_RR4
MODEM.ANT_RR5
MODEM.ANT_SW_EN
MODEM.ANT_SW_US
MODEM.ANT_TRIG
MODEM.ANT_TRIG_STOP
MODEM.DCLK
Available
Available
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Pin Definitions
Peripheral.Resource
PORT
PA
PB
PC
PD
MODEM.DIN
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
MODEM.DOUT
PDM.CLK
Available
Available
Available
Available
Available
Available
PDM.DAT0
PDM.DAT1
PRS.ASYNCH0
PRS.ASYNCH1
PRS.ASYNCH10
PRS.ASYNCH11
PRS.ASYNCH2
PRS.ASYNCH3
PRS.ASYNCH4
PRS.ASYNCH5
PRS.ASYNCH6
PRS.ASYNCH7
PRS.ASYNCH8
PRS.ASYNCH9
PRS.SYNCH0
PRS.SYNCH1
PRS.SYNCH2
PRS.SYNCH3
TIMER0.CC0
TIMER0.CC1
TIMER0.CC2
TIMER0.CDTI0
TIMER0.CDTI1
TIMER0.CDTI2
TIMER1.CC0
TIMER1.CC1
TIMER1.CC2
TIMER1.CDTI0
TIMER1.CDTI1
TIMER1.CDTI2
TIMER2.CC0
TIMER2.CC1
TIMER2.CC2
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Pin Definitions
Peripheral.Resource
PORT
PA
PB
PC
PD
TIMER2.CDTI0
TIMER2.CDTI1
TIMER2.CDTI2
TIMER3.CC0
TIMER3.CC1
TIMER3.CC2
TIMER3.CDTI0
TIMER3.CDTI1
TIMER3.CDTI2
TIMER4.CC0
TIMER4.CC1
TIMER4.CC2
TIMER4.CDTI0
TIMER4.CDTI1
TIMER4.CDTI2
USART0.CLK
USART0.CS
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
USART0.CTS
USART0.RTS
USART0.RX
USART0.TX
USART1.CLK
USART1.CS
USART1.CTS
USART1.RTS
USART1.RX
USART1.TX
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
QFN32 Package Specifications
7. QFN32 Package Specifications
7.1 QFN32 Package Dimensions
Figure 7.1. QFN32 Package Drawing
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
QFN32 Package Specifications
Table 7.1. QFN32 Package Dimensions
Dimension
Min
0.80
0.00
Typ
0.85
0.02
Max
0.90
0.05
A
A1
A3
b
0.20 REF
0.20
4.00
4.00
2.70
2.70
0.40 BSC
0.30
—
0.15
3.90
3.90
2.60
2.60
0.25
4.10
4.10
2.80
2.80
D
E
D2
E2
e
L
0.20
0.20
0.40
—
K
R
0.075
—
0.125
aaa
bbb
ccc
ddd
eee
fff
0.10
0.07
0.10
0.05
0.08
0.10
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
QFN32 Package Specifications
7.2 QFN32 PCB Land Pattern
Figure 7.2. QFN32 PCB Land Pattern Drawing
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
QFN32 Package Specifications
Table 7.2. QFN32 PCB Land Pattern Dimensions
Dimension
Typ
0.76
0.22
0.40
3.21
3.21
2.80
2.80
L
W
e
S
S1
L1
W1
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.101 mm (4 mils).
6. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.
7. A 2x2 array of 1.10 mm x 1.10 mm openings on a 1.30 mm pitch can be used for the center ground pad.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
10. Above notes and stencil design are shared as recommendations only. A customer or user may find it necessary to use
different parameters and fine tune their SMT process as required for their application and tooling.
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Rev. 1.0 | 88
EFR32BG22 Wireless Gecko SoC Family Data Sheet
QFN32 Package Specifications
7.3 QFN32 Package Marking
FFFF
PPPPPP
TTTTTT
YYWW
Figure 7.3. QFN32 Package Marking
The package marking consists of:
• FFFF – The product family codes.
1. Family Code ( B | M | F )
2. G (Gecko)
3. Series (2)
4. Device Configuration (1, 2, 3, ...)
• PPPPPP – The product option codes.
• 1-2. MCU Feature Codes
• 3-4. Radio Feature Codes
• 5. Flash (J = 1024k | I = 768k | H = 512k | W= 352k | G = 256k | F = 128k)
• 6. Temperature grade (G = -40 to 85 °C | I = -40 to 125 °C )
• TTTTTT – A trace or manufacturing code. The first letter is the device revision.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
TQFN32 Package Specifications
8. TQFN32 Package Specifications
8.1 TQFN32 Package Dimensions
Figure 8.1. TQFN32 Package Drawing
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
TQFN32 Package Specifications
Table 8.1. TQFN32 Package Dimensions
Dimension
Min
Typ
Max
A
0.27
0.30
0.33
A1
A2
b
0.20 REF
0.10 REF
0.20
0.15
3.90
3.90
2.60
2.60
0.25
4.10
4.10
2.80
2.80
D
4.00
E
4.00
D2
E2
e
2.70
2.70
0.40 BSC
0.32
L
0.22
0.42
K
0.33 REF
—
R
0.075
0.125
aaa
bbb
ccc
ddd
eee
fff
0.10
0.07
0.10
0.05
0.08
0.10
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
TQFN32 Package Specifications
8.2 TQFN32 PCB Land Pattern
Figure 8.2. TQFN32 PCB Land Pattern Drawing
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
TQFN32 Package Specifications
Table 8.2. TQFN32 PCB Land Pattern Dimensions
Dimension
Typ
0.76
0.22
0.40
3.21
3.21
2.80
2.80
L
W
e
S
S1
L1
W1
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.101 mm (4 mils).
6. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.
7. A 2x2 array of 1.10 mm x 1.10 mm openings on a 1.30 mm pitch can be used for the center ground pad.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
10. Above notes and stencil design are shared as recommendations only. A customer or user may find it necessary to use
different parameters and fine tune their SMT process as required for their application and tooling.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
TQFN32 Package Specifications
8.3 TQFN32 Package Marking
FFFF
PPPPPP
TTTTTT
YYWW
Figure 8.3. TQFN32 Package Marking
The package marking consists of:
• FFFF – The product family codes.
1. Family Code ( B | M | F )
2. G (Gecko)
3. Series (2)
4. Device Configuration (1, 2, 3, ...)
• PPPPPP – The product option codes.
• 1-2. MCU Feature Codes
• 3-4. Radio Feature Codes
• 5. Flash (J = 1024k | I = 768k | H = 512k | W= 352k | G = 256k | F = 128k)
• 6. Temperature grade (G = -40 to 85 °C | I = -40 to 125 °C )
• TTTTTT – A trace or manufacturing code. The first letter is the device revision.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
QFN40 Package Specifications
9. QFN40 Package Specifications
9.1 QFN40 Package Dimensions
Figure 9.1. QFN40 Package Drawing
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
QFN40 Package Specifications
Table 9.1. QFN40 Package Dimensions
Dimension
Min
0.80
0.00
Typ
0.85
0.02
Max
0.90
0.05
A
A1
A3
b
0.20 REF
0.20
5.00
5.00
3.70
3.70
0.40 BSC
0.40
—
0.15
4.90
4.90
3.55
3.55
0.25
5.10
5.10
3.85
3.85
D
E
D2
E2
e
L
0.30
0.20
0.50
—
K
R
0.075
—
—
aaa
bbb
ccc
ddd
eee
fff
0.10
0.07
0.10
0.05
0.08
0.10
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
QFN40 Package Specifications
9.2 QFN40 PCB Land Pattern
Figure 9.2. QFN40 PCB Land Pattern Drawing
Table 9.2. QFN40 PCB Land Pattern Dimensions
Dimension
Typ
4.25
4.25
3.85
3.85
0.40
0.22
0.74
S1
S
L1
W1
e
W
L
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
4. The stencil thickness should be 0.101 mm (4 mils).
5. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.
6. A 3x3 array of 0.90 mm square openings on a 1.20 mm pitch can be used for the center ground pad.
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
9. Above notes and stencil design are shared as recommendations only. A customer or user may find it necessary to use
different parameters and fine tune their SMT process as required for their application and tooling.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
QFN40 Package Specifications
9.3 QFN40 Package Marking
FFFF
PPPPPP
TTTTTT
YYWW
Figure 9.3. QFN40 Package Marking
The package marking consists of:
• FFFF – The product family codes.
1. Family Code ( B | M | F )
2. G (Gecko)
3. Series (2)
4. Device Configuration (1, 2, 3, ...)
• PPPPPP – The product option codes.
• 1-2. MCU Feature Codes
• 3-4. Radio Feature Codes
• 5. Flash (J = 1024k | I = 768k | H = 512k | W= 352k | G = 256k | F = 128k)
• 6. Temperature grade (G = -40 to 85 °C | I = -40 to 125 °C )
• TTTTTT – A trace or manufacturing code. The first letter is the device revision.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
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Rev. 1.0 | 98
EFR32BG22 Wireless Gecko SoC Family Data Sheet
Revision History
10. Revision History
Revision 1.0
June, 2020
• 3.7.2 Cryptographic Accelerator: Removed text referencing DPA.
• 3.7.4 Secure Debug with Lock/Unlock: Removed text referencing Secure Element.
• 4.1 Electrical Characteristics:
• Expanded Power Supply Pin Dependencies section to include more details and restrictions on DECOUPLE.
• Finalized remaining MIN / MAX specifications according to characterization and qualification results.
• Table 4.30 GPIO Pins (3V GPIO pins) on page 54: Relaxed 3.8 V, 125 °C GPIO maximum leakage specification on PA00, PA03,
PB00, PC03, PC04, and PD00 from 400 nA to 550 nA.
• Corrected BLE Bit Error Rate conditions for sensitivity measurements with 255 byte payload.
• Added GPIO hysteresis specification.
• Updated DCDC lifetime condition guidance in 4.4.1 DC-DC Operating Limits.
• Expanded IADC descriptions to include information at higher oversampling ratios and added typical performance curve.
• Corrected tolerance of dimension "L" in Table 8.1 TQFN32 Package Dimensions on page 91.
Revision 0.5
February, 2020
• 1. Feature List: Updated list slightly to highlight different features.
• Expanded 3.7 Security Features section and corrected security details.
• Added 3.9.2 Voltage Scaling section.
• 4.1 Electrical Characteristics:
• Additional characterization results and test limits added where available.
• Removed thermistor driver specification table until full software support becomes available.
• Updated 5.2 RF Matching Networks section with recommended match values.
• Updated 9.3 QFN40 Package Marking with mark details.
Revision 0.4
December, 2019
• 4.1 Electrical Characteristics:
• Added detailed lifetime information to DC-DC specifications section.
• Additional characterization results and preliminary test limits added where available.
• Added DC-DC efficiency plots and updated supply current plots to 4.20 Typical Performance Curves.
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EFR32BG22 Wireless Gecko SoC Family Data Sheet
Revision History
Revision 0.3
October, 2019
• In the front page block diagram, updated the lowest energy mode for LETIMER.
• Updated 3.5.2 Low Energy Timer (LETIMER) lowest energy mode.
• 1. Feature List updated with additional modulation formats, protocol stack, and security details.
• 2. Ordering Information:
• OPN numbering changes for security grade differentiator.
• Supported protocol stack details updated.
• 4.1 Electrical Characteristics:
• Additional characterization results and preliminary test limits added where available.
• Corrected maximum clock speed details in General Operating Conditions Table.
• Removed specification lines with 3 dBm output power conditions from RF transmit tables.
• Removed DECOUPLE BOD table.
• Added timing diagrams and specifications for PDM and USART SPI.
• Added 4.20 Typical Performance Curves.
Revision 0.2
July, 2019
• 2. Ordering Information: Updated part number to revision C, added several new variants.
• 4.1 Electrical Characteristics: Added early silicon characterization data to several tables, and refined specification conditions.
• 4.1 Electrical Characteristics: Added flash electrical characteristics table.
• Minor wording edits for System Overview sections.
Revision 0.1
April, 2019
Initial release.
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