CYW320ZXC-4T [SILICON]
Processor Specific Clock Generator, 200MHz, CMOS, PDSO56, 6 X 12 MM, LEAD FREE, MO-153, TSSOP2-56;
| 型号： | CYW320ZXC-4T |
| 厂家： | 
SILICON |
| 描述： | Processor Specific Clock Generator, 200MHz, CMOS, PDSO56, 6 X 12 MM, LEAD FREE, MO-153, TSSOP2-56 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总16页 (文件大小：164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W320-04
200 MHz Spread Spectrum Clock Synthesizer/Driver
with Differential CPU Outputs
Features
Benefits
• CompliantwithIntel® CK-Titanclocksynthesizer/driver
specifications
• Supports next-generation Pentium® processors using
differential clock drivers
• Multiple output clocks at different frequencies
• Motherboard clock generator
— Three pairs of differential CPU outputs, up to
200 MHz
— Supports multiple CPUs and a chipset
— Support for PCI slots and chipset
— Ten synchronous PCI clocks, three free-running
— Six 3V66 clocks
— Supports AGP, DRCG reference, and Hub Link
— Supports USB host controller and graphic controller
— Supports ISA slots and I/O chip
— Two 48 MHz clocks
— One reference clock at 14.318 MHz
— One VCH clock
• Enables reduction of electromagnetic interference
(EMI) and overall system cost
• Spread Spectrum clocking (down spread)
• Enables ACPI-compliant designs
• Power-down features (PCI_STOP#, CPU_STOP#
PWR_DWN#)
• Supports up to four CPU clock frequencies
• Enables ATE and “bed of nails” testing
• Widely available standard package enables lower cost
• Three Select inputs (Mode select and IC Frequency
Select)
• OE and Test Mode support
• 56-pin SSOP package and 56-pin TSSOP package
Logic Block Diagram
Pin Configurations
SSOP and TSSOP
Top View
REF
VDD_REF
VDD_REF
XTAL_IN
XTAL_OUT
GND_REF
PCI_F0
1
2
3
4
5
6
56
55
54
53
52
51
50
X1
X2
XTAL
OSC
PWR
REF
S1
S0
PLL Ref Freq
CPU_STOP#
Divider
Network
CPU0
PLL 1
PCI_F1
CPU#0
VDD_CPU
CPU1
VDD_CPU
CPU0:2
Stop
Clock
Control
PCI_F2
7
PWR
Gate
S0:2
PWR_GD#
VDD_PCI
GND_PCI
PCI0
49
48
47
46
8
CPU#0:2
CPU#1
9
CPU_STOP#
GND_CPU
VDD_CPU
10
11
PCI1
VDD_PCI
PCI_F0:2
PWR
PCI2
CPU2
45
44
43
42
41
12
13
Stop
Clock
Control
PCI3
CPU#2
MULT0#
PCI0:6
14
15
16
17
18
19
20
21
22
23
VDD_PCI
GND_PCI
PCI4
IREF
PCI_STOP#
PWR_DWN#
/2
VDD_3V66
3V66_0
GND_IREF
S2
PWR
40
39
38
PCI5
PCI6
VDD_3V66
3V66_2:4/
USB
66BUFF0:2
PWR
DOT
3V66_5/ 66IN
GND_3V66
VDD_ 48 MHz
37
36
35
34
66BUFF0/3V66_2
66BUFF1/3V66_3
GND_ 48 MHz
3V66_1/VCH
PCI_STOP#
3V66_0
VDD_48MHz
USB (48MHz)
PLL 2
PWR
66BUFF2/3V66_4
66IN/3V66_5
33
32
31
30
29
24
25
DOT (48MHz)
PWR_DWN#
VDD_CORE
GND_CORE
VDD_3V66
GND_3V66
26
27
28
VCH_CLK/ 3V66_1
SCLK
PWR_GD#
SDATA
SDATA
SCLK
SMBus
Logic
.......................Document #: 38-07010 Rev. *C Page 1 of 16
400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669
www.silabs.com
W320-04
Pin Summary
Name
Pins
56
Description
REF
3.3V 14.318-MHz clock output.
14.318-MHz crystal input.
14.318-MHz crystal input.
Differential CPU clock outputs.
3.3V 66-MHz clock output.
XTAL_IN
2
XTAL_OUT
CPU, CPU# [0:2]
3V66_0
3
44, 45, 48, 49, 51, 52
33
35
24
3V66_1/VCH
66IN/3V66_5
3.3V selectable through SMBus to be 66 MHz or 48 MHz.
66-MHz input to buffered 66BUFF and PCI or 66-MHz clock from
internal VCO.
66BUFF [2:0] /3V66 [4:2]
21, 22, 23
5, 6, 7,
66-MHz buffered outputs from 66Input or 66-MHz clocks from internal
VCO.
PCI_F [0:2]
PCI [0:6]
33-MHz clocks divided down from 66Input or divided down from 3V66.
10, 11, 12, 13, 16, 17, 18 PCI clock outputs divided down from 66Input or divided down from
3V66.
USB
DOT
S2
39
Fixed 48-MHz clock output.
38
Fixed 48-MHz clock output.
40
Special 3.3V 3-level input for Mode selection.
3.3V LVTTL inputs for CPU frequency selection.
S1, S0
IREF
54, 55
42
A precision resistor is attached to this pin, which is connected to the
internal current reference.
MULT0
43
3.3V LVTTL input for selecting the current multiplier for the CPU
outputs.
PWR_DWN#
PCI_STOP#
CPU_STOP#
PWRGD#
25
34
53
28
3.3V LVTTL input for Power_Down# (active LOW).
3.3V LVTTL input for PCI_STOP# (active LOW).
3.3V LVTTL input for CPU_STOP# (active LOW).
3.3V LVTTL input is a level sensitive strobe used to determine when
S[2:0] and MULTI0 inputs are valid and OK to be sampled (Active
LOW). Once PWRGD# is sampled LOW, the status of this output will
be ignored.
SDATA
SCLK
29
SMBus compatible SDATA.
SMBus compatible SCLK.
3.3V power supply for outputs.
30
VDD_REF, VDD_PCI,
VDD_3V66, VDD_CPU
1, 8, 14, 19, 32, 46, 50
VDD_48 MHz
VDD_CORE
37
26
3.3V power supply for 48 MHz.
3.3V power supply for PLL.
GND_REF, GND_PCI,
GND_3V66, GND_IREF,
VDD_CPU
4, 9, 15, 20, 31, 36, 41, 47 Ground for outputs.
GND_CORE
27
Ground for PLL.
.......................Document #: 38-07010 Rev. *C Page 2 of 16
W320-04
Function Table[1]
66BUFF[0:2]/
3V66[2:4]
(MHz)
CPU
3V66[0:1]
(MHz)
66IN/3V66_5 PCI_F/PCI
(MHz) (MHz)
USB/DOT
S2 S1 S0
(MHz)
REF0(MHz)
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
Hi-Z
(MHz)
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
Hi-Z
Notes
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
1, 5
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
66 MHz
66 MHz
66IN
66 MHz Input 66IN/2
66 MHz Input 66IN/2
66 MHz Input 66IN/2
66 MHz Input 66IN/2
1
100 MHz 66 MHz
200 MHz 66 MHz
133 MHz 66 MHz
66IN
1
66IN
1
66IN
0
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
Hi-Z
66 MHz
66 MHz
66 MHz
66 MHz
Hi-Z
33 MHz
33 MHz
33 MHz
33 MHz
Hi-Z
0
100 MHz 66 MHz
200 MHz 66 MHz
133 MHz 66 MHz
0
0
Mid
Mid
Mid
Mid
Hi-Z
Hi-Z
TCLK/2
TCLK/4
TCLK/4
TCLK/4
Reserved
Reserved
TCLK/8
Reserved
Reserved
TCLK
TCLK/2
Reserved
Reserved
5, 6, 7
–
Reserved Reserved Reserved
Reserved Reserved Reserved
Reserved
Reserved
–
Swing Select Functions
Mult0
Board Target Trace/Term Z
Reference R, IREF = VDD/(3*Rr)
Rr = 221 1%, IREF = 5.00 mA
Rr = 475 1%, IREF = 2.32 mA
Output Current VOH @ Z
0
1
50
50
IOH = 4*IREF 1.0V @ 50
OH = 6*IREF 0.7V @ 50
I
Clock Driver Impedances
Impedance
Buffer Name
CPU, CPU#
V
DD Range
Buffer Type
Min.
Typ.
50
Max.
Type X1
Type 5
REF
3.135–3.465
3.135–3.465
3.135–3.465
3.135–3.465
12
12
12
12
30
55
55
60
60
PCI, 3V66, 66BUFF
Type 5
30
USB
DOT
Type 3A
Type 3B
30
30
Clock Enable Configuration
PWR_DWN# CPU_STOP# PCI_STOP#
CPU
CPU# 3V66 66BUFF PCI_F PCI USB/DOT VCOS/ OSC
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
IREF*2 FLOAT LOW
LOW
ON
LOW LOW
LOW
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
FLOAT
LOW
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFF
ON
ON
ON
ON
OFF
ON
ON
ON
ON
ON
Note:
1. TCLK is a test clock driven in on the XTALIN input in test mode.
2. “Normal” mode of operation
3. Range of reference frequency allowed is min. = 14.316, nom. = 14.31818 MHz, max. = 14.32 MHz.
4. Frequency accuracy of 48 MHz must be +167PPM to match USB default.
5. Mid. is defined a Voltage level between 1.0V and 1.8V for three-level input functionality. Low is below 0.8V. High is above 2.0V.
6. Required for DC output impedance verification.
7. These modes are to use the SAME internal dividers as the CPU = 200 MHz mode. The only change is to slow down the internal VCO to allow under clock
margining.
.......................Document #: 38-07010 Rev. *C Page 3 of 16
W320-04
ability to stop after any complete byte has been transferred.
Indexed bytes are not allowed.
Serial Data Interface (SMBus)
To enhance the flexibility and function of the clock synthesizer,
a two-signal SMBus interface is provided according to SMBus
specification. Through the Serial Data Interface, various
device functions such as individual clock output buffers, can
be individually enabled or disabled. W320-04 supports both
block read and block write operations.
A block write begins with a slave address and a WRITE
condition. The R/W bit is used by the SMBus controller as a
data direction bit. A zero indicates a WRITE condition to the
clock device. The slave receiver address is 11010010 (D2h).
A command code of 0000 0000 (00h) and the byte count bytes
are required for any transfer. After the command code, the
core logic issues a byte count which describes number of
additional bytes required for the transfer, not including the
command code and byte count bytes. For example, if the host
has 20 data bytes to send, the first byte would be the number
20 (14h), followed by the 20 bytes of data. The byte count byte
is required to be a minimum of 1 byte and a maximum of 32
bytes It may not be 0. Figure 1 shows an example of a block
write.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts only block writes from
the controller. The bytes must be accessed in sequential order
from lowest to highest byte, (most significant bit first) with the
A transfer is considered valid after the acknowledge bit corre-
sponding to the byte count is read by the controller.
Figure 1.
Start Slave Address R/W 0/1
bit 1 1 0 1 0 0 1 0
A
Command
Code
0 0 0 0 0 0 0 0
A Byte Count = N A Data Byte 0
A
1
. . . Data Byte N-1 A Stop
bit
From Master to Slave
1 bit
7 bits
1
1
8 bits
1
8 bits
1
8 bits
8 bits
1
1 bit
From Slave to Master
Figure 1. An Example of a Block Write
Data Byte Configuration Map
Data Byte 0: Control Register (0 = Enable, 1 = Disable)
Affected
Power On
Default
Bit
Pin#
Name
Description
Spread Spectrum Enable
0 = Spread Off, 1 = Spread On
Type
Bit 7
5, 6, 7, 10, PCI [0:6]
11, 12, 13, CPU[2:0]
16, 17, 18, 3V66[1:0]
33, 35
R/W
0
Bit 6
Bit 5
–
TBD
TBD
R
0
0
35
3V66_1/VCH
VCH Select 66 MHz/48 MHz
0 = 66 MHz, 1 = 48 MHz
R/W
Bit 4
Bit 3
44, 45, 48, CPU [2:0]
49, 51, 52 CPU# [2:0]
CPU_STOP#
R
N/A
N/A
Reflects the current value of the external CPU_STOP# pin
10, 11, 12, PCI [6:0]
13, 16, 17,
18
PCI_STOP#
(Does not affect PCI_F [2:0] pins)
R/W
Bit 2
Bit 1
Bit 0
–
–
–
–
–
–
S2
R
R
R
N/A
N/A
N/A
Reflects the value of the S2 pin sampled on power-up
S1
Reflects the value of the S1 pin sampled on power-up
S0
Reflects the value of the S1 pin sampled on power-up
.......................Document #: 38-07010 Rev. *C Page 4 of 16
W320-04
Data Byte 1
Power On
Bit
Pin#
Name
Name
Name
Description
Type
Default
Bit 7
–
N/A
CPU Mult0 Value
R
N/A
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
52, 49, 45 CPU0:2
Three-State CPU0:2 during power down
0 = Normal; 1 = Three-stated
R/W
0
44, 45 CPU2
CPU2#
Allow Control of CPU2 with assertion of CPU_STOP#
0 = Not free running; 1 = Free running
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
1
1
1
48, 49 CPU1
CPU1#
Allow Control of CPU1 with assertion of CPU_STOP#
0 = Not free running;1 = Free running
51, 52 CPU0
CPU0#
Allow Control of CPU0 with assertion of CPU_STOP#
0= Not free running; 1 = Free running
44, 45 CPU2
CPU2#
CPU2 Output Enable
1 = Enabled; 0 = Disabled
48, 49 CPU1
CPU1#
CPU1Output Enable
1 = Enabled; 0= Disabled
51, 52 CPU0
CPU0#
CPU0 Output Enable
1 = Enabled; 0 = Disabled
Data Byte 2
Power On
Default
Bit
Bit 7
Pin#
–
Pin Description
Type
R 0
N/A
N/A
Bit 6
18
PCI6
PCI6 Output Enable
R/W
1
1
1
1
1
1
1
1 = Enabled; 0 = Disabled
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
17
16
13
12
11
10
PCI5
PCI4
PCI3
PCI2
PCI1
PCI0
PCI5 Output Enable
R/W
R/W
R/W
R/W
R/W
R/W
1 = Enabled; 0 = Disabled
PCI4 Output Enable
1 = Enabled; 0 = Disabled
PCI3 Output Enable
1 = Enabled; 0 = Disabled
PCI2 Output Enable
1 = Enabled; 0 = Disabled
PCI1 Output Enable
1 = Enabled; 0 = Disabled
PCI0 Output Enable
1 = Enabled; 0 = Disabled
Data Byte 3
Power On
Default
Bit
Bit 7
Pin#
38
39
7
Pin Description
DOT 48-MHz Output Enable
Type
R/W
DOT
1
1
0
Bit 6
USB
USB 48-MHz Output Enable
R/W
Bit 5
PCI_F2
Allow control of PCI_F2 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
R/W
Bit 4
Bit 3
6
5
PCI_F1
PCI_F0
Allow control of PCI_F1 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
R/W
R/W
0
0
Allow control of PCI_F0 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
Bit 2
Bit 1
Bit 0
7
6
5
PCI_F2
PCI_F1
PCI_F0
PCI_F2 Output Enable
PCI_F1Output Enable
PCI_F0 Output Enable
R/W
R/W
R/W
1
1
1
.......................Document #: 38-07010 Rev. *C Page 5 of 16
W320-04
Data Byte 4
Power On
Bit
Bit 7
Pin#
–
Name
Pin Description
Type
Default
TBD
N/A
N/A
R
0
0
1
Bit 6
–
TBD
R
Bit 5
33
3V66_0
3V66_0 Output Enable
R/W
1 = Enabled; 0 = Disabled
Bit 4
Bit 3
35
24
3V66_1/VCH
66IN/3V66_5
3V66_1/VCH Output Enable
1 = Enabled; 0 = Disabled
R/W
R/W
1
1
3V66_5 Output Enable
1 = Enable; 0 = Disable
NOTE: This bit should be used when pin 24 is configured
as 3v66_5 output. Do not clear this bit when pin 24 is
configured as 66in input.
Bit 2
Bit 1
Bit 0
23
22
21
66BUFF2
66BUFF1
66BUFF0
66-MHz Buffered 2 Output Enable
1 = Enabled; 0 = Disabled
R/W
R/W
R/W
1
1
1
66-MHz Buffered 1 Output Enable
1 = Enabled; 0 = Disabled
66-MHz Buffered 0 Output Enable
1 = Enabled; 0 = Disabled
Data Byte 5
Power On
Default
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
Name
Pin Description
Type
N/A
N/A
R
0
N/A
N/A
R
0
0
0
0
0
0
0
66BUFF [2:0]
66BUFF [2:0]
DOT
Tpd 66IN to 66BUFF propagation delay control
R/W
R/W
R/W
R/W
R/W
R/W
DOT edge rate control
USB edge rate control
DOT
USB
USB
Byte 6: Vendor ID
Bit
Bit 7
Description
Type
Power On Default
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
R
R
R
R
R
R
R
R
0
0
0
0
1
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Vendor ID Bit 2
Bit 1
Vendor ID Bit 1
Bit 0
Vendor ID Bit 0
.......................Document #: 38-07010 Rev. *C Page 6 of 16
W320-04
Storage Temperature (Non-Condensing) ....–65C to +150C
Max. Soldering Temperature (10 sec)....................... +260C
Junction Temperature................................................ +150C
Package Power Dissipation...............................................1
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Supply Voltage..................................................–0.5 to +7.0V
Input Voltage.............................................. –0.5V to VDD+0.5
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ............................ > 2000V
Operating Conditions[8] Over which Electrical Parameters are Guaranteed
Parameter
Description
3.3V Supply Voltages
Min.
Max.
Unit
V
DD_REF, VDD_PCI,VDD_CORE
,
3.135
3.465
V
VDD_3V66, VDD_CPU,
VDD_48 MHz
48-MHz Supply Voltage
Operating Temperature, Ambient
Input Pin Capacitance
2.85
0
3.465
70
V
TA
C
pF
pF
pF
Cin
5
CXTAL
CL
XTAL Pin Capacitance
22.5
Max. Capacitive Load on
USBCLK, REF
PCICLK, 3V66
20
30
f(REF)
Reference Frequency, Oscillator Nominal Value
14.318
14.318
MHz
Electrical Characteristics Over the Operating Range
Parameter
VIH
Description
Test Conditions
Min. Max. Unit
High-level Input Voltage
Low-level Input Voltage
Except Crystal Pads. Threshold Voltage for Crystal Pads = VDD/2 2.0
Except Crystal Pads
V
V
VIL
0.8
VOH
High-level Output Voltage USB, REF, 3V66
IOH = –1 mA
IOH = –1 mA
IOL = 1 mA
2.4
2.4
V
PCI
Low-level Output Voltage USB, REF, 3V66
PCI
V
VOL
0.4
0.55
5
V
IOL = 1 mA
V
IIH
IIL
Input HIGH Current
Input LOW Current
0 < VIN < VDD
0 < VIN < VDD
–5
–5
mA
mA
mA
5
IOH
High-level Output Current CPU
For IOH =6*IRef Configuration
Type X1, VOH = 0.65V 12.9
Type X1, VOH = 0.74V
14.9
–23
–33
27
REF, DOT, USB
Type 3, VOH = 1.00V
Type 3, VOH = 3.135V
Type 5, VOH = 1.00V
Type 5, VOH = 3.135V
Type 3, VOL = 1.95V
Type 3, VOL = 0.4V
Type 5, VOL = 1.95 V
Type 5, VOL = 0.4V
–29
–33
29
3V66, DOT, PCI, REF
IOL
Low-level Output Current REF, DOT, USB
mA
mA
3V66, PCI, REF
30
38
10
IOZ
Output Leakage Current
Three-state
IDD3
3.3V Power Supply Current VDD_CORE/VDD3.3 = 3.465V, FCPU = 133 MHz
360 mA
IDDPD3
3.3V Shut-down Current
3.3V Shut-down Current
VDD_CORE/VDD3.3 = 3.465V and @ IREF = 2.32 mA
VDD_CORE/VDD3.3 = 3.465V and @ IREF = 5.0 mA
25
45
mA
mA
IDDPD3
Note:
8. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
.......................Document #: 38-07010 Rev. *C Page 7 of 16
W320-04
-
Switching Characteristics[9] Over the Operating Range
Parameter
t1
Output
Description
Output Duty Cycle[10]
Test Conditions
Measured at 1.5V
Min.
45
Max.
55
Unit
%
All
t3
t3
t5
t5
t6
t7
t9
t9
t9
t9
USB, REF, DOT Falling Edge Rate
Between 2.4V and 0.4V
Between 2.4V and 0.4V
Measured at 1.5V
0.5
1.0
2.0
ns
PCI,3V66
3V66[0:1]
66BUFF[0:2]
PCI
Falling Edge Rate
4.0
V/ns
ps
3V66-3V66 Skew
500
175
500
3.5
66BUFF-66BUFF Skew
PCI-PCI Skew
Measured at 1.5V
ps
Measured at 1.5V
ps
3V66, PCI
3V66
3V66-PCI Clock Jitter
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
3V66 leads. Measured at 1.5V
Measured at 1.5V t9 = t9A – t9B
Measured at 1.5V t9 = t9A – t9B
Measured at 1.5V t9 = t9A – t9B
Measured at 1.5V t9 = t9A – t9B
1.5
ns
250
350
500
1000
ps
USB, DOT
PCI
ps
ps
REF
ps
CPU 1.0V Switching Characteristics
t2
CPU
Rise Time
Measured differential waveform from 175
–0.35V to +0.35V
467
ps
t3
CPU
Fall Time
Measured differential waveform from 175
–0.35V to +0.35V
467
ps
t4
t8
CPU
CPU
CPU
CPU
CPU-CPU Skew
Measured at Crossover
150
150
325
1.45
ps
ps
mV
V
Cycle-Cycle Clock Jitter
Rise/Fall Matching
Measured at Crossover t8 = t8A – t8B
Measured with test loads[11]
Voh
High-level Output Voltage
including overshoot
Measured with test loads[11]
Measured with test loads[11]
Measured with test loads[11]
0.92
–0.2
0.51
Vol
CPU
Low-level Output Voltage
including undershoot
0.35
0.76
V
V
Vcrossover
CPU
Crossover Voltage
CPU 0.7V Switching Characteristics
t2
CPU
Rise Time
Measured single ended waveform from 175
0.175V to 0.525V
700
700
ps
ps
t3
CPU
Fall Time
Measured single ended waveform from 175
0.175V to 0.525V
t4
t8
CPU
CPU
CPU-CPU Skew
Measured at Crossover
150
150
ps
ps
Cycle-Cycle Clock Jitter
Measured at Crossover t8 = t8A – t8B
With all outputs running
CPU
CPU
Rise/Fall Matching
Measured with test loads[12, 13]
Measured with test loads[13]
20
%
V
Voh
Vol
High-level Output Voltage
Including Overshoot
0.85
CPU
CPU
Low-level Output Voltage
Including Undershoot
Measured with test loads[13]
–0.15
0.43
V
V
Vcrossover
Crossover Voltage
Measured with test loads[13]
0.28
Notes:
9. All parameters specified with loaded outputs.
10. Duty cycle is measured at 1.5V when V = 3.3V. When V = 2.5V, duty cycle is measured at 1.25V.
DD
DD
11. The 1.0V test load is shown on the test circuit page.
12. Determined as a fraction of 2*(Trp – Trn)/(Trp +Trn) Where Trp is a rising edge and Trp is an intersecting falling edge.
13. The 0.7V test load is R = 33.2 ohm, R = 49.9 ohm in test circuit.
s
p
.......................Document #: 38-07010 Rev. *C Page 8 of 16
W320-04
Definition and Application of PWRGD# Signal
Vtt
VRM8.5
PWRGD#
CPU
BSEL0
BSEL1
3.3V
3.3V
3.3V
NPN
PWRGD#
10K
10K
S0
10K
10K
CLOCK
GMCH
GENERATOR
S1
.......................Document #: 38-07010 Rev. *C Page 9 of 16
W320-04
Switching Waveforms
Duty Cycle Timing (Single-ended Output)
t1B
t1A
Duty Cycle Timing (CPU Differential Output)
t1B
t1A
All Outputs Rise/Fall Time
VDD
0V
OUTPUT
t2
t3
CPU-CPU Clock Skew
Host_b
Host
Host_b
Host
t4
3V66-3V66 Clock Skew
3V66
3V66
PCI-PCI Clock Skew
PCI
PCI
.....................Document #: 38-07010 Rev. *C Page 10 of 16
W320-04
Switching Waveforms (continued)
3V66-PCI Clock Skew
3V66
PCI
t7
CPU Clock Cycle-Cycle Jitter
t8A
t8B
Host_b
Host
Cycle-Cycle Clock Jitter
t9A
t9B
CLK
PWRDWN# Assertion
66BUFF
PCI
Power Down Rest of Generator
PCI_F (APIC)
PWR_DWN#
CPU
CPU#
3V66
UNDEF
66IN
USB
REF
Note: PCI_STOP# asserted LOW
.....................Document #: 38-07010 Rev. *C Page 11 of 16
W320-04
PWRDWN# Deassertion
10-30 s min.
100-200 s max.
< 3 ms
66BUFF1/GMCH
66BUFF0,2
PCI
PCI_F (APIC)
PWR_DWN#
CPU
CPU#
3V66
66IN
USB
REF
Note: PCI_STOP# asserted LOW
PWRGD# Timing Diagrams
GND VRM 5/12V
PWRGD#
VID [3:0]
BSEL [1:0]
PWRGD# FROM
VRM
Possible glitch while Clock VCC is coming
up. Will be gone in 0.2–0.3 mS delay.
PWRGD# FROM
NPN
VCC CPU CORE
PWRGD#
0.2 -- 0.3 ms Wait for
Sample
delay
PWRGD#
VCC W320 CLOCK
GEN
BSELS
State 1 State 2
State 3
State 0
CLOCK STATE
OFF
OFF
ON
CLOCK VCO
ON
CLOCK OUTPUTS
Figure 2. CPU Power Before Clock Power
.....................Document #: 38-07010 Rev. *C Page 12 of 16
W320-04
GND VRM 5/12V
PWRGD#
VID [3:0]
BSEL [1:0]
PWRGD# FROM
VRM
PWRGD# FROM
NPN
VCC CPU CORE
PWRGD#
Sample
BSELS
0.2 – 0.3 ms
delay
Wait for
PWRGD#
VCC W320 CLOCK
GEN
State 1
State 2
State 3
State 0
OFF
CLOCK STATE
ON
ON
CLOCK VCO
OFF
CLOCK OUTPUTS
Figure 3. CPU Power After Clock Power
.....................Document #: 38-07010 Rev. *C Page 13 of 16
W320-04
Layout Example
+3.3V Supply
FB
VDDQ3
10 F
0.005
F
C1
C2
G
G
G
G
V
1
56
55
54
53
G
2
3
4
G
5
52
G
V
6
51
50
49
48
47
46
45
G
G
G
G
7
G
G
V
8
9
G
V
10
11
12
G
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
G
V
G
G
G
G
VDDQ3
G
V
G
G
C6
G
C5
G
G
G
V
G
G
G
V
G
G
FB = Dale ILB1206 - 300 or 2TDKACB2012L-120 or 2 Murata BLM21B601S.
C2 = 0.005 F
C6 = 10 F
C5 = 0.1 F
= VIA to respective supply plane layer.
µF
Ceramic Caps C1 = 10–22
= VIA to GND plane layer.
G
V
Note: Each supply plane or strip should have a ferrite bead and capacitors.
.....................Document #: 38-07010 Rev. *C Page 14 of 16
W320-04
Test Circuit
VDD_REF, VDD_PCI,
0.7V Test Load
VDD_3V66, VDD_CORE
VDD_48 MHz, VDD_CPU
4, 9, 15, 20, 27, 31, 36, 41
8, 14, 19, 26, 32, 37, 46, 50
Rp
Rs
W320-04
2 pF
Ref,USB Outputs
PCI,3V66 Outputs
CPU
Test Node
Test
Nodes
OUTPUTS
20 pF
2 pF
Rs
Test Node
Rp
30 pF
Note: Each supply pin must have an individual decoupling capacitor.
Note: All capacitors must be placed as close to the pins as is physically possible.
0.7V amplitude: RS = 33 ohm, RP = 50 ohm
VDD_REF, VDD_PCI,
VDD_3V66, VDD_CORE
VDD_48 MHz, VDD_CPU
1.0V Test Load
4, 9, 15, 20, 27, 31, 36, 41
8, 14, 19, 26, 32, 37, 46 ,50
33
2 pF
475
33
W320-04
Test
Nodes
Ref,USB Outputs
CPU
Test Node
OUTPUTS
20 pF
2 pF
63.4
63.4
PCI,3V66 Outputs
Test Node
1.0V Amplitude
30 pF
Ordering Information
Ordering Code
W320-04H
Package Type
Operating Range
Commercial 0C TO 70C
Commercial 0C TO 70C
Commercial 0C TO 70C
Commercial 0C TO 70C
56-pin SSOP
W320-04HT
56-pin SSOP - Tape and Reel
56-pin TSSOP
W320-04X
W320-04XT
56-pin TSSOP - Tape and Reel
Lead-Free
CYW320OXC-4
CYW320OXC-4T
CYW320ZXC-4
CYW320ZXC-4T
56-pin SSOP
Commercial 0C TO 70C
Commercial 0C TO 70C
Commercial 0C TO 70C
Commercial 0C TO 70C
56-pin SSOP - Tape and Reel
56-pin TSSOP
56-pin TSSOP - Tape and Reel
.....................Document #: 38-07010 Rev. *C Page 15 of 16
W320-04
Package Diagrams
56-Lead Shrunk Small Outline Package O56
.020
28
1
0.395
0.420
0.292
0.299
DIMENSIONS IN INCHES MIN.
MAX.
29
56
0.720
0.730
SEATING PLANE
0.005
0.010
0.088
0.092
0.095
0.110
.010
GAUGE PLANE
0.110
0.024
0.040
0.025
BSC
0.008
0.016
0°-8°
0.008
0.0135
56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56
0.249[0.009]
28
1
DIMENSIONS IN MM[INCHES] MIN.
MAX.
7.950[0.313]
8.255[0.325]
REFERENCE JEDEC MO-153
PACKAGE WEIGHT 0.42gms
5.994[0.236]
6.198[0.244]
PART #
Z5624 STANDARD PKG.
ZZ5624 LEAD FREE PKG.
29
56
13.894[0.547]
14.097[0.555]
1.100[0.043]
MAX.
GAUGE PLANE
0.25[0.010]
0.20[0.008]
0.508[0.020]
0.762[0.030]
0°-8°
0.051[0.002]
0.152[0.006]
0.851[0.033]
0.950[0.037]
0.500[0.020]
BSC
0.100[0.003]
0.200[0.008]
0.170[0.006]
0.279[0.011]
SEATING
PLANE
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Sil-
icon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the
use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or
parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, repre-
sentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized appli-
cation, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
.....................Document #: 38-07010 Rev. *C Page 16 of 16
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