CY28405OXCT_技术文档

CY28405

CK409-Compliant Clock Synthesizer

• Three differential CPU clock pairs

• Dial-A-Frequency^®

• Supports SMBus/I²C Byte, Word, and Block Read/Write

Features

• Supports Intel^®Springdale/Prescott (CK409)

• Selectable CPU frequencies

• 3.3V power supply

• Ideal Lexmark Spread Spectrum profile for maximum

electromagnetic interference (EMI) reduction

• Nine copies of PCI clock

• 48-pin SSOP package

• Four copies 3V66 clock with one optional VCH

• Two copies 48 MHz USB clock

• Two copies REF clock

CPU

x 3

3V66

x 4

PCI

x 9

REF

x 2

48M

x 2

Block Diagram

Pin Configuration

**FS_A/REF_0

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

VDDA

VSSA

IREF

**FS_B/REF_1

VDD_REF

XIN

VDD_REF

REF[0:1]

XIN

XTAL

OSC

CPUT_ITP

CPUC_ITP

VSS_CPU

CPUT1

CPUC1

VDD_CPU

CPUT0

CPUC0

VSS

DNC***

VDD

VTT_PWRGD#

SDATA

SCLK

3V66_0

3V66_1

VSS_3V66

VDD_3V66

XOUT

PLL Ref Freq

XOUT

VDD_CPU

VSS_REF

CPUT[0:1,ITP], CPUC[0:1,ITP]

Divider

Network

*FS_C/PCIF0

PLL 1

*FS_D/PCIF1

*FS_E/PCIF2

VDD_PCI

VSS_PCI

PCI0

9

FS_[A:E]

VTT_PWRGD#

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

IREF

PCI1

PCI2

PCI3

VDD_3V66

3V66_[0:2]

VDD_PCI

PCIF[0:2]

VDD_PCI

VSS_PCI

PCI4

PLL2

SELVCH

2

PCI[0:5]

PCI5

MODE

RESET#/PD#

DOT_48

USB_48

VSS_48

VDD_48

3V66_3/VCH

3V66_2/MODE*

3V66_3/VCH/SELVCH**

VDD_48MHz

DOT_48

PD#

USB_48

SSOP-48

* 150k Internal Pull-up

** 150k Internal Pull-down

*** Do Not Connect

2

SDATA

SCLK

I C

WD

Timer

RESET#

Logic

Rev 1.0, November 20, 2006

2200 Laurelwood Road, Santa Clara, CA 95054

Page 1 of 18

Tel:(408) 855-0555 Fax:(408) 855-0550

www.SpectraLinear.com

CY28405

Pin Description

Pin No.

Name

Type

O, SE

I

Description

1, 2

REF(0:1)

Reference Clock. 3.3V 14.318-MHz clock output.

1, 2, 7, 8, 9 FS_A, FS_B, FS_C,

FS_D, FS_E

3.3V LVTTL latched input for CPU frequency selection.

4

XIN

I

Crystal Connection or External Reference Frequency Input. This pin

has dual functions. It can be used as an external 14.318-MHz crystal

connection or as an external reference frequency input.

5

XOUT

O, SE

Crystal Connection. Connection for an external 14.318-MHz crystal

output.

39, 42, 45 CPUT(0:1,ITP)

38, 41, 44 CPUC(0:1,ITP)

O, DIF CPU Clock Output. Differential CPU clock outputs.

Do Not Connect.

36, 35

30, 29

DNC

3V66(0:1)

O, SE

66-MHz Clock Output. 3.3V 66-MHz clock from internal VCO.

25

3V66_3/VCH/SELVCH

I/O, SE 48- or 66-MHz Clock Output. 3.3V selectable through external SELVCH

PD

strapping resistor and SMBus to be 66-MHz or 48-MHz. Default is 66-MHz.

0 = 66 MHz, 1 = 48 MHz

26

3V66_2/MODE

I/O, SE 66-MHz Clock Output. 3.3V 66-MHz clock from internal VCO. Reset or

PU

Power-down Mode Select. Selects between RESET# output or PWRDWN#

input for the PWRDWN#/RESET# pin. Default is RESET#. 0 = PD#, 1 =

RESET

7, 8, 9

PCIF(0:2)

O, SE

Free Running PCI Output. 33-MHz clocks divided down from 3V66.

PCI Clock Output. 33-MHz clocks divided down from 3V66.

12, 13, 14, PCI(0:5)

15, 18, 19

22

21

46

USB_48

DOT_48

IREF

O, SE

I

Fixed 48-MHz clock output.

Current Reference. A precision resistor is attached to this pin which is

connected to the internal current reference.

20

33

RESET#/PD#

I/O, PU 3.3V LVTTL input for Power-down# active LOW. Watchdog Timeout

Reset Output

VTT_PWRGD#

I

3.3V LVTTL input is a level sensitive strobe used to latch the FS[A:E]

input (active LOW).

32

31

48

47

SDATA

SCLK

VDDA

VSSA

I/O

I

SMBus compatible SDATA.

SMBus compatible SCLOCK.

3.3V Power supply for PLL.

Ground for PLL.

PWR

GND

PWR

3, 10, 16, VDD(REF,PCI,48,3V66,C

3.3V Power supply for outputs.

24, 27, 34, PU,ITP)

40

6, 11, 17, VSS(REF,PCI,48,3V66,

GND

Ground for outputs.

23, 28, 37, CPU,ITP)

43

Rev 1.0,November 20, 2006

Page 2 of 18

CY28405

MODE Select

Frequency Select Pins

The hardware strapping MODE input pin can be used to select

the functionality of the RESET#/PD# pin. The default (internal

pull up) configuration is for this pin to function as a RESET#

Watchdog output. When pulled LOW during device power-up,

the RESET#/PD# pin will be configured to function as a Power

Down input pin.

Host clock frequency selection is achieved by applying the

appropriate logic levels to FS_A through FS_E inputs prior to

VTT_PWRGD# assertion (as seen by the clock synthesizer).

Upon VTT_PWRGD# being sampled low by the clock chip

(indicating processor VTT voltage is stable), the clock chip

samples the FS_A through FS_E input values. For all logic

levels of FS_A through FS_E, VTT_PWRGD# employs a

one-shot functionality in that once

a valid low on

VTT_PWRGD# has been sampled, all further VTT_PWRGD#

and FS_A through FS_E transitions will be ignored.

Table 1. Frequency Selection Table

Input Conditions

Output Frequency

PLL Gear

FS_E

FS_D

FS_C

FS_B

FS_A

Constants

FSEL_4 FSEL_3 FSEL_2 FSEL_1 FSEL_0

CPU

100.7

3V66

67.1

PCI

33.6

33.4

36.0

33.7

VCO Freq.

805.6

(G)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

24004009.32

Reserved

100.2

66.8

801.6

108.0

72.0

864.0

101.2

67.5

809.6

Reserved

125.7

Reserved

62.9

Reserved Reserved

Reserved

31.4

32.6

33.4

33.6

37.0

754.2

781.6

801.6

805.2

807.0

888.0

32005345.76

Reserved

130.3

65.1

133.6

66.8

134.2

67.1

134.5

67.3

148.0

74.0

Reserved

167.4

Reserved

55.8

Reserved Reserved

Reserved

27.9

28.3

29.2

30.0

30.8

31.7

33.6

33.5

669.6

680.0

700.0

720.0

740.0

760.0

807.2

803.4

803.6

48008018.65

24004009.32

32005345.76

48008018.65

Reserved

170.0

56.7

175.0

58.3

180.0

60.0

185.0

61.7

190.0

63.3

100.9

67.3

133.9

67.0

200.9

67.0

Reserved

100.0

Reserved

66.7

Reserved Reserved

33.3

800.0

24004009.32

32005345.76

48008018.65

Reserved

133.3

66.7

200.0

66.7

Reserved

Reserved Reserved

Rev 1.0,November 20, 2006

Page 3 of 18

CY28405

Serial Data Interface

Data Protocol

To enhance the flexibility and function of the clock synthesizer,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions, such as individual

clock output buffers, can be individually enabled or disabled.

The registers associated with the Serial Data Interface

initializes to their default setting upon power-up, and therefore

use of this interface is optional. The interface can also be

accessed during power-down operation.

The clock driver serial protocol accepts Byte Write, Byte Read,

Block Write and Block Read operation from any external I²C

controller. For Block Write/Read operation, the bytes must be

accessed in sequential order from lowest to highest byte (most

significant bit first) with the ability to stop after any complete

byte has been transferred. For Byte Write and Byte Read

operations, the system controller can access individual

indexed bytes. The offset of the indexed byte is encoded in the

command code, as described in Table 2.

The Block Write and Block Read protocol is outlined in Table 3

while Table 4 outlines the corresponding Byte Write and Byte

Read protocol. The slave receiver address is 11010010 (D2h).

Table 2. Command Code Definition

Bit

Description

7

0 = Block Read or Block Write operation

1 = Byte Read or Byte Write operation

(6:0)

Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations, these bits

should be ‘0000000’

Table 3. Block Read and Block Write Protocol

Block Write Protocol

Block Read Protocol

Description

Bit

1

Description

Bit

1

Start

2:8

9

Slave address – 7 bits

Write

2:8

9

Slave address – 7 bits

Write

10

Acknowledge from slave

10

Acknowledge from slave

Command Code – 8-bit ‘00000000’ stands for

block operation

Command Code – 8-bit ‘00000000’ stands for

block operation

11:18

19

20:27

28

Acknowledge from slave

Byte Count – 8 bits

19

20

Acknowledge from slave

Repeat start

Acknowledge from slave

Data byte 0 – 8 bits

21:27

28

Slave address – 7 bits

Read

29:36

37

Acknowledge from slave

Data byte 1 – 8 bits

29

Acknowledge from slave

Byte count from slave – 8 bits

Acknowledge

38:45

46

30:37

38

Acknowledge from slave

Data Byte N/Slave Acknowledge...

Data Byte N – 8 bits

Acknowledge from slave

Stop

....

39:46

47

Data byte from slave – 8 bits

Acknowledge

....

48:55

56

Data byte from slave – 8 bits

Acknowledge

....

Data bytes from slave/Acknowledge

Data byte N from slave – 8 bits

Not Acknowledge

....

Stop

Rev 1.0,November 20, 2006

Page 4 of 18

CY28405

Table 4. Byte Read and Byte Write Protocol

Byte Write Protocol

Byte Read Protocol

Description

Bit

1

Description

Bit

1

Start

2:8

9

Slave address – 7 bits

Write = 0

2:8

9

Slave address – 7 bits

Write = 0

10

Acknowledge from slave

10

Acknowledge from slave

11:18

Command Code – 8 bits

11:18

Command Code – 8 bits

‘1xxxxxxx’ stands for byte operation, bits[6:0] of

the command code represents the offset of the

byte to be accessed

‘1xxxxxxx’ stands for byte operation, bits[6:0]

of the command code represents the offset of

the byte to be accessed

19

20:27

28

Acknowledge from slave

Data byte from master – 8 bits

Acknowledge from slave

Stop

19

20

Acknowledge from slave

Repeat start

21:27

28

Slave address – 7 bits

Read = 1

29

Acknowledge from slave

Data byte from slave – 8 bits

Not Acknowledge

Stop

30:37

38

39

Byte 0: Control Register 0

Bit

@Pup

Name

Description

7

0

Test Bit 3

I2C_BYPASS_EN

Reserved, Set= 0 IO PLL TEST

6

1

PCIF

PCI

PCI Drive Strength Override

0 = Force All PCI and PCIF Outputs to Low Drive Strength

1= Force All PCI and PCIF Outputs to High Drive Strength

5

4

3

2

1

0

Reserved

FS_E

Reserved, Set= 0 PLL CPU VCO process correction test bit

Power up latched value of FS_E pin

HW

FS_D

Power up latched value of FS_D pin

FS_C

Power up latched value of FS_C pin

FS_B

Power up latched value of FS_B pin

FS_A

Power up latched value of FS_A pin

Byte 1: Control Register 1

Bit

7

@Pup

Name

Description

Reserved, set = 0

0

1

Reserved

6

Reserved, set = 1

5

Reserved, set = 1

4

Reserved, set = 1

3

Reserved, set = 1

2

CPUT_ITP, CPUC_ITP

CPUT/C_ITP Output Enable

0 = Disabled (three-state), 1 = Enabled

1

0

1

CPUT1, CPUC1

CPU(T/C)1 Output Enable,

0 = Disabled (three-state), 1 = Enabled

CPUT0, CPUC0

CPU(T/C)0 Output Enable

0 = Disabled (three-state), 1 = Enabled

Rev 1.0,November 20, 2006

Page 5 of 18

CY28405

Byte 2: Control Register 2

Bit

7

@Pup

Name

Description

0

Reserved

Reserved, set = 0

6

5

CPUT_ITP, CPUC_ITP

CPUT/C_ITP Pwrdwn drive mode

0 = Driven in power- down, 1 = three-state

4

3

0

CPUT1, CPUC1

CPU(T/C)1 Pwrdwn drive mode

0 = Driven in power-down, 1 = three-state

CPUT0, CPUC0

CPU(T/C)0 Pwrdwn drive mode

0 = Driven in power-down, 1 = three-state

2

1

0

Reserved

Byte 3: Control Register 3

Bit

@Pup

Name

Description

7

1

SW PCI_STP Function

0= PCI_STP assert, 1= PCI_STP deassert

When this bit is set to 0, all STOPPABLE PCI and PCIF outputs will be

stopped in a synchronous manner with no short pulses.

When this bit is set to 1, all STOPPED PCI and PCIF outputs will resume

in a synchronous manner with no short pulses.

6

5

1

Reserved

PCI5

Reserved

PCI5 Output Enable

0 = Disabled, 1 = Enabled

4

3

2

1

0

1

PCI4

PCI3

PCI2

PCI1

PCI0

PCI4 Output Enable

0 = Disabled, 1 = Enabled

PCI3 Output Enable

0 = Disabled, 1 = Enabled

PCI2 Output Enable

0 = Disabled, 1 = Enabled

PCI1 Output Enable

0 = Disabled, 1 = Enabled

PCI0 Output Enable

0 = Disabled, 1 = Enabled

Byte 4: Control Register 4

Bit

@Pup

Name

Description

7

0

USB_48

(404: 24_48MHz)

USB 48 (404: and 24MHz) Drive Strength Control

0 = High Drive Strength, 1 = Low Drive Strength

6

5

4

3

2

1

0

1

0

1

USB_48

PCIF2

PCIF1

PCIF0

PCIF2

PCIF1

PCIF0

USB_48 Output Enable

0 = Disabled, 1 = Enabled

Allow control of PCIF2 with assertion of SW PCI_STP

0 = Free Running, 1 = Stopped with SW PCI_STP

Allow control of PCIF1 with assertion of SW PCI_STP

0 = Free Running, 1 = Stopped with SW PCI_STP

Allow control of PCIF0 with assertion of SW PCI_STP

0 = Free Running, 1 = Stopped with SW PCI_STP

PCIF2 Output Enable

0 = Disabled, 1 = Enabled

PCIF1 Output Enable

0 = Disabled, 1 = Enabled

PCIF0 Output Enable

0 = Disabled, 1 = Enabled

Rev 1.0,November 20, 2006

Page 6 of 18

CY28405

Byte 5: Control Register 5

Bit

@Pup

Name

Description

7

1

DOT_48

DOT_48 Output Enable

0 = Disabled, 1 = Enabled

6

5

1

Reserved

HW

3V66_3/VCH/SELVCH

3V66_3/VCH/SELVCH Frequency Select

0 = 3V66 mode, 1 = VCH (48MHz) mode

May be written to override the power-up value.

4

1

3V66_3/VCH/SELVCH

3V66_3/VCH/SELVCH Output Enable

0 = Disabled,1 = Enabled

3

2

1

Reserved

3V66_2

Reserved

3V66_2 Output Enable

0 = Disabled, 1 = Enabled

1

0

1

3V66_1

3V66_0

3V66_1 Output Enable

0 = Disabled, 1 = Enabled

3V66_0 Output Enable

0 = Disabled, 1 = Enabled

Byte 6: Control Register 6

Bit

@Pup

Name

Description

7

0

REF

PCIF

Test Clock Mode

0 = Disabled, 1 = Enabled

PCI

3V66

When Test Clock Mode is enabled, the FS_A/REF_0 pin reverts to a

dedicated FS_A input, allowing asynchronous selection between Hi-Z and

REF/N mode.

3V66_3/VCH/SELVCH

USB_48

DOT_48

CPUT, CPUT_ITP

CPUC,CPUC_ITP

6

5

0

Reserved

Reserved, Set = 0

FS_A & FS_B Operation

0 = Normal, 1 = Test mode

4

3

2

0

Reserved

Reserved, Set = 0

PCIF

PCI

Spread Spectrum Enable

0 = Spread Off, 1 = Spread On

3V66

CPUT,CPUT_ITP

CPUC,CPUC_ITP

1

0

1

REF_1

REF_1 Output Enable

0 = Disabled, 1 = Enabled

REF_0

REF_0 Output Enable

0 = Disabled, 1 = Enabled

Byte 7: Vendor ID

Bit @Pup

Name

Description

Revision Code Bit 3

Revision Code Bit 2

Revision Code Bit 1

Revision Code Bit 0

Vendor ID Bit 3

7

6

5

4

3

2

1

0

1

0

1

0

Vendor ID Bit 2

Vendor ID Bit 1

Rev 1.0,November 20, 2006

Page 7 of 18

CY28405

Byte 7: Vendor ID

Bit @Pup

Name

Description

0

Vendor ID Bit 0

Byte 8: Control Register 8

Bit

7

@Pup

0

1

CPU

PCIF

PCI

Spread Spectrum Selection

‘000’ = ±0.20% triangular

‘001’ = + 0.12, – 0.62%

‘010’ = + 0.25, – 0.75%

6

5

3V66

‘011’ = –0.05, – 0.45% triangular

‘100’ = ± 0.25%

‘101’ = + 0.00, – 0.50%

‘110’ = ± 0.5%

‘111’ = ± 0.38%

4

3

2

1

0

FSEL_4

FSEL_3

FSEL_2

FSEL_1

FSEL_0

SW Frequency selection bits. See Table 1.

Byte 9: Control Register 9

Bit

@Pup

Name

Description

7

0

PCIF

PCIF Clock Output Drive Strength Control

0 = Low Drive strength, 1 = High Drive strength

6

5

4

3

2

0

1

PCI

PCI Clock Output Drive Strength

0 = Low Drive strength, 1 = High Drive strength

3V66

3V66 Clock Output Drive Strength

0 = Low Drive strength, 1 = High Drive strength

REF

REF Clock Output Drive Strength

0 = Low Drive strength, 1 = High Drive strength

1

Reserved

(‘404: 1)

1

Reserved

(Reserved for CY28404:

REF2

Reserved

(Reserved for CY28404:

REF2 Output Enable

0 = Disabled, 1 = Enabled)

1

0

Reserved

Vendor Test Mode (always program to 0) PLL Bypass Test

Vendor Test Mode (always program to 0) PLL Leakage Test

Byte 10: Control Register 10

Bit

7

@Pup

Name

PCI_Skew1

Description

0

PCI skew control

00 = Normal

01 = –500 ps

10 = Reserved

11 = +500 ps

6

PCI_Skew0

5

4

0

3V66_Skew1

3V66_Skew0

3V66 skew control

00 = Normal

01 = –150 ps

10 = +150 ps

11 = +300 ps

3

2

1

Reserved

Reserved, Set = 1

Rev 1.0,November 20, 2006

Page 8 of 18

CY28405

Byte 10: Control Register 10 (continued)

Bit

1

@Pup

Name

Description

1

Reserved

Reserved, Set = 1

0

Byte 11: Control Register 11

Bit

7

@Pup

Name

0

Reserved

Vendor Test Mode (always program to 0)

6

Recovery_Frequency

This bit allows selection of the frequency setting that the clock will be

restored to once the system is rebooted

0: Use Hardware settings

1: Use Last SW table Programmed values

5

4

0

Watchdog Time Stamp

Reload

Toenable this function the registerbit must first be set to “0” before toggling

to “1”.

0: Do not reload

1: Reset timer but continue to count.

WD_Alarm

This bit is set to “1” when the Watchdog times out. It is reset to “0” when

the system clears the WD_TIMER time stamp

3

2

1

0

WD_TIMER3

WD_TIMER2

WD_TIMER1

WD_TIMER0

Watchdog timer time stamp selection:

0000: Off

0001: 2 second

0010: 4 seconds

0011: 6 seconds

.

1110: 28seconds

1111: 30seconds

Byte 12: Control Register 12

Bit

7

@Pup

Name

CPU_FSEL_N8

CPU_FSEL_N7

CPU_FSEL_N6

CPU_FSEL_N5

CPU_FSEL_N4

CPU_FSEL_N3

CPU_FSEL_N2

CPU_FSEL_N1

Description

0

If Prog_Freq_EN is set, the values programmed inCPU_FSEL_N[8:0] and

CPU_FSEL_M[6:0] will be used to determine the CPU output frequency.

The setting of FS_Override bit determines the frequency ratio for CPU and

other output clocks. When it is cleared, the same frequency ratio stated in

the Latched FS[E:A] register will be used. When it is set, the frequency

ratio stated in the SEL[4:0] register will be used.

6

5

4

3

2

1

0

Byte 13: Control Register 13

Bit

7

@Pup

Name

CPU_FSEL_N0

CPU_FSEL_M6

CPU_FSEL_M5

CPU_FSEL_M4

CPU_FSEL_M3

CPU_FSEL_M2

CPU_FSEL_M1

CPU_FSEL_M0

Description

0

IfProg_Freq_ENisset, thevaluesprogrammedinCPU_FSEL_N[8:0]and

CPU_FSEL_M[6:0] will be used to determine the CPU output frequency.

The setting of FS_Override bit determines the frequency ratio for CPU and

other output clocks. When it is cleared, the same frequency ratio stated in

the Latched FS[E:A] register will be used. When it is set, the frequency

ratio stated in the SEL[4:0] register will be used.

6

5

4

3

2

1

0

Rev 1.0,November 20, 2006

Page 9 of 18

CY28405

Byte 14: Control Register 14

Bit

@Pup

Name

Description

7

0

FS_(E:A)

FS_Override

0 = Select operating frequency by FS(E:A) input pins

1 = Select operating frequency by FSEL(4:0) settings

6

5

4

3

2

1

0

1

0

Reserved

Reserved, Set = 1

Reserved, Set = 0

Pro_Freq_EN

Programmable output frequencies enabled

0 = Disabled, 1 = Enabled

Dial-a-Frequency Programming

Crystal Recommendations

When the programmable output frequency feature is enabled

(Pro_Freq_EN bit is set), the CPU output frequency is deter-

mined by the following equation:

The CY28405 requires a Parallel Resonance Crystal.

Substituting a series resonance crystal will cause the

CY28405 to operate at the wrong frequency and violate the

ppm specification. For most applications there is a 300-ppm

frequency shift between series and parallel crystals due to

incorrect loading.

Fcpu = G * N/M

“N” and “M” are the values programmed in Programmable

Frequency Select N-Value Register and M-Value Register,

respectively.

Crystal Loading

“G” stands for the PLL Gear Constant, which is determined by

the programmed value of FS[E:A] or SEL[4:0]. The value is

listed in Table 1.

Crystal loading plays a critical role in achieving low ppm perfor-

mance. To realize low ppm performance, the total capacitance

the crystal will see must be considered to calculate the appro-

priate capacitive loading (CL).

The ratio of N and M need to be greater than “1” [N/M> 1].

The following table lists set of N and M values for different

frequency output ranges. This example use a fixed value for

the M-Value Register and select the CPU output frequency by

changing the value of the N-Value Register.

Figure 1 shows a typical crystal configuration using the two

trim capacitors. An important clarification for the following

discussion is that the trim capacitors are in series with the

crystal not parallel. It’s a common misconception that load

capacitors are in parallel with the crystal and should be

approximately equal to the load capacitance of the crystal.

This is not true.

Table 5. Examples of N and M Value for Different CPU

Frequency Range

Range of N-Value

Fixed Value

for M-Value

Register

Register for

Different CPU

Frequency

Ranges

Gear

Constants

100 –125 24004009.32

126 – 166 32005345.76

167 – 200 48008018.65

48

200 – 250

189 – 249

167 – 200

Table 6. Crystal Recommendations

Frequency

Drive

Shunt Cap Motional

Tolerance

(max.)

Stability

(max.)

Aging

(max.)

Cut

Loading Load Cap

Parallel 20 pF

(Fund)

(max.)

14.31818 MHz

AT

0.1 mW

5 pF

0.016 pF

50 ppm

5 ppm

Rev 1.0,November 20, 2006

Page 10 of 18

CY28405

As mentioned previously, the capacitance on each side of the

crystal is in series with the crystal. This mean the total capac-

itance on each side of the crystal must be twice the specified

load capacitance (CL). While the capacitance on each side of

the crystal is in series with the crystal, trim capacitors

(Ce1,Ce2) should be calculated to provide equal capacitative

loading on both sides.

Use the following formulas to calculate the trim capacitor

values for Ce1 and Ce2.

Load Capacitance (each side)

Figure 1. Crystal Capacitive Clarification

Ce = 2 * CL - (Cs + Ci)

Calculating Load Capacitors

Total Capacitance (as seen by the crystal)

1

In addition to the standard external trim capacitors, trace

capacitance and pin capacitance must also be considered to

correctly calculate crystal loading. As mentioned previously,

the capacitance on each side of the crystal is in series with the

crystal. This means the total capacitance on each side of the

crystal must be twice the specified crystal load capacitance

(CL). While the capacitance on each side of the crystal is in

series with the crystal, trim capacitors (Ce1,Ce2) should be

calculated to provide equal capacitive loading on both sides.

CLe

=

1

(

)

+

Ce2 + Cs2 + Ci2

Ce1 + Cs1 + Ci1

CL....................................................Crystal load capacitance

CLe......................................... Actual loading seen by crystal

..................................... using standard value trim capacitors

Ce..................................................... External trim capacitors

Cs............................................. Stray capacitance (trace,etc)

Ci ............. Internal capacitance (lead frame, bond wires etc)

Clock Chip

PD# (Power-down) Clarification

Ci2

Ci1

The PD# pin is used to shut off all clocks and PLLs without

having to remove power from the device. All clocks are shut

down in a synchronous manner so has not to cause glitches

while transitioning to the power down state.

3 to 6p

PD# – Assertion

X2

X1

Cs2

Cs1

When PD# is sampled LOW by two consecutive rising edges

of the CPUC clock then all clock outputs (except CPUT) clocks

must be held LOW on their next HIGH to LOW transition. CPU

clocks must be held with CPUT clock pin driven HIGH with a

value of 2x Iref and CPUC undriven as the default condition.

There exists an I²C bit that allows for the CPUT/C outputs to

be three-stated during power-down. Due to the state of internal

logic, stopping and holding the REF clock outputs in the LOW

state may require more than one clock cycle to complete

Trace

2.8pF

XTAL

Ce1

Ce2

Trim

33pF

Figure 2. Crystal Loading Example

PWRDWN#

CPUT, 133MHz

CPUC, 133MHz

3V66, 66MHz

USB, 48MHz

PCI, 33MHz

REF, 14.31818

Figure 3. Power-down Assertion Timing Waveforms

Rev 1.0,November 20, 2006

Page 11 of 18

CY28405

PD# Deassertion

The power-up latency between PD# rising to a valid logic ‘1’

level and the starting of all clocks is less than 1.8 ms. The

CPUT/C outputs must be driven to greater than 200 mV is less

than 300 μs.

Tstable

<1.8ms

PWRDWN#

CPUT, 133MHz

CPUC, 133MHz

3V66, 66MHz

USB, 48MHz

PCI, 33MHz

REF, 14.31818

Tdrive_PWRDN#

<300μs, >200mV

Figure 4. Power-down Deassertion Timing Waveforms

FS_A, FS_B

VTT_PWRGD#

PWRGD_VRM

0.2-0.3mS

Delay

Wait for

VTT_PWRGD#

Device is not affected,

VTT_PWRGD# is ignored

Sample Sels

State 2

VDD Clock Gen

Clock State

State 0

Off

State 1

State 3

On

Clock Outputs

Clock VCO

On

Off

Figure 5. VTT_PWRGD Timing Diagram

Rev 1.0,November 20, 2006

Page 12 of 18

CY28405

S2

S1

VTT_PWRGD# = Low

Delay

Sample

>0.25mS

Inputs straps

VDDA = 2.0V

Wait for 1.146ms

S0

S3

VDDA = off

Normal

Operation

Enable Outputs

Power Off

VTT_PWRGD# = toggle

Figure 6. Clock Generator Power-up/Run State Diagram

Rev 1.0,November 20, 2006

Page 13 of 18

CY28405

Absolute Maximum Conditions

Parameter

V_DD

Description

Core Supply Voltage

Condition

Min.

–0.5

–65

0

Max.

Unit

V

4.6

V_DDA

V_IN

Analog Supply Voltage

Input Voltage

V

Relative to V _SS

V_DD+ 0.5

+150

70

VDC

°C

T_S

Temperature, Storage

Temperature, Operating Ambient

Temperature, Junction

Non-functional

Functional

T_A

°C

T_J

Functional

–

150

°C

ESD_HBM

Ø_JC

ESD Protection (Human Body Model) MIL-STD-883, Method 3015

2000

–

V

Dissipation, Junction to Case

Dissipation, Junction to Ambient

Flammability Rating

Mil-Spec 883E Method 1012.1

JEDEC (JESD 51)

At 1/8 in.

15

45

°C/W

Ø_JA

UL–94

MSL

V – 0

1

Moisture Sensitivity Level

Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing

is NOT required.

DC Electrical Specifications

Parameter

Description

Conditions

3.3V ± 5%

Min.

3.135

–

Max.

Unit

V

V_DD, V_DDA3.3 Operating Voltage

3.465

V_ILI2C

V_IHI2C

V_IL

Input Low Voltage

Input High Voltage

Input Low Voltage

Input High Voltage

Input Leakage Current

SDATA, SCLK

–

1.0

–

2.2

–

0.8

V_SS– 0.5

2.0

V

V_IH

V_DD+ 0.5

5

V

I_IL

Except Pull-ups or Pull-downs

0 < V_IN< V_DD

–5

µA

V_OL

V_OH

I_OZ

Output Low Voltage

Output High Voltage

High-impedance Output Current

Input Pin Capacitance

Output Pin Capacitance

Pin Inductance

I_OL= 1 mA

–

0.4

V

I_OH= –1 mA

2.4

–

10

–10

µA

pF

nH

V

C_IN

2

5

C_OUT

L_IN

3

6

–

7

V_XIH

V_XIL

I_DD

Xin High Voltage

0.7V_DD

V_DD

0.3V_DD

280

Xin Low Voltage

0

–

V

Dynamic Supply Current

At 200 MHz and all outputs

mA

loaded per Table 9 and Figure 7

I_PD

Power-down Supply Current

PD# Asserted

–

1

mA

Rev 1.0,November 20, 2006

Page 14 of 18

CY28405

AC Electrical Specifications

Parameter

Crystal

Description

Conditions

Min.

Max.

Unit

T_DC

XIN Duty Cycle

The device will operate

reliably with input duty cycles

up to 30/70 but the REF clock

duty cycle will not be within

specification

47.5

52.5

%

T_PERIOD

T_R/ T_F

T_CCJ

XIN period

When Xin is driven from an

external clock source

69.841

71.0

10.0

ns

XIN Rise and Fall Times

XIN Cycle to Cycle Jitter

Long-term Accuracy

Measured between 0.3V_DD

and 0.7V_DD

–

As an average over 1 μs

duration

500

300

ps

L_ACC

Over 150ms

ppm

CPU at 0.7V

T_DC

CPUT and CPUC Duty Cycle

100-MHz CPUT and CPUC Period

133-MHz CPUT and CPUC Period

200-MHz CPUT and CPUC Period

Any CPU to CPU Clock Skew

CPU Cycle to Cycle Jitter

MeasuredatcrossingpointV_OX

Measured at crossing point V_OX

MeasuredatcrossingpointV_OX

Measured at crossing point V_OX

45

9.9970

7.4978

4.9985

–

55

%

ns

ps

T_PERIOD

T_SKEW

T_CCJ

10.003

7.5023

5.0015

100

–

125

T_R/ T_F

CPUT and CPUC Rise and Fall Times Measured from V_OL= 0.175

to V_OH= 0.525V

175

–

700

20

ps

%

T_RFM

Rise/Fall Matching

Determined as a fraction of

2*(T_R– T_F)/ (T_R+ T_F)

ΔT_R

Rise Time Variation

–

125

ps

mv

V

ΔT_F

Fall Time Variation

125

V_HIGH

V_LOW

V_OX

Voltage High

Math average, see Figure 7

Math average,see Figure 7

660

–150

250

–

850

Voltage Low

–

550

Crossing Point Voltage at 0.7V Swing

Maximum Overshoot Voltage

Minimum Undershoot Voltage

Ring Back Voltage

V_OVS

V_UDS

V_RB

V_HIGH+0.3

–

–0.3

–

V

See Figure 7. Measure SE

0.2

V

3V66

T_DC

3V66 Duty Cycle

Measurement at 1.5V

Measurement at 2.4V

Measurement at 0.4V

45

55

15.0045

15.0799

–

%

ns

T_PERIOD

T_HIGH

Spread Disabled 3V66 Period

Spread Enabled 3V66 Period

3V66 High Time

14.9955

4.9500

4.5500

T_LOW

3V66 Low Time

–

T_R/ T_F

3V66 Rise and Fall Times

Measured between 0.4V and

2.4V

0.5

2.0

ns

T_SKEW

T_CCJ

Any 3V66 to Any 3V66 Clock Skew

3V66 Cycle to Cycle Jitter

Measurement at 1.5V

–

250

ps

PCI/PCIF

T_DC

PCIF and PCI Duty Cycle

Measurement at 1.5V

Measurement at 2.4V

45

55

30.0009

30.1598

–

%

ns

T_PERIOD

T_HIGH

Spread Disabled PCIF/PCI Period

Spread Enabled PCIF/PCI Period

PCIF and PCI High Time

29.9910

12.0

Rev 1.0,November 20, 2006

Page 15 of 18

CY28405

AC Electrical Specifications (continued)

Parameter

T_LOW

Description

PCIF and PCI Low Time

Conditions

Min.

Max.

Unit

Measurement at 0.4V

12.0

–

ns

T_R/ T_F

PCIF and PCI Rise and Fall Times

Measured between 0.4V and

2.4V

0.5

2.0

ns

T_SKEW

T_CCJ

Any PCI Clock to Any PCI Clock Skew Measurement at 1.5V

–

500

250

ps

PCIF and PCI Cycle to Cycle Jitter

Measurement at 1.5V

DOT

T_DC

Duty Cycle

Measurement at 1.5V

Measurement at 2.4V

Measurement at 0.4V

45

55

%

ns

T_PERIOD

T_HIGH

Period

20.8257

8.994

8.794

20.8340

10.486

10.386

DOT High Time

DOT Low Time

Rise and Fall Times

T_LOW

T_R/ T_F

Measured between 0.4V and

2.4V

0.5

–

1.0

ns

ps

T_CCJ

Cycle to Cycle Jitter

10-μs period

350

USB

T_DC

Duty Cycle

Measurement at 1.5V

Measurement at 2.4V

Measurement at 0.4V

45

55

%

ns

T_PERIOD

T_HIGH

Period

20.8257

8.094

7.694

20.8340

10.036

9.836

USB High Time

USB Low Time

Rise and Fall Times

T_LOW

T_R/ T_F

Measured between 0.4V and

2.4V

1.0

–

2.0

ns

ps

T_CCJ

Cycle to Cycle Jitter

125-μs period

350

REF

T_DC

REF Duty Cycle

REF Period

Measurement at 1.5V

45

55

%

T_PERIOD

T_R/ T_F

69.827

69.855

ns

REF Rise and Fall Times

Measured between 0.4V and

2.4V

1.0

–

4.0

V/ns

ps

T_CCJ

REF Cycle to Cycle Jitter

Measurement at 1.5V

1000

ENABLE/DISABLE and SET-UP

T_STABLEAll Clock Stabilization from Power-up

T_SS

–

10.0

0

1.5

–

ms

ns

Stopclock Set-up Time

Stopclock Hold Time

T_SH

–

Table 7. Group Timing Relationship and Tolerances

Offset

Group

Conditions

3V66 Leads PCI

Min.

1.5 ns

Max.

3V66 to PCI

3.5 ns

Table 8. USB to DOT Phase Offset

Parameter

DOT Skew

USB Skew

VCH SKew

Typical

0°

Value

0.0 ns

Tolerance

1000 ps

180°

0°

Rev 1.0,November 20, 2006

Page 16 of 18

CY28405

Table 9. Maximum Lumped Capacitive Output Loads

Test and Measurement Set-up

Clock

Max Load

Units

pF

For Differential CPU and SRC Output Signals

PCI Clocks

3V66 Clocks

USB Clock

DOT Clock

REF Clock

30

20

10

30

The following diagram shows lumped test load configurations

for the differential Host Clock Outputs.

pF

M easurem ent

Point

2pF

T_PCB

33Ω

CPUT

49.9Ω

M easurem ent

Point

2pF

T_PCB

33Ω

CPUC

IREF

49.9Ω

475Ω

Figure 7. 0.7V Load Configuration

O u tp u t u nd e r T e st

P ro b e

L o a d C a p

3 .3 V s ig n a ls

tD C

-

3 .3 V

2 .4 V

1 .5 V

0 .4 V

0 V

T r

T f

Figure 8. Lumped Load For Single-Ended Output Signals (for AC Parameter Measurement)

Table 10.CPU Clock Current Select Function

Board Target Trace/Term Z

Reference R, I_REF– V_DD(3*R_REF

)

Output Current

V_OH@ Z

50 Ohms

R_REF= 475 1%, I_REF= 2.32 mA

I_OH= 6*I_REF

0.7V @ 50

Rev 1.0,November 20, 2006

Page 17 of 18

CY28405

Ordering Information

Part Number

CY28405OC

Package Type

Product Flow

48-pin Shrunk Small Outline package (SSOP)

48-pin Shrunk Small Outline package (SSOP) – Tape and Reel

Commercial, 0° to 70°C

CY28405OCT

Lead Free

CY28405OXC

CY28405OXCT

48-pin Shrunk Small Outline package (SSOP)

Commercial, 0° to 70°C

48-pin Shrunk Small Outline package (SSOP) – Tape and Reel

Package Drawing and Dimensions

48-Lead Shrunk Small Outline Package O48

While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir-

cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in

normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica-

tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional

processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any

circuitry or specification without notice.

Rev 1.0, November 20, 2006

Page 18 of 18


型号：	CY28405OXCT
厂家：	SILICON
描述：	Processor Specific Clock Generator, 200.9MHz, CMOS, PDSO48, LEAD FREE, SSOP-48 时钟光电二极管外围集成电路晶体
文件：	总18页 (文件大小：191K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY28405OXCT [SILICON]

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