CY28316PVCT [SILICON]
Processor Specific Clock Generator, 200MHz, CMOS, PDSO48, 0.300 INCH, SSOP-48;
| 型号： | CY28316PVCT |
| 厂家： | 
SILICON |
| 描述： | Processor Specific Clock Generator, 200MHz, CMOS, PDSO48, 0.300 INCH, SSOP-48 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总17页 (文件大小：203K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY28316
FTG for VIA PL133T and PLE133T
Features
• Single-chip system frequency synthesizer for VIA
PL133T and PLE133T chipsets
• Vendor ID and Revision ID support
• Programmable drive strength for SDRAM and PCI
output clocks
• Programmable clock output frequency with less than
1 MHz increment
• Programmable output skew for CPU, PCI, and SDRAM
• Integrated fail-safe Watchdog Timer for system
recovery
• Maximized electromagnetic interference (EMI)
suppression using Cypress’s Spread Spectrum
technology
• Automatically switches to HW-selected or
SW-programmed clock frequency when Watchdog
Timer time-out occurs
• Available in 48-pin SSOP
Key Specifications
• Capable of generating system RESET after a Watchdog
Timer time-out occurs or a change in output frequency
via SMBus interface
CPU to CPU Output Skew:......................................... 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
• SupportsSMBusbyteRead/WriteandblockRead/Write
operations to simplify system BIOS development
[1]
Block Diagram
Pin Configuration
VDD_REF
REF0
VDD_REF
GND_REF
X1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VTT_PWRGD#
REF0
REF1/FS2*
GND_CPU
CPU0
CPU1
VDD_CPU
RST#
SDRAM_12
GND_SDRAM
SDRAM0
SDRAM1
VDD_SDRAM
SDRAM2
SDRAM3
GND_SDRAM
SDRAM4
SDRAM5
VDD_SDRAM
SDRAM6
1
2
3
4
5
6
7
8
REF1/FS2*
X1
X2
XTAL
OSC
X2
PLL Ref Freq
VDD_PCI
*FS4/PCI0
*FS3/PCI1
GND_PCI
PCI2
9
VTTPWRGD#
PCI3
PCI4
PCI5
PCI6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CPU0:1
PLL 1
÷2,3,4
VDD_PCI
SDRAMIN
GND_SDRAM
SDRAM11
SDRAM10
VDD_SDRAM
SDRAM9
SDRAM8
GND_SDRAM
SDATA
VDD_PCI
PCI0/FS4*
PCI1/FS3*
PCI2:6
SDATA
SCLK
SMBus
Logic
Reset
Logic
SDRAM7
RST#
VDD_48MHz
48MHz/FS0*
24_48MHz/FS1*
VDD_48MHz
48MHz/FS0*
PLL2
SMBus
{
SCLK
÷2
24_48MHz/FS1*
VDD_SDRAM
SDRAM0:12
SDRAMIN
13
Note:
1. Signals marked with ‘*’ have internal pull-up resistors.
Rev 1.0, November 20, 2006
Page 1 of 17
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555 Fax:(408) 855-0550
www.SpectraLinear.com
CY28316
Pin Definitions
Pin Name
Pin No.
Pin Type
Pin Description
CPU0:1
44, 43
O
O
CPU Clock Output 0 through 1: CPU clocks for processor and chipset.
PCI2:6
9, 10, 11, 12,
13
PCI Clock Outputs 2 through 6: 3.3V 33-MHz PCI clock outputs. Frequency is
set by FS0:4 inputs or through serial data interface.
PCI1/FS3
7
I/O
Fixed PCI Clock Output/Frequency Select 3: 3.3V PCI clock outputs. As an
output, frequency is set by FS0:4 inputs or through the serial data interface. This
pin also serves as a power-on strap option to determine the device operating
frequency, as described in Table 5.
PCI0/FS4
6
I/O
Fixed PCI Clock Output/Frequency Select 4: 3.3V PCI clock outputs. This pin
also serves as a power-on strap option to determine the device operating
frequency, as described in Table 5.
RST#
41
26
O
(open-drain)
Reset# Output: Open drain system reset output.
48MHz/FS0
I/O
I/O
I/O
48-MHz Output/Frequency Select 0: 3.3V 48-MHz non-spread spectrum output.
This pin also serves as a power-on strap option to determine the device operating
frequency as described in Table 5.
24_48MHz/
FS1
25
46
24_48MHz Output/Frequency Select 1: 3.3V 24- or 48-MHz non-spread
spectrum output. This pin also serves as a power-on strap option to determine the
device operating frequency, as described in Table 5.
REF1/FS2
Reference Clock Output 1/Frequency Select 2: 3.3V 14.318-MHz output clock.
This pin also serves as a power-on strap option to determine the device operating
frequency as described in Table 5.
REF0
47
15
O
I
Reference Clock Output 0: 3.3V 14.318-MHz output clock.
SDRAM Buffer Input Pin: Reference input for SDRAM buffer.
SDRAMIN
SDRAM0:12 38, 37, 35, 34,
32, 31, 29, 28,
21, 20, 18, 17,
40
O
SDRAM Outputs: These thirteen dedicated outputs provide copies of the signal
provided at the SDRAMIN input.
SCLK
SDATA
X1
24
23
3
I
I/O
I
Clock pin for SMBus circuitry.
Data pin for SMBus circuitry.
Crystal Connection or External Reference Frequency Input: This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.
X2
4
O
I
Crystal Connection: An output connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
VTT_PWRGD#
48
VTT_PWRGD#: 3.3V LVTTL compatible input that controls the FS0:4 to be latched
and enables all outputs. CY28316 will sample the FS0:4 inputs and enable all clock
outputs after all VDD become valid and VTT_PWRGD# is held LOW.
VDD_REF,
VDD_PCI,
VDD_SDRAM,
VDD_48MHz
1, 5, 14, 19,
27, 30, 36
P
Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs,
PCI outputs, reference outputs, 48-MHz output, and 24_48-MHz output. Connect
to 3.3V supply.
VDD_CPU
42
P
Power Connection: Power supply for CPU outputs. Connect to 2.5V supply.
GND_REF,
GND_PCI,
2, 8, 16, 22,
33, 39, 45
G
Ground Connections: Connect all ground pins to the common system ground
plane.
GND_SDRAM,
VDD_48MHz,
VDD_CPU
Rev 1.0,November 20, 2006
Page 2 of 17
CY28316
Serial Data Interface
Data Protocol
The CY28316 features a two-pin, serial data interface that can
be used to configure internal register settings that control
particular device functions.
The clock driver serial protocol supports byte/word Write,
byte/word Read, block Write and block Read operations from
the controller. For block Write/Read operation, the bytes must
be accessed in sequential order from lowest to highest byte,
with the ability to stop after any complete byte has been trans-
ferred. For byte/word Write and byte Read operations, the
system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code.
The definition for the command code is defined in Table 1.
Table 1. Command Code Definition
Bit
Descriptions
7
0 = Block read or block write operation
1 = Byte/Word read or byte/word write operation
6:0
Byte offset for byte/word read or write operation. For block read or write operations, these bits
need to be set at ‘0000000.’
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Description
Bit
1
Description
Start
Bit
1
Start
2:8
9
Slave address – 7 bits
Write
2:8
9
Slave address – 7 bits
Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code – 8 bits
‘00000000’ stands for block operation
11:18
Command Code – 8 bits
‘00000000’ stands for block operation
19
20:27
28
Acknowledge from slave
Byte Count – 8 bits
19
20
Acknowledge from slave
Repeat start
Acknowledge from slave
Data byte 0 – 8 bits
21:27
28
Slave address – 7 bits
Read
29:36
37
Acknowledge from slave
Data byte 1 – 8 bits
29
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge
38:45
46
30:37
38
Acknowledge from slave
Data Byte N/Slave Acknowledge...
Data Byte N – 8 bits
...
39:46
47
Data byte from slave – 8 bits
Acknowledge
...
...
Acknowledge from slave
Stop
48:55
56
Data byte from slave – 8 bits
Acknowledge
...
...
Data bytes from slave/Acknowledge
Data byte N from slave – 8 bits
Not acknowledge
...
...
...
Stop
Table 3. Word Read and Word Write Protocol
Word Write Protocol
Word Read Protocol
Description
Bit
1
Description
Start
Bit
1
Start
2:8
9
Slave address – 7 bits
Write
2:8
9
Slave address – 7 bits
Write
10
Acknowledge from slave
10
Acknowledge from slave
Rev 1.0,November 20, 2006
Page 3 of 17
CY28316
Table 3. Word Read and Word Write Protocol (continued)
Word Write Protocol
Word Read Protocol
Description
Bit
Description
Bit
11:18
Command Code – 8 bits
‘1xxxxxxx’ stands for byte or word operation
bit[6:0] of the command code represents the offset
of the byte to be accessed
11:18
Command Code – 8 bits
‘1xxxxxxx’ stands for byte or word operation
bit[6:0] of the command code represents the offset
of the byte to be accessed
19
20:27
28
Acknowledge from slave
Data byte low – 8 bits
Acknowledge from slave
Data byte high – 8 bits
Acknowledge from slave
Stop
19
20
Acknowledge from slave
Repeat start
21:27
28
Slave address – 7 bits
Read
29:36
37
29
Acknowledge from slave
Data byte low from slave – 8 bits
Acknowledge
38
30:37
38
39:46
47
Data byte high from slave – 8 bits
Not acknowledge
48
Stop
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Description
Bit
1
Description
Start
Bit
1
Start
2:8
9
Slave address – 7 bits
Write
2:8
9
Slave address – 7 bits
Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code – 8 bits
‘1xxxxxxx’ stands for byte operation
bit[6:0] of the command code represents the offset
of the byte to be accessed
11:18
Command Code – 8 bits
‘1xxxxxxx’ stands for byte operation
bit[6:0] of the command code represents the offset
of the byte to be accessed
19
20:27
28
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
19
20
Acknowledge from slave
Repeat start
21:27
28
Slave address – 7 bits
Read
29
29
Acknowledge from slave
Data byte from slave – 8 bits
Not acknowledge
Stop
30:37
38
39
Rev 1.0,November 20, 2006
Page 4 of 17
CY28316
CY28316 Serial Configuration Map
1. The serial bits will be read by the clock driver in the following
order:
Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N – Bits 7, 6, 5, 4, 3, 2, 1, 0
2. All unused register bits (reserved and N/A) should be
written to a “0” level.
3. All register bits labeled “Write with 1" must be written to “1”
during initialization.
Byte 0: Control Register 0
Bit
Pin#
Name
Spread Select1
SEL2
Default
Description
See definition in Bit[0].
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
–
–
–
–
–
0
0
0
0
0
See Table 5.
See Table 5.
See Table 5.
SEL1
SEL0
FS_Override
0 = Select operating frequency by FS[4:0] input pins.
1 = Select operating frequency by SEL[4:0] settings.
Bit 2
Bit 1
Bit 0
–
–
–
SEL4
0
0
0
See Table 5.
See Table 5.
‘00’ = OFF.
SEL3
Spread Select0
‘01’ = – 0.5%.
‘10’ = 0.5%.
‘11’ = 0.25%.
Byte 1: Control Register 1
Bit
Bit 7
Pin#
6
Name
Default
Description
Latched FS4 input
Latched FS3 input
Latched FS2 input
Latched FS1 input
Latched FS0 input
CPU0
X
X
X
X
X
1
Latched FS[4:0] inputs. These bits are read-only.
Bit 6
7
Bit 5
46
25
26
44
43
–
Bit 4
Bit 3
Bit 2
(Active/Inactive).
(Active/Inactive).
Write with ‘1.’
Bit 1
CPU1
1
Bit 0
Vendor Test Mode
1
Byte 2: Control Register 2
Bit
Bit 7
Pin#
40
6
Name
SDRAM12
PCI0
Default
Description
(Active/Inactive).
1
1
1
1
1
1
1
1
Bit 6
(Active/Inactive).
Bit 5
13
12
11
10
9
PCI6
(Active/Inactive).
Bit 4
PCI5
(Active/Inactive).
Bit 3
PCI4
(Active/Inactive).
Bit 2
PCI3
(Active/Inactive).
Bit 1
PCI2
(Active/Inactive).
Bit 0
7
PCI1
(Active/Inactive).
Rev 1.0,November 20, 2006
Page 5 of 17
CY28316
Byte 3: Control Register 3
Bit
Pin#
Name
SDRAM8:11
SEL_48MHz
Default
Description
Bit 7
Bit 6
21, 20, 18, 17
–
1
0
(Active/Inactive).
0 = 24 MHz.
1 = 48 MHz.
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
26
48MHz
1
1
1
1
1
1
(Active/Inactive).
(Active/Inactive).
(Active/Inactive).
(Active/Inactive).
(Active/Inactive).
(Active/Inactive).
25
24_48MHz
SDRAM6:7
SDRAM4:5
SDRAM2:3
SDRAM0:1
29, 28
32, 31
35, 34
38, 37
Byte 4: Control Register 4
Bit
Bit 7
Pin#
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Default
Description
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
0
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte 5: Control Register 5
Bit
Bit 7
Pin#
–
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
REF1
Default
Description
0
0
0
0
0
0
1
1
Reserved.
Bit 6
–
Reserved.
Bit 5
–
Reserved.
Bit 4
–
Reserved.
Bit 3
–
Reserved.
Bit 2
–
Reserved.
Bit 1
46
47
(Active/Inactive).
(Active/Inactive).
Bit 0
REF0
Byte 6: Watchdog Timer Register
Bit
Name
PCI_Skew1
PCI_Skew0
Default
Pin Description
Bit 7
Bit 6
0
0
PCI skew control.
00 = Normal.
01 = –500 ps.
10 = Reserved.
11 = +500 ps.
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WD_TIMER4
WD_TIMER3
WD_TIMER2
WD_TIMER1
WD_TIMER0
1
1
1
1
1
0
These bits store the time-out value of the Watchdog Timer. The scale of the
timer is determined by the prescaler. The timer can support a value of 150 ms
to 4.8 sec when the prescaler is set to 150 ms. If the prescaler is set to 2.5 sec,
itcan support avaluefrom 2.5 sec to 80sec. When theWatchdogTimer reaches
“0,” it will set the WD_TO_STATUS bit and generate Reset if RST_EN_WD is
enabled.
WD_PRE_
SCALER
0 = 150 ms.
1 = 2.5 sec.
Rev 1.0,November 20, 2006
Page 6 of 17
CY28316
Byte 7: Control Register 7
Bit
Bit 7
Pin#
–
Name
Reserved
Default
Pin Description
0
1
1
0
0
0
0
0
Reserved.
Bit 6
25
26
–
24_48MHz_DRV
48MHz_DRV
Reserved
0 = Norm, 1 = High Drive.
0 = Norm, 1 = High Drive.
Reserved.
Bit 5
Bit 4
Bit 3
–
Reserved
Reserved.
Bit 2
–
Reserved
Reserved.
Bit 1
–
Reserved
Reserved.
Bit 0
–
Reserved
Reserved.
Byte 8: Vendor ID and Revision ID Register (Read Only)
Bit
Name
Revision_ID3
Revision_ID2
Revision_ID1
Revision_ID0
Vendor_ID3
Vendor_ID2
Vendor _ID1
Vendor _ID0
Default
Pin Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
1
0
0
0
Revision ID bit[3].
Revision ID bit[2].
Revision ID bit[1].
Revision ID bit[0].
Bit[3] of Cypress’s Vendor ID. This bit is read-only.
Bit[2] of Cypress’s Vendor ID. This bit is read-only.
Bit[1] of Cypress’s Vendor ID. This bit is read-only.
Bit[0] of Cypress’s Vendor ID. This bit is read-only.
Byte 9: System RESET and Watchdog Timer Register
Bit
Name
Default
Pin Description
SDRAM clock output drive strength.
0 = Normal.
Bit 7
Bit 6
SDRAM_DRV
0
1 = High Drive.
PCI_DRV
0
PCI clock output drive strength.
0 = Normal.
1 = High Drive.
Bit 5
Bit 4
Reserved
0
0
Reserved
RST_EN_WD
This bit will enable the generation of a Reset pulse when a Watchdog Timer
time-out occurs.
0 = Disabled.
1 = Enabled.
Bit 3
RST_EN_FC
0
This bit will enable the generation of a Reset pulse after a frequency change
occurs.
0 = Disabled.
1 = Enabled.
Bit 2
Bit 1
WD_TO_STATUS
WD_EN
0
0
Watchdog Timer Time-out Status bit.
0 = No time-out occurs (Read); Ignore (Write).
1 = Time-out occurred (Read); Clear WD_TO_STATUS (Write).
0 = Stop and reload Watchdog Timer. Unlock CY28316 from recovery frequency
mode.
1 = Enable Watchdog Timer. It will start counting down after a frequency change
occurs.
Note: CY28316 will generate a system Reset, reload a recovery frequency, and
lock itself into a recovery frequency mode after a Watchdog Timer time-out
occurs. Under recovery frequency mode, CY28316 will not respond to any
attempt to change output frequency via the SMBus control bytes. System
software can unlock CY28316 from its recovery frequency mode by clearing the
WD_EN bit.
Rev 1.0,November 20, 2006
Page 7 of 17
CY28316
Byte 9: System RESET and Watchdog Timer Register (continued)
Bit
Name
Default
Pin Description
CPU0:1 clock output drive strength.
0 = Normal.
Bit 0
CPU0:1_DRV
0
1 = High Drive.
Byte 10: Skew Control Register
Bit
Name
CPU0:1_Skew2
CPU0:1_Skew1
CPU0:1_Skew0
Default
Description
Bit 7
Bit 6
Bit 5
0
0
0
CPU0:1 output skew control.
000 = Normal.
001 = –150 ps.
010 = –300 ps.
011 = –450 ps.
100 = +150 ps.
101 = +300 ps.
110 = +450 ps.
111 = +600 ps.
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Byte 11: Recovery Frequency N-Value Register
Bit
Name
Default
Pin Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ROCV_FREQ_N7
ROCV_FREQ_N6
ROCV_FREQ_N5
ROCV_FREQ_N4
ROCV_FREQ_N3
ROCV_FREQ_N2
ROCV_FREQ_N1
ROCV_FREQ_N0
0
0
0
0
0
0
0
0
If ROCV_FREQ_SEL is set, CY28316 will use the values programmed in
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery
CPU output frequency when a Watchdog Timer time-out occurs. The setting
of FS_Override bit determines the frequency ratio for CPU and PCI. When it
is cleared, CY28316 will use the same frequency ratio stated in the Latched
FS[4:0] register. When it is set, CY28316 will use the frequency ratio stated in
the SEL[4:0] register. CY28316 supports programmable CPU frequencies
ranging from 50 MHz to 248 MHz. CY28316 will change the output frequency
whenever there is an update to either ROCV_FREQ_N[7:0] or
ROCV_FREQ_M[6:0]. Therefore it is recommended to use word or block Write
to update both registers within the same SMBus bus operation.
Byte 12: Recovery Frequency M-Value Register
Bit
Name
Default
Pin Description
Bit 7
ROCV_FREQ_SEL
0
ROCV_FREQ_SEL determines the source of the recover frequency when a
Watchdog Timer time-out occurs. The clock generator will automatically switch
to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL.
0 = From latched FS[4:0].
1 = From the settings of ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0].
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ROCV_FREQ_M6
ROCV_FREQ_M5
ROCV_FREQ_M4
ROCV_FREQ_M3
ROCV_FREQ_M2
ROCV_FREQ_M1
ROCV_FREQ_M0
0
0
0
0
0
0
0
If ROCV_FREQ_SEL is set, CY28316 will use the values programmed in
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery
CPU output frequency when a Watchdog Timer time-out occurs. The setting
of the FS_Override bit determines the frequency ratio for CPU, SDRAM, and
PCI. When it is cleared, CY28316 will use the same frequency ratio stated in
the Latched FS[4:0] register. When it is set, CY28316 will use the frequency
ratio stated in the SEL[4:0] register. CY28316 supports programmable CPU
frequencies ranging from 50 MHz to 248 MHz. CY28316 will change the output
frequency whenever there is an update to either ROCV_FREQ_N[7:0] or
ROCV_FREQ_M[6:0]. Therefore, itis recommendedtousewordor block Write
to update both registers within the same SMBus bus operation.
Rev 1.0,November 20, 2006
Page 8 of 17
CY28316
Byte 13: Programmable Frequency Select N-Value Register
Bit
Name
Default
Pin Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPU_FSEL_N7
CPU_FSEL_N6
CPU_FSEL_N5
CPU_FSEL_N4
CPU_FSEL_N3
CPU_FSEL_N2
CPU_FSEL_N1
CPU_FSEL_N0
0
0
0
0
0
0
0
0
If Prog_Freq_EN is set, CY28316 will use the values programmed in
CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output
frequency. The new frequency will start to load whenever CPU_FSELM[6:0]
is updated. The setting of the FS_Override bit determines the frequency ratio
for CPU, SDRAM, and PCI. When it is cleared, CY28316 will use the same
frequency ratio stated in the Latched FS[4:0] register. When it is set, CY28316
will use the frequency ratio stated in the SEL[4:0] register. CY28316 supports
programmable CPU frequencies ranging from 50 MHz to 248 MHz.
Byte 14: Programmable Frequency Select M-Value Register
Bit
Name
Default
Description
Bit 7
Pro_Freq_EN
0
Programmable output frequencies enabled.
0 = Disabled.
1 = Enabled.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPU_FSEL_M6
CPU_FSEL_M5
CPU_FSEL_M4
CPU_FSEL_M3
CPU_FSEL_M2
CPU_FSEL_M1
CPU_FSEL_M0
0
0
0
0
0
0
0
If Prog_Freq_EN is set, CY28316 will use the values programmed in
CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output
frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is
updated. The setting of the FS_Override bit determines the frequency ratio for
CPU, SDRAM, and PCI. When it is cleared, CY28316 will use the same
frequency ratio stated in the Latched FS[4:0] register. When it is set, CY28316
will use the frequency ratio stated in the SEL[4:0] register. CY28316 supports
programmable CPU frequencies ranging from 50 MHz to 248 MHz.
Byte 15: Reserved Register
Bit Pin#
Name
Reserved
Default
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
–
–
–
–
–
–
–
–
0
0
0
0
0
0
1
1
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved
Reserved
Reserved
Reserved
Vendor test mode
Vendor test mode
Vendor test mode
Reserved. Write with ‘0.’
Test mode. Write with ‘1.’
Test mode. Write with ‘1.’
Byte 16: Reserved Register
Bit
Pin#
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Default
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
–
–
–
–
–
–
–
0
0
0
0
0
0
0
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Byte 17: Reserved Register
Bit Pin#
Name
Reserved
Reserved
Default
Description
Bit 7
Bit 6
–
–
0
0
Reserved.
Reserved.
Rev 1.0,November 20, 2006
Page 9 of 17
CY28316
Byte 17: Reserved Register (continued)
Bit
Pin#
Name
Reserved
Default
Description
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
–
–
–
–
-
0
0
0
0
0
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved
Reserved
Reserved
Reserved
Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes
Input Conditions
Output Frequency
FS4
SEL4
0
FS3
SEL3
0
FS2
SEL2
0
FS1
SEL1
0
FS0
SEL0
0
PLL Gear
Constant (G)
CPU
200.0
190.0
180.0
170.0
166.0
160.0
150.0
145.0
140.0
136.0
130.0
124.0
67.2
PCI
33.3
38.0
36.0
34.0
33.2
32.0
37.5
36.3
35.0
34.0
32.5
31.0
33.6
33.6
39.3
33.6
33.5
33.5
38.3
33.5
33.4
33.4
36.7
33.4
35.0
30.0
28.3
39.0
33.3
33.3
37.5
33.3
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
100.8
118.0
134.4
67.0
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
100.5
115.0
134.0
66.8
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
100.2
110.0
133.6
105.0
90.0
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
85.0
1
1
0
1
1
78.0
1
1
1
0
0
66.6
1
1
1
0
1
100.0
75.0
1
1
1
1
0
1
1
1
1
1
133.3
Rev 1.0,November 20, 2006
Page 10 of 17
CY28316
Programmable Output Frequency, Watchdog Timer,
and Recovery Output Frequency
Functional Description
The Programmable Output Frequency feature allows users to
generate any CPU output frequency in the range of 50 MHz to
248 MHz. Cypress offers the most dynamic and the simplest
programming interface for system developers to utilize this
feature in their platforms.
when the system hangs or gets unstable. System BIOS or
other control software can enable the Watchdog Timer before
it attempts to make a frequency change. If the system hangs
and a Watchdog Timer time-out occurs, a system reset will be
generated and a recovery frequency will be activated.
The Watchdog Timer and Recovery Output Frequency
features allow users to implement a recovery mechanism
Table 6. Register Summary
All the related registers are summarized in Table 6.
Name
Description
Pro_Freq_EN
Programmable output frequencies enabled.
0 = Disabled (default).
1 = Enabled.
When it is disabled, the operating output frequency will be determined by either the latched value of
FS[4:0] inputs or the programmed value of SEL[4:0]. If FS_Override bit is clear, latched FS[4:0] inputs
will be used. If the FS_Override bit is set, the programmed value of SEL[4:0] will be used. When it is
enabled, the CPU output frequency will be determined by the programmed value of CPUFSEL_N,
CPUFSEL_M, and the PLL Gear Constant. The program value of FS_Override, SEL[4:0] or the latched
value of FS[4:0] will determine the PLL Gear Constant and the frequency ratio between CPU and other
frequency outputs.
FS_Override
When Pro_Freq_EN is cleared or disabled,
0 = Select operating frequency by FS input pins (default).
1 = Select operating frequency by SEL bits in SMBus control bytes.
When Pro_Freq_EN is set or enabled,
0 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are
based on the latched value of FS input pins (default).
1 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are
based on the programmed value of SEL bits in SMBus control bytes.
CPU_FSEL_N,
CPU_FSEL_M
When Prog_Freq_EN is set or enabled, the values programmed in CPU_FSEL_N[7:0] and
CPU_FSEL_M[6:0] determine the CPU output frequency. The new frequency will start to load whenever
there is an update to either CPU_FSEL_N[7:0] or CPU_FSEL_M[6:0]. Therefore, it is recommended
to use word or block Write to update both registers within the same SMBus bus operation. The setting
of the FS_Override bit determines the frequency ratio for CPU and PCI. When FS_Override is cleared
or disabled, the frequency ratio follows the latched value of the FS input pins. When FS_Override is
set or enabled, the frequency ratio follows the programmed value of SEL bits in SMBus control bytes.
ROCV_FREQ_SEL
ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog Timer time-out
occurs. The clock generator will automatically switch to the recovery CPU frequency based on the
selection on ROCV_FREQ_SEL.
0 = From latched FS[4:0].
1 = From the settings of ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0].
ROCV_FREQ_N[7:0], When ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and
ROCV_FREQ_M[6:0] ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency when a Watchdog
Timer time-out occurs. The setting of the FS_Override bit determines the frequency ratio for CPU and
SDRAM. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be
used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. The new frequency
will start to load whenever there is an update to either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0].
Therefore, it is recommended to use word or block Write to update both registers within the same
SMBus bus operation.
WD_EN
0 = Stop and reload Watchdog Timer. Unlock CY28316 from recovery frequency mode.
1 = Enable Watchdog Timer. It will start counting down after a frequency change occurs.
Note: CY28316 will generate system reset, reload a recovery frequency, and lock itself into a recovery
frequency mode after a Watchdog Timer time-out occurs. Under recovery frequency mode, CY28316
will not respond to any attempt to change output frequency via the SMBus control bytes. System
software can unlock CY28316 from its recovery frequency mode by clearing the WD_EN bit.
WD_TO_STATUS
Watchdog Timer Time-out Status bit.
0 = No time-out occurs (Read); Ignore (Write).
1 = Time-out occurred (Read); Clear WD_TO_STATUS (Write).
Rev 1.0,November 20, 2006
Page 11 of 17
CY28316
Table 6. Register Summary
Name
Description
WD_TIMER[4:0]
These bits store the time-out value of the Watchdog Timer. The scale of the timer is determine by the
prescaler. The timer can support a value of 150 ms to 4.8 sec when the prescaler is set to 150 ms. If
the prescaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. When the Watchdog Timer
reaches “0,” it will set the WD_TO_STATUS bit.
WD_PRE_SCALER
RST_EN_WD
0 = 150 ms.
1 = 2.5 sec.
This bit will enable the generation of a Reset pulse when a watchdog timer time-out occurs.
0 = Disabled.
1 = Enabled.
RST_EN_FC
This bit will enable the generation of a Reset pulse after a frequency change occurs.
0 = Disabled.
1 = Enabled.
How to Program CPU Output Frequency?
When the programmable output frequency feature is enabled
(Pro_Freq_EN bit is set), the CPU output frequency is deter-
mined by the following equation:
The ratio of (N+3) and (M+3) needs to be greater than “1”
[(N+3)/(M+3) > 1].
Table lists set of N and M values for different frequency output
ranges. This example uses a fixed value for the M-Value
Register and selects the CPU output frequency by changing
the value of the N-Value Register.
Fcpu = G * (N+3)/(M+3).
“N” and “M” are the values programmed in the Programmable
Frequency Select N-Value Register and M-Value Register,
respectively.
“G” stands for the PLL Gear Constant, which is determined by
the programmed value of FS[4:0] or SEL[4:0]. The value is
listed in Table 3.
Table 7. Examples of N and M Value for Different CPU Frequency Range
Fixed Value for
Range of N-Value Register
for Different CPU Frequency
Frequency Ranges
50 MHz – 129 MHz
130 MHz – 248 MHz
Gear Constants
M-Value Register
48.00741
93
45
97–255
48.00741
127–245
Rev 1.0,November 20, 2006
Page 12 of 17
CY28316
Absolute Maximum Ratings[2.]
Stresses greater than those listed in this table may cause
permanent damage to the device. These represent a stress
rating only. Operation of the device at these or any other condi-
tions above those specified in the operating sections of this
specification is not implied. Maximum conditions for extended
periods may affect reliability.
Parameter
DD, VIN
TSTG
TB
Description
Voltage on any pin with respect to GND
Storage Temperature
Rating
–0.5 to +7.0
–65 to +150
–55 to +125
0 to +70
Unit
V
V
°C
°C
°C
kV
Ambient Temperature under Bias
Operating Temperature
TA
ESDPROT
Input ESD Protection
2 (min.)
DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V 5%[3]
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Supply Current
IDD
IDD
Logic Inputs
3.3V Supply Current
260
25
mA
mA
2.5V Supply Current
VIL
VIH
IIL
Input Low Voltage
Input High Voltage
Input Low Current[4]
Input High Current[4]
GND – 0.3
2.0
0.8
VDD + 0.3
–25
V
V
µA
µA
IIH
10
Clock Outputs
VOL
VOH
IOL
Output Low Voltage
Output High Voltage
Output Low Current PCI
REF
IOL = 1 mA
50
mV
V
IOH = –1 mA
VOL = 1.5V
3.1
70
50
50
50
70
70
50
50
50
70
110
70
135
100
100
100
135
135
100
100
100
135
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
OL = 1.5V
48 MHz
VOL = 1.5V
70
24 MHz
SDRAM
V
V
OL = 1.5V
OL = 1.5V
70
110
110
70
IOH
Output High Current PCI
VOH = 1.5V
REF
V
V
V
V
OH = 1.5V
OH = 1.5V
OH = 1.5V
OH = 1.5V
48 MHz
24 MHz
SDRAM
70
70
110
Crystal Oscillator
VTH
X1 Input Threshold Voltage[5]
VDDQ3 = 3.3V
1.65
18
V
CLOAD
Load Capacitance, Imposed on External
Crystal[6]
pF
CIN,X1
X1 Input Capacitance[7]
Pin X2 unconnected
Except X1 and X2
TBD
pF
Pin Capacitance/Inductance
CIN Input Pin Capacitance
5
6
7
pF
pF
nH
COUT
Output Pin Capacitance
Input Pin Inductance
LIN
Notes:
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. All clock outputs loaded with 6" 60: transmission lines with 20-pF capacitors.
4. CY28316 logic inputs (except FS3) have internal pull-up devices (pull-ups not full CMOS level). Logic input FS3 has an internal pull-down device.
5. X1 input threshold voltage (typical) is V /2.
DD
6. The CY28316 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. The total load placed on the crystal
is 18 pF; this includes typical stray capacitance of short PCB traces to the crystal.
7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
Rev 1.0,November 20, 2006
Page 13 of 17
CY28316
AC Electrical Characteristics (TA = 0°C to +70°C, VDDQ3 = 3.3V 5%, fXTL = 14.31818 MHz)
AC clock parameters are tested and guaranteed over stated
operating conditions using the stated lump capacitive load at
the clock output; Spread Spectrum is disabled.
CPU Clock Outputs (CPUT0, CPUC0, CPU_CS)[8]
CPU = 100 MHz
CPU = 133 MHz
Parameter
tR
Description
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Min. Typ. Max. Min. Typ. Max. Unit
1.0
1.0
45
4.0
4.0
55
1.0
1.0
45
4.0 V/ns
4.0 V/ns
tF
tD
Measured at 50% point
55
%
ps
tJC
fST
Jitter, Cycle to Cycle
375
375
Frequency Stabilization Assumes full supply voltage reached
3
3
ms
from Power-up (cold
start)
within 1 ms from power-up. Short
cycles exist prior to frequency
stabilization.
Zo
AC Output Impedance VO = VX
50
50
:
PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 20 pF)
Parameter Description Test Condition/Comments
tP Measured on the rising edge at 1.5V
Min. Typ. Max. Unit
Period
30
12
12
1
ns
ns
tH
tL
High Time
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
Low Time
ns
tR
tF
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
4
4
V/ns
V/ns
%
Measured from 2.4V to 0.4V
1
tD
tJC
Measured on the rising and falling edges at 1.5V
45
55
Jitter, Cycle-to-Cycle
Measured on the rising edge at 1.5V. Maximum difference of
cycle time between two adjacent cycles.
250 ps
tSK
tO
Output Skew
Measured on the rising edge at 1.5V
500 ps
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on the rising edge at 1.5
1.5V. CPU leads PCI output.
4
3
ns
ms
:
fST
Zo
Frequency Stabilization Assumes full supply voltage reached within 1 ms from
from Power-up (cold start) power-up. Short cycles exist prior to frequency stabilization.
AC Output Impedance
Average value during switching transition. Used for deter-
mining series termination value.
30
REF0:1 Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Frequency generated by the crystal oscillator
Measured from 0.4V to 2.4V
Min.
Typ.
Max. Unit
f
14.318
MHz
tR
0.5
0.5
2
2
V/ns
V/ns
%
tF
Measured from 2.4V to 0.4V
tD
Measured on the rising and falling edges at 1.5V 45
55
3
fST
Frequency Stabilization from Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to
frequency stabilization.
ms
Power-up (cold start)
AC Output Impedance
Zo
Average value during switching transition. Used
for determining series termination value.
40
:
Note:
8. Refer to Figure 1 for K7 operation clock driver test circuit.
Rev 1.0,November 20, 2006
Page 14 of 17
CY28316
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Frequency, Actual
Deviation from 48 MHz
PLL Ratio
Test Condition/Comments
Determined by PLL divider ratio (see m/n below)
(48.008 – 48)/48
Min.
Typ.
48.008
+167
Max. Unit
MHz
f
fD
ppm
m/n
tR
(14.31818 MHz × 57/17 = 48.008 MHz)
Measured from 0.4V to 2.4V
57/17
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
0.5
0.5
45
2
2
V/ns
V/ns
%
tF
Measured from 2.4V to 0.4V
tD
Measured on the rising and falling edges at 1.5V
Assumes full supply voltage reached within 1 ms
55
3
fST
Frequency Stabilization
ms
from Power-up (cold start) from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
40
:
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Frequency, Actual
Deviation from 24 MHz
PLL Ratio
Test Condition/Comments
Determined by PLL divider ratio (see m/n below)
(24.004 – 24)/24
Min.
Typ.
24.004
+167
Max. Unit
MHz
f
fD
ppm
m/n
tR
(14.31818 MHz × 57/34 = 24.004 MHz)
Measured from 0.4V to 2.4V
57/34
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
0.5
0.5
45
2
2
V/ns
V/ns
%
tF
Measured from 2.4V to 0.4V
tD
Measured on the rising and falling edges at 1.5V
55
3
fST
Frequency Stabilization
Assumes full supply voltage reached within 1 ms
ms
from Power-up (cold start) from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
40
:
Rev 1.0,November 20, 2006
Page 15 of 17
CY28316
Layout Diagram
+2.5V Supply
FB
+3.3V Supply
FB
VDDQ3
10 PF
0.005 PF
10 PF
0.005 PF
C3
C4
C3
C4
G
G
G
G
G
V
DDQ3
Core
V
1
2
3
4
48
47
46
45
G
G
G
G
G
G
V
5
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
V
G
G
G
G
G
G
V
G
G
G
G
V
G
G
G
G
V
G
V
G
G
G
G
G
21
22
23
24
28
27
26
25
V
G
G
G
FB = Dale ILB1206 - 300 (300:ꢀ@ 100 MHz) or TDK ACB2012L-120
PF C6 = 0.01 PF
PF C4 = 0.005
Ceramic Caps C3 = 10–22
= VIA to GND plane layer
V =VIA to respective supply plane layer
G
Note: Each supply plane or strip should have a ferrite bead and capacitors
Rev 1.0,November 20, 2006
Page 16 of 17
CY28316
Ordering Information
Ordering Code
CY28316PVC
Package Type
48-pin SSOP (300 mils)
48-pin SSOP (300 mils) – Tape and Reel
Operating Range
Commercial, 0°C to +70°C
Commercial, 0°C to +70°C
CY28316PVCT
Package Drawing and Dimensions
48-lead Shrunk Small Outline Package O48
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir-
cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in
normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica-
tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional
processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any
circuitry or specification without notice.
Rev 1.0, November 20, 2006
Page 17 of 17
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