C8051F220-GQ [SILICON]
Microcontroller, 8-Bit, FLASH, 25MHz, CMOS, PQFP48, ROHS COMPLIANT, TQFP-48;![C8051F220-GQ](http://pdffile.icpdf.com/pdf2/p00278/img/icpdf/C8051F220-GQ_1661613_icpdf.jpg)
型号: | C8051F220-GQ |
厂家: | ![]() |
描述: | Microcontroller, 8-Bit, FLASH, 25MHz, CMOS, PQFP48, ROHS COMPLIANT, TQFP-48 时钟 微控制器 外围集成电路 |
文件: | 总2页 (文件大小:406K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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C8051F220
25 MIPS, 8 kB Flash, 8-Bit ADC, 48-Pin Mixed-Signal MCU
Analog Peripherals
High-Speed 8051 µC Core
8-Bit ADC
-
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
-
-
-
-
-
-
±1/2 LSB INL; no missing codes
Programmable throughput up to 100 ksps
-
Up to 25 MIPS throughput with 25 MHz system clock
Expanded interrupt handler; up to 21 interrupt sources
-
32 external inputs (each port I/O can be configured as an ADC input on-
the-fly)
Memory
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
-
-
256 bytes data RAM
Data-dependent windowed interrupt generator
8 kB Flash; in-system programmable in 512 byte sectors (512 bytes are
V
from external pin or V
TwoRcEoFmparators
DD
reserved)
Digital Peripherals
-
Programmable hysteresis
Configurable to generate interrupts or reset
-
-
-
-
32 port I/O; all are 5 V tolerant
Hardware SPI™ and UART serial ports available concurrently
3 general-purpose 16-bit counter/timers
-
VDD Monitor and Brown-out Detector
On-Chip JTAG Debug
Dedicated watchdog timer; bidirectional reset
-
-
-
-
On-chip emulation circuitry facilitates full-speed, non-intrusive, in-circuit
emulation
Supports breakpoints, single stepping, watchpoints, inspect/modify
memory, and registers
Clock Sources
-
-
-
Internal programmable oscillator: 2–16 MHz
External oscillator: Crystal, RC, C, or Clock
Can switch between clock sources on-the-fly
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
Fully compliant with IEEE 1149.1 specification
Supply Voltage: 2.7 to 3.6 V
-
Typical operating current: 9 mA at 25 MHz
Typical stop mode current: <0.1 uA
-
48-Pin TQFP
- Temperature Range: –40 to +85 °C
VDD
VDD
Analog/Digital
Power
P0.0/TX
Port 0
P
0
P0.1/RX
P0.2//INT0
P0.3//INT1
P0.4/T0
Latch
UART
P
0
GND
GND
NC
NC
NC
D
r
P0.5/T1
M
U
X
Timer 0
Timer 1
Timer 2
P0.6/T2
v
P0.7/T2EX
Port 1
Latch
P1.0/CP0+
P1.1/CP0-
P1.2/CP0
P1.3/CP1+
P1.4/CP1-
P1.5/CP1
P1.6/SYSCLK
P1.7
TCK
TMS
TDI
8 kB FLASH
P
1
8
0
5
1
JTAG
Logic
P
1
Debug HW
WDT
CP0+
CP0-
CP0
TDO
CP0
CP1
256 byte
RAM
D
r
Reset
M
U
X
RST
CP1+
CP1-
v
CP1
VDD
SYSCLK
MONEN
Monitor
P2.0/NSS
P2.1/MISO
P2.2/MOSI
P2.3/SCK
P2.4
C
o
r
P
2
P
2
Port 2
External
Oscillator
Circuit
XTAL1
XTAL2
SFR Bus
Latch
SPI
System Clock
D
r
M
U
X
P2.5
P2.6
e
Internal
v
P2.7
Oscillator
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P
3
Port 3
Latch
D
r
v
A
M
U
X
8-bit
AIN0-AIN31
PGA
100 ksps
ADC
VDD
VREF
General Purpose
Copyright © 2004 by Silicon Laboratories
6.15.2004
C8051F220
25 MIPS, 8 kB Flash, 8-Bit ADC, 48-Pin Mixed-Signal MCU
Selected Electrical Specifications
(TA = –40 to +85 C°, VDD = 2.7 V unless otherwise specified unless otherwise specified)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
GLOBAL CHARACTERISTICS
Digital Supply Voltage
2.7
3.6
V
Digital Supply Current
with CPU active
Clock = 25 MHz
Clock = 1 MHz
9
0.4
11
7
mA
mA
µA
µA
Clock = 32 kHz; VDD Monitor Disabled
Oscillator not running; VDD Monitor
Enabled
Digital Supply Current
(shutdown)
Oscillator not running; VDD Monitor
Disabled
0.1
1.5
µA
V
Digital Supply RAM Data
Retention Voltage
CPU & DIGITAL I/O PORTS
Clock Frequency Range
Port Output High Voltage
Port Output Low Voltage
Input High Voltage
DC
25
MHz
V
IOH = –3 mA, Port I/O push-pull
IOL = 8.5 mA
VDD – 0.7
0.6
V
0.7 x VDD
V
Input Low Voltage
0.3 x VDD
fCLK/2
V
SPI Bus Clock Frequency fCLK=MCU Clock; SPI in Master
MHz
Mode
A/D CONVERTER
Resolution
8
bits
LSB
LSB
dB
Integral Nonlinearity
±1/2
±1/4
Differential Nonlinearity
Signal to Noise Ratio
Throughput Rate
Guaranteed Monotonic
| CP+ – CP- | = 100 mV
49
100
ksps
V
Input Voltage Range
COMPARATORS
Response Time
0
VREF
4
µs
V
Input Voltage Range
Input Bias Current
Input Offset Voltage
–0.25
–5
VDD + 0.25
+5
0.001
nA
mV
–10
+10
C8051F226DK Development Kit
Package Information
D
MIN NOM MAX
(mm) (mm) (mm)
D1
A
-
-
-
1.20
0.15
A1 0.05
E1
E
A2 0.95 1.00 1.05
b
D
0.17 0.22 0.27
-
-
-
-
-
9.00
7.00
0.50
9.00
7.00
-
-
-
-
-
48
D1
e
PIN 1
IDENTIFIER
1
e
A2
E
A
E1
A1
b
General Purpose
Copyright © 2004 by Silicon Laboratories
6.15.2004
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders
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