598AAA000118DGR [SILICON]
LVPECL Output Clock Oscillator,;
| 型号： | 598AAA000118DGR |
| 厂家： | 
SILICON |
| 描述： | LVPECL Output Clock Oscillator, 振荡器 |
| 文件： | 总27页 (文件大小：532K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si598/Si599
10–810 MHZ I2C PROGRAMMABLE XO/VCXO
Features
Programmable with 28 parts per
trillion frequency resolution
Integrated crystal provides stability
and low phase noise
Frequency changes up to
±3500 ppm are glitchless
I2C programmable output
frequencies from 10 to 810 MHz
0.5 ps RMS phase jitter
Superior power supply rejection:
0.3–0.4 ps additive jitter
Available LVPECL, CMOS, LVDS,
and CML outputs
1.8, 2.5, or 3.3 V supply
Pin- and register-compatible with
Si570/571
–40 to 85 °C operation
Industry-standard 5x7 mm package
Applications
Ordering Information:
See page 21.
SONET / SDH / xDSL
Ethernet / Fibre Channel
3G SDI / HD SDI
Multi-rate PLLs
Multi-rate reference clocks
Frequency margining
Digital PLLs
CPU / FPGA FIFO control
Adaptive synchronization
Agile RF local oscillators
Pin Assignments:
See page 20.
Description
(Top View)
The Si598 XO/Si599 VCXO utilizes Silicon Laboratories' advanced DSPLL®
circuitry to provide a low-jitter clock at any frequency. They are user-
programmable to any output frequency from 10 to 810 MHz with 28 parts per
SDA
7
NC
VDD
1
2
3
6
5
4
2
trillion (PPT) resolution. The device is programmed via a 2-pin I C compatible
serial interface. The wide frequency range and ultra-fine programming resolution
make these devices ideal for applications that require in-circuit dynamic frequency
adjustments or multi-rate operation with non-integer related rates. Using an
integrated crystal, these devices provide stable low jitter frequency synthesis and
replace multiple XOs, clock generators, and DAC controlled VCXOs.
OE
CLK–
CLK+
GND
8
Functional Block Diagram
SCL
Si598
VDD
Power Supply Filtering
OE
SDA
7
Fixed
Frequency
Oscillator
Any Frequency
DSPLL®
10 to 810 MHz
Clock Synthesis
CLK+
CLK–
VC
VDD
1
2
3
6
5
4
OE
CLK–
CLK+
Vc
ADC
I2C Interface
(Si599)
GND
8
SCL
SDA
SCL
GND
Si599
Rev. 1.1 6/18
Copyright © 2018 by Silicon Laboratories
Si598/Si599
Si598/Si599
TABLE OF CONTENTS
Section
Page
1. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.1. Programming a New Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2
3.2. I C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4. Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5. Si598 (XO) Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
6. Si599 (VCXO) Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
7. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
8. Si59x Mark Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
9. Outline Diagram and Suggested Pad Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
10. 8-Pin PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Rev. 1.1
2
Si598/Si599
1. Detailed Block Diagrams
VDD
GND
fXTAL
M
CLKOUT+
CLKOUT–
DCO
÷HS_DIV
÷N1
fosc
RFREQ
OE
Control
Interface
SDA
SCL
NVM
RAM
Figure 1. Si598 Detailed Block Diagram
VDD
GND
fXTAL
M
CLKOUT+
CLKOUT–
ADC
VC
DCO
÷HS_DIV
÷N1
+
fosc
VCADC
RFREQ
OE
SDA
SCL
Control
Interface
NVM
RAM
Figure 2. Si599 Detailed Block Diagram
Rev. 1.1
3
Si598/Si599
2. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
3.3 V option
2.5 V option
1.8 V option
Min
2.97
2.25
1.71
Typ
3.3
2.5
1.8
Max
3.63
2.75
1.89
Units
V
V
V
Supply Voltage1
VDD
Output enabled
LVPECL
CML
—
—
—
—
130
120
110
100
120
108
99
mA
mA
mA
mA
Supply Current
IDD
LVDS
CMOS
90
Tristate mode
—
0.75 x VDD
—
60
—
—
75
—
mA
V
Output Enable (OE)2,
Serial Data (SDA),
Serial Clock (SCL)
VIH
VIL
0.5
V
Operating Temperature Range
TA
–40
—
85
ºC
Notes:
1. Selectable parameter specified by part number. See Section 7. Ordering Information on page 21 for further details.
2. OE pin includes a 17 k pullup resistor to VDD for OE Active High Option. OE pin includes 17 kpull down for OE
Active Low. See Section “7.Ordering Information”.
Table 2. VC Control Voltage Input (Si599)
(Typical values TA = 25 ºC, VDD = 3.3 V, min/max limits VDD = 1.8 ±5%, 2.5 or 3.3 V ±10%, TA = –40 to 85 ºC unless otherwise
noted)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Control Voltage Tuning Slope1,2,3
KV
10 to 90% of VDD
—
—
—
—
—
45
95
125
185
380
—
—
—
—
—
ppm/V
ppm/V
ppm/V
ppm/V
ppm/V
Control Voltage Linearity4
LVC
BSL
–5
–10
9.3
500
—
±1
±5
+5
+10
10.7
—
%
%
Incremental
Modulation Bandwidth
VC Input Impedance
VC Input Capacitance
Nominal Control Voltage
BW
ZVC
10.0
—
kHz
k
pF
V
CVC
50
—
VCNOM
VC
@ fO
—
VDD/2
—
—
Control Voltage Tuning Range
0
VDD
V
Notes:
1. Positive slope; selectable option by part number. See 7. Ordering Information on page 21.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. KV variation is ±10% of typical values.
4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope
determined with VC ranging from 10 to 90% of VDD
.
4
Rev. 1.1
Si598/Si599
Table 3. CLK± Output Frequency Characteristics
(Typical values TA = 25 ºC, VDD= 3.3 V, min/max limits VDD = 1.8 ±5%, 2.5 or 3.3 V ±10%, TA = –40 to 85 ºC unless otherwise
noted)
Parameter
Symbol
Test Condition
LVPECL/LVDS/CML
CMOS
Min
10
10
—
Typ
—
Max
810
160
±30
Units
MHz
MHz
ppm
ppm
ppm
Programmable Frequency
Range1,2,3
fO
—
Temp stability = ±20 ppm
Temp stability = ±25 ppm
Temp stability = ±50 ppm
—
1,2,4,5
Total Stability (Si598)
—
—
±50
—
—
±100
–20
–50
—
—
+20
+50
Temperature Stability (Si599)1,5
Absolute Pull Range1,5 (Si599)
TA = –40 to +85 ºC
ppm
APR
tOSC
±10
—
—
—
±370
10
ppm
ms
Powerup Time6
Notes:
1. See Section 7. Ordering Information on page 21 for further details.
2. Specified at time of order by part number. Three frequency grades are available:
Grade A covers 10 to 810 MHz.
Grade B covers 10 to 280 MHz.
Grade C covers 10 to 160 MHz.
3. Nominal output frequency set by VCNOM = 1/2 x VDD
.
4. Includes initial accuracy, temperature drift, shock, vibration, power supply and load drift. ±100 ppm and ±50 ppm
options include 15 years aging at 70 °C. ±30 ppm option includes 10 years aging at 40 °C.
5. Selectable parameter specified by part number. See 7. Ordering Information on page 21.
6. Time from power up or tristate mode to fO.
Rev. 1.1
5
Si598/Si599
Table 4. CLK± Output Levels and Symmetry
(Typical values TA = 25 ºC, VDD = 3.3 V, min/max limits VDD = 1.8 ±5%, 2.5 or 3.3 V ±10%, TA = –40 to 85 ºC unless otherwise
noted)
Parameter
Symbol
VO
Test Condition
mid-level
Min
VDD – 1.42
1.1
Typ
—
Max
VDD – 1.25
1.9
Units
V
LVPECL Output Option1
VOD
VSE
swing (diff)
—
VPP
VPP
swing (single-ended)
mid-level
0.55
—
0.95
VO
1.125
0.5
1.20
0.7
1.275
0.9
V
LVDS Output Option2
CML Output Option2
swing (diff)
VOD
VO
VPP
2.5/3.3 V option mid-level
1.8 V option mid-level
2.5/3.3 V option swing (diff)
1.8 V option swing (diff)
IOH = 32 mA
—
—
VDD – 1.30
—
—
V
V
VDD – 0.36
1.10
0.35
0.8 x VDD
—
1.50
0.425
—
1.90
0.50
VDD
0.4
350
—
VPP
VPP
V
VOD
VOH
VOL
CMOS Output Option3
IOL = 32 mA
—
V
LVPECL/LVDS/CML
CMOS with CL = 15 pF
—
—
ps
ns
t
R, tF
Rise/Fall Time (20/80 %)
—
1
LVPECL:
LVDS:
CMOS:
V
DD – 1.3 V (diff)
1.25 V (diff)
DD/2
SYM
48
—
52
%
Symmetry (duty cycle)
V
Notes:
1. 50 to VDD – 2.0 V.
2. Rterm = 100 (differential).
3. CL = 15 pF sinking or sourcing 12 mA for VDD = 3.3 V, 6 mA for VDD = 2.5 V, 3 mA for VDD = 1.8 V.
6
Rev. 1.1
Si598/Si599
Table 5. CLK± Output Phase Jitter (Si598)
(Typical values TA = 25 ºC, VDD = 3.3 V, min/max limits VDD = 1.8 ±5%, 2.5 or 3.3 V ±10%, TA = –40 to 85 ºC unless otherwise
noted)
Parameter
Symbol
Test Condition
LVPECL/LVDS/CML1
CMOS 3.3 V2
Min
—
—
—
—
—
—
—
—
Typ
0.5
0.6
0.3
0.5
0.5
0.6
0.5
0.5
Max Units
Phase Jitter (RMS Random)
12 kHz to 20 MHz Integration Bandwidth
—
—
—
—
1
ps
ps
ps
ps
ps
ps
ps
ps
φJ-RANDOM
Phase Jitter (RMS Random)
1.875 to 20 MHz Integration Bandwidth
LVPECL/LVDS/CML1
CMOS 3.3 V2
Phase Jitter (RMS)
12 kHz to 20 MHz Integration Bandwidth
LVPECL/LVDS/CML1
CMOS 3.3 V2
1
φJ
Phase Jitter (RMS)
1.875 to 20 MHz Integration Bandwidth
LVPECL/LVDS/CML1
CMOS 3.3 V2
—
—
Notes:
1. 50 to 810 MHz, 3.3 V/2.5 V only.
2. 50 to 160 MHz, single-ended CMOS output phase jitter measured using 33 series termination into 50 phase noise
test equipment. 3.3 V supply voltage option only.
Table 6. CLK± Output Phase Jitter (Si599)
(Typical values TA = 25 ºC, VDD = 3.3 V, min/max limits VDD = 1.8 ±5%, 2.5 or 3.3 V ±10%, TA = –40 to 85 ºC unless otherwise
noted)
Parameter
Symbol
Test Condition
Kv = 45 ppm/V
Min
—
Typ
0.5
0.5
0.5
0.5
0.7
Max
—
Units
Phase Jitter (RMS)1,2
for FOUT of 50 MHz < FOUT
810 MHz
J
ps
12 kHz to 20 MHz
Kv = 95 ppm/V
ps
ps
ps
ps
12 kHz to 20 MHz
—
—
Kv = 125 ppm/V
12 kHz to 20 MHz
—
—
Kv = 185 ppm/V
12 kHz to 20 MHz
—
—
Kv = 380 ppm/V
12 kHz to 20 MHz
—
—
Notes:
1. Differential Modes: LVPECL/LVDS/CML.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
Rev. 1.1
7
Si598/Si599
Table 7. CLK± Output Period Jitter
(Typical values TA = 25 ºC, VDD = 3.3 V unless otherwise noted)
Parameter
Period Jitter*
Symbol
Test Condition
RMS
Min
—
Typ
3
Max
—
Units
ps
JPER
Peak-to-Peak
—
35
—
ps
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles.
Table 8. CLK± Output Phase Noise (Typical, Si599)
(Typical values TA = 25 ºC, VDD = 3.3 V)
Offset Frequency
74.25 MHz
185 ppm/V
LVPECL
148.5 MHz
185 ppm/V
LVPECL
155.52 MHz
95 ppm/V
LVPECL
Units
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
–77
–68
–95
–77
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
–101
–121
–134
–149
–151
–150
–101
–119
–127
–144
–147
–148
–116
–128
–144
–147
–148
10 MHz
20 MHz
Table 9. Power Supply Noise Rejection
(Typical values TA = 25 ºC, VDD = 3.3 V)
Parameter
Symbol Test Condition
Min
Typ
0.32
0.36
0.36
0.32
Max Units
RMS Additive Jitter due to Power Supply Noise*
100 kHz
—
—
—
—
—
—
—
—
ps
ps
ps
ps
300 kHz
φPSRR
700 kHz
1 MHz
*Note: Measured with 100 mVp-p sinusoid applied to power supply pin. VDD = 3.3 V, LVPECL.
Table 10. Spurious Performance
(Typical values TA = 25 ºC, VDD = 3.3 V)
Parameter
Symbol
Test Condition
LVPECL, LVDS, CML1
LVPECL, LVDS, CML2
CMOS1
Min
—
Typ
Max Units
75
64
77
—
—
—
dB
dB
dB
SFDR
—
Spurious Free Dynamic Range
—
Notes:
1. 10 to 160 MHz.
2. 10 to 810 MHz.
8
Rev. 1.1
Si598/Si599
Table 11. Environmental Compliance
The Si598/599 meets the following qualification test requirements.
Parameter
Mechanical Shock
Conditions/Test Method
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2036
J-STD-020, MSL1
Mechanical Vibration
Solderability
Gross & Fine Leak
Resistance to Solder Heat
Moisture Sensitivity Level
Contact Pads
Gold over Nickel
Table 12. Programming Constraints and Timing
(Typical values TA = 25 ºC, VDD = 3.3 V, min/max limits VDD = 1.8 ±5%, 2.5 or 3.3 V ±10%, TA = –40 to 85 ºC unless
otherwise noted)
Parameter
Symbol
CKOF
MRES
Test Condition
Min
10
Typ
—
Max
810
—
Unit
MHz
ppt
Output Frequency Range
Frequency Reprogramming
Resolution
—
28
Internal Oscillator Frequency
fOSC
4850
—
—
5670
—
MHz
MHz
Internal Crystal Frequency
Accuracy
fXTAL
Maximum variation is
±2000 ppm
39.17
Delta Frequency for
Continuous Output
From center frequency –3500
—
+3500
10
ppm
ms
µs
Unfreeze to NewFreq
Timeout*
Settling Time for Small
Frequency Change
<±3500 ppm from
center frequency
—
—
—
—
100
10
Settling Time for Large
Frequency Change
>±3500 ppm from
center frequency after
setting NewFreq bit
ms
*Note: Applies when using large frequency change procedure outlined in section “3.1.2.Reconfiguring the Output Clock for
Large Changes in Output Frequency”.
Rev. 1.1
9
Si598/Si599
Table 13. Thermal Characteristics
(Typical values TA = 25 ºC, VDD = 3.3 V)
Parameter
Symbol
Test Condition
Still Air
Min
—
Typ
84.6
38.8
—
Max
—
Unit
°C/W
°C/W
°C
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Case
Ambient Temperature
JA
Still Air
—
—
JC
TA
TJ
–40
—
85
Junction Temperature
—
125
°C
Table 14. Absolute Maximum Ratings
Parameter
Supply Voltage, 1.8 V Option
Supply Voltage, 2.5/3.3 V Option
Input Voltage
Symbol
VDD
VDD
VI
Rating
Units
–0.5 to +1.9
–0.5 to +3.8
–0.5 to VDD + 0.3
–55 to +125
2000
V
V
V
ºC
Storage Temperature
TS
ESD Sensitivity (HBM, per JESD22-A114)
Soldering Temperature (lead-free profile)
ESD
TPEAK
tP
V
260
ºC
Soldering Temperature Time @ TPEAK (lead-free profile)
20–40
seconds
Notes:
1. Stresses beyond the absolute maximum ratings may cause permanent damage to the device. Functional operation or
specification compliance is not implied at these conditions.
2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at
www.silabs.com/VCXO for further information, including soldering profiles.
10
Rev. 1.1
Si598/Si599
The 38-bit resolution of RFREQ allows the DCO
frequency to have a programmable frequency resolution
3. Functional Description
The Si598 XO and the Si599 VCXO are low-jitter of 28 ppt.
oscillators ideally suited for applications requiring
As shown in Figure 3, the device allows reprogramming
programmable frequencies. The Si59x can be
programmed to generate any output clock in the range
of 10 to 810 MHz with frequency resolution of 30 parts
per trillion. Output jitter performance exceeds the strict
requirements of high-speed communication systems
including OC-48/STM-16, 3G SDI, and Gigabit
Ethernet.
of the DCO frequency up to ±3500 ppm from the center
frequency configuration without interruption to the
output clock. Changes greater than the ±3500 ppm
window will cause the device to recalibrate its internal
tuning circuitry, forcing the output clock to momentarily
stop and start at any arbitrary point during a clock cycle.
This re-calibration process establishes a new center
The Si59x consists of a digitally-controlled oscillator frequency and can take up to 10 ms. Circuitry receiving
(DCO) based on Silicon Laboratories' third-generation a clock from the Si59x device that is sensitive to glitches
DSPLL technology, which is driven by an internal fixed- or runt pulses may have to be reset once the
frequency crystal reference.
recalibration process is complete.
The device's default output frequency is set at the 3.1.1. Reconfiguring the Output Clock for a Small
factory and can be reprogrammed through the two-wire
I2C serial port. Once the device is powered down, it will
return to its factory-set default output frequency.
Change in Frequency
For output changes less than ±3500 ppm from the
center frequency configuration, the DCO frequency is
The Si599 has a pullable output frequency using the the only value that needs reprogramming. Since
voltage control input pin. This makes the Si599 an ideal fDCO = fXTAL x RFREQ, and that fXTAL is fixed, changing
choice for high-performance, low-jitter, phase-locked the DCO frequency is as simple as reconfiguring the
loops. The Si598 is digitally pullable using the I2C RFREQ value as outlined below:
interface and is ideal for digital PLL applications.
1. Using the serial port, read the current RFREQ value
(registers 0x08–0x12).
3.1. Programming a New Output Frequency
2. Calculate the new value of RFREQ given the change
The output frequency (fout
)
is determined by
in frequency.
programming the DCO frequency (fDCO) and the
device's output dividers (HS_DIV, N1). The output
frequency is calculated using the following equation:
fout_new
------------------------
fout_current
RFREQnew = RFREQcurrent
fDCO
fXTAL RFREQ
------------------------------------------
HSDIV N1
3. Using the serial port, write the new RFREQ value
(registers 0x08—0x12). Multi-byte changes to
RFREQ can freeze the DCO to avoid unintended
RFREQ values.
----------------------------------------
Output Dividers
fout
=
=
The DCO frequency is adjustable in the range of 4.85 to
5.67 GHz by setting the high-resolution 38-bit fractional
multiplier (RFREQ). The DCO frequency is the product
of the internal fixed-frequency crystal (fXTAL) and
RFREQ.
Example:
An Si598 generating a 148.35 MHz clock must be
reconfigured "on-the-fly" to generate a 148.5 MHz clock.
This represents a change of +1011.122 ppm, which is
well within the ±3500 ppm window.
Center
Frequency
Configuration
small frequency changes can be made
without interruption to the output clock
-3500 ppm
+3500 ppm
5.67 GHz
4.85 GHz
Figure 3. DCO Frequency Range
11
Rev. 1.1
Si598/Si599
A typical frequency configuration for this example:
RFREQcurrent = 0x8858199E9
RFREQ, HSDIV, and N1 are calculated to generate a
new output frequency (fout_new). New values can be
calculated manually or with the Si59x-EVB software,
which provides a user-friendly application to help find
the optimum values.
F
F
out_current = 148.35 MHz
out_new = 148.50 MHz
Calculate RFREQnew to change the output frequency
from 148.35 to 148.5 MHz:
The first step in manually calculating the frequency
configuration is to determine new frequency divider
values (HSDIV, N1). Given the desired output frequency
(fout_new), find the frequency divider values that will
keep the DCO oscillation frequency in the range of 4.85
to 5.67 GHz.
148.50 MHz
-------------------------------
RFREQnew = 0x8858199E9
= 0x887B6473C
148.35 MHz
Note that performing calculations with RFREQ requires
a minimum of 38-bit arithmetic precision.
fDCO_new = fout_new HSDIVnew N1new
Valid values of HSDIV are 9 or 11. N1 can be selected
as 1 or any even number up to 128 (i.e., 1, 2, 4, 6, 8, 10
Relatively small changes in output frequency may
require writing more than one RFREQ register. Such
multi-register RFREQ writes can impact the output clock
…
128). To help minimize the device's power
consumption, the divider values should be selected to
keep the DCO's oscillation frequency as low as
possible. The lowest value of N1 with the highest value
of HS_DIV also results in the best power savings.
frequency on
updating.
a
register-by-register basis during
Interim changes to the output clock during RFREQ
writes can be prevented by using the following
procedure:
Once HS_DIV and N1 have been determined, the next
step is to calculate the reference frequency multiplier
(RFREQ).
1. Freeze the "M" value (Set Register 135 bit 5 = 1)
2. Write the new frequency configuration (RFREQ)
3. Unfreeze the "M" value (Set Register 135 bit 5 = 0)
fDCO_new
----------------------
=
RFREQnew
fXTAL
3.1.2. Reconfiguring the Output Clock for Large
Changes in Output Frequency
RFREQ is programmable as a 38-bit binary fractional
frequency multiplier with the first 10 most significant bits
(MSBs) representing the integer portion of the multiplier
and the 28 least significant bits (LSBs) representing the
fractional portion.
For output frequency changes outside of ±3500 ppm
from the center frequency, it is likely that both the DCO
frequency and the output dividers need to be
reprogrammed. Note that changing the DCO frequency
outside of the ±3500 ppm window will cause the output
to momentarily stop and restart at any arbitrary point in
a clock cycle. Devices sensitive to glitches or runt
pulses may have to be reset once reconfiguration is
complete.
Before entering a fractional number into the RFREQ
register, it must be converted to a 38-bit integer using a
bitwise left shift operation by 28 bits, which effectively
multiplies RFREQ by 228.
The process for reconfiguring the output frequency
outside of a ±3500 ppm window is shown below:
Example:
RFREQ = 136.3441409d
1. Using the serial port, read the current values for
RFREQ, HSDIV, and N1.
Multiply RFREQ by 228 = 36599601635.42d
Discard the fractional portion = 36599601635d
Convert to hexadecimal = 0x8858199E9
2. Calculate fXTAL for the device. Note that because of
slight variations of the internal crystal frequency from
one device to another, each device may have a
different RFREQ value or possibly even different
HSDIV or N1 values to maintain the same output
frequency. It is necessary to calculate fXTAL for each
device.
Once the new values for RFREQ, HSDIV, and N1 are
determined, they can be written directly into the device
from the serial port using the following procedure:
1. Freeze the DCO (bit 4 of Register 137)
Fout HSDIV N1
2. Write the new frequency configuration (RFREQ,
HS_DIV, N1)
--------------------------------------------------
=
fXTAL
RFREQ
Once fXTAL has been determined, new values for
Rev. 1.1
12
Si598/Si599
3. Unfreeze the DCO and assert the NewFreq bit (bit 6 5.67 GHz. In this case, keeping the same output
of Register 135) within the maximum Unfreeze to
NewFreq Timeout in Table 12, “Programming
Constraints and Timing,” on page 9.
dividers will still keep fDCO within its range limits:
fDCO_new = fout_new HSDVnew N1new
The process of freezing and unfreezing the DCO will
cause the output clock to momentarily stop and start at
any arbitrary point during a clock cycle. This process
can take up to 10 ms. Circuitry that is sensitive to
glitches or runt pulses may have to be reset after the
new frequency configuration is written.
= 161.1328125 MHz 4 8 = 5.156250000 GHz
Calculate the new value of RFREQ given the new DCO
frequency:
fDCO_new
----------------------
= 131.637733d= 0x83A342779
RFREQnew
=
fXTAL
Example:
An Si598 generating 156.25 MHz must be re-configured
to generate a 161.1328125 MHz clock (156.25 MHz x
66/64). This frequency change is greater than
±3500 ppm.
2
3.2. I C Interface
The control interface to the Si598 is an I2C-compatible
2-wire bus for bidirectional communication. The bus
consists of a bidirectional serial data line (SDA) and a
serial clock input (SCL). Both lines must be connected
to the positive supply via an external pullup.Fast mode
operation is supported for transfer rates up to 400 kbps
as specified in the I2C-Bus Specification standard.
fout = 156.25 MHz
Read the current values for RFREQ, HS_DIV, N1:
RFREQcurrent = 0x7FA611E85 = 34265439877d,
34265439877d / 228 = 127.64871074631810d
HS_DIV = 4
Figure 4 shows the command format for both read and
write access. Data is always sent MSB. Data length is 1
byte. Read and write commands support 1 or more data
bytes as illustrated. The master must send a Not
Acknowledge and a Stop after the last read data byte to
terminate the read command. The timing specifications
and timing diagram for the I2C bus can be found in the
I2C-Bus Specification standard (fast mode operation).
The device I2C address is specified in the part number.
N1 = 8
Calculate fXTAL, fDCO_current
fDCO_current = fout HSDV N1 = 5.000000000 GHz
fDCO_current
--------------------------------------
= 39.17 MHz
fXTAL
=
RFREQcurrent
Given fout_new = 161.1328125 MHz, choose output
dividers that will keep fDCO within the range of 4.85 to
S Slave Address
0
A Byte Address
A
Data
A
A
Data
P
Write Command
(Optional 2nd data byte and acknowledge illustrated)
A Byte Address
Data
S Slave Address
0
A
Data
Slave Address
N
A
S
1
A
P
Read Command
(Optional data byte and acknowledge before the last data byte and not acknowledge illustrated)
From master to slave
From slave to master
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH).
Required after the last data byte to signal the end of the read comand to the slave.
S – START condition
P – STOP condition
Figure 4. I2C Command Format
13
Rev. 1.1
Si598/Si599
4. Serial Port Registers
Note: Registers not documented are reserved. Values within reserved registers and reserved bits must not be changed.
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
7
High Speed/
N1 Dividers
HS_DIV[2:0]
N1[6:2]
8
9
Reference
Frequency
N1[1:0]
RFREQ[37:32]
Reference
Frequency
RFREQ[31:24]
RFREQ[23:16]
RFREQ[15:8]
RFREQ[7:0]
10
11
12
135
Reference
Frequency
Reference
Frequency
Reference
Frequency
NewFreq/
Freeze/
Memory
Control
Reserved NewFreq Freeze M Freeze
VCADC
Reserved
RECALL
137
Freeze DCO
Reserved
Freeze
DCO
Reserved
14
Rev. 1.1
Si598/Si599
Register 7. High Speed/N1 Dividers
Bit
D7
D6
HS_DIV[2:0]
R/W
D5
D4
D3
D2
N1[6:2]
R/W
D1
D0
Name
Type
Bit
Name
Function
7:5
HS_DIV[2:0] DCO High Speed Divider.
Sets value for high speed divider that takes the DCO output fOSC as its clock input.
000 = 4
001 = 5
010 = 6
011 = 7
100 = Not used.
101 = 9
110 = Not used.
111 = 11
4:0
N1[6:2]
CLKOUT Output Divider.
Sets value for CLKOUT output divider. Allowed values are [1] and [2, 4, 6, ..., 27]. Illegal
odd divider values will be rounded up to the nearest even value. The value for the N1
register can be calculated by taking the divider ratio minus one. For example, to divide by
10, write 0001001 (9 decimal) to the N1 registers.
0000000 = 1
1111111 = 27
Register 8. Reference Frequency
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
N1[1:0]
R/W
RFREQ[37:32]
R/W
Bit
Name
Function
7:6
N1[1:0]
CLKOUT Output Divider.
Sets value for CLKOUT output divider. Allowed values are [1] and [2, 4, 6, ..., 27]. Ille-
gal odd divider values will be rounded up to the nearest even value. The value for the
N1 register can be calculated by taking the divider ratio minus one. For example, to
divide by 10, write 0001001 (9 decimal) to the N1 registers.
0000000 = 1
1111111 = 27
5:0
RFREQ[37:32] Reference Frequency.
Frequency control input to DCO.
Rev. 1.1
15
Si598/Si599
Register 9. Reference Frequency
Bit
D7
D6
D5
D4
D3
D2
D2
D2
D1
D1
D1
D0
D0
D0
Name
Type
RFREQ[31:24]
R/W
Bit
Name
Function
7:0
RFREQ[31:24]
Reference Frequency.
Frequency control input to DCO.
Register 10. Reference Frequency
Bit
D7
D6
D5
D4
D3
Name
Type
RFREQ[23:16]
R/W
Bit
Name
Function
7:0
RFREQ[23:16] Reference Frequency.
Frequency control input to DCO.
Register 11. Reference Frequency
Bit
D7
D6
D5
D4
RFREQ[15:8]
R/W
D3
Name
Type
Bit
Name
Function
7:0
RFREQ[15:8] Reference Frequency.
Frequency control input to DCO.
16
Rev. 1.1
Si598/Si599
Register 12. Reference Frequency
Bit
D7
D6
D5
D4
RFREQ[7:0]
R/W
D3
D2
D1
D0
Name
Type
Bit
Name
Function
7:0
RFREQ[7:0]
Reference Frequency.
Frequency control input to DCO.
Register 135. NewFreq/Freeze/Memory Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
NewFreq
Freeze M
Freeze
RECALL
VCADC
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset settings = 00xxxx00
Bit
7
Name
Function
Reserved
NewFreq
This bit should read 0 in normal operation.
6
New Frequency Applied.
Alerts the DSPLL that a new frequency configuration has been applied. This bit will
clear itself when the new frequency is applied. Write 0x40 to this register to assert
NewFreq.
5
4
Freeze M
Freezes the M Control Word.
Prevents interim frequency changes when writing RFREQ registers.
Freeze
Freezes the VCDADC Output Word.
VCADC
May be used to hold the nominal output frequency of the Si599. Do not use with Si598.
3:1
0
Reserved
RECALL
Always zero.
Recall NVM into RAM.
0 = No operation.
1 = Write NVM bits into RAM. Bit is internally reset following completion of operation.
Rev. 1.1
17
Si598/Si599
Register 137. Freeze DCO
Bit
D7
D6
D5
D4
Freeze DCO
R/W
D3
D2
D1
D0
Name
Type
R/W
R/W
R/W
R
R
R
R
Reset settings = Si598: 0000xxxx, Si599: 1000xxxx
Bit
Name
Function
7
Reserved
0: Si598
1: Si599
6:5
4
Reserved
This bits should read 0 in normal operation.
Freeze DCO Freeze DCO.
Freezes the DSPLL so the frequency configuration can be modified.
Si598: Write 0x10 to this register to Freeze DCO.
Si599: Write 0x90 to this register to Freeze DCO.
3:0
Reserved
Read only.
18
Rev. 1.1
Si598/Si599
5. Si598 (XO) Pin Descriptions
(Top View)
SDA
7
NC
VDD
1
2
3
6
5
4
OE
CLK–
CLK+
GND
8
SCL
Table 15. Si598 Pin Descriptions
Type
Pin
Name
Function
No Connect.
1
NC
N/A
Make no external connection to this pin.
Output Enable.*
2
OE
Input
See 7. Ordering Information on page 21.
3
4
GND
Ground
Output
Electrical and Case Ground.
Oscillator Output.
CLK+
CLK–
(NC for CMOS)
Output
(N/A for CMOS)
Complementary Output.
5
(NC for CMOS, do not make external connection).
6
7
VDD
Power
Power Supply Voltage.
2
SDA
Bidirectional
Open Drain
I C Serial Data.
2
8
SCL
Input
I C Serial Clock.
*Note: OE pin includes a 17 k resistor to VDD for OE active high option or 17 k to GND for OE active low option.
Rev. 1.1
19
Si598/Si599
6. Si599 (VCXO) Pin Descriptions
(Top View)
SDA
7
VC
VDD
1
6
5
4
OE
2
3
CLK–
CLK+
GND
8
SCL
Table 16. Si599 Pin Descriptions
Type
Pin
Name
Function
1
VC
Analog Input
Input
Control Voltage.
Output Enable.*
2
OE
See 7. Ordering Information on page 21.
Electrical and Case Ground.
Oscillator Output.
3
4
GND
Ground
Output
CLK+
CLK–
(NC for CMOS)
Output
(N/A for CMOS)
Complementary Output.
5
(NC for CMOS, do not make external connection).
6
7
VDD
Power
Power Supply Voltage.
2
SDA
Bidirectional
Open Drain
I C Serial Data.
2
8
SCL
Input
I C Serial Clock.
*Note: OE pin includes a 17 k resistor to VDD for OE active high option or 17 k to GND for OE active low option.
20
Rev. 1.1
Si598/Si599
7. Ordering Information
The Si598/Si599 supports a wide variety of options including frequency range, start-up frequency, temperature
stability, tuning slope, output format, and VDD. Specific device configurations are programmed into the Si598/Si599
at time of shipment. Configurations are specified using the Part Number Configuration chart shown below. Silicon
Labs provides a web browser-based part number configuration utility to simplify this process. Refer to
www.silabs.com/VCXOPartNumber to access this tool and for further ordering instructions. The Si598/Si599 XO/
VCXO series is supplied in an industry-standard, RoHS compliant, 8-pad, 5x7 mm package. Tape and reel
packaging is an ordering option.
X
X
D
G
R
59x
X
XXX XXX
R = Tape and Reel
Blank = Coil Tape
Operating Temp Range (°C)
–40 to +85 °C
598 Programmable
XO Product Family
G
599 Programmable
Device Revision Letter
VCXO Product Family
Six-Digit Start-up Frequency/I2C Address Designator
The Si59x supports a user-defined start-up frequency between
10–810 MHz. The start-up frequency must be in the same frequency range
as that specified by the Frequency Grade 3rd option code.
1st Option Code
The Si59x supports a user-defined I 2C 7-bit address. Each unique start-up
frequency/I2C address combination is assigned a six-digit numerical code.
VDD Output Format Output Enable Polarity
A
B
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
T
3.3 LVPECL
3.3 LVDS
3.3 CMOS
3.3 CML
2.5 LVPECL
2.5 LVDS
2.5 CMOS
2.5 CML
1.8 CMOS
1.8 CML
3.3 LVPECL
3.3 LVDS
3.3 CMOS
3.3 CML
2.5 LVPECL
2.5 LVDS
2.5 CMOS
2.5 CML
1.8 CMOS
1.8 CML
High
High
High
High
High
High
High
High
High
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
This code can be requested during the part number request process
. Refer
to www.silabs.com/VCXOPartNumber to request an Si59x part number.
3rd Option Code
Frequency Grade
Code
Frequency Range Supported (MHz)
10-810
10-280
A
B
C
10-160 (CMOS available to 160 MHz)
2nd Option Code
Code Temperature Stability (ppm, max , ±) Total Stablility (ppm, max, ±)
A
B
C
50
25
20
100
50
30
Si598
U
V
W
2nd Option Code
Tuning Slope
Note:
Temperature
Minimum APR
CMOS available to 160 MHz.
Stability
± ppm (max)
Kv
ppm/V (typ)
380
(±ppm) for VDD @
Code
A
B
C
D
E
F
G
3.3 V
370
160
130
100
65
70
35
15
2.5 V
275
110
80
75
50
45
20
N/A
1.8 V
200
80
50
40
25
10
N/A
N/A
20
20
50
20
20
50
50
20
185
185
125
95
125
95
45
H
Notes:
Si599
1. For best jitter and phase noise performance , always choose the smallest Kv that meets
the application’s minimum APR requirements . See AN266 for more information.
2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an
APR of ±25 ppm is able to lock to a clock with a ±25 ppm stability over 15 years over all
operating conditions.
3. Nominal pull range (±) = 0.5 x VDD x tuning slope.
4. Minimum APR values noted above include worst case values for all parameters .
Figure 5. Part Number Convention
Rev. 1.1
21
Si598/Si599
Table 17. Standard Si598 Part Numbers
2
Part Number
VDD
Output
Format
Total Stability Frequency
Range
Startup
Frequency
I C Address
598CCC000107DG
598BCA000107DG
3.3V
3.3V
CMOS
LVDS
30 ppm
30 ppm
10–160 MHz
10–810 MHz
10 MHz
10 MHz
0x55
0x55
22
Rev. 1.1
Si598/Si599
8. Si59x Mark Specification
Figure 6 illustrates the mark specification for the Si59x. Table 18 lists the line information.
Figure 6. Mark Specification
Table 18. Si59x Top Mark Description
Line
Position
Description
1
1–10
“SiLabs"+ Part Family Number, 59x (first 3 characters in part number where x = 8
indicates a 598 device and x = 9 indicates a 599 device).
2
3
1–10
Option1 + Option2 + Option3 + ConfigNum(6) + Temp
Trace Code
Pin 1 orientation mark (dot)
Position 1
Position 2
Product Revision (D)
Tiny Trace Code (4 alphanumeric characters per assembly release instructions)
Year (least significant year digit), to be assigned by assembly site (ex: 2010 = 0)
Calendar Work Week number (1–53), to be assigned by assembly site
“+” to indicate Pb-Free and RoHS-compliant
Position 3–6
Position 7
Position 8–9
Position 10
Rev. 1.1
23
Si598/Si599
9. Outline Diagram and Suggested Pad Layout
Figure 7 illustrates the package details for the Si598/Si599. Table 19 lists the values for the dimensions shown in
the illustration.
Figure 7. Si598/Si599 Outline Diagram
Table 19. Package Diagram Dimensions (mm)
Dimension
Min
1.50
1.30
0.90
0.50
0.30
Nom
1.65
1.40
1.00
0.60
—
Max
1.80
1.50
1.10
0.70
0.60
A
b
b1
c
c1
D
D1
e
E
E1
H
L
L1
p
5.00 BSC
4.40
2.54 BSC
7.00 BSC
6.20
4.30
4.50
6.10
0.55
1.17
1.07
1.80
6.30
0.75
1.37
1.27
2.60
0.65
1.27
1.17
—
R
0.70 REF
—
aaa
bbb
ccc
ddd
eee
—
—
—
—
—
0.15
0.15
0.10
0.10
0.05
—
—
—
—
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
24
Rev. 1.1
Si598/Si599
10. 8-Pin PCB Land Pattern
Figure 8 illustrates the 8-pin PCB land pattern for the Si598/Si599. Table 20 lists the values for the dimensions
shown in the illustration.
Figure 8. Si598/Si599 PCB Land Pattern
Table 20. PCB Land Pattern Dimensions (mm)
Dimension
Min
Max
D2
D3
5.08 REF
5.705 REF
2.54 BSC
4.20 REF
e
E2
GD
GE
VD
VE
0.84
2.00
—
—
8.20 REF
7.30 REF
1.70 TYP
1.545 TYP
2.15 REF
1.3 REF
X1
X2
Y1
Y2
ZD
—
—
6.78
6.30
ZE
Note:
1. Dimensioning and tolerancing per the ANSI Y14.5M-1994
specification.
2. Land pattern design follows IPC-7351 guidelines.
3. All dimensions shown are at maximum material condition
(MMC).
4. Controlling dimension is in millimeters (mm).
Rev. 1.1
25
Si598/Si599
REVISION HISTORY
Revision 1.1
June, 2018
Changed “Trays” to “Coil Tape” in 7. Ordering Information on page 21.
Revision 1.0
Updated Register 135, “NewFreq/Freeze/Memory Control,” on page 17.
Updated Register 137, “Freeze DCO,” on page 18.
Revision 0.9
Updated Si598/599 devices to support frequencies up to 810 MHz for LVPECL, LVDS, and CML outputs.
Added Table 13, “Thermal Characteristics,” on page 10.
Updated ESD HBM sensitivity rating in Table 14 on page 10.
Updated Table 11 on page 9 to include "Moisture Sensitivity Level" and "Contact Pads" rows.
Updated Figure 6 and Table 18 on page 23 to reflect specific marking information.
Corrected pin 7 and pin 8 designation in package diagram in Figure 7 on page 24.
26
Rev. 1.1
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