S-8235AAE-TCT1U [SII]
FOR AUTOMOTIVE BATTERY PROTECTION IC;
| 型号： | S-8235AAE-TCT1U |
| 厂家： | 
SEIKO INSTRUMENTS INC |
| 描述： | FOR AUTOMOTIVE BATTERY PROTECTION IC |
| 文件： | 总24页 (文件大小：1650K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S-8235A Series
FOR AUTOMOTIVE BATTERY PROTECTION IC
FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
www.sii-ic.com
© SII Semiconductor Corporation, 2013-2016
Rev.1.7_00
The S-8235A Series, for automotive use, is utilized for secondary protection of lithium-ion rechargeable batteries, and
incorporates high-accuracy voltage detection circuits and delay circuits. Short-circuiting between cells makes it possible for
serial connection of 3-cell to 5-cell. By connecting in cascade, the S-8235A Series protects 6-serial or more cells lithium-ion
rechargeable battery pack.
The S-8235A Series performs a self-test operation to confirm overcharge detection.
Caution This product can be used in vehicle equipment and in-vehicle equipment. Before using the product in the
purpose, contact to SII Semiconductor Corporation is indispensable.
Features
•
High-accuracy voltage detection circuit for each cell
Overcharge detection voltage n (n = 1 to 5)
3.60 V to 4.50 V (50 mV step)
Accuracy 20 mV (Ta = +25°C)
Accuracy 30 mV (Ta = −5°C to +55°C)
Overcharge hysteresis voltage n (n = 1 to 5)
0.0 mV to −550 mV (50 mV step)
−300 mV to −550 mV
−100 mV to −250 mV
0.0 mV to −50 mV
Accuracy 20%
Accuracy 50 mV
Accuracy 25 mV
•
•
•
•
•
•
•
Self-test operation to confirm overcharge detection is available.
Cascade connection is available.
Delay times for overcharge detection can be set by an internal circuit only (External capacitors are unnecessary).
High-withstand voltage:
Absolute maximum rating 26 V
6 V to 24 V
Ta = −40°C to +85°C
Wide operation voltage range:
Wide operation temperature range:
Low current consumption
At VCUn − 1.0 V for each cell:
At 2.3 V for each cell:
10 μA max. (Ta = +25°C)
8 μA max. (Ta = +25°C)
•
•
Lead-free (Sn 100%), halogen-free
AEC-Q100 qualified *1
*1. Contact our sales office for details.
Application
•
Lithium-ion rechargeable battery pack (for secondary protection)
Package
•
16-Pin TSSOP
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FOR AUTOMOTIVE BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8235A Series
Rev.1.7_00
Block Diagram
VDD
VC1
VC2
VC3
VC4
VC5
+
−
NPI
+
−
CTL
Delay
circuit
+
−
Overcharge
control
CO
circuit
+
−
+
−
CLKO
VSS
CLKI
RSTI
CAI
RSTO
Self-test
control
circuit
CAO
Remark
The diodes in the figure are parasitic diodes.
Figure 1
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FOR AUTOMOTIVE BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.7_00
S-8235A Series
AEC-Q100 Qualified
This IC supports AEC-Q100 for the operation temperature grade 3.
Contact our sales office for details of AEC-Q100 reliability specification.
Product Name Structure
1. Product name
S-8235A xx
-
TCT1
U
Environmental code
U:
Lead-free (Sn 100%), halogen-free
Package abbreviation and IC packing specifications*1
TCT1: 16-Pin TSSOP, Tape
Serial code*2
Sequentially set from AA to ZZ
*1. Refer to the tape drawing.
*2. Refer to "3. Product name list".
2. Package
Table 1 Package Drawing Codes
Package Name
Dimension
FT016-A-P-SD
Tape
Reel
16-Pin TSSOP
FT016-A-C-SD
FT016-A-R-S1
3. Product name list
Table 2
Overcharge Detection Overcharge Hysteresis Overcharge Detection
Delay Time*1
Product Name
Voltage
[VCU
Voltage
[VHC
]
]
[tCU]
S-8235AAA-TCT1U
S-8235AAB-TCT1U
S-8235AAC-TCT1U
S-8235AAD-TCT1U
S-8235AAE-TCT1U
S-8235AAG-TCT1U
S-8235AAH-TCT1U
S-8235AAI-TCT1U
S-8235AAJ-TCT1U
4.050 V
4.050 V
4.250 V
4.350 V
4.350 V
4.550 V
3.825 V
4.450 V
4.500 V
−0.050 V
−0.250 V
−0.250 V
−0.150 V
−0.150 V
−0.250 V
−0.250 V
−0.150 V
−0.350 V
1.0 s
1.0 s
2.0 s
2.0 s
1.0 s
1.0 s
4.0 s
1.0 s
512 ms
*1. Overcharge detection delay time is selectable in 1.0 s / 2.0 s / 4.0 s / 8.0 s.
Remark Please contact our sales office for products with detection voltage values other than those specified above.
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FOR AUTOMOTIVE BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8235A Series
Rev.1.7_00
Pin Configuration
1. 16-Pin TSSOP
Top view
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Figure 2
Table 3
Pin No.
Symbol
Description
1
2
VDD
Input pin for positive power supply
Positive voltage monitoring pin of battery 1
Negative voltage monitoring pin of battery 1,
Positive voltage monitoring pin of battery 2
Negative voltage monitoring pin of battery 2,
Positive voltage monitoring pin of battery 3
Negative voltage monitoring pin of battery 3,
Positive voltage monitoring pin of battery 4
Negative voltage monitoring pin of battery 4,
Positive voltage monitoring pin of battery 5
Negative voltage monitoring pin of battery 5
Input pin for negative power supply
Connection pin of charge control FET gate
Output pin for chip active signal
VC1
3
4
5
6
VC2
VC3
VC4
VC5
7
VSS
NPI
8
9
CO
10
11
12
13
14
15
16
CAO
CLKI
RSTI
RSTO
CLKO
CAI
Input pin for clock signal
Input pin for reset signal
Output pin for reset signal
Output pin for clock signal
Input pin for chip active signal
CTL
Input pin for charge control
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FOR AUTOMOTIVE BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.7_00
S-8235A Series
Absolute Maximum Ratings
Table 4
(Ta = +25°C unless otherwise specified)
Item
Symbol
Applied Pin
Absolute Maximum Rating Unit
Input voltage between VDD pin and VSS pin VDS
Input voltage between VDD pin and NPI pin VDN
VDD
VSS − 0.3 to VSS + 26
VNPI − 0.3 to VNPI + 26
VSS − 0.3 to VSS + 26
VSS − 0.3 to VDD + 0.3
VDD − 26 to VDD + 0.3
VSS − 0.3 to VDD + 0.3
1100*1
V
V
VDD
VC1
V
V
Input pin voltage
VIN
VC2, VC3, CLKI, RSTI, CAI, CTL
V
V
VC4, VC5
Output pin voltage
VOUT
PD
CO, CAO, CLKO, RSTO
Power dissipation
−
−
−
mW
°C
°C
Operation ambient temperature
Storage temperature
Topr
Tstg
−40 to +85
−40 to +125
*1. When mounted on board
[Mounted board]
(1) Board size:
(2) Name:
114.3 mm × 76.2 mm × t1.6 mm
JEDEC STANDARD51-7
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
1200
1000
800
600
400
200
0
0
50
100
150
Ambient temperature (Ta) [°C]
Figure 3 Power Dissipation of Package (When Mounted on Board)
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FOR AUTOMOTIVE BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8235A Series
Rev.1.7_00
Electrical Characteristics
Table 5
(Ta = +25°C, VDS = VDD − VSS = V1 + V2 + V3 + V4 + V5, unless otherwise specified)
Item
Symbol
VCUn
Condition
Min.
Typ.
Max.
Unit
Detection Voltage
VCU
− 0.020
VCU
− 0.030
VHC × 0.8
VHC
− 0.050
VHC
− 0.025
VCU
+ 0.020
VCU
+ 0.030
VHC × 1.2
VHC
+ 0.050
VHC
+ 0.025
VCU
V
−
Overcharge detection
voltage n
(n = 1, 2, 3, 4, 5)
Ta = −5°C ~ +55°C*1
VCU
VHC
VHC
V
V
V
−550 mV ≤ VHC ≤ −300 mV
−250 mV ≤ VHC ≤ −100 mV
Overcharge hysteresis
voltage n
(n = 1, 2, 3, 4, 5)
VHCn
VHC
V
VHC = −50 mV, 0 mV
Input Voltage
Operation voltage between
VDD pin and NPI pin
CLKI pin voltage "H"
CLKI pin voltage "L"
RSTI pin voltage "H"
RSTI pin voltage "L"
CAI pin voltage "H"
CAI pin voltage "L"
CTL pin voltage "H"
VDNOP
6
24
V
−
−
VDN = 17.5 V
VDN = 17.5 V
VDN = 17.5 V
VDN = 17.5 V
VDN = 17.5 V
VDN = 17.5 V
VDN = 17.5 V
VDN = 17.5 V
VCLKIH
VCLKIL
VRSTIH
VRSTIL
VCAIH
VCAIL
V
V
V
V
V
V
V
V
VNPI + 0.5
−
−
−
−
−
−
−
−
−
−
VNPI + 0.05
VNPI + 0.5
−
VNPI + 0.05
−
VDD − 0.5
−
−
VDD − 0.05
−
VDD − 0.05
−
VCTLH
VCTLL
CTL pin voltage "L"
Input Current
VDD − 0.5
Current consumption
during operation
Current consumption
during overdischarge
VCn pin current
IOPE
IOPED
IVCn
5
4
0
10
8
V1 = V2 = V3 = V4 = V5 = VCU − 1.0 V
V1 = V2 = V3 = V4 = V5 = 2.3 V
−
−
μA
μA
μA
1.0
V1 = V2 = V3 = V4 = V5 = VCU − 1.0 V
−1.0
(n = 1, 2, 3, 4, 5)
0.9
0.7
−1.1
−1.3
3.0
−1.0
3.0
−1.0
0.4
1.0
1.0
−1.0
−1.0
10
−0.7
10
−0.7
0.7
1.1
1.3
−0.9
−0.7
20
−0.4
20
−0.4
1.0
mA
mA
mA
mA
μA
μA
μA
μA
μA
μA
μA
μA
V1 = V2 = V3 = V4 = V5 = VCU − 1.0 V
VCn pin pull-down current
(n = 2, 3)
IVCLn
Ta = −40°C ~ +85°C*1
V1 = V2 = V3 = V4 = V5 = VCU − 1.0 V
VCn pin pull-up current
(n = 3, 4, 5)
IVCHn
Ta = −40°C ~ +85°C*1
CLKI pin current "H"
CLKI pin current "L"
RSTI pin current "H"
RSTI pin current "L"
CAI pin current "H"
CAI pin current "L"
CTL pin current "H"
CTL pin current "L"
Output Current
ICLKIH
ICLKIL
IRSTIH
IRSTIL
ICAIH
ICAIL
−
−
−
−
−
−
−
−
−20
0.4
−20
−10
0.7
−10
−3.0
1.0
−3.0
ICTLH
ICTLL
CO pin source current
CO pin sink current
CAO pin source current
CAO pin sink current
RSTO pin source current
RSTO pin sink current
CLKO pin source current
CLKO pin sink current
ICOH
ICOL
−
−
−
−
−
−
−
−
−
400
−
10
−
10
−
10
−
−
−
−
−
−
−
−
−20
−
−10
−
−10
−
μA
μA
μA
μA
μA
μA
μA
μA
ICAOH
ICAOL
IRSTOH
IRSTOL
ICLKOH
ICLKOL
−10
−
Delay Time
Overcharge detection delay
time
Overcharge timer reset delay
time
tCU
tTR
tCU
12
s
−
−
tCU × 0.8
tCU × 1.2
6
20
ms
*1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by
design, not tested in production.
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FOR AUTOMOTIVE BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.7_00
S-8235A Series
Test Circuit
In Figure 4, the following statuses are the initial statuses 1 to 4.
Initial status 1: Set V1 = V2 = V3 = V4 = V5 = 2.8 V, SWCO = SWCAO = SWRSTO = SWCLKO = OFF, V8 = 0 V, V9 = 5 V,
V12 = V13 = 0 V.
Initial status 2: Set V1 = V2 = V3 = V4 = V5 = 3.5 V in initial status 1.
Initial status 3: Set V9 = 0 V in initial status 2, and output 8 clocks*1 from V8.
Initial status 4: Set V1 = V2 = V3 = V4 = V5 = 2.8 V, V8 = 0 V, V9 = 0 V, V12 = V13 = 0 V.
*1. 1 clock is defined as follows.
"H": Output of 5 V for 50 ms or more
"L": Output of 0 V for 50 ms or more
S-8235A
A
A
A
A
A
A
1
2
16
15
14
13
12
11
CTL
CAI
VDD
VC1
V1
V2
V3
V4
V5
CLKO
RSTO
RSTI
CLKI
CAO
CO
3 VC2
4 VC3
5 VC4
6 VC5
7 VSS
10
9
NPI
8
SWCAO
SWRSTO
SWCLKO
SWCO
A
A
A
A
A
A
V
V
A
A
V
V
V6
V7
V8 V9 V10
V11
V12 V13
Figure 4 Test Circuit
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FOR AUTOMOTIVE BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8235A Series
Rev.1.7_00
1. Overcharge detection voltage n (VCUn), Overcharge hysteresis voltage n (VHCn
)
Set V1 = V2 = V3 = V4 = V5 = VCU − 0.050 V in initial status 1. VCU1 is defined as the voltage V1 when the CO pin
output changes after the V1 voltage is gradually increased. VCUn (n = 2 to 5) can also be defined in the same way as
VCU1
.
Moreover, set V1 = VCU + 0.050 V, V2 = V3 = V4 = V5 = 2.8 V in initial status 1. VHC1 is defined as the difference
between V1 and VHC1 when the CO pin output changes again after the V1 voltage is gradually decreased. VHCn
(n = 2 to 5) can also be defined in the same way as VHC1
.
2. CLKI pin voltage "H" (VCLKIH), CLKI pin voltage "L" (VCLKIL), RSTI pin voltage "L" (VRSTIL),
RSTI pin voltage "H" (VRSTIH
)
VCLKIH is defined as the voltage V8 when the CLKO pin output changes after the voltage V8 is gradually increased in
initial status 3. After that, VCLKIL is defined as the voltage V8 when the CLKO pin output changes again after the
voltage V8 is gradually decreased.
VRSTIL is defined as the voltage V9 when the CLKO pin output changes after the voltage V9 is gradually decreased in
initial status 2. After that, VRSTIH is defined as the voltage V9 when the CLKO pin output changes again after the
voltage V9 is gradually increased.
3. CAI pin voltage "H" (VCAIH), CAI pin voltage "L" (VCAIL
)
Set V12 = VDN − 0.5 V, V9 = 0 V in initial status 2. Repeat increasing the voltage V12 and outputting 9 clocks from V8.
CAIH is defined as the minimum voltage V12 when the CAO pin output changes.
V
Set V12 = VDN, V9 = 0 V in initial status 2. Repeat decreasing the voltage V12 and outputting 9 clocks from V8. VCAIL
is defined as the maximum voltage V12 when the CAO pin output does not change.
4. CTL pin voltage "H" (VCTLH), CTL pin voltage "L" (VCTLL
)
Set V13 = VDN − 0.5 V in initial status 2. VCTLH is defined as the voltage V13 when the CO pin output changes after the
voltage V13 is gradually increased.
Set V13 = VDN in initial status 2. VCTLL is defined as the voltage V13 when the CO pin output changes again after the
voltage V13 is gradually decreased.
5. Current consumption during operation (IOPE), Current consumption during overdischarge (IOPED
)
Set V1 = V2 = V3 = V4 = V5 = VCU − 1.0 V, V8 = V9 = VDN in initial status 1. IOPE is defined as the total current which
flows in the VDD pin and the VC1 pin.
Set V1 = V2 = V3 = V4 = V5 = 2.3 V, V8 = V9 = VDN in initial status 1. IOPED is defined as the total current which flows
in the VDD pin and the VC1 pin.
6. VCn pin current (IVCn
)
Set V1 = V2 = V3 = V4 = V5 = VCU − 1.0 V in initial status 1. IVCn is defined as the current which flows in the VCn pin
(n = 1 to 5), respectively.
7. VCn pin pull-down current (IVCLn), VCn pin pull-up current (IVCHn
)
Set V1 = V2 = V3 = V4 = V5 = VCU − 1.0 V, V9 = 0 V in initial status 1. IVCL2 is defined as the current which flows in the
VC2 pin after increasing the voltage V8 up to 5 V.
I
VCL3 is defined as the current which flows in the VC3 pin subsequently after decreasing the voltage V8 down to 0 V
and increasing the voltage V8 up to 5 V. After that, each time increasing the voltage V8 up to 5 V from 0 V, the current
which flows in the VCn pin (n = 3 to 5) is defined in order of IVCH3, IVCH4, and IVCH5, respectively.
8. CLKI pin current "H" (ICLKIH), CLKI pin current "L" (ICLKIL
)
Set V8 = VDN − 2.0 V, V9 = 0 V in initial status 2. ICLKIH is defined as the maximum current which flows in the CLKI pin
when voltage V8 is gradually increased. ICLKIL is defined as the current which flows in the CLKI pin after setting V9 =
0 V in initial status 2.
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FOR AUTOMOTIVE BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.7_00
S-8235A Series
9. RSTI pin current "H" (IRSTIH), RSTI pin current "L" (IRSTIL
)
Set V9 = VDN − 2.0 V in initial status 2. IRSTIH is defined as the maximum current which flows in the RSTI pin when the
voltage V9 is gradually increased. IRSTIL is defined as the current which flows in the RSTI pin after setting V9 = 0 V in
initial status 2.
10. CAI pin current "H" (ICAIH), CAI pin current "L" (ICAIL
)
ICAIH is defined as the current which flows in the CAI pin after setting V9 = 0 V, V12 = VDN in initial status 2.
Set V12 = 2.0 V, V9 = 0 V. ICAIL is defined as the minimum current which flows in the CAI pin when the voltage V12 is
gradually decreased.
11. CTL pin current "H" (ICTLH), CTL pin current "L" (ICTLL
)
ICTLH is defined as the current which flows in the CTL pin after setting V13 = VDN in initial status 2.
Set V13 = 2.0 V, V9 = 0 V in initial status 2. ICTLL is defined as the minimum current which flows in the CTL pin when
the voltage V13 is gradually decreased.
12. CO pin sink current (ICOL), CO pin source current (ICOH
)
ICOL is defined as the current which flows in the CO pin after setting SWCO = ON, V6 = 0.5 V in initial status 2.
COH is defined as the current which flows in the CO pin after setting SWCO = ON, V13 = VDN, V6 = VDN − 0.5 V in initial
I
status 2.
13. CAO pin sink current (ICAOL), CAO pin source current (ICAOH
)
ICAOL is the current which flows in the CAO pin after setting SWCAO = ON, V7 = 0.5 V in initial status 2.
CAOH is the current which flows in the CAO pin after setting SWCAO = ON, V9 = 0.5 V, V8 = 5 V, V7 = VDN − 0.5 V in
I
initial status 2.
14. RSTO pin sink current (IRSTOL), RSTO pin source current (IRSTOH
)
IRSTOL is defined as the current which flows in the RSTO pin after setting SWRSTO = ON, V10 = 0.5 V in initial status 3.
RSTOH is defined as the current which flows in the RSTO pin after setting SWRSTO = ON, V10 = VDN − 0.5 V in initial
I
status 2.
15. CLKO pin sink current (ICLKOL), CLKO pin source current (ICLKOH
)
ICLKOL is defined as the current which flows in the CLKO pin after setting SWCLKO = ON, V9 = 0 V, V11 = 0.5 V in initial
status 2.
ICLKOH is defined as the current which flows in the CLKO pin after setting SWCLKO = ON, V11 = VDN − 0.5V in initial
status 2.
16. Overcharge detection delay time (tCU)
tCU is defined as the time period until the CO pin output changes after increasing the voltage V1 up to 5.0 V in initial
status 1.
17. Overcharge timer reset delay time (tTR)
Increase the voltage V1 up to 5.0 V in initial status 1 (first rising), and decrease the voltage V1 down to 2.8 V within tCU
.
After that, increase voltage V1 up to 5.0 V again (second rising), and measure the time period until the CO pin output
changes. If the time period from when the voltage V1 is decreased to the second rising is short, CO pin output
changes after tCU is elapsed from the first rising. When the time period is gradually made longer, CO pin output
changes after tCU is elapsed from the second rising. tTR is defined as the time period from when the voltage V1 is
decreased to the second rising.
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FOR AUTOMOTIVE BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8235A Series
Rev.1.7_00
Operation
1. Normal status
If the voltage of each of the batteries is lower than "overcharge detection voltage n (VCUn) + overcharge hysteresis
voltage n (VHCn)", CO pin output changes to "L". This is called normal status.
2. Overcharge status
When the voltage of one of the batteries exceeds VCUn during a charging operation at normal status, and the status is
retained for overcharge detection delay time (tCU) or longer, CO pin output changes to "H". This is called overcharge
status.
VHCn
VCUn
Battery voltage
(n = 1 to 5)
tTR or
tTR or
shorter
longer
CO pin
tCU or shorter
tCU
Figure 5 Overcharge Detection Operation
2.0 ms typ.
10
FOR AUTOMOTIVE BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.7_00
S-8235A Series
3. Overcharge timer reset function
The S-8235A Series has an overcharge timer reset function.
If overcharge release noise which temporarily falls below overcharge detection voltage n (VCUn) is input during
overcharge detection delay time (tCU) from when the voltage of one of the batteries during a charging operation exceeds
VCUn until when charging is stopped, tCU is continuously counted if the time of overcharge release noise is shorter than
overcharge timer reset delay time (tTR). On the other hand, under the same status, if the time of overcharge release
noise is tTR or longer, counting of tCU is reset once. After that, when VCUn is exceeded, counting tCU resumes.
VHCn
tTR or
shorter
tTR or
longer
t
TR or
shorter
VCUn
Battery voltage
(n = 1 to 5)
tCU or
shorter
tTR
CO pin
Timer reset
tCU
Figure 6 Overcharge Timer Reset Operation
4. Status of pins
The status of pins for the S-8235A Series is shown in Table 6.
When inputting "H" to the CTL pin, the CO pin outputs "H" in 1.0 ms typ. at normal status, and maintains "H" at
overcharge status. Each of the RSTO pin, the CLKO pin, and the CAO pin outputs a signal in 1.0 ms typ. from inputting.
When performing a self-test operation, input "L" to the RSTI pin. Refer to " Self-test Function" for the self-test
operation.
Table 6
I/O Symbol
RSTI
Normal Operation
"H"
Self-test Operation
"L"
CTL
CLKI
CAI
"H"
"H"
"L"
"H"
"H"
"L"
Input
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"L" (Normal status) /
"H" (Overcharge status)
"L" (Normal status) /
"H" (Overcharge status)
CO
RSTO
CLKO
CAO
"H"
"H"
"L"
Refer to "2. RSTO pin" in " Self-test Function"
Refer to "3. CLKO pin"in" Self-test Function"
Refer to "4. CAO pin" in " Self-test Function"
Output
11
FOR AUTOMOTIVE BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8235A Series
Rev.1.7_00
Battery Protection IC Connection Example
1. 8-serial cell (5-cell + 3-cell, cascade connection)
EB+
1 VDD
2 VC1
3 VC2
4 VC3
5 VC4
6 VC5
7 VSS
8 NPI
CTL 16
RVDD
RVC1
RVC2
RVC3
RVC4
RVC5
RVSS
RNPI
CVDD
1 kΩ
1 kΩ
CAI 15
CLKO 14
RSTO 13
CVC1
CVC2
CVC3
CVC4
CVC5
CVSS
CNPI
S-8235A
RSTI 12
CLKI 11
CAO 10
(2)
RIFRST
RIFCLK
CO
9
1000 pF
1000 pF
1000 pF
1000 pF
RIFC
1 VDD
2 VC1
3 VC2
4 VC3
5 VC4
6 VC5
7 VSS
8 NPI
CTL 16
CAI 15
RVDD
RVC1
RVC2
RVC3
RVC4
RVC5
RVSS
RNPI
CVDD
CVC1
CVC2
CVC3
CVC4
CVC5
CVSS
CNPI
RIFCA
CLKO 14
RSTO 13
S-8235A
(1)
RSTI 12
CLKI 11
CAO 10
Input for reset signal
1 kΩ
Input for clock signal
1 kΩ
1 kΩ
1 kΩ
Output for chip active signal
Output for charge control
CO
9
EB−
Figure 7
Table 7 Constants for External Components
Part
Min.
0.1
Typ.
1
Max.
Unit
kΩ
kΩ
MΩ
μF
RVDD, RNPI
RVCn, RVSS
1
1.2
−
0.25
1.2
5.1
0.1
0.1
RIFC, RIFCA, RIFCLK, RIFRST
CVDD, CNPI
−
0.075
0.075
1
CVCn, CVSS
1
μF
Caution 1. The above constants are subject to change without prior notice.
2. The example of connection shown above and the constants will not guarantee successful
operation. Perform thorough evaluation using the actual application to set the constants.
3. RVC1 to RVC5 should be the same constant. CVDD, CVC1 to CVC5, CVSS, and CNPI should be the same
constant.
4. Set RVDD and CVDD so that the condition RVDD × CVDD ≥ 7.5 × 10-5 is satisfied.
5. Set RVCn and CVCn so that the condition 1.0 ≤ (RVCn × CVCn) / (RVDD × CVDD) ≤ 1.2 is satisfied.
6. Connect RIFC, RIFCA, RIFCLK, and RIFRST as close to the input pin as possible.
Remark n = 1 to 5
12
FOR AUTOMOTIVE BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.7_00
S-8235A Series
Self-test Function
The S-8235A Series has a self-test function to confirm overcharge detection operation.
Due to the self-test function, a current flows in an external resistor, the voltage between voltage monitoring pins expands,
and then the S-8235A Series spuriously becomes overcharge status (Refer to Figure 8). IVCLn or IVCHn flows in RVCn during
the self-test operation. Since the S-8235A Series detects overcharge when the voltage between voltage monitoring pins
exceeds overcharge detection voltage n (VCUn), it is possible to confirm whether the S-8235A Series normally detects the
overcharge or not by monitoring the CO pin output signal.
RVC1
VC1
V1 (< VCU1
)
CO
+
−
"H"
RVC2
VC2
IVCL2
V2
V1 + IVCL2 × RVC2 (≥ VCU1)
Figure 8 Self-test Operation between VC1 Pin and VC2 Pin
When not using the self-test function, short-circuit the CLKI pin and the VDD pin, the RSTI pin and the VDD pin via a
resistor of 1 kΩ, respectively. And short-circuit the CAI pin and the NPI pin via a resistor of 1 kΩ.
1. Self-test operation at the time of cascade connection
The S-8235A Series devices can be connected in cascade.
By connecting as shown in Figure 7, the S-8235A Series protects 6-serial or more cells lithium-ion rechargeable battery
pack.
At the time of cascade connection, the CO pin output signal for upper device of the S-8235A Series is transmitted by
connecting the CO pin and the CTL pin, and is output from the CO pin at the lower device. Therefore, it is possible to
confirm whether all devices of the S-8235A Series normally detects the overcharge or not by monitoring the CO pin
output signal for the lowest device of the S-8235A Series.
On the other hand, the CAO pin output signal for the upper device of the S-8235A Series is transmitted by connecting
the CAO pin and the CAI pin, and is output from the CAO pin at the lower device. Therefore, it is possible to confirm
which device of the S-8235A Series is in a self-test operation by monitoring the CAO pin output signal for the lowest
device of the S-8235A Series.
13
FOR AUTOMOTIVE BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8235A Series
Rev.1.7_00
2. RSTO pin
The RSTO pin outputs a reset signal to the next device. The reset signal is transmitted from the lower device to the
upper device. When "H" is input to the RSTI pin, the S-8235A Series is reset and performs a normal operation. When
inputting "L", the reset operation is released, and a self-test operation is initiated.
The RSTO pin outputs "L" after the 8th clock falling when inputting a clock signal (10 Hz typ.) to the CLKI pin (a1 in
Figure 9). Thereby, a self-test operation in the next device is initiated.
The RSTO pin outputs "H" when inputting "H" to the RSTI pin (a2 in Figure 9).
3. CLKO pin
The CLKO pin outputs a clock signal to the next device. The clock signal is transmitted from the lower device to the
upper device. The CLKO pin outputs "L" when inputting "L" to the RSTI pin (b1 in Figure 9). After that, the CLKO pin
outputs "H" at the 9th clock or subsequent clocks, and outputs "L" after falling (b2 in Figure 9). Thereby, a clock signal
is input to the next device.
The CLKO pin outputs "H" when inputting "H" to the RSTI pin (b3 in Figure 9).
4. CAO pin
The CAO pin outputs a chip active signal to the next device. The signal is to confirm which device of the S-8235A
Series is in a self-test operation. The chip active signal is transmitted from the upper device to the lower device. The
CAO pin output signal from the 1st clock to the 8th clock is controlled according to a clock signal that is input to the
CLKI pin, and, at the 9th clock or subsequent clocks, it is controlled according to a signal that is input to the CAI pin of
the lower device from the CAO pin of the upper device.
The CAO pin outputs "H" at the 1st clock rising when inputting a clock signal to the CLKI pin after inputting "L" to the
RSTI pin (c1 in Figure 9). Thereby, it is possible to confirm that a self-test operation is performed.
And then, the CAO pin outputs "L" at the 8th clock falling (c2 in Figure 9).
At the 9th clock or subsequent clocks, the CAO pin outputs "H" at the next clock rising when inputting "H" to the CAI
pin (c3 in Figure 9). For this reason, the CAO pin of each device outputs "H" with a delay of 1 clock. Therefore, it is
possible to confirm which device is in a self-test operation if the CAO pin output of the lowest device is monitored.
When a self-test operation is performed in a device of "m" stage, the CAO pin output of the lowest device is as follows.
After that, the CAO pin outputs "L" when inputting "L" to the CAI pin (c4 in Figure 9).
m = 1:
m = 2 to 8:
m ≥ 9:
The CAO pin outputs "H" at the 1st clock rising after inputting "L" to the RSTI pin.
The CAO pin outputs "H" at m clock rising after it outputs "L".
The CAO pin maintains "L" after it outputs "L".
The CAO pin outputs "L" when inputting "H" to the RSTI pin (c5 in Figure 9).
5. VCn Pin (n = 2 to 5)
When inputting a clock signal to the CLKI pin, IVCL2 flows from the VC2 pin from the 1st clock rising to its falling (d1 in
Figure 9). IVCL3 flows from the VC3 pin from the 2nd clock rising to its falling (d2 in Figure 9). And IVCH3 flows from the
VC3 pin from the 3rd clock rising until its falling (d3 in Figure 9). IVCH4 flows from the VC4 pin at the 4th clock (d4 in
Figure 9). IVCH5 flows from the VC5 pin at the 5th clock (d5 in Figure 9).
6. Overcharge detection delay time (tCU) during self-test operation
When inputting a clock signal to the CLKI pin, tCU is shortened to 8 ms typ. from the 1st clock rising to the 7th clock
rising. The time period from when inputting "L" to the RSTI pin until the 1st clock rising and the time period from the 7th
clock rising to the 8th clock falling are shortened to 32 ms typ., respectively. tCU changes to the original value at the 9th
or subsequent clocks.
14
FOR AUTOMOTIVE BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.7_00
S-8235A Series
RSTI
CLKI
CAI
1
2
4
5
6
7
8
9
3
a1
a2
RSTO
CLKO
CAO
IVCL2
b2
b1
c1
d1
b3
c5
c2
c3
c4
d2
IVCL3
IVCH3
IVCH4
IVCH5
d3
d4
d5
Figure 9
15
FOR AUTOMOTIVE BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8235A Series
Rev.1.7_00
7. Example of self-test operation
By connecting in cascade, the S-8235A Series performs a self-test operation in 6-serial or more cells protection circuit.
The example of a self-test operation at the time of cascade connection is as follows.
Refer to Table 6 in " Operation" for the output pin voltage to be set depending on the input pin voltage.
CTL (2)
CAI (2)
CLKO (2)
RSTO (2)
L
D
RSTI (2)
CLKI (2)
E
CAO (2)
F
CO (2)
G
CTL (1)
I
CAI (1)
CLKO (1)
RSTO (1)
RSTI (1)
CLKI (1)
CAO (1)
CO (1)
K
A
1
2
1
J
C
H
B
Figure 10 Timing Chart during Self-test Operation in 8-serial Cell (5-cell + 3-cell) Protection Circuit
<A> When inputting "L" to the RSTI pin of the S-8235A (1) (hereinafter, it is indicated as (1)), the self-test operation is
initiated.
<B> When a clock signal is input to the CLKI pin of (1), the overcharge detection operation of (1) is confirmed.
<C> It is possible to confirm that the self-test operation is performed in (1).
<D> The RSTO pin of (1) outputs "L", and then the voltage is input to the RSTI pin of the S-8235A (2) (hereinafter, it
is indicated as (2)).
<E> The CLKO pin output of (1) is input to the CLKI pin of (2).
<F> When a clock signal is input to the CLKI pin of (2), the overcharge detection operation of (2) is confirmed.
<G> The CO pin output of (2) is input to the CTL pin of (1).
<H> The CO pin output of (2) is output from the CO pin of (1).
<I> The CAO pin output of (2) is input to the CAI pin of (1).
<J> It is possible to confirm that the self-test operation is performed in (2).
<K> When inputting "H" to the RSTI pin of (1), the RSTO pin outputs "H".
<L> When "H" is input to the RSTI pin of (2), the self-test operation is terminated.
Caution 1. The S-8235A Series changes to the overcharge status if the voltage between voltage monitoring
pins exceeds overcharge detection voltage n (VCUn) during a self-test operation.
2. Since the voltage between voltage monitoring pins does not exceed VCUn when a self-test
operation is performed in battery voltage drop, the S-8235A Series may not detect the
overcharge.
16
FOR AUTOMOTIVE BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.7_00
S-8235A Series
Precautions
• The application conditions for the input voltage, output voltage, and load current should not exceed the package power
dissipation.
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
• SII Semiconductor Corporation claims no responsibility for any and all disputes arising out of or in connection with any
infringement by products including this IC of patents owned by a third party.
17
FOR AUTOMOTIVE BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8235A Series
Rev.1.7_00
Characteristics (Typical Data)
1. Detection voltage
1. 1 VCU vs. Ta
1. 2 VCU + VHC vs. Ta
VCU = 4.050 V
VHC = −0.050 V
4.150
4.100
4.050
4.000
3.950
4.100
4.050
4.000
3.950
3.900
40
25
0
25
50
75 85
40
25
0
25
50
75 85
Ta [C]
Ta [C]
2. Current consumption
2. 1 IOPE vs. Ta
2. 2 IOPED vs. Ta
VDD = 15.25 V
VDD = 10.5 V
10
8
8
6
4
2
0
6
4
2
0
−
40
−
25
0
25
50
75 85
−
40
−
25
0
25
50
75 85
Ta [C]
Ta [C]
2. 3 IOPE vs. VDD
Ta = +25°C
60
50
40
30
20
10
0
0
5
10
15
20
25
30
VDD [V]
18
FOR AUTOMOTIVE BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.7_00
S-8235A Series
3. Delay time
3. 1 tCU vs. Ta
VDD = 17.5 V
1.2
1.1
1.0
0.9
0.8
−
40
−
25
0
25
50
75 85
Ta [C]
4. Output current
4. 1 ICOH vs. VDD
4. 2 ICOL vs. VDD
Ta = +25°C
Ta = +25°C
0
−250
−500
−750
10000
7500
5000
2500
0
0
−1000
5
10
15
20
25
30
0
5
10
15
20
25
30
V
DD [V]
VDD [V]
4. 3 ICAOH vs. VDD
4. 4 ICAOL vs. VDD
Ta = +25°C
Ta = +25°C
0
−250
−500
−750
10000
7500
5000
2500
0
0
−1000
5
10
15
20
25
30
0
5
10
15
20
25
30
V
DD [V]
VDD [V]
19
FOR AUTOMOTIVE BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8235A Series
Rev.1.7_00
5. Output current
5. 1 IVCLn vs. Ta
5. 2 IVCHn vs. VDD
VDD = 15.25 V
VDD = 15.25 V
1.4
1.2
1.0
0.8
0.6
−0.7
−0.9
−1.1
−1.3
−
40
−
25
25
25
25
0
0
0
0
25
50
75 85
−
40
−
25
25
25
25
0
0
0
0
25
50
75 85
Ta [C]
Ta [C]
5. 3 ICLKIH vs. Ta
5. 4 ICLKIL vs. Ta
VDD = 15.25 V
VDD = 17.5 V
20.0
15.0
10.0
5.0
−0.4
−0.6
−0.8
−1.0
0.0
−
40
−
25
50
75 85
−
40
−
−
−
25
50
75 85
Ta [C]
Ta [C]
5. 5 IRSTIH vs. Ta
5. 6 IRSTIL vs. Ta
VDD = 17.5 V
VDD = 17.5 V
20.0
15.0
10.0
5.0
−0.4
−0.6
−0.8
−1.0
0.0
−
40
−
25
50
75 85
−
40
25
50
75 85
Ta [C]
Ta [C]
5. 7 ICTLH vs. Ta
5. 8 ICTLL vs. Ta
0.0
VDD = 17.5 V
VDD = 17.5 V
1.0
−5.0
0.8
0.6
0.4
−10.0
−15.0
−20.0
−
40
−
25
50
75 85
−
40
25
50
75 85
Ta [C]
Ta [C]
Remark n = 1 to 5
20
5.1±0.2
16
9
8
1
0.17±0.05
0.22±0.08
0.65
No. FT016-A-P-SD-1.2
TITLE
TSSOP16-A-PKG Dimensions
FT016-A-P-SD-1.2
No.
ANGLE
mm
UNIT
SII Semiconductor Corporation
+0.1
-0
4.0±0.1
ø1.5
0.3±0.05
2.0±0.1
8.0±0.1
1.5±0.1
ø1.6±0.1
(7.2)
4.2±0.2
+0.4
-0.2
6.5
1
16
8
9
Feed direction
No. FT016-A-C-SD-1.1
TITLE
TSSOP16-A-Carrier Tape
FT016-A-C-SD-1.1
No.
ANGLE
mm
UNIT
SII Semiconductor Corporation
21.4±1.0
17.4±1.0
+2.0
-1.5
17.4
Enlarged drawing in the central part
ø21±0.8
2±0.5
ø13±0.2
No. FT016-A-R-S1-1.0
TITLE
No.
TSSOP16-A- Reel
FT016-A-R-S1-1.0
ANGLE
UNIT
QTY.
4,000
mm
SII Semiconductor Corporation
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notice.
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SII Semiconductor Corporation is not responsible for damages caused by the reasons other than the products or
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